Semiconductor device

Abstract

This semiconductor device includes: a first transistor with a first semiconductor layer, a second semiconductor layer, and a first gate electrode, formed on a first surface of a substrate; a first power line formed on a second surface of the substrate, and in electrical connection to the first semiconductor layer; a second power line electrically connected to the second semiconductor layer; a third power line; a first signal line disposed to overlap the first gate electrode in a plan view; a first via which is formed in the substrate and which connects the first gate electrode and the first signal line; and a second transistor and a third transistor which are formed on the first surface of the substrate and which are connected to the first power line and the third power line. This allows a power switch circuit to be disposed appropriately in cases where there is a via that connects directly from the back surface of a semiconductor substrate to a gate electrode on the front surface of the semiconductor substrate.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] BS-PDN (Backside Power Delivery Network) technology is known, which supplies power from the back surface of a semiconductor substrate to elements such as transistors formed on the front surface of the semiconductor substrate. Technology is also known in which a via is provided that directly connects the back surface of the semiconductor substrate to the gate electrode of a transistor on the front surface of the semiconductor substrate. Technology is also known in which a power switch circuit is provided that switches the supply of power to a circuit on and off.

[0003] US Patent Application Publication No. 2023 / 0178435 US Patent Application Publication No. 2023 / 0067311 US Patent Application Publication No. 2022 / 0123023 US Patent Application Publication No. 2022 / 0181258 International Publication No. 2020 / 065916 International Publication No. 2020 / 066797 International Publication No. 2020 / 217396 International Publication No. 2020 / 217400 US Patent Application Publication No. 2021 / 0366902 US Patent Application Publication No. 2022 / 0102479 US Patent Application Publication No. 2021 / 0210600

[0004] M. Kobrinsky, "A new VLSI R&D frontier: cell-level interconnects to enable back-side power delivery networks and 3D device stacking", 2023 Symposium on VLSI Technology and Circuits Advance Program: Workshop3 (June 11, 2023), Internet <URL: https: / / archive.vlsisymposium.org / 23web / files / program / VLSI2023_Advanceprogram0612.pdf>

[0005] When there is a via that directly connects from the back surface of the semiconductor substrate to the gate electrode on the front surface of the semiconductor substrate, no detailed consideration has been given to how to arrange the power switch circuit that switches the power supply to the circuit on and off.

[0006] The present invention has been made in consideration of the above points, and aims to appropriately arrange a power switch circuit when there is a via that directly connects from the back surface of a semiconductor substrate to a gate electrode on the front surface of the semiconductor substrate.

[0007] In one aspect of the present invention, a semiconductor device includes a substrate, a first semiconductor layer and a second semiconductor layer formed on a first surface of the substrate, a first nanosheet connecting the first semiconductor layer and the second semiconductor layer, a first gate electrode covering the first nanosheet, a first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode, a first power supply line electrically connecting to the first semiconductor layer, a second power supply line electrically connecting to the second semiconductor layer, a third power supply line, a first signal line arranged to overlap the first gate electrode in a planar view, which are formed on a second surface of the substrate opposite to the first surface, a first via formed in the substrate, connecting the first gate electrode and the first signal line, and arranged to overlap the first gate electrode and the first signal line in a planar view, a third semiconductor layer and a fourth semiconductor layer formed on the first surface, and a third semiconductor layer and a fourth semiconductor layer arranged to overlap the third semiconductor layer in a planar view. a fifth semiconductor layer disposed on the fourth semiconductor layer in a planar view, a sixth semiconductor layer disposed so as to overlap the fourth semiconductor layer in a planar view, a second nanosheet connecting the third semiconductor layer and the fourth semiconductor layer, a third nanosheet connecting the fifth semiconductor layer and the sixth semiconductor layer, a second gate electrode covering the second nanosheet and the third nanosheet, a second transistor having the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the second gate electrode, and a third transistor having the fifth semiconductor layer, the sixth semiconductor layer, the third nanosheet, and the second gate electrode, wherein one of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the first power supply line, one of the fifth semiconductor layer and the sixth semiconductor layer is electrically connected to the third power supply line, and the other of the third semiconductor layer and the fourth semiconductor layer and the other of the fifth semiconductor layer and the sixth semiconductor layer are electrically connected to the first signal line.

[0008] According to the disclosed technique, when there is a via that directly connects from the back surface of the semiconductor substrate to the gate electrode on the front surface of the semiconductor substrate, the power switch circuit can be appropriately arranged.

[0009] 7 is a plan view showing an example of a layout of a semiconductor device in a first embodiment. FIG. 8 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of FIG. 1. FIG. 9 is a circuit diagram showing an example of a circuit arranged in the standard cell block of FIG. 1. FIG. 10 is a diagram showing a legend for circuit elements used in the plan views of the circuits described below. FIG. 11 is a plan view showing an example of a circuit layout of a BSM1 layer and a BSM2 layer in a region where a power switch circuit of FIG. 3 is formed. FIG. 12 is a plan view showing an example of a bottom-side circuit layout formed on the surface of a substrate in a region where a power switch circuit of FIG. 5 is formed. FIG. 13 is a plan view showing an example of a top-side circuit layout formed on the bottom-side circuit of FIG. 6 in a region where a power switch circuit of FIG. 5 is formed. FIG. 14 is a cross-sectional view showing an example of a cross section taken along line X1-X1' in FIGS. 5 to 7. FIG. 15 is a cross-sectional view showing an example of a cross section taken along line X2-X2' in FIGS. 5 to 7. FIG. 16 is a cross-sectional view showing an example of a cross section taken along line Y1-Y1' in FIGS. 5 to 7. FIG. 17 is a cross-sectional view showing an example of a cross section taken along line Y2-Y2' in FIGS. 5 to 7. FIG. 18 is a plan view showing an example of a bottom-side circuit layout in a region where a power switch circuit of a first modified example of the first embodiment is formed. 12 in a first modified example of the first embodiment. FIG. 13 is a plan view showing an example of a circuit layout on the top side formed on the circuit on the bottom side of FIG. 12 in a first modified example of the first embodiment. FIG. 14 is a plan view showing an example of a circuit layout on the top side of a region where a power switch circuit is formed in a second modified example of the first embodiment. FIG. 15 is a plan view showing an example of a circuit layout on the bottom side of a region where a power switch circuit is formed in a third modified example of the first embodiment. FIG. 16 is a plan view showing an example of a circuit layout on the top side of a region where a power switch circuit is formed in a fourth modified example of the first embodiment. FIG. 17 is a plan view showing another example of a circuit layout of a power switch circuit in the fourth modified example of the first embodiment. FIG. 18 is a plan view showing an example of a circuit layout of a BSM1 layer and a BSM2 layer in a region where a power switch circuit of the semiconductor device of the second embodiment is formed.22. A plan view showing an example of a circuit layout on the bottom side in a region where the power switch circuit of FIG. 20 is formed. A plan view showing an example of a circuit layout on the top side in a region where the power switch circuit of FIG. 20 is formed. A cross-sectional view showing an example of a cross section taken along line X3-X3' in FIGS. 20 to 22. A cross-sectional view showing an example of a cross section taken along line X4-X4' in FIGS. 20 to 22. A cross-sectional view showing an example of a cross section taken along line X5-X5' in FIGS. 20 to 22. A cross-sectional view showing an example of a cross section taken along line Y3-Y3' in FIGS. 20 to 22.

[0010] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply potential is also used to indicate a power supply line or a power supply terminal to which the power supply potential is supplied.

[0011] 1 shows an example of the layout of a semiconductor device according to the first embodiment. For example, the semiconductor device 100 shown in FIG. 1 may be a SoC (System on Chip), a standalone FPGA (Field-Programmable Gate Array), or the like.

[0012] The semiconductor device 100 has a plurality of I / O cells IOC and IOCP and an internal circuit region INTR. The I / O cell IOC is an interface circuit for a signal SGNL such as an input signal, an output signal, or an input / output signal. The I / O cell IOCP is an interface circuit for a power supply potential or a ground potential.

[0013] Each I / O cell IOC, IOCP is connected to an internal circuit region INTR. For example, the internal circuit region INTR has one or more standard cell blocks SCB in which standard cells are provided. Note that the internal circuit region INTR may also be equipped with logic circuits other than standard cells, or may also be equipped with a memory. The memory may be equipped within the standard cell block SCB.

[0014] Fig. 2 shows an example of a cross-sectional structure of the semiconductor device 100 of Fig. 1. The semiconductor device 100 has a substrate SUB, a wiring layer WL1 formed on the front surface FS side of the substrate SUB, and a wiring layer WL2 formed on the back surface BS side of the substrate SUB. The front surface FS of the substrate SUB is an example of a first surface, and the back surface BS of the substrate SUB is an example of a second surface.

[0015] A CFET (Complementary Field Effect Transistor) is formed on the surface of the substrate. The CFET has a source S and a drain D formed in semiconductor layers on a bottom side (BTM) that is closer to the substrate SUB and a top side (TOP) that is farther from the substrate SUB. Hereinafter, wiring and semiconductor layers arranged on the bottom BTM side may be denoted by the symbol BTM, and wiring and semiconductor layers arranged on the top TOP side may be denoted by the symbol TOP.

[0016] The wiring arranged on the bottom BTM side may also be referred to as bottom wiring BTMW, and the wiring arranged on the top TOP side may also be referred to as top wiring TOPW. Furthermore, a part of the CFET structure may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer. The semiconductor layer may be referred to as source / drain S / D, even if it does not function as a transistor. Furthermore, a part of the CFET structure may be referred to as an NMOS transistor or a PMOS transistor depending on the conductivity type of its semiconductor layer, even if it does not function as a transistor.

[0017] The CFET has a nanosheet NS that interconnects the source S and drain D on the bottom BTM side and a nanosheet NS that interconnects the source S and drain D on the top TOP side. The CFET has a gate insulating film (not shown) formed on each nanosheet NS and a gate electrode GT that is common to the top TOP side and the bottom BTM side.

[0018] The wiring layer WL1 may have a wiring layer FSM1 (FSM stands for Frontside Metal) on which the wiring W3 is formed above the top region. The wiring layer WL1 may have multiple wiring layers FSM. Hereinafter, the wiring layer FSM is also referred to as an FSM layer.

[0019] The wiring layer WL2 has wiring layers BSM1 and BSM2 (BSM stands for Backside Metal). The wiring layer WL2 may have one wiring layer BSM, or may have three or more wiring layers BSM. For example, wirings W1 and W2 such as power lines, ground lines, or signal lines are formed in the wiring layers BSM1 and BSM2, respectively. The wirings W1 and W2 may be connected to each other via vias VIA.

[0020] A power supply line or a ground line of the wiring layer BSM1 is connected to one end of a via VIA such as a TSV formed in the substrate SUB, and the other end of the via VIA is directly connected to the source S or drain D of the CFET. A signal line of the wiring layer BSM1 is connected to one end of a via VIA such as a TSV, and the other end of the via VIA is directly connected to a gate electrode GT (hereinafter also referred to as gate GT) of the CFET. A via VIA such as a TSV directly connected to the gate GT is sometimes also referred to as a DGC (Direct Gate Contact).

[0021] The wiring W1 of the wiring layer BSM1 may be connected to a buried wiring BPR (Buried Power Rail) buried in the surface of the substrate SUB through a via VIA such as a TSV. The wiring layer WL2 may be a wiring layer formed on the back surface of the substrate SUB, or may be a wiring layer formed in another chip attached to the back surface of the substrate SUB. Hereinafter, the wiring layers BSM1 and BSM2 are also referred to as a BSM1 layer and a BSM2 layer.

[0022] 3 shows an example of a circuit arranged in the standard cell block SCB of FIG. 1. The standard cell block SCB has a power switch circuit PSW and standard cells SC. The standard cells SC are connected to a virtual power line VVDD and a ground line VSS, and operate by receiving a virtual power potential VVDD from the virtual power line VVDD. The standard cells SC have various logic circuits.

[0023] The power switch circuit PSW is connected to a power line TVDD and a ground line VSS and operates. The power switch circuit PSW includes a control circuit CNTL and a switch transistor SWT. For example, the control circuit CNTL includes a buffer circuit BUF including inverters INV1 and INV2 connected in series. The inverter INV1 receives an input signal BUFin and outputs a control signal PSWsig that controls the switch transistor SWT. The inverter INV2 receives the control signal PSWsig and outputs an output signal BUFout. The power line TVDD is an example of a first power line, and the virtual power line VVDD is an example of a second power line. The ground line VSS is an example of a third power line.

[0024] The switch transistor SWT has a PMOS transistor whose source is connected to the power supply line TVDD and whose drain is connected to the virtual power supply line VVDD, and operates by receiving the potential of a control signal PSWsig from the control circuit CNTL as a gate potential. While the switch transistor SWT is on, the power supply line TVDD and the virtual power supply line VVDD are electrically connected, and the power supply potential TVDD is supplied to the standard cell SC via the virtual power supply line VVDD. While the switch transistor SWT is off, the electrical connection between the power supply line TVDD and the virtual power supply line VVDD is cut off, and the virtual power supply line VVDD is set to a floating state.

[0025] 4 shows a legend for circuit elements used in the plan views of the circuits described below. Note that in the legend, various vias are indicated by solid line shapes, but in the plan views shown in FIG. 5 and subsequent figures, vias hidden by wiring arranged above are indicated by dashed line shapes.

[0026] 5 shows an example of a circuit layout of the BSM1 layer and the BSM2 layer in the region where the power switch circuit PSW of FIG. 3 is formed. The wiring in the BSM1 layer extends in the Y direction and is arranged at intervals in the X direction. The wiring in the BSM2 layer extends in the X direction and is arranged at intervals in the Y direction. The Y direction is an example of a first direction, and the X direction is an example of a second direction. For example, in FIG. 5, the buffer circuit BUF is arranged in the upper left region of FIG. 5, and the switch transistor SWT is arranged in a region where the buffer circuit BUF is not formed.

[0027] In the BSM1 layer and the BSM2 layer, wiring of the same type (for example, a virtual power line VVDD or a control signal line PSWsig) may be connected to each other through a via VIA (BSM1-BSM2). In the region of the power switch circuit PSW, the power line TVDD, the virtual power line VVDD, the control signal line PSWsig, and the input signal line BUFin are formed using the BSM1 layer, and the power line TVDD and the control signal line PSWsig are formed using the BSM2 layer. The signal line PSWsig in the BSM1 layer is an example of a first signal line, and the input signal line BUFin in the BSM1 layer is an example of a second signal line. The control signal line PSWsig in the BSM1 layer is connected to the gate GT (not shown) of the switch transistor SWT through a via VIA (DGC).

[0028] 6 shows an example of a circuit layout on the side of a bottom BTM formed on the surface of a substrate SUB in the region where the power switch circuit PSW is formed. A PMOS transistor including a P-type semiconductor layer Pdiff is formed on the side of the bottom BTM. The symbols S and D shown in the semiconductor layer Pdiff indicate a source and a drain, respectively.

[0029] The switch transistor SWT is formed by a gate GT and a plurality of PMOS transistors each including a source S and a drain D adjacent to the gate GT in the Y direction. One end of the via VIA (DGC) is directly connected to the gate GT of the switch transistor SWT (PMOS transistor), and the other end of the via VIA (DGC) is directly connected to the control signal line PSWsig of the BSM1 layer.

[0030] The switch transistor SWT is an example of a first transistor, and the gate GT of the switch transistor SWT is an example of a first gate electrode. The nanosheet NS of the switch transistor SWT is an example of a first nanosheet. The source S of the PMOS transistor of the switch transistor SWT is an example of either a first semiconductor layer or a second semiconductor layer. The drain D of the PMOS transistor of the switch transistor SWT is an example of the other of the second semiconductor layer or the first semiconductor layer. The via VIA (DGC) connected to the gate GT of the switch transistor SWT is an example of a first via.

[0031] The source S of the switch transistor SWT (PMOS transistor) is connected to the power supply line TVDD of the BSM1 layer through the bottom wiring BTMW and the via VIA (BSM1-BTM). That is, the source S of the switch transistor SWT is connected to the power supply line TVDD of the BSM1 layer, which is arranged offset in the X direction from the switch transistor SWT in a plan view. The sources S of the switch transistors SWT arranged side by side in the X direction may be connected to each other by the bottom wiring BTMW.

[0032] The drain D of the switch transistor SWT is connected to the virtual power line VVDD of the BSM1 layer through the bottom wiring BTMW and the via VIA (BSM1-BTM). That is, the drain D of the switch transistor SWT is connected to the virtual power line VVDD of the BSM1 layer, which is arranged offset in the X direction from the switch transistor SWT in a plan view. The drains D of the switch transistors SWT arranged side by side in the X direction may be connected to each other by the bottom wiring BTMW.

[0033] The PMOS transistors of inverters INV1 and INV2 are formed in the buffer circuit BUF region. The sources S of the PMOS transistors of inverters INV1 and INV2 are connected to the power supply line TVDD in the BSM1 layer via the bottom wiring BTMW and a via VIA (BSM1-BTM). One end of the via VIA (DGC) is directly connected to the gates GT of the PMOS transistors of inverters INV1 and INV2, and the other end of the via VIA (DGC) is directly connected to the control signal line PSWsig in the BSM1 layer. The gate GT of the PMOS transistor of inverter INV1 receives the input signal BUFin, and the gate GT of the PMOS transistor of inverter INV2 receives the control signal PSWsig output from the inverter INV1.

[0034] The PMOS transistor of the inverter INV1 is an example of a second transistor, and the gate GT of the inverter INV1 is an example of a second gate electrode. The nanosheet NS of the PMOS transistor of the inverter INV1 is an example of a second nanosheet. The source S of the PMOS transistor of the inverter INV1 is an example of either the third semiconductor layer or the fourth semiconductor layer. The drain D of the PMOS transistor of the inverter INV1 is an example of the other of the third semiconductor layer or the fourth semiconductor layer. The via VIA (DGC) connected to the gate GT of the inverter INV1 is an example of a second via.

[0035] The drains D of the PMOS transistors of the inverters INV1 and INV2 are connected to a top wiring TOPW formed on the top TOP side (FIG. 7) via a bottom wiring BTMW and a via VIA (BTM-TOP), and are connected to the drains D of the NMOS transistors of the inverters INV1 and INV2. A control signal PSWsig is output from the drain D of the inverter INV1 and connected to the gate of the switch transistor SWT via a via VIA (BSM1-BTM), a control signal line PSWsig in the BSM1 layer, and a via VIA (DGC). The output of the inverter INV1 and the input of the inverter INV2 may be connected via a wiring FSMW in the FSM layer (not shown). The via VIA (DGC) through which the control signal PSWsig is transmitted is an example of a third via.

[0036] 6, the drains D of the inverters INV1 and INV2 of the buffer circuit BUF are arranged adjacent to the source S of the switch transistor SWT. However, by interchanging the positions of the sources S and drains D of the inverters INV1 and INV2 of the buffer circuit BUF in the Y direction, the sources S of the inverters INV1 and INV2 and the switch transistor SWT may share the source S.

[0037] 7 shows an example of a circuit layout on the top TOP side formed on the circuit on the bottom BTM side of FIG. 6 in the region where the power switch circuit PSW of FIG. 5 is formed. An NMOS transistor including an N-type semiconductor layer Ndiff is formed on the top side. The symbols S and D shown in the semiconductor layer Ndiff indicate the source and drain, respectively. A semiconductor layer Ndiff without either the symbol S or D is set to an open state, for example, and does not function as a transistor.

[0038] For example, the semiconductor layer Ndiff of the NMOS transistor formed in the region of the switch transistor SWT is in an open state and does not function as an NMOS transistor. The nanosheet NS of the NMOS transistor formed in the region of the switch transistor SWT is an example of a fourth nanosheet. The semiconductor layer Ndiff of the NMOS transistor formed in the region of the switch transistor SWT is an example of either the sixth semiconductor layer or the seventh semiconductor layer. The semiconductor layer Ndiff of the NMOS transistor formed in the region of the switch transistor SWT is an example of the other of the sixth semiconductor layer or the seventh semiconductor layer.

[0039] The NMOS transistor of the inverter INV1 is an example of a third transistor, and the nanosheet NS of the NMOS transistor of the inverter INV1 is an example of a third nanosheet. The source S of the NMOS transistor of the inverter INV1 is an example of either the fifth semiconductor layer or the sixth semiconductor layer. The drain D of the NMOS transistor of the inverter INV1 is an example of the other of the fifth semiconductor layer or the sixth semiconductor layer.

[0040] In the buffer circuit BUF region, NMOS transistors of inverters INV1 and INV2 are formed. The drains D of the NMOS transistors of inverters INV1 and INV2 are connected to the bottom wiring BTM in FIG. 6 via the top wiring TOPW and a via VIA (BTM-TOP), and are connected to the drains D of the NMOS transistors of inverters INV1 and INV2. The sources S of the NMOS transistors of inverters INV1 and INV2 are connected to the ground line VSS of the BSM1 layer via the top wiring TOPW and a via VIA (BSM1-TOP). The gates GT of the NMOS transistors of inverters INV1 and INV2 are directly connected to the via VIA (DGC), as shown in FIG. 6.

[0041] Fig. 8 shows an example of a cross section taken along line X1-X1' in Fig. 5 to Fig. 7. In the switch transistor SWT and the buffer circuit BUF, a P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the source S or drain D of the PMOS transistor.

[0042] The sources S of the switch transistor SWT and the PMOS transistor of the buffer circuit BUF are connected to the power supply line TVDD of the BSM1 layer via the bottom wiring BTMW and the via VIA. The drain D of the switch transistor SWT (PMOS transistor) is connected to the virtual power supply line VVDD of the BSM1 layer via the bottom wiring BTMW and the via VIA.

[0043] The sources S of the NMOS transistors of the inverters INV1 and INV2 of the buffer circuit BUF are connected to the ground line VSS of the BSM1 layer through the top wiring TOPW, the N-type semiconductor layer Ndiff of the switch transistor SWT, and the via VIA. In the switch transistor SWT, the N-type semiconductor layer Ndiff formed on the top TOP side is set to an open state except for the semiconductor layer Ndiff that connects the sources S of the NMOS transistors of the buffer circuit BUF to the ground line VSS.

[0044] 8, the ground line VSS of the BSM1 layer is connected to the top wiring TOPW through a via VIA (BSM1-TOP). However, the ground line VSS of the BSM1 layer may be connected to the top wiring TOPW through a via VIA (BSM1-BTM), a bottom wiring BTM, and a via VIA (BTM-TOP), not shown, instead of the via VIA (BSM1-TOP).

[0045] 9 shows an example of a cross section taken along line X2-X2' in FIGS. 5 to 7. The drains D (PSWsig) of the PMOS transistor and NMOS transistor of inverter INV1 of buffer circuit BUF are connected to each other via top wiring TOPW, via VIA, and bottom wiring BTMW. The drains D (BUFout) of the PMOS transistor and NMOS transistor of inverter INV2 of buffer circuit BUF are connected to each other via top wiring TOPW, via VIA, and bottom wiring BTMW.

[0046] The source S of the switch transistor SWT (PMOS transistor) is connected to the power supply line TVDD of the BSM1 layer via the bottom wiring BTMW and the via VIA. The drain D of the switch transistor SWT (PMOS transistor) is connected to the virtual power supply line VVDD of the BSM1 layer via the bottom wiring BTMW and the via VIA.

[0047] For example, the wiring and vias, etc. of the BSM1 layer and BSM2 layer below the substrate SUB are integrally formed on the underside of the substrate SUB on which the power switch circuit PSW, etc. are formed, using a semiconductor manufacturing process. Note that the wiring and vias, etc. of the BSM1 layer and BSM2 layer below the substrate SUB may be formed on a substrate separate from the substrate SUB on which the power switch circuit PSW and standard cell SC are formed. In this case, the wiring layer including the wiring and vias, etc. of the BSM1 layer and BSM2 layer formed on the separate substrate is joined to the underside of the substrate SUB.

[0048] Fig. 10 shows an example of a cross section taken along line Y1-Y1' in Fig. 5 to Fig. 7. Fig. 11 shows an example of a cross section taken along line Y2-Y2' in Fig. 5 to Fig. 7. The P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the source S or drain D of a PMOS transistor. The N-type semiconductor layer Ndiff of the inverters INV1 and INV2 formed on the top TOP side functions as the source S or drain D of an NMOS transistor.

[0049] The drain D (PSWsig) of the source S of the PMOS transistor and NMOS transistor of the inverter INV1 shown in FIG. 10 and the gate GT of the inverter INV2 shown in FIG. 11 may be connected to the gate GT of the switch transistor SWT not only via the control signal line PSWsig of the BSM1 layer but also via the control signal line PSWsig of the BSM2 layer.

[0050] The gate GT, which is provided in common to the PMOS transistor and the NMOS transistor, is directly connected to one end of the via VIA (DGC). Between the P-type semiconductor layers Pdiff adjacent in the Y direction, a nanosheet NS on the bottom BTM side is formed, which extends through the gate GT. Between the N-type semiconductor layers Ndiff adjacent in the Y direction, a nanosheet NS on the top TOP side is formed, which extends through the gate GT.

[0051] 12 and 13 show an example of a circuit layout of an area where a power switch circuit is formed in a first modified example of the first embodiment. Fig. 12 shows the circuit layout on the bottom BTM side, and Fig. 13 shows the circuit layout on the top TOP side. Detailed descriptions of elements similar to those in Figs. 6 and 7 will be omitted. The layout area shown in Figs. 12 and 13 is half the size in the X direction of the layout area shown in Figs. 6 and 7.

[0052] The circuit layout of the PMOS transistors of the buffer circuit BUF is similar to that of the PMOS transistors of the buffer circuit BUF in FIG. 6 . However, the ground line VSS of the BSM1 layer is arranged within the region of the buffer circuit BUF. For example, the ground line VSS of the BSM1 layer is arranged between the divided power supply lines TVDD extending in the Y direction at the center in the X direction. The circuit layout of the PMOS transistors of the switch transistor SWT is similar to that of the switch transistor SWT in FIG. 6 , except that the number of PMOS transistors (the number of gates GT) is reduced from 12 to 4. In the switch transistor SWT, the drains D arranged on both sides of the power supply line TVDD of the BSM1 layer in plan view may be connected to each other via a bottom wiring BTMW (not shown).

[0053] 13 shows an example of a top-side circuit layout formed on the bottom-side circuit of FIG. 12 in the first modified example of the first embodiment. In the circuit layout shown in FIG. 13, the sources S and drains D of the NMOS transistors of the inverters INV1 and INV2 of the buffer circuit BUF are swapped with respect to FIG. 7. That is, the Y-direction positions of the sources S and drains D of the NMOS transistors of the inverters INV1 and INV2 are reversed from the Y-direction positions of the drains D and sources S of the PMOS transistors of the inverters INV1 and INV2 shown in FIG.

[0054] For this reason, the drain D of the NMOS transistor of the inverter INV1 is connected to the control signal line PSWsig(TOPW) via the top wiring TOPW, the via VIA(TOP-FSM), the wiring FSMW of the FSM layer, and the via VIA(TOP-FSM). Similarly, the drain D of the NMOS transistor of the inverter INV2 is connected to the output signal line BUFout(TOPW) via the top wiring TOPW, the via VIA(TOP-FSM), the wiring FSMW of the FSM layer, and the via VIA(TOP-FSM).

[0055] This allows the drains D of the NMOS transistors of the inverters INV1 and INV2 to be connected to the drains D of the PMOS transistors of the inverters INV1 and INV2 via the via VIA (BTM-TOP) and bottom wiring BTMW shown in Fig. 12. The circuit layout of the NMOS transistor of the switch transistor SWT is similar to the circuit layout of the NMOS transistor of the switch transistor SWT in Fig. 7.

[0056] 14 shows an example of a circuit layout on the top side of the region where the power switch circuit PSW is formed in the second modified example of the first embodiment. Detailed descriptions of elements similar to those in FIG. 7 will be omitted. The layout shown in FIG. 14 is the same as that in FIG. 7 except that the semiconductor layer Ndiff of the NMOS transistor not used as the switch transistor SWT in the CFET is connected to the ground line VSS and fixed to the ground potential VSS. The circuit layout on the top side of the region where the power switch circuit PSW is formed in the second modified example of the first embodiment is the same as that in FIG. 6 and therefore will not be shown.

[0057] For example, in the region of the switch transistor SWT, the semiconductor layers Ndiff (sources S and drains D of the NMOS transistors) aligned in the X direction are electrically connected to each other by a top wiring TOPW extending in the X direction. One or more rows of the semiconductor layers Ndiff aligned in the Y direction may be connected to the wiring FSMW of the FSM layer through vias VIA (TOP-FSM). This allows the semiconductor layers Ndiff aligned in the Y direction to be electrically connected to each other.

[0058] By connecting the source S and drain D of the NMOS transistor to a voltage line such as a ground line VSS with a fixed potential without leaving them open, the potentials of the source S and drain D of the NMOS transistor can be stabilized. This makes it possible to suppress, for example, fluctuations in the characteristics of the NMOS transistor due to noise, etc. Also, it is possible to suppress charge / discharge currents (leak currents) in the source region and drain region. Note that the source S and drain D of the NMOS transistor may be set in an open state while connected to each other by the top wiring TOPW.

[0059] The configuration in which the open-state semiconductor layer Ndiff is connected to the ground line VSS and the configuration in which the open-state semiconductor layers Ndiff aligned in the Y direction are connected to each other via the wiring FSMW of the FSM layer may be applied to other embodiments (including modified examples).

[0060] 15 and 16 show an example of a circuit layout of an area where a power switch circuit PSW is formed in a third modified example of the first embodiment. Fig. 15 shows the circuit layout on the bottom BTM side, and Fig. 16 shows the circuit layout on the top TOP side. Detailed descriptions of elements similar to those in Figs. 6 and 7 will be omitted.

[0061] 15 and 16, the N-type semiconductor layer Ndiff of the NMOS transistor of the CFET is formed on the bottom BTM side, and the P-type semiconductor layer Pdiff of the PMOS transistor of the CFET is formed on the top TOP side. Therefore, the switch transistor SWT is formed on the top TOP side.

[0062] On the bottom BTM side shown in Fig. 15, the semiconductor layer Ndiff is set to an open state, but may be connected to the ground line VSS via the bottom wiring BTMW and the via VIA (BSM1-BTM) as in Fig. 14. On the bottom BTM side shown in Fig. 15, the drain D of the NMOS transistor of the buffer circuit BUF is connected to the drain D of the PMOS transistor of the standard cell SC on the top TOP side shown in Fig. 16 via the bottom wiring BTMW and the via VIA (BTM-TOP). The source S of the NMOS transistor of the buffer circuit BUF is electrically connected to the ground line VSS of the BSM1 layer that is arranged in an area where the power supply line TVDD of the divided BSM1 layer extending in the Y direction is not arranged, as in Fig. 12.

[0063] 16, the source S (Pdiff) of the switch transistor SWT (PMOS transistor) is connected to the power supply line TVDD of the BSM1 layer via the top wiring TOPW and the via VIA (BSM1-TOP). The drain D (Pdiff) of the switch transistor SWT is connected to the virtual power supply line VVDD of the BSM1 layer via the top wiring TOPW and the via VIA (BSM1-TOP).

[0064] 16, the source S of the PMOS transistor of the buffer circuit BUF is connected to the power supply line TVDD of the BSM1 layer through the top wiring TOPW and the via VIA (BSM1-TOP). Note that the configuration in which the NMOS transistor is arranged on the bottom BTM side and the PMOS transistor is arranged on the top TOP side may be applied to other embodiments (including modified examples).

[0065] 16, the top wiring TOP connected to the source S and drain D of the PMOS transistor is connected to the wiring in the BSM1 layer through a via VIA (BSM1-TOP). However, the top wiring TOP may be connected to the wiring in the BSM1 layer through a via VIA (BTM-TOP), a bottom wiring BTM, and a via VIA (BSM1-BTM), which are not shown. Furthermore, the control signal line PSWsig connected to the output (drain D) of the inverter INV1 may be connected to the gate GT of the switch transistor SWT and the gate GT of the inverter INV2 through a control signal line PSWsig in the BSM2 layer (not shown) in addition to the control signal line PSWsig in the BSM1 layer.

[0066] 17 and 18 show an example of a circuit layout of an area where a power switch circuit is formed in a fourth modification of the first embodiment. Fig. 17 shows the circuit layout on the bottom BTM side, and Fig. 18 shows the circuit layout on the top TOP side. Detailed descriptions of elements similar to those in Figs. 6 and 7 will be omitted.

[0067] In the fourth modification, the switch transistor SWT (PMOS transistor) is arranged not only on the bottom BTM side shown in Fig. 17 but also on the top TOP side shown in Fig. 18. Since the switch transistor SWT is arranged in a region adjacent in the X direction to the source S of the NMOS transistor of the inverter INV2 shown in Fig. 18, the ground line VSS of the BSM1 layer is arranged at a position adjacent to the buffer circuit BUF.

[0068] In addition, in the region of the switch transistor SWT, a via VIA (BTM-TOP) that interconnects the bottom wiring BTMW and top wiring TOPW of the power supply line TVDD, and a via VIA (BTM-TOP) that interconnects the bottom wiring BTMW and top wiring TOPW of the virtual power supply line VVDD are arranged. This allows the source S and drain D of the PMOS transistor arranged on the top TOP side to be connected to the power supply line TVDD and the virtual power supply line VVDD, respectively.

[0069] For example, the ground line VSS of the BSM1 layer is arranged between two separated virtual power supply lines VVDD located at the center in the X direction. In this case, as shown in Figures 17 and 18, the standard cell SC may be arranged side by side in the Y direction with a power supply switch circuit PSW including a switch transistor SWT and a buffer circuit BUF. The virtual power supply line VVDD of the BSM1 layer located at the center in the X direction of the standard cell SC region may be connected to another virtual power supply line VVDD of the BSM2 layer (not shown) via a virtual power supply line VVDD of the BSM2 layer.

[0070] 19 shows another example of the circuit layout of the power switch circuit PSW in the fourth modified example of the first embodiment. The switch transistors SWT may be arranged to surround the buffer circuits BUF arranged at the ends of the power switch circuit PSW. That is, the buffer circuits BUF may be arranged to be sandwiched between the switch transistors SWT in the Y direction. The circuit layout shown in FIG. 19 can be realized, for example, by arranging the switch transistors SWT on the Y-direction front side of the circuit layouts shown in FIGS. 5 to 7 and 14 to 18.

[0071] In this case, even if the virtual power line VVDD in the BSM1 layer is divided by the ground line VSS in the BSM1 layer provided around the buffer circuit BUF, the virtual power potential VVDD is supplied from the switch transistor SWT to both of the divided virtual power lines VVDD in the BSM1 layer. Therefore, even if the divided virtual power lines VVDD in the BSM1 layer are not connected to each other via wiring in the BSM2 layer, a voltage can be supplied to each of the divided virtual power lines VVDD in the BSM1 layer. Note that the gates and semiconductor layers (not shown) of the switch transistor SWT and the buffer circuit BUF may be arranged symmetrically with respect to the dashed line.

[0072] As described above, in the first embodiment, by using the via VIA (DGC), it is possible to connect the control signal line PSWsig on the back surface of the semiconductor substrate SUB to the gate GT of the switch transistor SWT without using wiring formed on the front surface FS side of the substrate SUB. Also, by using the via VIA (DGC), it is possible to connect the input signal line BUFin on the back surface of the semiconductor substrate SUB to the gate GT of the inverter INV1 without using wiring formed on the front surface FS side of the substrate SUB.

[0073] Furthermore, by using the via VIA (DGC), the control signal line PSWsig on the back surface of the semiconductor substrate SUB can be connected to the gate GT of the inverter INV2 without using the bottom wiring BTMW or the top wiring TOPW. As a result, it is possible to prevent a decrease in the layout density of the switch transistors SWT due to limitations imposed by the wiring of the bottom wiring BTMW or the top wiring TOPW, and it is possible to prevent a decrease in the wiring density of the BSM1 layer. Therefore, when there is a via VIA (DGC) that directly connects from the back surface of the semiconductor substrate SUB to the gate GT on the front surface of the semiconductor substrate SUB, the power switch circuit PSW can be appropriately arranged.

[0074] By connecting the source S and drain D of the NMOS transistor of the switch transistor SWT to a voltage line such as the ground line VSS, which has a fixed potential, without leaving them open, the potentials of the source S and drain D of the NMOS transistor can be stabilized. This makes it possible to suppress fluctuations in the characteristics of the NMOS transistor due to noise, for example. It also makes it possible to suppress charge / discharge currents (leak currents) in the source and drain regions.

[0075] By forming the switch transistors SWT on both the bottom BTM side and the top TOP side, the number of switch transistors SWT can be increased. As a result, when the layout area of ​​the power switch circuit PSW is the same, the current supply capability of the switch transistors SWT can be improved. Note that the configuration in which the switch transistors SWT are formed on both the bottom BTM side and the top TOP side may be applied to other embodiments (including modified examples).

[0076] Second Embodiment Figure 20 shows an example of a circuit layout of the BSM1 layer and the BSM2 layer in the region where the power switch circuit PSW of the semiconductor device of the second embodiment is formed. Detailed description of the same elements as in Figure 5 will be omitted. For example, the power switch circuit PSW shown in Figure 20 is mounted in the standard cell block SCB of the semiconductor device 100, similar to Figure 1. The cross-sectional structure of the semiconductor device 100 on which the power switch circuit PSW of Figure 20 is mounted is similar to that of Figure 2. The circuit arranged in the standard cell block SCB is similar to that of Figure 3.

[0077] 20, the wiring in the BSM1 layer is spaced apart in the Y direction and extends in the X direction. The wiring in the BSM2 layer is spaced apart in the X direction and extends in the Y direction. That is, in FIG. 20, the arrangement directions of the wiring in the BSM1 layer and the wiring in the BSM2 layer are reversed from those in FIG. 5. Also, in FIG. 20, the buffer circuit BUF is arranged in the lower right region of FIG. 20, and the switch transistor SWT is arranged in a region where the buffer circuit BUF is not formed.

[0078] Fig. 21 shows an example of a circuit layout on the bottom BTM side in the region where the power switch circuit PSW in Fig. 20 is formed. In this embodiment, the arrangement direction (Y direction) of the power supply line TVDD, virtual power supply line VVDD, and control signal line PSWsig in the BSM1 layer is the same as the extension direction (Y direction) of the nanosheet NS of the CFET formed in the power switch circuit PSW.

[0079] This allows the arrangement direction of the CFET sources S and the arrangement direction of the CFET drains D to be the same as the arrangement direction of the wiring in the BSM1 layer. Therefore, the CFET sources S and drains D can be directly connected to vias (BSM1-BTM) that are connected to the power supply line TVDD and the virtual power supply line VVDD in the BSM1 layer, respectively. As a result, the power supply line TVDD and the virtual power supply line VVDD can be easily connected from the bottom of the substrate SUB to not only the CFET gates GT but also the CFET sources S and drains D, respectively.

[0080] The ground line VSS of the BSM1 layer is arranged along the X direction in the region of the buffer circuit BUF, and is connected to the top wiring TOPW (FIG. 22) through a via VIA (BSM1-TOP).

[0081] 22 shows an example of a circuit layout on the TOP side in the region where the power switch circuit PSW of FIG. 20 is formed. The circuit layout on the TOP side is the same as that of FIG. 7 except for the position where the buffer circuit BUF is arranged, and the semiconductor layer Ndiff and gate of the power switch circuit PSW are set to an open state. Note that the semiconductor layer Ndiff may be connected to the ground line VSS as in FIG. 14.

[0082] Fig. 23 shows an example of a cross section taken along line X3-X3' in Fig. 20 to Fig. 22. Fig. 24 shows an example of a cross section taken along line X4-X4' in Fig. 20 to Fig. 22. Fig. 25 shows an example of a cross section taken along line X5-X5' in Fig. 20 to Fig. 22. Fig. 26 shows an example of a cross section taken along line Y3-Y3' in Fig. 20 to Fig. 22.

[0083] In this embodiment, the source S of the PMOS transistor of the switch transistor SWT can be directly connected to a via VIA (DGC) connected to the power supply line TVDD in the BSM1 layer, as shown in Figures 23 and 26. The drain D of the PMOS transistor of the switch transistor SWT can be directly connected to a via VIA (DGC) connected to the virtual power supply line VVDD in the BSM1 layer, as shown in Figures 25 and 26.

[0084] 24 and 26, the gate GT of the switch transistor SWT can be directly connected to the via VIA (DGC) connected to the signal line PSWsig in the BSM1 layer. As shown in Fig. 24, the gate GT of the inverter INV1 in the buffer circuit BUF can be directly connected to the via VIA (DGC) connected to the input signal line BUFin in the BSM1 layer. As shown in Fig. 24 and 26, the gate GT of the inverter INV2 in the buffer circuit BUF can be directly connected to the via VIA (DGC) connected to the control signal line PSWsig in the BSM1 layer.

[0085] As described above, in the second embodiment, as in the first embodiment, the power switch circuit PSW can be appropriately arranged when there is a via VIA (DGC) that directly connects from the back surface of the semiconductor substrate SUB to the gate GT on the front surface of the semiconductor substrate SUB.

[0086] Furthermore, in the second embodiment, the arrangement direction (Y direction) of the power supply line TVDD, virtual power supply line VVDD, ground line VSS, input signal line BUFin, and control signal PSWsig in the BSM1 layer is set to be the same as the extension direction of the nanosheet NS, thereby allowing the arrangement direction (Y direction) of the source S, gate GT, and drain D of the CFET to be aligned with the arrangement direction of the wiring in the BSM1 layer.

[0087] Therefore, the source S and drain D of the CFET can be directly connected to the via VIA (BSM1-BTM) which is connected to the power supply line TVDD, virtual power supply line VVDD, and control signal line PSWsig of the BSM1 layer, respectively. Also, the gate DT of the CFET can be directly connected to the via VIA (DGC) which is connected to the control signal PSWsig and input signal line BUFin of the BSM1 layer, respectively. As a result, the power supply line TVDD, virtual power supply line VVDD, and control signal line PSWsig can be easily connected from the bottom of the substrate SUB to not only the gate GT of the CFET but also the source S and drain D of the CFET.

[0088] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0089] 100 Semiconductor device BPR Buried wiring BSM1, BSM2 Wiring layer BTMW Bottom wiring BUF Buffer circuit BUFin Input signal BUFout Output signal CNTL Control circuit D Drain FSM1 Wiring layer FSMW Wiring GT Gate INTR Internal circuit area INV1, INV2 Inverter IOC, IOCP I / O cell Ndiff Semiconductor layer NM NMOS transistor NS Nanosheet Pdiff Semiconductor layer PSW Power switch circuit PSWsig Control signal line S Source SC Standard cell SCB Standard cell block SCsig Control signal SGNL Signal SUB Substrate SWT Switch transistor TOPW Top wiring TVDD Power line VIA Via VSS Ground line VVDD Virtual power line W1, W2, W3 Wiring WL1, WL2 Wiring layer

Claims

1. A substrate; a first semiconductor layer and a second semiconductor layer formed on a first surface of the substrate; a first nanosheet connecting the first semiconductor layer and the second semiconductor layer; a first gate electrode covering the first nanosheet; a first transistor having the first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode; a first power supply line electrically connecting to the first semiconductor layer, a second power supply line electrically connecting to the second semiconductor layer, a third power supply line, and a first signal line arranged to overlap the first gate electrode in a planar view, which are formed on a second surface of the substrate opposite to the first surface; a first via formed in the substrate, connecting the first gate electrode and the first signal line, and arranged to overlap the first gate electrode and the first signal line in a planar view; a third semiconductor layer and a fourth semiconductor layer formed on the first surface; a fifth semiconductor layer arranged to overlap the third semiconductor layer in a planar view; a sixth semiconductor layer arranged to overlap the fourth semiconductor layer in a planar view; a second nanosheet connecting the third semiconductor layer and the fourth semiconductor layer; a third nanosheet connecting the fifth semiconductor layer and the sixth semiconductor layer; a second gate electrode covering the second nanosheet and the third nanosheet; a second transistor having the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the second gate electrode; and a third transistor having the fifth semiconductor layer, the sixth semiconductor layer, the third nanosheet, and the second gate electrode, wherein one of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the first power supply line, and one of the fifth semiconductor layer and the sixth semiconductor layer is electrically connected to the third power supply line, The other of the third semiconductor layer and the fourth semiconductor layer and the other of the fifth semiconductor layer and the sixth semiconductor layer are electrically connected to the first signal line.

2. The semiconductor device according to claim 1, further comprising: a second signal line formed on the second surface and arranged to overlap the second gate electrode in a planar view; and a second via formed in the substrate, connecting the second gate electrode and the second signal line, and arranged to overlap the second signal line and the second gate electrode in a planar view.

3. The semiconductor device according to claim 2, further comprising a third via formed on the substrate and arranged at a position where the other of the third semiconductor layer and the fourth semiconductor layer, or the other of the fifth semiconductor layer and the sixth semiconductor layer, overlaps with the first signal line in a planar view, and connecting the other of the third semiconductor layer and the fourth semiconductor layer, or the other of the fifth semiconductor layer and the sixth semiconductor layer, to the first signal line.

4. The semiconductor device according to claim 1, wherein one or both of the first power supply line and the second power supply line are arranged offset from the first transistor and the second transistor in a plan view.

5. The semiconductor device according to claim 4, wherein the first semiconductor layer and the second semiconductor layer of the first transistor are arranged side by side in a first direction, the third semiconductor layer and the fourth semiconductor layer of the second transistor are arranged side by side in the first direction, the first nanosheet of the first transistor and the second nanosheet of the second transistor extend in the first direction, the first signal line extends in the first direction and is arranged to overlap the first transistor and the second transistor in a planar view, and the first power supply line and the second power supply line extend in the first direction.

6. The semiconductor device according to claim 1, wherein the third semiconductor layer and the fourth semiconductor layer of the second transistor are arranged side by side in a first direction, the fifth semiconductor layer and the sixth semiconductor layer of the third transistor are arranged side by side in the first direction, and the first power supply line, the second power supply line, the third power supply line, and the first signal line extend in a second direction different from the first direction.

7. A semiconductor device according to any one of claims 1 to 6, comprising: a seventh semiconductor layer arranged to overlap the first semiconductor layer in a planar view; an eighth semiconductor layer arranged to overlap the second semiconductor layer in a planar view; and a fourth nanosheet arranged to overlap the first nanosheet in a planar view.

8. The semiconductor device according to claim 7, wherein the seventh semiconductor layer and the eighth semiconductor layer are set in a floating state or are electrically connected to a voltage line having a fixed potential.

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