Multilayer electronic component

Abstract

The present invention provides a multilayer electronic component in which reliability of wire bonding performed to an external electrode is improved. This multilayer electronic component 1 comprises: a multilayer body 2 that has a first surface F1 and a second surface F2, which are opposite to each other in the stacking direction T, a third surface F3 and a fourth surface F4, which are opposite to each other in a first direction L that intersects with the stacking direction T, and a fifth surface 5F and a sixth surface 6F, which are opposite to each other in a second direction W that intersects with the stacking direction T and the first direction L; and external electrodes 3 that are respectively disposed on the third surface F3 and the fourth surface F4 of the multilayer body 2. The external electrodes 3 each have a base electrode layer 3a and a plating layer 3b, and the glossiness of the outermost surface of the plating layer 3b is 63% or more.

Description

Multilayer electronic components

[0001] The present invention relates to a multilayer electronic component.

[0002] Multilayer electronic components are often mounted on a substrate using solder or the like. However, multilayer electronic components may be adversely affected by flux contained in the solder. For this reason, multilayer electronic components are sometimes mounted by wire bonding (see, for example, Patent Document 1).

[0003] Japanese Utility Model Application Laid-Open Publication No. 5-4451

[0004] However, when the external electrodes of a multilayer electronic component are formed using a conductive paste by a dipping method, the surface tension of the conductive paste tends to make the centers of the external electrodes rounded, which reduces the contact area between the tip of the capillary used for wire bonding and the surface of the external electrodes, making it difficult to ensure good connectivity between the external electrodes and the wires.

[0005] Furthermore, when the conductive paste is sintered, the surface of the external electrode may become wavy due to the influence of glass components contained in the conductive paste, which may result in poor connectivity between the wire and the external electrode even during ultrasonic treatment during wire bonding.

[0006] Furthermore, when performing wire bonding, it is first necessary to perform image processing to identify the positions of the external electrodes of the multilayer electronic component. However, if the positions of the external electrodes of the multilayer electronic component cannot be identified in the image processing process, wire bonding cannot be performed.

[0007] An object of the present invention is to provide a multilayer electronic component in which the reliability of wire bonding to external electrodes is improved.

[0008] In order to solve the above-described problems, one aspect of the present invention provides a multilayer electronic component comprising: a laminate having first and second surfaces that face each other in a stacking direction, third and fourth surfaces that face each other in a first direction that intersects with the stacking direction, and fifth and sixth surfaces that face each other in a second direction that intersects with the stacking direction and the first direction; and external electrodes that are arranged on the third and fourth surfaces of the laminate, respectively, wherein the external electrodes have a base electrode layer and a plating layer, and the gloss of an outermost surface of the plating layer is 63% or higher.

[0009] In order to solve the above-mentioned problems, another aspect of the present invention provides a multilayer electronic component comprising: a laminate having first and second surfaces that face each other in a stacking direction, third and fourth surfaces that face each other in a first direction that intersects with the stacking direction, and fifth and sixth surfaces that face each other in a second direction that intersects with the stacking direction and the first direction; and external electrodes arranged on the third and fourth surfaces of the laminate, respectively, wherein the external electrodes have a base electrode layer and a plating layer, and the linearity of the base electrode layer is 1.21 or less.

[0010] According to the present invention, it is possible to provide a multilayer electronic component in which the reliability of wire bonding to external electrodes is improved during wire bonding.

[0011] 1 is a schematic perspective view of a multilayer ceramic capacitor 1. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 of FIG. 1 , and is a diagram showing a state in which the capacitor is mounted on a substrate 100 and wire-bonded. FIG. 3 is an enlarged view illustrating the linearity of a portion of the base electrode layer 3 a in FIG. 2. FIG. 4 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1. FIG. 5 is a diagram illustrating a wire-bonding method. FIG. 6 is a table showing evaluation results 1 for image recognition of the multilayer ceramic capacitor 1. FIG. 7 is a table showing evaluation results 2 for evaluating connectivity between wires and external electrodes in the multilayer ceramic capacitor 1. FIG. 8 is a diagram showing a state in which a multilayer ceramic capacitor 1A of another embodiment according to the present invention is mounted on a substrate 100.

[0012] A multilayer ceramic capacitor 1 will now be described as one embodiment of the multilayer electronic component of the present invention. Fig. 1 is a schematic perspective view of the multilayer ceramic capacitor 1. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II in Fig. 1, and also shows the state in which the multilayer ceramic capacitor 1 has been mounted on a substrate 100 and wire-bonded.

[0013] (Multilayer Ceramic Capacitor 1) The multilayer ceramic capacitor 1 includes a laminate 2 and a pair of external electrodes 3 provided on each of two opposing surfaces of the laminate 2, that is, a third surface F3 and a fourth surface F4.

[0014] In the following description, the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked will be referred to as the stacking direction T, which is a term used to describe the orientation of the multilayer ceramic capacitor 1. In the multilayer ceramic capacitor 1, the direction in which the pair of external electrodes 3 is provided and which intersects with the stacking direction T will be referred to as the first direction L. The direction which intersects with both the first direction L and the stacking direction T will be referred to as the second direction W. In the embodiment, the stacking direction T, the first direction L, and the second direction W are perpendicular to one another.

[0015] The multilayer ceramic capacitor 1 of the embodiment has a dimension longer in the stacking direction T than in the first direction L. The second external electrode 32 on the fourth face F4 side of the multilayer ceramic capacitor 1 is attached to a first land 101 provided on one surface of the substrate 100 via solder 102, as shown in FIG.

[0016] (Laminate 2) The laminate 2 has an inner layer portion 11 and two outer layer portions 12 arranged so as to sandwich the inner layer portion 11 from both sides in the stacking direction T. The inner layer portion 11 includes a plurality of pairs of dielectric layers 14 and internal electrode layers 15.

[0017] 1 , a pair of outer surfaces facing each other in the stacking direction T will be referred to as a first surface F1 and a second surface F2, a pair of outer surfaces facing each other in the first direction L will be referred to as a third surface F3 and a fourth surface F4, and a pair of outer surfaces facing each other in the second direction W will be referred to as a fifth surface F5 and a sixth surface F6. Note that the surface of the laminate 2 may be roughened.

[0018] The intersection of two of the first face F1, second face F2, third face F3, fourth face F4, fifth face F5, and sixth face F6 is called a ridge, and the intersection of three of these faces is called a corner. The ridges and corners are preferably rounded, as this helps prevent chipping and cracking. When the ridges and corners are rounded, the surfaces excluding the corners and ridges may be flat.

[0019] (Inner layer portion 11) The inner layer portion 11 has a first internal electrode layer 151 having one end exposed on the third face F3, a second internal electrode layer 152 having one end exposed on the fourth face F4, and a dielectric layer 14 stacked alternately with the first internal electrode layer 151 and the second internal electrode layer 152.

[0020] The dielectric layer 14 has a first region covering one end of the first internal electrode layer 151 and the second internal electrode layer 152 in the first direction L that is not exposed on the third face F3 or the fourth face F4, and a second region covering at least a part of one surface of the first internal electrode layer 151 and the second internal electrode layer 152 in the stacking direction T. In other words, the first region means the area between the first internal electrode layer 151 and the fourth face F4 and the area between the second internal electrode layer 152 and the third face F3. The second region covers at least a part of the surface of the first internal electrode layer 151 and the second internal electrode layer 152 on the first face F1 side.

[0021] It is preferable that the dielectric component most abundant in the first region and the dielectric component most abundant in the second region are the same type. The dielectric component may be, for example, but is not limited to, Ba, Ti, Ca, Zr, Sr, etc. For example, CaTiO ３ and CaZrO ３ When a large amount of SrTiO is contained, it is possible to make it difficult for a dielectric breakdown to occur between the end of the first internal electrode layer 151 in the first direction L and the second external electrode 32, and between the first internal electrode layer 151 and the second internal electrode layer 152. ３ etc. can also be used as the main component.

[0022] The second region is made of a material with a high dielectric constant, such as BaTiO ３ It is preferable that the insulating film is formed of the following material.

[0023] The internal electrode layer 15 has a facing region where the first internal electrode layer 151 and the second internal electrode layer 152 face each other, and a leading region that is led out from the facing region onto the third face F3 and the fourth face F4. The internal electrode layer 15 may have a width that varies toward one end of the exposed internal electrode.

[0024] The components of the first internal electrode layer 151 and the second internal electrode layer 152 can be, but are not limited to, metals such as Ni, Cu, Ag, Pd, Au, and Sn, or alloys containing at least one of these metals, such as Ag-Pd alloys. Furthermore, by including Sn in the first internal electrode layer 151 and the second internal electrode layer 152, electric field concentration at the interface can be alleviated, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is included in only one of the internal electrode layers 15, the first internal electrode layer 151 or the second internal electrode layer 152.

[0025] When the regions between the first internal electrode layer 151 and the fifth face F5 and between the second internal electrode layer 152 and the fifth face F5 are defined as fifth surface side regions, and the regions between the first internal electrode layer 151 and the sixth face F6 and between the second internal electrode layer 152 and the sixth face F6 are defined as sixth surface side regions, there may be segregation of Si in the fifth surface side region and the sixth surface side region present on both sides of these internal electrode layers 15 in the second direction W. This can improve the flexural strength of the multilayer ceramic capacitor 1.

[0026] (Outer Layer Portion 12) The outer layer portion 12 includes a first outer layer portion 121 and a second outer layer portion 122. The first outer layer portion 121 and the second outer layer portion 122 are each formed of an insulating material. When the outer layer portion 12 is formed of the same type of dielectric material as the first and second regions of the dielectric layer 14, each outer layer portion 12 may be formed of multiple outer dielectric layers or a single outer dielectric layer. The dielectric layer 14 and the outer layer portion 12 may be formed of different components. For example, the dielectric layer 14 may have a higher dielectric constant than the outer layer portion 12, and the outer layer portion 12 may be formed of a component with good moisture resistance, weather resistance, and strength resistance. Alternatively, the outer layer portion 12 may be formed of a DLC film or a different insulating material such as an insulating resin.

[0027] (External electrode 3) The external electrode 3 has a first external electrode 31 arranged on the third face F3 and a second external electrode 32 arranged on the fourth face F4. The external electrode 3 is preferably arranged so as to extend around the first face F1, the second face F2, the fifth face F5, and the sixth face F6. The first external electrode 31 and the second external electrode 32 each have a base electrode layer 3a and a plating layer 3b.

[0028] (Base electrode layer 3a) In this embodiment 1, the base electrode layer 3a contains a metal component and a glass component. The base electrode layer 3a preferably contains Cu as its main component. However, the base electrode layer 3a may contain a metal component other than Cu and a glass component. Examples of the glass component include oxides of Ba, Sr, Si, Ca, Zn, Al, or B. Examples of other metal components include Mg, Cr, Sr, Al, Na, and Fe.

[0029] As a first modification, the base electrode layer 3a may contain a metal component and the same type of dielectric component as the dielectric layer 14. This allows the laminate 2 and the base electrode layer 3a to be formed by simultaneous firing, thereby improving the connectivity between the internal electrodes and the base electrode layer 3a.

[0030] As a second modification, the base electrode layer 3a may contain a conductive component and a resin component, whereby the stress relaxation effect of the resin can suppress the occurrence of cracks.

[0031] As a third modification, the base electrode layer 3 a may be formed of a plating layer containing 99% or more by volume of a metal component. In this case, the plating layer is directly connected to the internal electrode 3 .

[0032] (Linearity) The linearity of the base electrode layer 3a disposed on the third face F3 and the fourth face F4 is preferably 1.21 or less, and more preferably 1.11 or less. The linearity is defined as follows. FIG. 3 is an enlarged view of the base electrode layer 3a in FIG. 2 to explain the linearity (the plating layer 3b is not shown). When the linear distance between two points P and Q on the surface of the base electrode layer 3a in the cross section shown in FIG. 3 is T1, and the distance between the same two points along the shape of the surface of the base electrode layer 3a is T2, the linearity is defined as T2 / T1. A high linearity indicates a high degree of unevenness on the surface of the base electrode layer 3a, while a low linearity indicates a low degree of unevenness on the surface of the base electrode layer 3a.

[0033] Specifically, the linearity is determined as follows: (1) The multilayer ceramic capacitor 1 is polished in the second direction W, for example, from the fifth face F5 side toward the sixth face F6 side, to positions 2 / 5, 3 / 5, and 4 / 5 of W0. W0 is the dimension of the multilayer ceramic capacitor 1 in the second direction. Then, images of the outermost surface of the base electrode layer 3a in a cross section in the first direction L × stacking direction T are taken at each of the three positions, 2 / 5, 3 / 5, and 4 / 5 of W0. The images are taken, for example, with a scanning electron microscope (SEM) at a magnification of 10,000 times.

[0034] (2) From the SEM image of the captured top surface of the base electrode layer 3a, the length of the top surface of the base electrode layer 3a is calculated by "perimeter length" - "average vertical chord length" x 2 - "image width".

[0035] (3) The linearity of the base electrode layer 3a is defined as "the length of the outermost surface of the base electrode layer 3a" / "image width."

[0036] (4) The average value of the linearity of the base electrode layer 3a in the three regions of 2 / 5, 3 / 5, and 4 / 5 of W0 is defined as the linearity of the base electrode layer 3a.

[0037] As described above, the linearity of the base electrode layer 3a disposed on the third face F3 and the fourth face F4 is preferably 1.21 or less, and more preferably 1.11 or less. When the linearity of the base electrode layer 3a is 1.21 or less, the linearity of the outermost surface of the external electrode 3 is good (small) even after the plating layer 3b is formed thereon. Therefore, when wire bonding is performed to the external electrode 3, the connectivity between the wire 202 and the external electrode 3 can be improved.

[0038] (Plating Layer 3b) In the embodiment, the plating layer 3b disposed outside the base electrode layer 3a preferably has at least two layers, with an Au plating layer 3b2 on the outermost surface. In the embodiment, for example, the plating layer 3b includes, from the base electrode layer 3a side, a Ni plating layer 3b1 and an Au plating layer 3b2. However, this is not limited thereto, and the plating layer 3b may have a three-layer structure, in which case, for example, from the base electrode layer 3a side, the plating layer 3b may include a Ni plating layer, a Sn plating layer, and an Au plating layer. The Ni plating layer 3b1 can prevent the base electrode layer 3a from being eroded by solder, and having the Au plating layer 3b2 on the outermost surface can improve Au wire bonding properties.

[0039] However, the type of plating layer 3b is not limited to this and may be other types. In the case of other types, it is preferable that the plating layer 3b contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing such a metal. It is preferable that the plating layer 3b does not contain glass. The metal ratio per unit volume of the plating layer 3b is preferably 99 volume % or more.

[0040] (Glossiness) In this embodiment, the glossiness of the outermost surface of the plating layer 3b is 63% or more, and more preferably 71% or more. The glossiness is defined as follows: (1) An image of the entire outermost surface of the plating layer 3b is captured from a first direction L, for example, using a VHX-1000 camera manufactured by Keyence Corporation. (2) The entire image of the outermost surface of the plating layer 3b is then binarized, for example, into black and white using ImageJ (trademark). Based on the obtained binarized values, the glossiness is defined as {(white area) / (total area)}×100(%). (3) For example, when the brightness range of the captured image is 0 to N, a threshold value of N / 2 is used to determine whether a value equal to or greater than N / 2 is white, and a value less than N / 2 is black. As an example, when the brightness range of the captured image is 0 to 255, a threshold value of 128 is used to determine whether a value equal to or greater than 128 is white, and a value less than 128 is black. At this time, the light intensity (%) of the illumination method is measured with Keyence VHX-1000 coaxial incident light at 100% and ring illumination at 0%.

[0041] (Method of Manufacturing the Multilayer Ceramic Capacitor 1) Next, a method of manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. FIG.

[0042] (Laminated block manufacturing process S1) A dielectric sheet for the dielectric layer 14 and a conductive paste for the internal electrode layer 15 are prepared. The dielectric sheet and the conductive paste for the internal electrode layer 15 contain a binder and a solvent. The binder and the solvent may be known.

[0043] On the dielectric sheet, a conductive paste for the internal electrode layer 15 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 151 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 152 is formed are prepared.

[0044] A predetermined number of dielectric sheets on which no pattern of the internal electrode layers is printed are stacked to form a portion that will become the first outer layer portion 121 on the first surface F1 side. A dielectric sheet on which the pattern of the first internal electrode layer 151 is printed and a dielectric sheet on which the pattern of the second internal electrode layer 152 is printed are stacked in that order on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layers is not printed are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second outer layer portion 122 on the second surface F2 side. In this way, a laminated sheet is produced. The produced laminated sheet is then pressed in the stacking direction T by means of a hydrostatic press or the like to produce a laminated block.

[0045] (Laminated Block Cutting Step S2) The laminated block is cut into laminated chips of a predetermined size. At this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0046] (Firing step S3) The laminated chip is fired to produce the laminate 2. The firing temperature is preferably 900° C. or higher and 1400° C. or lower, depending on the materials of the dielectric layers 14 and the internal electrode layers 15. Note that firing may not be performed at this stage, and the laminated chip may be fired together with the base electrode layers 3 a in the base electrode forming step S4 described below.

[0047] (Base electrode formation step S4) A conductive paste to form the base electrode layer 3 a is applied to the third surface F3 side and the fourth surface F4 side of the laminate 2. In this embodiment, a conductive paste containing a glass component and a metal is applied by a method such as dipping.

[0048] Thereafter, a baking process is performed to form the base electrode layer 3a. The baking temperature at this time is preferably 700°C or higher and 900°C or lower. When the conductive paste is sintered in this baking process, the surface shape of the base electrode layer 3a may become wavy due to the influence of glass components contained in the conductive paste. If the surface shape of the base electrode layer 3a becomes wavy, this will also affect the surface shape of the outermost surface of the external electrode 3, causing the outermost surface of the external electrode 3 to also become wavy. As a result, when ultrasonic treatment is performed to insert the wire during wire bonding, as described below, there is a possibility that good connectivity between the wire and the external electrode cannot be ensured.

[0049] Therefore, first, the linearity of the base electrode layer 3a is improved. Linearity can be improved, for example, by using a barrel method or by impacting the surface with zirconia or other balls. When impacting the surface with balls, if the diameter of the balls is too large, some areas of the top surface of the base electrode layer 3a will not be impacted by the balls. Furthermore, if the impact speed of the balls is too fast or strong, some areas of the base electrode layer 3a will be chipped. Therefore, the diameter of the balls and the impact speed are appropriately adjusted to suit the improvement of linearity.

[0050] It is also possible to improve the linearity of the base electrode layer 3 a after forming the plating layer 3 b, as described below, without improving the linearity of the base electrode layer 3 a at this stage. If the above treatment is performed after forming the base electrode layer 3 a, the treatment time after the plating layer formation step described below can be shortened.

[0051] (Plating Layer Forming Step S5) In this embodiment, the plating layer 3b includes, in order from the base electrode layer 3a side, a Ni plating layer 3b1 and an Au plating layer 3b2. The Ni plating layer 3b1 and the Au plating layer 3b2 are formed by electrolytic plating using, for example, a barrel plating method.

[0052] After the formation of the Au plating layer 3b2, similar to the method for improving the linearity of the base electrode layer 3a described above, the linearity and gloss of the Au plating layer 3b2 on the outermost surface of the external electrode 3 can be improved by, for example, using a barreling method or impacting the surface with zirconia or other boulders. When impacting the surface with boulders, if the diameter of the boulders is too large, some areas of the outermost surface of the Au plating layer 3b2 will not be impacted by the boulders. Furthermore, if the impact speed of the boulders is too fast or too fast, some areas of the Au plating layer 3b2 will be chipped. Therefore, the diameter of the boulders and the impact speed are appropriately adjusted to improve linearity. Furthermore, although the linearity of the base electrode layer 3a was improved in this case, even if the linearity and gloss of the outermost surface of the plating layer are low, the gloss of the Au plating layer 3b2, which is the outermost surface of the plating layer, can be increased to 63% or higher by performing the above-described process.

[0053] By the above manufacturing method, a multilayer ceramic capacitor 1 is manufactured in which the gloss of the Au plating layer 3b2, which is the outermost surface of the plating layer, is 63% or more and the linearity of the base electrode layer 3a is 1.21 or less.

[0054] (Wire Bonding Process) In the multilayer ceramic capacitor 1 of the embodiment manufactured in this manner, for example, the second external electrode 32 on the fourth face F4 side is bonded to a first land 101 provided on one surface of the substrate 100 via solder 102, as shown in FIG.

[0055] One end of a wire 202 is connected to the first external electrode 31 on the third face F3 side of the multilayer ceramic capacitor 1. The other end of the wire 202 is connected to, for example, a second land 103 on the substrate 100 other than the first land 101 to which the multilayer ceramic capacitor 1 is joined.

[0056] 5 is a diagram illustrating the wire bonding method. Wire bonding is performed using a bonding device (only the capillary 200 portion is shown, the entire device is not shown) equipped with a capillary 200 having an inner hole 201. A wire 202 is inserted into the inner hole 201 of the capillary 200, and the wire 202 can be fed out from the tip of the capillary 200.

[0057] In this embodiment, the wires 202 are made of gold, and the outermost surfaces of the external electrodes 3 of the multilayer ceramic capacitor 1 are Au plated layers 3b2, so that the bonding between the wires 202 and the external electrodes 3 is good.

[0058] The bonding device first detects the position of the external electrode 3 of the multilayer ceramic capacitor 1 using an image processing mechanism, and then moves the capillary 200 onto the external electrode 3 of the multilayer ceramic capacitor 1 using a movement mechanism.

[0059] When detecting the positions of the external electrodes 3 of the multilayer ceramic capacitor 1 using an image processing mechanism, first, light is irradiated onto the entire substrate 100 on which the multilayer ceramic capacitor 1 is mounted, and the positions of the external electrodes 3 of the multilayer ceramic capacitor 1 are image-recognized based on the light reflected from the external electrodes 3.

[0060] At this time, if the glossiness of the outermost surface of the external electrodes 3 of the multilayer ceramic capacitor 1 is low, the amount of reflected light becomes insufficient, resulting in poor image recognition, making it impossible to detect the positions of the external electrodes 3 and thus making it impossible to perform accurate wire bonding.

[0061] However, in this embodiment, the glossiness of the plating layer 3b on the outermost surface of the external electrode 3 is 63% or more. Therefore, the external electrode 3 can be clearly recognized from the captured image, the possibility of erroneous detection of the position of the external electrode 3 is low, and the tip of the capillary 200 can be accurately moved to the position of the external electrode 3.

[0062] Next, the capillary 200 is moved above the external electrode 3, and the tip of the wire 202 is melted by discharge or the like to form a ball. Then, the capillary 200 is moved downward, and the ball at the tip of the wire 202 is crimped onto the external electrode 3 of the multilayer ceramic capacitor 1 as shown in Figure 5(a), and one end of the wire 202 is connected to the external electrode 3 of the multilayer ceramic capacitor 1 by applying ultrasonic waves or the like.

[0063] At this time, if the outermost surface of the external electrode 3 has many irregularities or is curved, the bonding strength between the wire 202 and the external electrode 3 will be poor. However, in the external electrode 3 of this embodiment, the linearity of the base electrode layer 3a is 1.21 or less. Therefore, even after the plating layer 3b is formed thereon, the linearity of the outermost surface of the external electrode 3 is low. In other words, the outermost surface of the external electrode 3 has few irregularities, is not curved, and even if it is curved, the degree of curvature is small. Therefore, the wire 202 and the external electrode 3 are bonded well.

[0064] After connecting one end of the wire 202 to the external electrode 3 of the multilayer ceramic capacitor 1, the wire 202 is fed out of the inner hole 201 of the capillary 200 and moved to the second land 103, as shown in Figure 5(b), and the wire 202 is pressed against the second land 103 and bonded while applying ultrasonic vibration, and then the wire 202 is cut. This connects the external electrode 3 of the multilayer ceramic capacitor 1 to the second land 103 on the substrate 100 side.

[0065] <Evaluation Result 1> Next, evaluation result 1 for the image recognition ability of the multilayer ceramic capacitor 1 of the embodiment will be described. 100 multilayer ceramic capacitors each having an Au plating layer on the outermost surface of the external electrode, with the gloss of the Au plating layer being 39%, 50%, 63%, 71%, or 79%, were prepared. The dimensions of the multilayer ceramic capacitors were the same as follows: Dimension in the first direction L: 0.4 mm Dimension in the second direction W: 0.2 mm Dimension in the stacking direction T: 0.2 mm

[0066] Of these multilayer ceramic capacitors, the multilayer ceramic capacitors having an Au plating layer gloss of 63%, 71%, or 79% are multilayer ceramic capacitors 1 of the embodiment, and the multilayer ceramic capacitors having an Au plating layer gloss of 39% or 50% are comparative examples.

[0067] The chip recognition rate and the number of recognition failures were examined in an actual bonding device for the multilayer ceramic capacitors of the comparative example and the embodiment, each having a different gloss level of 100.

[0068] FIG. 6 is a table showing evaluation results 1 for the image recognizability of the multilayer ceramic capacitor 1. As shown in FIG. 6, in the case of the comparative multilayer ceramic capacitor having a glossiness of 39%, which is less than 63%, the recognition failure rate was 3 / 100. In addition, in the case of the comparative multilayer ceramic capacitor having a glossiness of 50%, which is less than 63%, the recognition failure rate was 1 / 100. In contrast, in the case of the multilayer ceramic capacitor 1 of the embodiment having a glossiness of 63% or more, i.e., 63%, 71%, or 79%, the recognition failure rate was 0 / 100, and all of the multilayer ceramic capacitors could be recognized. From the above, it can be seen that the multilayer ceramic capacitor 1 of the embodiment has high image recognizability in a bonding device.

[0069] <Evaluation Result 2> Next, evaluation result 2, which evaluated the connectivity between the wires and the external electrodes in the multilayer ceramic capacitor 1 of the embodiment, will be described. As in evaluation result 1, 100 multilayer ceramic capacitors were prepared, each having an Au plating layer on the outermost surface of the external electrode, with the gloss of the Au plating layer being 39%, 50%, 63%, 71%, or 79%. The dimensions of the multilayer ceramic capacitors were the same as below. Dimension in first direction L: 0.4 mm Dimension in second direction W: 0.2 mm Dimension in stacking direction T: 0.2 mm

[0070] Of these multilayer ceramic capacitors, the multilayer ceramic capacitors having an Au plating layer gloss of 63%, 71%, or 79% are multilayer ceramic capacitors 1 of the embodiment, and the multilayer ceramic capacitors having an Au plating layer gloss of 39% or 50% are comparative examples.

[0071] Then, an Au wire was brought into contact with the center of the external electrode of each of these multilayer ceramic capacitors with a different gloss level of 100, and after performing ultrasonic treatment for 5 ms, the connectivity was evaluated based on whether or not the Au wire and the external electrode were connected.

[0072] FIG. 7 is a table showing evaluation results 2 of the evaluation of the connectivity between the wires and the external electrodes of the multilayer ceramic capacitor 1. As shown in FIG. 7, in the case of the comparative multilayer ceramic capacitor having a gloss of 39%, which is less than 63%, the connection failure rate was 15 / 100. In addition, in the case of the comparative multilayer ceramic capacitor having a gloss of 50%, which is less than 63%, the recognition failure rate was 9 / 100. In contrast, in the case of the multilayer ceramic capacitor 1 of the embodiment having a gloss of 63%, the connection failure rate was 2 / 100. In addition, in the case of the multilayer ceramic capacitor 1 of the embodiment having a gloss of 71% or 79%, the connection failure rate was 0 / 100, confirming that the multilayer ceramic capacitor was fully connected.

[0073] Furthermore, as the linearity of the base electrode layer 3a decreases, the glossiness of the Au plating layer 3b2 formed on the outermost surface increases. For example, when the linearity of the base electrode layer 3a was 1.21, the glossiness of the Au plating layer 3b2 formed on the outermost surface was 66%. When the linearity of the base electrode layer 3a was 1.11, the glossiness of the Au plating layer 3b2 formed on the outermost surface was 77%.

[0074] That is, when the linearity of the base electrode layer 3a is 1.21 or less, which is within the range of the multilayer ceramic capacitor 1 according to the embodiment, the recognition failure rate is 0 / 100 and the connection failure rate is 2 / 100 or less. When the linearity of the base electrode layer 3a is 1.11 or less, which is a more preferable range of the multilayer ceramic capacitor 1 according to the embodiment, the recognition failure rate is 0 / 100 and the connection failure rate is also 0 / 100 or less. Therefore, even when viewed from the perspective of the linearity of the base electrode layer 3a, good results were obtained in terms of recognition and connection of the multilayer ceramic capacitor 1 according to the embodiment.

[0075] (Multilayer ceramic capacitor according to another embodiment) In the above embodiment, the dimension of the multilayer ceramic capacitor 1 in the stacking direction T is longer than the first direction L and the second direction W. As shown in Fig. 2 , the multilayer ceramic capacitor 1 is joined to a first land 101 provided on one surface of the substrate 100 by, for example, solder 102, and the second external electrode 32 on the fourth surface F4 side is joined to the first land 101 via the solder 102. However, the multilayer ceramic capacitor 1 is not limited to this.

[0076] 8 is a diagram showing a state in which a multilayer ceramic capacitor 1A according to another embodiment of the present invention is mounted on a substrate 100. The dimension of the multilayer ceramic capacitor 1A in the lamination direction T may be shorter than the dimension in the first direction L in which the external electrodes 3 are formed on both ends as shown in the figure, and also shorter than the dimension in the second direction W, not shown. The external electrodes 3 of the multilayer ceramic capacitor 1A according to another embodiment extend longer around the first face F1, the second face F2, the fifth face F5, and the sixth face F6 than those of the multilayer ceramic capacitor 1 according to the above-described embodiment.

[0077] In other respects, the multilayer ceramic capacitor 1A is similar in configuration to the multilayer ceramic capacitor 1 of the above-described embodiment, and therefore a description of similar portions will be omitted. That is, the external electrodes 31 and 32 of the multilayer ceramic capacitor 1A of this other embodiment include a base electrode layer and a plating layer, and the gloss of the outermost surface of the plating layer is 63% or more, preferably 71% or more, and the linearity of the base electrode layer is 1.21 or less, preferably 1.11 or less.

[0078] The second surface F2 of the multilayer ceramic capacitor 1A of this embodiment is bonded to a first land 101 provided on one surface of the substrate 100 by, for example, epoxy resin 105. The wires 202 extend from both the external electrodes 31 and 32 that extend toward the first surface F1.

[0079] In the multilayer ceramic capacitor 1A of the other embodiments, as in the multilayer ceramic capacitor 1 of the embodiment, good results can be obtained in terms of recognition and connectivity during wire bonding.

[0080] Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and various changes and modifications can be made as follows.

[0081] <1> A multilayer electronic component comprising: a laminate having first and second surfaces opposed to each other in a stacking direction; third and fourth surfaces opposed to each other in a first direction intersecting the stacking direction; and fifth and sixth surfaces opposed to each other in a second direction intersecting the stacking direction and the first direction; and external electrodes arranged on the third and fourth surfaces of the laminate, respectively, wherein the external electrodes have a base electrode layer and a plating layer, and the gloss of an outermost surface of the plating layer is 63% or higher.

[0082] <2> The multilayer electronic component according to <1>, wherein the external electrodes are also arranged on the first surface, the second surface, the fifth surface, and the sixth surface.

[0083] <3> The multilayer electronic component according to <1> or <2>, wherein the outermost surface of the plating layer has a glossiness of 71% or more.

[0084] <4> The laminated electronic component according to any one of <1> to <3>, wherein the linearity of the underlying electrode layer is 1.21 or less.

[0085] <5> The multilayer electronic component according to any one of <1> to <4>, wherein the linearity of the underlying electrode layer is 1.11 or less.

[0086] <6> A multilayer electronic component comprising: a laminate having first and second surfaces opposed to each other in a stacking direction; third and fourth surfaces opposed to each other in a first direction intersecting the stacking direction; and fifth and sixth surfaces opposed to each other in a second direction intersecting the stacking direction and the first direction; and external electrodes arranged on the third and fourth surfaces of the laminate, respectively, wherein the external electrodes have a base electrode layer and a plating layer, and the linearity of the base electrode layer is 1.21 or less.

[0087] <7> The multilayer electronic component according to <6>, wherein the linearity of the underlying electrode layer is 1.11 or less.

[0088] <8> The multilayer electronic component according to claim 1 or claim 6, wherein the plating layer includes an Au plating layer on an outermost surface.

[0089] <9> The multilayer electronic component according to any one of <1> to <8>, wherein the base electrode layer contains a glass component and Cu.

[0090] <10> The multilayer electronic component according to any one of <1> to <9>, wherein the base electrode layer contains a dielectric component and Ni.

[0091] REFERENCE SIGNS LIST 1, 1A Multilayer ceramic capacitor 2 Laminate 3 External electrode 3a Base electrode layer 3b Plating layer 3b1 Ni plating layer 3b2 Au plating layer 11 Inner layer portion 12 Outer layer portion 14 Dielectric layer 15 Internal electrode layer 100 Substrate 101 First land 103 Second land 200 Capillary 201 Inner hole 202 Wire F1 First surface F2 Second surface F3 Third surface F4 Fourth surface F5 Fifth surface F6 Sixth surface T Stacking direction L First direction W Second direction

Claims

1. A multilayer electronic component comprising: a laminate having first and second surfaces that face each other in the stacking direction; third and fourth surfaces that face each other in a first direction that intersects with the stacking direction; and fifth and sixth surfaces that face each other in a second direction that intersects with the stacking direction and the first direction; and external electrodes arranged on the third and fourth surfaces of the laminate, respectively, wherein the external electrodes have a base electrode layer and a plating layer, and the gloss of the outermost surface of the plating layer is 63% or higher.

2. The multilayer electronic component according to claim 1, wherein the external electrodes are also disposed on the first surface, the second surface, the fifth surface, and the sixth surface.

3. The multilayer electronic component according to claim 1 or 2, wherein the gloss of the outermost surface of the plating layer is 71% or more.

4. The multilayer electronic component according to any one of claims 1 to 3, wherein the linearity of the base electrode layer is 1.21 or less.

5. A multilayer electronic component comprising: a laminate having first and second surfaces opposed to each other in a stacking direction; third and fourth surfaces opposed to each other in a first direction intersecting the stacking direction; and fifth and sixth surfaces opposed to each other in a second direction intersecting the stacking direction and the first direction; and external electrodes arranged on the third and fourth surfaces of the laminate, respectively, wherein the external electrodes have a base electrode layer and a plating layer, and the linearity of the base electrode layer is 1.21 or less.

6. The multilayer electronic component according to any one of claims 1 to 5, wherein the linearity of the base electrode layer is 1.11 or less.

7. The multilayer electronic component according to any one of claims 1 to 6, wherein the plating layer includes an Au plating layer on the outermost surface.

8. The multilayer electronic component according to any one of claims 1 to 7, wherein the base electrode layer contains a glass component and Cu.

9. The multilayer electronic component according to any one of claims 1 to 8, wherein the base electrode layer contains a dielectric component and Ni.

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