Semiconductor device

Abstract

Provided is a semiconductor device which allows for miniaturization and high integration. This semiconductor device includes: a first insulating layer; a first transistor, a second transistor, and a second insulating layer on the first insulating layer; a first capacitive element on the first transistor; a second capacitive element on the second transistor; and a third insulating layer on the first and second transistors, wherein a semiconductor layer of the first transistor and a semiconductor layer of the second transistor are provided along the side walls of an opening in the second insulating layer, one of either the source or the drain of the first transistor and one of either the source or the drain of the second transistor are provided apart from each other on the first insulating layer, respective first electrodes of the first and second capacitive elements are provided apart from each other and are provided along the side walls of an opening in the second insulating layer, and a first opening and a second opening overlap each other in a plan view.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (IC chips) such as LSIs, CPUs, or memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with large on-state current.An object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, or memory device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device or memory device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, or memory device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention includes a first insulating layer, a first transistor, a second transistor, and a second insulating layer over the first insulating layer, a first capacitor, a second capacitor, a third insulating layer, and a fourth insulating layer, in which the first capacitor is located over the first transistor and the second capacitor is located over the second transistor, the first transistor includes a first conductive layer, a first oxide semiconductor layer, a fifth insulating layer, and a second conductive layer, and the second transistor includes a third conductive layer, a second oxide semiconductor layer, a fifth insulating layer, and a fourth insulating layer. The semiconductor device includes a second conductive layer, the first conductive layer and the third conductive layer being provided on a first insulating layer and spaced apart from each other, the third insulating layer having a first region provided in contact with an upper surface of the second conductive layer, the second insulating layer having a first opening, the first opening having a region overlapping with the first conductive layer, a region overlapping with the third conductive layer, and a region located between the first conductive layer and the third conductive layer and overlapping with the first insulating layer, the first oxide semiconductor layer and the second oxide semiconductor layer having regions provided along sidewalls of the first opening, The fifth insulating layer is located on the first conductive layer and the third conductive layer, the second conductive layer is located on the fifth insulating layer, and the fifth insulating layer has a region overlapping with a sidewall of the first opening with the first oxide semiconductor layer sandwiched therebetween and a region overlapping with a sidewall of the first opening with the second oxide semiconductor layer sandwiched therebetween; the first capacitor has a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer; the second capacitor has a sixth conductive layer, a sixth insulating layer, and a fifth conductive layer; the fourth conductive layer and the sixth conductive layer are mutually disposed on the third insulating layer. The semiconductor device is provided with a fifth conductive layer that is spaced apart from the fourth conductive layer, and has a second region that overlaps with the fourth conductive layer with a sixth insulating layer sandwiched therebetween, and a third region that overlaps with the sixth conductive layer with the sixth insulating layer sandwiched therebetween, the second region being located on the fourth conductive layer, the third region being located on the sixth conductive layer, the fourth insulating layer having a second opening, the fourth conductive layer and the sixth conductive layer each having a region that is located along a sidewall of the second opening, and the first opening and the second opening having regions that overlap with each other in a planar view.

[0014] In addition, in the above structure, it is preferable that the third insulating layer has a fourth region provided in contact with a side surface of the second conductive layer, the fourth conductive layer has a region overlapping with a side surface of the second conductive layer with the fourth region of the third insulating layer sandwiched therebetween, and the sixth conductive layer has a region overlapping with a side surface of the second conductive layer with the fourth region of the third insulating layer sandwiched therebetween.

[0015] In the above structure, it is preferable that the first transistor has a seventh conductive layer over the second insulating layer, the first oxide semiconductor layer has a region in contact with a top surface of the first conductive layer and a region in contact with a top surface of the seventh conductive layer, the second transistor has an eighth conductive layer over the second insulating layer, the second oxide semiconductor layer has a region in contact with a top surface of the third conductive layer and a region in contact with a top surface of the eighth conductive layer, the fourth conductive layer has a region overlapping with the seventh conductive layer in a planar view, and the sixth conductive layer has a region overlapping with the eighth conductive layer in a planar view.

[0016] In addition, in the above structure, it is preferable that the fourth conductive layer has a region in contact with the top surface of the seventh conductive layer and a region overlapping with the side surface of the second conductive layer with the third insulating layer sandwiched therebetween, and the sixth conductive layer has a region in contact with the top surface of the eighth conductive layer and a region overlapping with the side surface of the second conductive layer with the third insulating layer sandwiched therebetween.

[0017] Furthermore, in the above structure, it is preferable that the semiconductor device has a ninth conductive layer and a tenth conductive layer, the fourth conductive layer and the seventh conductive layer are connected via the ninth conductive layer, the sixth conductive layer and the eighth conductive layer are connected via the tenth conductive layer, the ninth conductive layer has a region in contact with the top surface of the seventh conductive layer and a region overlapping with a side surface of the second conductive layer with the third insulating layer sandwiched therebetween, and the tenth conductive layer has a region in contact with the top surface of the eighth conductive layer and a region overlapping with a side surface of the second conductive layer with the third insulating layer sandwiched therebetween.

[0018] One embodiment of the present invention provides a semiconductor device including a first insulating layer, a first transistor, a second transistor, and the second insulating layer over the first insulating layer, a third insulating layer over the second insulating layer, a first capacitor over the first transistor, and a second capacitor over the second transistor, wherein the first transistor includes a first semiconductor layer, a fourth insulating layer, a first conductive layer, a second conductive layer over the first insulating layer, and a third conductive layer over the third insulating layer, and The semiconductor device has a second semiconductor layer, a fifth insulating layer, a first conductive layer, a fourth conductive layer on the first insulating layer, and a fifth conductive layer on the third insulating layer, the first conductive layer being located between the second insulating layer and the third insulating layer, the second conductive layer and the fourth conductive layer being provided on the first insulating layer at a distance from each other, the second insulating layer, the first conductive layer, and the third insulating layer each having an opening, and the opening in the second insulating layer and the opening in the first conductive layer overlap each other in a plan view. The opening in the third insulating layer and the opening in the first conductive layer overlap each other in a plan view, the first semiconductor layer faces side surfaces of the openings in the second insulating layer, the first conductive layer, and the third insulating layer with a fourth insulating layer sandwiched therebetween, the first semiconductor layer has a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer, and the second semiconductor layer faces side surfaces of the openings in the second insulating layer, the first conductive layer, and the third insulating layer with a fifth insulating layer sandwiched therebetween. the second semiconductor layer faces a side surface of the first portion, the second semiconductor layer has a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the first capacitance element has a sixth conductive layer, a seventh conductive layer, and a sixth insulating layer; the second capacitance element has an eighth conductive layer, a seventh conductive layer, and a sixth insulating layer, and the sixth insulating layer has a region located between the sixth conductive layer and the seventh conductive layer and a region located between the eighth conductive layer and the seventh conductive layer.

[0019] In addition, in the above structure, it is preferable that there is a seventh insulating layer on the first transistor and the second transistor, the seventh insulating layer has a second opening, the sixth conductive layer and the eighth conductive layer each have a region provided along a sidewall of the second opening, and the first opening and the second opening have regions that overlap each other in a planar view.

[0020] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, or memory device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, or memory device can be provided.

[0021] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0022] FIG. 1A is a plan view showing an example of a semiconductor device. FIGS. 1B and 1C are cross-sectional views showing an example of a semiconductor device. FIG. 1D is a schematic perspective view showing an example of a semiconductor device. FIG. 2A is a plan view showing an example of a semiconductor device. FIGS. 2B and 2C are cross-sectional views showing an example of a semiconductor device. FIG. 3A is a cross-sectional view showing an example of a semiconductor device. FIG. 3B is a plan view showing an example of a semiconductor device. FIG. 3C is a cross-sectional view showing an example of a semiconductor device. FIG. 4A is a plan view showing an example of a semiconductor device. FIGS. 4B and 4C are cross-sectional views showing an example of a semiconductor device. FIG. 4D is an example of a circuit diagram. FIG. 5A is a plan view showing an example of a semiconductor device. FIGS. 5B to 5E are cross-sectional views showing an example of a semiconductor device. FIG. 6A is a plan view showing an example of a semiconductor device. FIGS. 6B and 6C are cross-sectional views showing an example of a semiconductor device. FIG. 7A is a plan view showing an example of a semiconductor device. FIGS. 7B to 7E are cross-sectional views showing an example of a semiconductor device. FIG. 8A is a plan view showing an example of a semiconductor device. FIG. 8B is a cross-sectional view showing an example of a semiconductor device. FIG. 8C is an example of a circuit diagram. FIG. 9A is a cross-sectional view showing an example of a semiconductor device. FIG. 9B is a plan view showing an example of a semiconductor device. FIGS. 9C and 9D are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10D are cross-sectional views showing an example of a semiconductor device. FIGS. 11A to 11C are plan views showing an example of a semiconductor device. FIG. 12A is a plan view showing an example of a semiconductor device. FIG. 12B is a cross-sectional view showing an example of a semiconductor device. FIG. 13A is a cross-sectional view showing an example of a semiconductor device. FIG. 13B is a plan view showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIGS. 15A and 15B are cross-sectional views showing an example of a semiconductor device. FIG. 16A is a plan view showing an example of a semiconductor device. FIG. 16B is a cross-sectional view showing an example of a semiconductor device. FIG. 16C is an example of a circuit diagram. FIG. 17A is a plan view showing an example of a semiconductor device. FIG. 17B is a cross-sectional view showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a manufacturing method of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing an example of a manufacturing method of a semiconductor device. FIG. 19A is a plan view showing an example of a manufacturing method of a semiconductor device.19B and 19C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 20A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIGS. 20B and 20C are cross-sectional views illustrating an example of a manufacturing method of a semiconductor device. FIG. 21A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIG. 21B is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIG. 22 is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIG. 23A is a plan view illustrating an example of a manufacturing method of a semiconductor device. FIG. 23B is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIG. 24 is a cross-sectional view illustrating an example of a manufacturing method of a semiconductor device. FIG. 25A is a cross-sectional view illustrating an example of a semiconductor device. FIG. 25B is a plan view illustrating an example of a semiconductor device. FIGS. 26A and 26B are plan layouts illustrating an example of a memory device. FIG. 27 is a perspective view illustrating an example of a memory device. FIG. 28A is a circuit diagram illustrating an example of a memory device. FIG. 28B is a plan layout illustrating an example of a memory device. FIG. 29 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 30 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 31 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 32A to 32F are diagrams illustrating an example of a circuit configuration of a memory cell. FIGS. 33A and 33B are perspective views illustrating an example of a configuration of a semiconductor device. FIG. 34 is a block diagram illustrating a CPU. FIGS. 35A and 35B are perspective views of a semiconductor device. FIGS. 36A and 36B are perspective views of a semiconductor device. FIG. 37 is a conceptual diagram illustrating a hierarchy of a memory device. FIGS. 38A and 38B are circuit diagrams of a semiconductor device according to one embodiment of the present invention, and FIG. 38C is a diagram illustrating an example of an electronic component using a semiconductor device according to one embodiment of the present invention. FIG. 39 is a diagram illustrating an example of an electronic component. FIGS. 40A to 40C are a diagram illustrating an example of a mainframe computer. FIG. 40D is a diagram illustrating an example of space equipment. FIG. 40E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 41A to 41F are diagrams illustrating examples of electronic devices. FIGS. 42A to 42G are diagrams illustrating examples of electronic devices. FIGS. 43A to 43F are diagrams illustrating examples of electronic devices.

[0023] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0024] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0025] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0026] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0027] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0028] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0029] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0030] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0031] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0032] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0033] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0034] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0035] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0036] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0037] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0038] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0039] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0040] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0041] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0042] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0043] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0044] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0045] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0046] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0047] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0048] In the transistor of one embodiment of the present invention, a source electrode, an oxide semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0049] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thickness of the first insulating layer, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0050] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, for example, stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, large-scale integration and low power consumption of the memory device can be achieved.

[0051] In this embodiment, a structure of a semiconductor device according to one embodiment of the present invention will be described.

[0052] <Configuration Example 1 of Semiconductor Device> A semiconductor device according to one embodiment of the present invention includes a plurality of capacitors. Another embodiment of the present invention includes two capacitors arranged in the same opening. Specifically, in one embodiment of the present invention, a first insulating layer has a first opening, and first electrodes of the two capacitors are provided in the first opening. The two capacitors preferably share a second electrode. For example, a conductive layer arranged in the first opening can be used as a second electrode shared by the two capacitors.

[0053] <Configuration Example 1-1 of Semiconductor Device> Fig. 1A is a plan view of a semiconductor device having two capacitance elements. Fig. 1B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 shown in Fig. 1A. Fig. 1C is a cross-sectional view corresponding to the dashed-dotted line C3-C4 shown in Fig. 1A.

[0054] The semiconductor device shown in FIGS. 1A to 1C includes an insulating layer 210 and a capacitor element 100 a and a capacitor element 100 b on the insulating layer 210 .

[0055] The capacitor 100a has a conductive layer 115a, an insulating layer 130 on the conductive layer 115a, and a conductive layer 120 on the insulating layer 130. The capacitor 100b has a conductive layer 115b, an insulating layer 130 on the conductive layer 115b, and a conductive layer 120 on the insulating layer 130. Fig. 1D is a schematic perspective view of the capacitor 100b. Note that some components (such as insulating layers) are omitted in Fig. 1D.

[0056] The insulating layer 180 has an opening 190 that reaches the insulating layer 210 .

[0057] The conductive layer 115a has a region covering the sidewall of the insulating layer 180 in the opening 190 and a region covering the top surface of the insulating layer 210. The conductive layer 115b has a region covering the sidewall of the insulating layer 180 in the opening 190 and a region covering the top surface of the insulating layer 210.

[0058] The conductive layers 115a and 115b are each located within the opening 190 and are spaced apart from each other. The conductive layers 115a and 115b have a region along the sidewall of the insulating layer 180 of the opening 190. The conductive layers 115a and 115b have a region along the periphery of the opening. The conductive layers 115a and 115b are provided inside the periphery of the opening. When the top surface of the opening 190 has a circular shape, the top surface of the conductive layers 115a and 115b may have, for example, a circular shape with a portion removed, and may include a region along part of the periphery of the opening 190. For example, in FIG. 1A , the conductive layers 115a and 115b each have a shape with approximately half of a circle removed. Each of the conductive layers 115a and 115b can also be expressed as having a portion that is provided in an arc shape when viewed from above.

[0059] As shown in FIGS. 1A to 1C, by making the top surfaces of the conductive layers 115a and 115b line-symmetrical, the areas of the conductive layers 115a and 115b can be made approximately the same when viewed from above.

[0060] The conductive layers 115a and 115b may have different areas in a top view. Fig. 2A is a modified example of the plan view shown in Fig. 1A, in which the area of ​​the conductive layer 115a is larger than the area of ​​the conductive layer 115b. Fig. 2B is a cross-sectional view corresponding to the dashed dotted line C1-C2 shown in Fig. 2A, and Fig. 2C is a cross-sectional view corresponding to the dashed dotted line C3-C4 shown in Fig. 2A.

[0061] By reducing the difference in area between the conductive layers 115a and 115b, the variation in capacitance value between the capacitors 100a and 100b can be reduced.

[0062] The insulating layer 130 has a region sandwiched between the conductive layers 115a and 120, and this region functions as a dielectric layer of the capacitor 100a. The insulating layer 130 also has a region sandwiched between the conductive layers 115b and 120, and this region functions as a dielectric layer of the capacitor 100b. The insulating layer 130 also has a region covering the top surface of the insulating layer 180.

[0063] The conductive layer 120 is provided on the insulating layer 130. The conductive layer 120 is preferably provided so as to fill the opening 190. The conductive layer 120 also has a region that covers the upper surface of the insulating layer 180. When a plurality of openings 190 are provided in the insulating layer 180 and a capacitor element is provided in each opening 190, the conductive layer 120 may be shared. For example, by providing the conductive layer 120 so as to extend to an adjacent opening 190, a configuration can be achieved in which the conductive layer 120 is shared between the adjacent openings 190.

[0064] In FIG. 1B and other figures, the height of the upper end of conductive layer 115a and the height of the upper end of conductive layer 115b are lower than the height of the upper surface of insulating layer 180. The heights of the upper ends of conductive layer 115a, conductive layer 115b, and insulating layer 180 can be evaluated using, for example, the upper surfaces of the substrate, insulating layer, conductive layer, etc. located below insulating layer 180 as a reference. Specifically, for example, the upper surface of insulating layer 210 may be used as a reference. Alternatively, the heights of conductive layer 115a and conductive layer 115b may be evaluated using the height of the vicinity of opening 190 on the upper surface of insulating layer 180 as a reference. Furthermore, the upper ends of conductive layer 115a and conductive layer 115b each have a tapered shape with respect to the substrate surface or the upper surface of an insulating layer, etc., above the substrate. Specifically, for example, the angle formed with the upper surface of insulating layer 210 is less than 90°. The conductive layers 115a and 115b each have an upper end with rounded corners in the cross-sectional view shown in FIG. 1B and other drawings.

[0065] By forming the conductive layers 115a and 115b in this shape, it is possible to alleviate electric field concentration between the lower electrode (conductive layer 115a or conductive layer 115b) and the upper electrode (conductive layer 120) at the upper end of the conductive layer 115a and the upper end of the conductive layer 115b.

[0066] 3A, the conductive layers 115a and 115b may have a shape in which the upper ends thereof are substantially flush with the upper surface of the insulating layer 180. In addition, as shown in FIG.

[0067] Fig. 3B shows a modified example of Fig. 1A. Fig. 3C is a cross-sectional view corresponding to the dashed dotted line C1-C2 shown in Fig. 3A. Also, the cross-sectional view corresponding to the dashed dotted line C3-C4 shown in Fig. 3A is the same as Fig. 1C, so it will not be described.

[0068] 1A to 1C in that the conductive layers 115a and 115b have a region located outside the opening 190 and a region covering the top surface of the insulating layer 180. In Figures 3B and 3C, the conductive layers 115a and 115b each have a region provided inside the periphery of the opening 190 and a region provided outside the periphery. The semiconductor device shown in Figures 3B and 3C can be formed without removing the entire conductive film on the insulating layer 180, which may simplify the process.

[0069] 3B and 3C show an example in which the top surface shapes of the conductive layers 115a and 115b are rectangular, but the outer peripheries of the conductive layers 115a and 115b in plan view may be curved, for example, arc-shaped.

[0070] <Configuration Example 1-2 of Semiconductor Device> The capacitor element 100a and the capacitor element 100b can be suitably connected to the semiconductor element, wiring, electrode, and the like provided in the layer below each of them.

[0071] 4A to 4C show an example in which conductive layers 240a, 240b, etc. are provided below a layer in which capacitor elements 100a and 100b are provided. Here, Fig. 4A is a plan view of a semiconductor device having capacitor elements 100a and 100b, Fig. 4B is a cross-sectional view corresponding to dashed dotted line C1-C2 shown in Fig. 4A, and Fig. 4C is a cross-sectional view corresponding to dashed dotted line C3-C4 shown in Fig. 4A.

[0072] 4D is an example of a circuit diagram corresponding to the semiconductor device shown in FIGS. 4A to 4C . The capacitors CAa and CAb can correspond to the capacitors 100a and 100b, respectively. One electrode of the capacitor CAa and one electrode of the capacitor CAb are shared, and the shared electrode can correspond to the conductive layer 120. The other electrode of the capacitor CAa can correspond to the conductive layer 115a, and the wiring to which the conductive layer 115a is connected can correspond to the conductive layer 240a. The other electrode of the capacitor CAb can correspond to the conductive layer 115b, and the wiring to which the conductive layer 115b is connected can correspond to the conductive layer 240b.

[0073] The conductive layer 240a can be preferably used as a source electrode or a drain electrode of a transistor 200a described later, and the conductive layer 240b can be preferably used as a source electrode or a drain electrode of a transistor 200b described later.

[0074] In the configurations of the capacitor elements 100a and 100b shown in FIGS. 4A to 4C, the description of the common features with the capacitor elements 100a and 100b shown in FIGS. 1A to 1C may be omitted.

[0075] The semiconductor device shown in FIGS. 4A to 4C includes an insulating layer 288 over the insulating layer 210, a conductive layer 215a over the conductive layer 240a, and a conductive layer 215b over the conductive layer 240b.

[0076] 4A to 4C, the insulating layer 105 is located on the insulating layer 288, and the insulating layer 180, the conductive layer 115a, and the conductive layer 115b are located on the insulating layer 105. In addition, in FIG. 4A to 4C, the insulating layer 130 is in contact with the top surface of the insulating layer 105 in a region between the conductive layer 115a and the conductive layer 115b.

[0077] Although specific examples are not shown in Figures 4B and 4C, as described below, a semiconductor element such as a transistor can be disposed on the insulating layer 210, and an insulating layer 288 can be provided on the semiconductor element. The insulating layer 288 is disposed between the semiconductor element and the capacitor elements 100a and 100b and can function as an interlayer insulating layer. Since the insulating layer 288 functions as an interlayer film, it preferably has a low dielectric constant. By using a material with a low dielectric constant as an interlayer insulating layer, parasitic capacitance generated between wirings can be reduced. The insulating layer 288 can be formed as a single layer or a stack of insulating layers containing a material with a low dielectric constant. Examples of materials with a low dielectric constant include silicon oxide and silicon oxynitride. Silicon oxide and silicon oxynitride are thermally stable and are therefore preferable from the perspective of improving the characteristics and reliability of semiconductor devices.

[0078] For example, a barrier insulating layer against hydrogen is preferably used for the insulating layer 105 provided over the insulating layer 288. With such a structure, diffusion of hydrogen from above the transistors 200a and 200b to the oxide semiconductor layers 230a and 230b can be suppressed.

[0079] The insulating layer 105 can be formed using, for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, silicon nitride oxide, or the like.

[0080] The conductive layer 215a is provided in the insulating layer 288 and the insulating layer 105 and can function as a plug connecting the conductive layer 240a and the conductive layer 115a. The conductive layer 215b is provided in the insulating layer 288 and the insulating layer 105 and can function as a plug connecting the conductive layer 240b and the conductive layer 115b.

[0081] The insulating layer 180 is located on the insulating layer 105 and on the conductive layers 215a and 215b. The opening 190 in the insulating layer 180 reaches the top surface of the insulating layer 105. The conductive layer 115a is located on the conductive layer 215a and the insulating layer 105, and the conductive layer 115b is located on the conductive layer 215b and the insulating layer 105.

[0082] The top surface shape of the opening 190 is not limited to a circle. For example, it can be a circle, an approximately circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). The top surface shape and arrangement of the opening 190 can be changed, for example, to match the area, shape, and arrangement of the semiconductor elements disposed below the capacitive elements 100a and 100b. This may increase the degree of integration of the semiconductor device.

[0083] By providing the conductive layer 240a overlapping the conductive layer 115a, the degree of integration of the semiconductor device can be increased. Similarly, by providing the conductive layer 240b overlapping the conductive layer 115b, the degree of integration of the semiconductor device can be increased.

[0084] <Configuration Example 1-3 of Semiconductor Device> The semiconductor device shown in Figures 5A to 5C differs from Figures 4A to 4C mainly in that an insulating layer 287 is provided. Figure 5A is a plan view of the semiconductor device, Figure 5B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 shown in Figure 5A, and Figure 5C is a cross-sectional view corresponding to the dashed-dotted line C3-C4 shown in Figure 5A. Figure 5D is an enlarged view of the region surrounded by the two-dot dashed line in Figure 5B.

[0085] The insulating layer 287 is disposed between the conductive layer 215a and the conductive layer 215b, and covers a portion of the conductive layer 240a and a portion of the conductive layer 240b.

[0086] The conductive layers 215a and 215b are disposed so as to fill openings provided in the insulating layer 288 and the insulating layer 105. In a plan view, the insulating layer 287 has a region overlapping with the opening where the conductive layer 215a is provided and a region overlapping with the opening where the conductive layer 215b is provided. For the insulating layer 287, it is preferable to use a material that is not etched or has a low etching rate under the etching conditions for opening the insulating layer 288. This allows the insulating layer 287 to remain when opening the insulating layer 288.

[0087] The insulating layer 287 is preferably a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layers 215a and 215b and prevent the resistance from increasing. For example, the insulating layer 287 can be made of silicon nitride, silicon nitride oxide, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, or the like. Examples of oxides containing one or both of aluminum and hafnium that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate).

[0088] By covering a conductive layer, a semiconductor layer, etc. (not shown in Figures 5A to 5C) that is preferably insulated from the conductive layer 215a with an insulating layer 287, the insulating layer 287 can be disposed between the conductive layer 215a and the conductive layer, the semiconductor layer, etc., and can provide insulation between the conductive layer 215a and the conductive layer, the semiconductor layer, etc.

[0089] Similarly, by covering a conductive layer (not shown in Figures 5A to 5C) that is preferably insulated from the conductive layer 215b with an insulating layer 287, the insulating layer 287 can be disposed between the conductive layer 215b and the conductive layer, thereby providing insulation between the conductive layer 215b and the conductive layer.

[0090] The conductive layer 240a has a region that is covered with the insulating layer 287 and a region that is not covered with the insulating layer 287. The conductive layer 240a is preferably in contact with the conductive layer 215a in the region that is not covered with the insulating layer 287.

[0091] Similarly, the conductive layer 240b has a region that is covered with the insulating layer 287 and a region that is not covered with the insulating layer 287. The conductive layer 240b is preferably in contact with the conductive layer 215b in the region that is not covered with the insulating layer 287.

[0092] In the example of the semiconductor device shown in Figures 5A to 5D, the conductive layer 240a has a two-layer structure of a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1, and the conductive layer 240b has a two-layer structure of a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1.

[0093] As will be described later in transistors 200a, 200b, and the like, when a material that can suitably reduce contact resistance with a semiconductor layer of the transistor is used for the conductive layers 240a2 and 240b2, or a material that can suitably reduce contact resistance with the conductive layer 215a, the conductive layer 215b, the conductive layer 115a, the conductive layer 115b, or the like is used for the conductive layers 240a1 and 240b1, it is preferable to provide an opening in the conductive layer 240a2 that reaches the conductive layer 240a1 so that the conductive layer 215a is in contact with the conductive layer 240a1, and it is preferable to provide an opening in the conductive layer 240b2 that reaches the conductive layer 240b1 so that the conductive layer 215b is in contact with the conductive layer 240b1.

[0094] Figure 5E shows a modification of Figure 5D. Figure 5E differs from Figure 5D mainly in that conductive layer 240a1 and conductive layer 240b1 each have a recess, and conductive layer 215a and conductive layer 215b are provided to fill the recess. This configuration allows the contact area between conductive layer 215a and conductive layer 240a1 to be increased, further reducing contact resistance. Furthermore, the contact area between conductive layer 215b and conductive layer 240b1 can be increased, further reducing contact resistance.

[0095] <Configuration example 1-4 of semiconductor device> In the configurations shown in FIGS. 6A to 6C , the conductive layer 215a or the like is not provided between the conductive layer 240a and the conductive layer 115a, and the conductive layer 115a is disposed on and in contact with the conductive layer 240a, and the conductive layer 215b or the like is not provided between the conductive layer 240b and the conductive layer 115b, and the conductive layer 115b is disposed on and in contact with the conductive layer 240b.

[0096] 6A is a plan view of the semiconductor device, FIG. 6B is a cross-sectional view corresponding to the dashed dotted line C1-C2 shown in FIG. 6A, and FIG. 6C is a cross-sectional view corresponding to the dashed dotted line C3-C4 shown in FIG. 6A.

[0097] The conductive layer 240a and the conductive layer 240b are provided on the insulating layer 210. The insulating layer 180 is provided on the insulating layer 210, the conductive layer 240a, and the conductive layer 240b. The insulating layer 180 has openings 190 that reach the top surfaces of the conductive layer 240a and the conductive layer 240b.

[0098] The structure shown in FIG. 6A does not have the insulating layer 288, the conductive layer 215a, the conductive layer 215b, etc., compared to the structure shown in FIG. 5A, and therefore the process can be simplified.

[0099] <Configuration Example 1-5 of Semiconductor Device> The configuration shown in FIGS. 7A to 7C differs from that shown in FIGS. 6A to 6C mainly in that an insulating layer 287 is provided.

[0100] Fig. 7A is a plan view of the semiconductor device, Fig. 7B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 shown in Fig. 7A, and Fig. 7C is a cross-sectional view corresponding to the dashed-dotted line C3-C4 shown in Fig. 7A. Fig. 7D is an enlarged view of the area surrounded by the two-dot-dotted line in Fig. 7B.

[0101] The insulating layer 287 has a region disposed between the conductive layers 240a and 240b, a region covering the conductive layer 240a, and a region covering the conductive layer 240b.

[0102] The conductive layer 115a and the conductive layer 115b each have a region covering the top surface of the insulating layer 287 and a region covering the side surface of the insulating layer 287. In each of the conductive layers 115a and 115b, the region covering the side surface of the insulating layer 287 can also function as an electrode of a capacitor.

[0103] The insulating layer 287 can be made thicker to further increase the area of ​​the side surfaces of the insulating layer 287. This can increase the area of ​​the conductive layer 115a that functions as an electrode of the capacitor 100a and the area of ​​the conductive layer 115b that functions as an electrode of the capacitor 100b, thereby increasing the capacitance values ​​of the capacitors 100a and 100b.

[0104] The insulating layer 287 has a region that overlaps with the opening 190 in a plan view. It is preferable to use a material for the insulating layer 287 that is not etched under the etching conditions for the insulating layer 180 when the opening 190 is formed, or that has a low etching rate. This allows the insulating layer 287 to remain when the opening 190 is formed.

[0105] In the example of the semiconductor device shown in Figures 7A to 7D, the conductive layer 240a has a two-layer structure of a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1, and the conductive layer 240b has a two-layer structure of a conductive layer 240b1 and a conductive layer 240b2 on the conductive layer 240b1.

[0106] 7B and 7D, it is preferable to provide an opening in the conductive layer 240a2 that reaches the conductive layer 240a1, and to provide the conductive layer 115a so as to be in contact with the side surface of the opening and the top surface of the conductive layer 240a1. It is also preferable to provide an opening in the conductive layer 240b2 that reaches the conductive layer 240b1, and to provide the conductive layer 115b so as to be in contact with the side surface of the opening and the top surface of the conductive layer 240b1.

[0107] Figure 7E shows a modification of Figure 7D. Figure 7E differs from Figure 7D mainly in that conductive layer 240a1 and conductive layer 240b1 each have a recess, and conductive layer 115a and conductive layer 115b are provided to fill the recess. This configuration allows the contact area between conductive layer 115a and conductive layer 240a1 to be increased, further reducing contact resistance. Furthermore, the contact area between conductive layer 115b and conductive layer 240b1 can be increased, further reducing contact resistance.

[0108] <Configuration Example 2 of Semiconductor Device> A semiconductor device according to one embodiment of the present invention includes a plurality of transistors. Another embodiment of the present invention includes two transistors arranged in the same opening. Specifically, in one embodiment of the present invention, the second insulating layer has a second opening, and semiconductor layers of the two transistors are provided in the second opening. The two transistors preferably share a gate electrode. For example, a conductive layer arranged in the second opening can be used as a gate electrode shared by the two transistors.

[0109] A semiconductor device according to one embodiment of the present invention includes a plurality of capacitors and a plurality of transistors. The semiconductor device according to one embodiment of the present invention includes a first insulating layer, a second insulating layer, two capacitors, and two transistors. The first insulating layer has a first opening, and the second insulating layer has a second opening. The two transistors are disposed in the same second opening, and the two capacitors are disposed in the same first opening. The two capacitors are disposed over the two transistors.

[0110] A semiconductor device according to one embodiment of the present invention includes two transistors located in a second opening of a second insulating layer and two capacitors located in a first opening of a first insulating layer over the second insulating layer. One of the two transistors is preferably connected to one of the two capacitors. The other of the two transistors is preferably connected to the other of the two capacitors. By connecting the transistors and the capacitors, the semiconductor device can be used as a memory cell. The semiconductor device according to one embodiment of the present invention can include a plurality of memory cells.

[0111] 8A , 8B , and 9A include a memory cell 150 a and a memory cell 150 b. The memory cell 150 a includes a capacitor 100 a and a transistor 200 a. The memory cell 150 b includes a capacitor 100 b and a transistor 200 b. FIG. 8A is a plan view of the semiconductor device, FIG. 8B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 shown in FIG. 8A , and FIG. 9A is a cross-sectional view corresponding to the dashed-dotted line C3-C4 shown in FIG. 8A .

[0112] For the capacitor elements 100a and 100b, reference can be made to the capacitor elements 100a and 100b shown in FIGS. 1A to 5C and the like.

[0113] The transistors 200a and 200b are provided over an insulating layer 210. An insulating layer 288, an insulating layer 105, and an insulating layer 180 are provided over the transistors 200a and 200b. An insulating layer 280 and an insulating layer 281 are provided over the insulating layer 210, and a conductive layer 255 is provided between the insulating layer 280 and the insulating layer 281. As described later, the conductive layer 255 functions as a second gate of the transistors 200a and 200b.

[0114] The capacitor 100a is located over the transistor 200a, and the capacitor 100b is located over the transistor 200b. The conductive layer 115a of the capacitor 100a is located over the insulating layer 105 and the conductive layer 215a. The conductive layer 115b of the capacitor 100b is located over the insulating layer 105 and the conductive layer 215b. The conductive layer 215a is provided in the openings of the insulating layer 288 and the insulating layer 105. The conductive layer 215b is provided in the openings of the insulating layer 288 and the insulating layer 105. The conductive layer 215a is preferably provided on and in contact with the conductive layer 240a of the transistor 200a. The conductive layer 215b is preferably provided on and in contact with the conductive layer 240b of the transistor 200b. The conductive layer 115 a and the conductive layer 115 b preferably have a region in contact with the sidewall of the insulating layer 180 in the region where the opening 190 is located.

[0115] The transistor 200a includes a conductive layer 220a and a conductive layer 240a which function as one of a source electrode and a drain electrode, an oxide semiconductor layer 230a, an insulating layer 250, a conductive layer 260 which functions as a first gate electrode, an insulating layer 225, and a conductive layer 255 which functions as a second gate electrode.

[0116] The transistor 200b includes a conductive layer 220b and a conductive layer 240b functioning as one of a source electrode and a drain electrode, an oxide semiconductor layer 230b, an insulating layer 250, a conductive layer 260 functioning as a first gate electrode, an insulating layer 225, and a conductive layer 255 functioning as a second gate electrode.

[0117] The conductive layer 260 has an upper surface and a side surface thereof that is located outside the opening 290, and is covered with an insulating layer 287. Figure 8B shows an example in which the insulating layer 287 has an insulating layer 287a that overlaps with the upper surface of the conductive layer 260 and an insulating layer 287b that overlaps with the sidewall of the conductive layer 260.

[0118] The conductive layer 240a, the conductive layer 240b, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the insulating layer 250 each have a region located over the insulating layer 281. The insulating layer 287 overlaps with the conductive layer 240a, the conductive layer 240b, the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, and the insulating layer 250 in a region covering the side surface of the conductive layer 260.

[0119] When the conductive layers 215a and 215b are formed, openings into which the respective conductive layers are embedded are provided in the insulating layer 288 and the insulating layer 105. The material used for the insulating layer 287 is preferably a material that is not etched or has a low etching rate in the etching step for providing the openings in the insulating layer 288.

[0120] It is preferable to use a barrier insulating layer against oxygen as the insulating layer 287. This can suppress oxidation of the conductive layer 260 and prevent the resistance from increasing.

[0121] 8B , the conductive layer 215a and the conductive layer 215b each have a region in contact with the insulating layer 287. In the configuration example shown in FIG. 8B , the conductive layer 215a is not in contact with a region of the conductive layer 240a that overlaps with the insulating layer 287 in a plan view. In addition, the conductive layer 215b is not in contact with a region of the conductive layer 240b that overlaps with the insulating layer 287 in a plan view.

[0122] The transistors 200a and 200b will be described in detail later.

[0123] 11A shows the top view shown in FIG. 8A in which some components are omitted, and the conductive layers 115a, 115b, 215a, 215b, the oxide semiconductor layer 230a, and the oxide semiconductor layer 230b are indicated by solid lines.

[0124] FIG. 11B shows a diagram in which some components are omitted from the top view shown in FIG. 8A, and the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the conductive layer 240a, and the conductive layer 240b are indicated by solid lines.

[0125] 11C shows a diagram in which some components are omitted from the top view shown in FIG. 8A, and the conductive layer 255, the conductive layer 220a, and the conductive layer 220b are indicated by solid lines.

[0126] The top surface shape and arrangement of the opening 190 can be changed, for example, to match the area, shape, and arrangement of the semiconductor elements arranged below the capacitor elements 100a and 100b. This may increase the degree of integration of the semiconductor device. The top view shown in Figure 9B is a modification of the top view shown in Figure 8A, and shows an example in which the top surface shape of the opening 190 is elliptical.

[0127] 8B. Conductive layer 240a has a two-layer structure consisting of conductive layer 240a1 and conductive layer 240a2 on conductive layer 240a1. Conductive layer 240b has a two-layer structure consisting of conductive layer 240b1 and conductive layer 240b2 on conductive layer 240b1. In FIG. 10A, conductive layer 215a penetrates conductive layer 240a2 and contacts the top surface of conductive layer 240a1. Conductive layer 215b penetrates conductive layer 240b2 and contacts the top surface of conductive layer 240b1.

[0128] FIG. 10B is a modified example of the cross-sectional view of FIG. 10A, in which conductive layer 215a is provided to fill a recess provided in conductive layer 240a1, and conductive layer 215b is provided to fill a recess provided in conductive layer 240b1.

[0129] 8B shows an example in which the end of the oxide semiconductor layer 230a on the insulating layer 281 is located more inward than the end of the conductive layer 240a on the insulating layer 281, but as shown in FIG. 10C , the end of the conductive layer 240a and the end of the oxide semiconductor layer 230a may be aligned. Alternatively, as shown in FIG. 10D , the end of the oxide semiconductor layer 230a may be positioned outward than the end of the conductive layer 240a and cover the side surface of the conductive layer 240a. Similarly, the end of the conductive layer 240b and the end of the oxide semiconductor layer 230b may be aligned, or the end of the oxide semiconductor layer 230b may be positioned outward than the end of the conductive layer 240b and cover the side surface of the conductive layer 240b.

[0130] 8A and other figures are composed of an insulating layer 287a, which is a region located on the upper surface of the conductive layer 260, and an insulating layer 287b, which is a region covering the side surface. The insulating layer 287a and the insulating layer 287b can be made of the same material. Alternatively, the insulating layer 287a and the insulating layer 287b may be made of different materials.

[0131] The insulating layers 287a and 287b preferably have a low etching rate under etching conditions for forming an opening in the insulating layer 288.

[0132] The insulating layer 287a and the insulating layer 287b can be formed using silicon nitride, silicon nitride oxide, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, etc. Examples of oxides containing one or both of aluminum and hafnium that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate).

[0133] The insulating layer 287a and the insulating layer 287b may each have a stacked structure. For example, the insulating layer 287a and the insulating layer 287b may have a two-layer structure including a layer containing one or more of the above-described materials and a layer containing one or more other of the above-described materials. Alternatively, the insulating layer 287a and the insulating layer 287b may have a stacked structure including three or more layers.

[0134] Alternatively, the insulating layer 287 a and the insulating layer 287 b may each have a stacked structure including a layer containing any of the above materials and a layer containing another material. For example, a stacked structure of a first layer containing any of the above materials and a second layer containing silicon oxide or silicon oxynitride may be used.

[0135] The insulating layer 287a and the insulating layer 287b may be formed in different steps. For example, the insulating layer 287a may be used as a mask layer when forming the conductive layer 260, and the insulating layer 287b may be formed as a sidewall insulating layer on the side surface of the conductive layer 260 by, for example, anisotropic etching. In that case, the insulating layer 287b may be formed not only on the side surface of the conductive layer 260 but also on the top surface of the insulating layer 287a.

[0136] Alternatively, the insulating layer 287a and the insulating layer 287b may be formed by processing the same insulating film.

[0137] Even when different materials are used for insulating layer 287a and insulating layer 287b, the boundary between insulating layer 287a and insulating layer 287b may not be clearly observed when observing the cross section of the semiconductor device using an electron microscope or the like.

[0138] When the insulating layer 287a has a laminated structure, its upper layer may be made of a material different from that of the insulating layer 287b (or the same material but with a different film quality) and have an etching selectivity with respect to (the upper layer of) the insulating layer 287b (or the same material but with a different film quality). Here, having an etching selectivity means that the etching rate of the upper layer of the insulating layer 287a is sufficiently low under the etching conditions for (the upper layer of) the insulating layer 287b.

[0139] For example, silicon nitride and silicon oxide on the silicon nitride can be used as the insulating layer 287 a, and silicon nitride can be used as the insulating layer 287 b. With this structure, even if the etching time is extended in etching to form the insulating layer 287 b as a sidewall insulating layer, the insulating layer 287 a on the conductive layer 260 can be prevented from disappearing.

[0140] By extending the etching time when forming the insulating layer 287b, it is possible to remove unnecessary sidewall insulating layer formed in regions with small steps, and to selectively form the insulating layer 287b on the sidewalls of the conductive layer 260. An example of a region with small steps is the step between the conductive layer 240a (conductive layer 240b) and the insulating layer 281. In this case, the thickness of the conductive layer 240a (conductive layer 240b) is smaller than the thickness of the conductive layer 260.

[0141] Fig. 9C shows an example of a cross section of the conductive layer 260 including a region extending in the positive Y direction beyond C3 in the configuration shown in Fig. 9A. Fig. 9D shows an example of a cross section of the conductive layer 260 including a region extending in the negative Y direction beyond C4 in the configuration shown in Fig. 9A.

[0142] 9C shows a first end of the conductive layer 240a that forms the opening 290, and a second end located in the positive Y direction from the first end. The conductive layer 260 extends outward from the second end of the conductive layer 240a, in this case in the positive Y direction, and has a region that overlaps with the second end of the conductive layer 240a.

[0143] 9D shows a first end of the conductive layer 240b that forms the opening 290 and a second end located in the negative Y direction from the first end. The conductive layer 260 extends outward from the second end of the conductive layer 240b, in the negative Y direction here, and has a region that overlaps with the second end of the conductive layer 240b.

[0144] 8C is an example of a circuit diagram corresponding to the semiconductor device shown in FIGS. 8A, 8B, and 9A, and includes a memory cell MC1 and a memory cell MC2. The memory cell MC1 includes a transistor M1a and a capacitance element CAa, and the memory cell MC2 includes a transistor M1b and a capacitance element CAb. The memory cells MC1 and MC2 can correspond to the memory cells 150a and 150b.

[0145] One electrode of the capacitor CAa is connected to the wiring CAL, and the other electrode is connected to one of the source and drain of the transistor M1a. The other of the source and drain of the transistor M1a is connected to the wiring BILa. The first gate of the transistor M1a is connected to the wiring WOL, and the second gate is connected to the wiring BG.

[0146] One electrode of the capacitor CAb is connected to the wiring CAL, and the other electrode is connected to one of the source and drain of the transistor M1b. The other of the source and drain of the transistor M1b is connected to the wiring BILb. The first gate of the transistor M1b is connected to the wiring WOL, and the second gate is connected to the wiring BG.

[0147] The capacitors CAa and CAb can correspond to the capacitors 100a and 100b, respectively, and the transistors M1a and M1b can correspond to the transistors 200a and 200b, respectively. The wirings BILa and BILb can correspond to the conductive layers 220a and 220b. The wirings WOL and BG can correspond to the conductive layers 255 and 260. The other electrode of the capacitor CAa can correspond to the conductive layer 115a, and one of the source and drain electrodes of the transistor M1a can correspond to the conductive layer 240a. The other electrode of the capacitor CAb can correspond to the conductive layer 115b, and one of the source and drain electrodes of the transistor M1b can correspond to the conductive layer 240b.

[0148] 12A , 12B, and 13A include a memory cell 150 a and a memory cell 150 b. The memory cell 150 a includes a capacitor 100 a and a transistor 200 a. The memory cell 150 b includes a capacitor 100 b and a transistor 200 b. FIG. 12A is a plan view of the semiconductor device, FIG. 12B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 shown in FIG. 12A , and FIG. 13A is a cross-sectional view corresponding to the dashed-dotted line C3-C4 shown in FIG. 12A .

[0149] For the capacitor elements 100a and 100b, reference can be made to the capacitor elements 100a and 100b shown in FIGS. 1A to 3C, 6A to 7E, and the like.

[0150] The transistors 200a and 200b are provided over an insulating layer 210. The capacitor 100a is provided over the transistor 200a, and the capacitor 100b is provided over the transistor 200b. An insulating layer 280 and an insulating layer 281 are provided over the insulating layer 210, and a conductive layer 255 is provided between the insulating layer 280 and the insulating layer 281.

[0151] The conductive layer 115a included in the capacitor 100a is located over the conductive layer 240a and the insulating layer 287. The conductive layer 115b included in the capacitor 100b is located over the conductive layer 240b and the insulating layer 287. The conductive layer 115a is preferably provided on and in contact with the conductive layer 240a. The conductive layer 115b is preferably provided on and in contact with the conductive layer 240b. The conductive layers 115a and 115b preferably have a region in contact with the sidewall of the insulating layer 180 in the opening 190.

[0152] 12B, conductive layer 115a does not contact the region of conductive layer 240a that overlaps with insulating layer 287 in a plan view. Furthermore, conductive layer 115b does not contact the region of conductive layer 240b that overlaps with insulating layer 287 in a plan view.

[0153] The top surface shape of the opening 190 is not limited to a circle. The top surface view shown in Fig. 13B is a modification of the top surface view shown in Fig. 12A, and shows an example in which the top surface shape of the opening 190 is elliptical.

[0154] 14A is an enlarged view of a region including conductive layers 240a and 240b in the cross-sectional view shown in FIG. 12B. Conductive layer 240a has a two-layer structure consisting of conductive layer 240a1 and conductive layer 240a2 on conductive layer 240a1. Conductive layer 240b has a two-layer structure consisting of conductive layer 240b1 and conductive layer 240b2 on conductive layer 240b1. In FIG. 14A, conductive layer 215a penetrates conductive layer 240a2 and contacts the top surface of conductive layer 240a1. Furthermore, conductive layer 215b penetrates conductive layer 240b2 and contacts the top surface of conductive layer 240b1.

[0155] FIG. 14B is a modified example of the cross-sectional view of FIG. 14A, in which conductive layer 215a is provided to fill a recess provided in conductive layer 240a1, and conductive layer 215b is provided to fill a recess provided in conductive layer 240b1.

[0156] 12B shows an example in which the end of the oxide semiconductor layer 230a on the insulating layer 281 is located more inward than the end of the conductive layer 240a on the insulating layer 281. However, as shown in FIG. 15A , the conductive layer 240a has an end forming the opening 290 and an end located more outward than the end as viewed from the opening 290. The outer end may be aligned with the end of the oxide semiconductor layer 230a located more outward than the end of the conductive layer 240a and cover the side surface of the conductive layer 240a, as shown in FIG. 15B . Similarly, the end of the conductive layer 240b may be aligned with the end of the oxide semiconductor layer 230b, or the end of the oxide semiconductor layer 230b may be aligned more outward than the end of the conductive layer 240b and cover the side surface of the conductive layer 240b.

[0157] <Configuration Example 2-3 of Semiconductor Device> In the configurations illustrated in FIGS. 8A , 8B, and 9A , examples are shown in which the transistor 200 a and the transistor 200 b each have a conductive layer 260 functioning as a first gate and a conductive layer 255 functioning as a second gate; however, a configuration without a first gate or a second gate is also possible.

[0158] For example, in the structures illustrated in FIGS. 8A, 8B, and 9A, the transistor 200a and the transistor 200b may not include the conductive layer 255.

[0159] 8A, 8B, and 9A, the transistor 200a and the transistor 200b may each have a structure that does not include the conductive layer 260. FIGS. 16A and 16B show examples of a semiconductor device that does not include the conductive layer 260 and the insulating layer 287. FIG. 16A is a plan view of the semiconductor device, and FIG. 16B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 shown in FIG. 16A. FIG. 16C is an example of a circuit diagram corresponding to the semiconductor device shown in FIGS. 16A and 16B.

[0160] 17A and 17B differs from the configuration shown in Figures 12A to 12B mainly in that it does not have conductive layer 260 and insulating layer 287 is embedded in opening 290. Figure 17A is a plan view of the semiconductor device, and Figure 17B is a cross-sectional view corresponding to dashed dotted line C1-C2 shown in Figure 17A.

[0161] 17A and 17B, the insulating layer 287 has an area inside the opening 290 and an area provided on the insulating layer 281.

[0162] The insulating layer 287 overlaps with the opening 290 in a plan view and has a region that is higher than the top surfaces of the conductive layers 240a and 240b. As a result, the surfaces on which the conductive layers 115a and 115b are formed have convex portions. By increasing the thickness of the insulating layer 287, the height of the convex portions increases, and the areas of the conductive layers 115a and 115b can be increased. As a result, the capacitance values ​​of the capacitors 100a and 100b can be increased.

[0163] <Transistor 200a and Transistor 200b> Fig. 25A is an enlarged cross-sectional view of the transistor 200a and the transistor 200b shown in Fig. 8B, Fig. 12B, etc. Fig. 25B is a cross-sectional view taken along dashed dotted line C5-C6 shown in Fig. 25A.

[0164] In the transistor 200a, the oxide semiconductor layer 230a functions as a semiconductor layer, the conductive layer 255 functions as a first gate electrode, the insulating layer 225 functions as a first gate insulating layer, the conductive layer 260 functions as a second gate electrode, the insulating layer 250 functions as a second gate insulating layer, the conductive layer 220a functions as one of a source electrode and a drain electrode, and the conductive layer 240a functions as the other of the source and drain electrodes. In the transistor 200b, the oxide semiconductor layer 230b functions as a semiconductor layer, the conductive layer 255 functions as a first gate electrode, the insulating layer 225 functions as a first gate insulating layer, the conductive layer 260 functions as a second gate electrode, the insulating layer 250 functions as a second gate insulating layer, the conductive layer 220b functions as one of a source electrode and a drain electrode, and the conductive layer 240b functions as the other of the source and drain electrodes.

[0165] The conductive layer 255 is provided to extend in the X direction, and the conductive layer 260 is provided to extend in the Y direction. The region where the conductive layer 255 extends functions as a first gate wiring, and the region where the conductive layer 260 extends functions as a second gate wiring. The direction in which the conductive layer 260 extends may be parallel to the direction in which the conductive layer 255 extends. For example, the conductive layer 260 may be provided to extend in the X direction.

[0166] The conductive layer 220a and the conductive layer 220b are provided on the insulating layer 210 and spaced apart from each other. The conductive layer 220a and the conductive layer 220b are provided extending in the Y direction. The conductive layer 220a and the conductive layer 220b may be provided extending in the X direction or may be provided in an island shape.

[0167] The insulating layer 280 is located on the conductive layer 220a and the conductive layer 220b, and the insulating layer 281 is located on the conductive layer 255.

[0168] The conductive layer 240a and the conductive layer 240b are provided spaced apart from each other on the insulating layer 281. The conductive layer 240a and the conductive layer 240b are provided extending in the Y direction. The conductive layer 240a and the conductive layer 240b may be provided extending in the X direction or may be provided in an island shape.

[0169] The conductive layer 240a has a cutout portion at a position overlapping the opening 290. Specifically, as shown in a plan view such as FIG. 11B, the conductive layer 240a has a rectangular shape with the area overlapping the circular opening 290 cut out (removed). In plan view, the outline of the cutout portion matches or approximately matches a part of the outline of the opening 290. For example, in plan view, if the opening 290 is circular, the cutout portion will be arc-shaped. The side surface of the opening 290 can be considered to include the side surfaces of the insulating layer 280, the conductive layer 255, the insulating layer 281, and the conductive layer 240a.

[0170] When the conductive layers 240a and 240b do not have a cutout portion, for example, when the side surfaces of the conductive layers 240a and 240b facing each other are straight in a plan view and the conductive layers 240a and 240b do not overlap with the opening 290, the distance between the conductive layers 240a and 240b is at least the same as or longer than the width of the opening 290. On the other hand, when the conductive layers 240a and 240b each have a cutout portion, the distance between the conductive layers 240a and 240b, specifically, the shortest distance between the conductive layers 240a and 240b at a position where they do not overlap with the opening 290, can be made shorter than the width of the opening 290. Therefore, the distance between the conductive layers 240a and 240b can be shortened, and the integration degree of the semiconductor device can be increased.

[0171] 25A and 25B , the insulating layer 225 has a region in contact with the side surface of the insulating layer 281, a region in contact with the side surface of the conductive layer 255, and a region in contact with the side surface of the insulating layer 280 within the opening 290. The insulating layer 225 also has a region in contact with the side surface of the conductive layer 240a on the opening 290 side, and a region in contact with the side surface of the conductive layer 240b on the opening 290 side. The insulating layer 225 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0172] The insulating layer 225 has a region in contact with the side surface of the conductive layer 220a facing the opening 290 and a region in contact with the side surface of the conductive layer 220b facing the opening 290. The insulating layer 225 also has a region in contact with the insulating layer 210.

[0173] 25B , the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are spaced apart from each other, and each of the oxide semiconductor layers 230a and 230b in the opening 290 has an arc shape in plan view.

[0174] The oxide semiconductor layer 230a is provided in the opening 290 so as to cover a part of the insulating layer 225. The oxide semiconductor layer 230a has a region facing the conductive layer 255 in the opening 290 with the insulating layer 225 sandwiched therebetween. The oxide semiconductor layer 230a has a region in contact with the top surface of the conductive layer 220a in the opening 290 and a region in contact with the top surface of the conductive layer 240a outside the opening 290. The oxide semiconductor layer 230a also has a region in contact with a portion of the insulating layer 210 that overlaps with the opening 290.

[0175] Furthermore, outside the opening 290, the end of the oxide semiconductor layer 230a is located closer to the opening 290 than the end of the conductive layer 240a. Furthermore, in a plan view, the outline of the oxide semiconductor layer 230a outside the opening 290 is located more inward than the outline of the conductive layer 240a outside the opening 290. In this case, the upper surface of the conductive layer 240a has a region in contact with the insulating layer 250 and a region in contact with the oxide semiconductor layer 230a.

[0176] The insulating layer 250 is provided to cover the oxide semiconductor layer 230a and the oxide semiconductor layer 230b in the opening 290. The insulating layer 250 is provided on the insulating layer 281 to cover the top surfaces and side surfaces of the oxide semiconductor layer 230a, the oxide semiconductor layer 230b, the conductive layer 240a, and the conductive layer 240b. The insulating layer 250 has a region that is in contact with a part of the portion of the insulating layer 210 that overlaps with the opening 290. The insulating layer 250 has a recessed portion at a position that overlaps with the opening 290.

[0177] The conductive layer 260 is provided so as to fill at least a part of a recess of the insulating layer 250. The conductive layer 260 has, in the opening 290, a region facing the oxide semiconductor layer 230a with the insulating layer 250 sandwiched therebetween and a region facing the oxide semiconductor layer 230b with the insulating layer 250 sandwiched therebetween. The conductive layer 260 also has, in the opening 290, a region facing the conductive layer 255 with the insulating layer 225, the oxide semiconductor layer 230a, and the insulating layer 250 sandwiched therebetween and a region facing the conductive layer 255 with the insulating layer 225, the oxide semiconductor layer 230b, and the insulating layer 250 sandwiched therebetween.

[0178] As described above, the oxide semiconductor layer 230a is provided inside the opening 290. The transistor 200a has a structure in which one of the source electrode and the drain electrode (here, the conductive layer 220a) is located below and the other of the source electrode and the drain electrode (here, the conductive layer 240a) is located above, and thus current flows vertically. That is, a channel is formed along the side surface of the opening 290. That is, the transistor 200a is a vertical transistor.

[0179] The conductive layer 255 has a region facing the conductive layer 260 with the insulating layer 225, the oxide semiconductor layer 230a, and the insulating layer 250 sandwiched therebetween. A region of the oxide semiconductor layer 230a sandwiched between the conductive layer 255 and the conductive layer 260 and its vicinity functions as a channel formation region of the transistor 200a. A region of the oxide semiconductor layer 230a overlapping with the conductive layer 260 may also function as a channel formation region. One of a region of the oxide semiconductor layer 230a near the conductive layer 220a and a region of the oxide semiconductor layer 230a near the conductive layer 240a functions as a source region, and the other functions as a drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0180] With the above structure, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200a to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0181] Furthermore, the semiconductor device of this embodiment has a structure in which the channel formation regions of the transistor 200a and the transistor 200b are provided in one opening 290. With this structure, miniaturization or high integration of the semiconductor device can be achieved.

[0182] The transistor 200a and the transistor 200b each include a conductive layer 255 that functions as a first gate electrode and a conductive layer 260 that functions as a second gate electrode. The potential applied to the conductive layer 260 is changed independently of the potential applied to the conductive layer 255, so that the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 260, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 260, the drain current when the potential applied to the conductive layer 255 is 0 V can be made smaller than when a negative potential is not applied. Note that the conductive layer 255 may function as a second gate electrode, and the conductive layer 260 may function as a first gate electrode.

[0183] Alternatively, the conductive layer 260 may be connected to the conductive layer 255. By connecting the conductive layer 255 and the conductive layer 260 and applying the same potential thereto, it is possible to increase the on-current, reduce variations in initial characteristics, suppress deterioration of electrical characteristics in a negative GBT (Gate Bias-Temperature) stress test, and suppress fluctuations in the on-current rise voltage at different drain voltages.

[0184] The conductive layer 240a is preferably not located inside the opening 290. That is, the conductive layer 240a preferably does not have a region in contact with the side surface of the insulating layer 281 in the opening 290. With this structure, the cutout portion of the conductive layer 240a (a portion where a region overlapping with the opening 290 is cut out) and the opening of the insulating layer 281 can be formed simultaneously. Furthermore, when the side surface of the conductive layer 240a and the side surface of the insulating layer 281 are aligned or substantially aligned in the opening 290, the film thickness distribution of the insulating layer 225, the oxide semiconductor layer 230a, and the like provided inside the opening 290 can be made uniform. Furthermore, the insulating layer 225, the oxide semiconductor layer 230a, and the like can be prevented from being separated by a step or the like between the conductive layer 240a and the insulating layer 281.

[0185] The side surface of the conductive layer 255 on the opening 290 side faces the side surface of the oxide semiconductor layer 230a with the insulating layer 225 interposed therebetween, and the side surface of the conductive layer 260 faces the side surface of the oxide semiconductor layer 230a with the insulating layer 250 interposed therebetween. That is, in a plan view, at least a part of the portion of the oxide semiconductor layer 230a located at the opening 290 becomes a channel formation region. In this case, for example, the oxide semiconductor layer 230a is provided along the periphery of the opening 290, and the channel width of the transistor 200a is determined by the periphery of the region of the opening 290 where the oxide semiconductor layer 230a is provided. Here, the periphery of the opening 290 depends on the width of the opening 290 (or the diameter if the opening 290 is circular in a plan view). Furthermore, as the distance between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b increases, the area in which the oxide semiconductor layer 230a and the oxide semiconductor layer 230b are not disposed increases in the opening 290, that is, the area of ​​the oxide semiconductor layer 230a and the oxide semiconductor layer 230b decreases. In other words, it can be said that the channel width of the transistor 200a depends on the width of the opening 290 (the diameter when the opening 290 is circular in plan view) and the distance between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b.

[0186] 25A and 25B show the width D of the opening 290, and FIG. 25B shows the channel width W of the transistor 200a and the distance Hab between the oxide semiconductor layer 230a and the oxide semiconductor layer 230b. Note that the distance Hab can be measured in the XY plane including the conductive layer 255. Alternatively, the measurement may be performed in the XY plane including the insulating layer 281, the XY plane including the insulating layer 280, or the like. The distance Hab may also be calculated by observing a cross section.

[0187] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. Meanwhile, the area occupied by the transistor 200a, for example, the area of ​​the transistor 200a in a plan view, is roughly determined by the width D of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200a, thereby enabling a semiconductor device to be highly integrated.

[0188] The width D of the opening 290 may vary in the depth direction (or in the Z direction when the side surfaces of the opening 290 are perpendicular to the substrate surface). Here, the shortest distance between the two side surfaces of the insulating layer 281 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the insulating layer 281 is used as the width D of the opening 290. The cross-sectional view here refers to a cross section passing through the center (or center of gravity) of the opening 290 as viewed from the Z direction, viewed from the X direction or the Y direction. Alternatively, the width D may be the width of the opening 290 at the highest position in the insulating layer 281, the width of the opening 290 at the lowest position, the width of the opening 290 at the midpoint between these, or the average of these three widths. Here, an example is shown in which the width D is determined using the width of the opening 290 in the insulating layer 281, but the method for determining the width D is not particularly limited. For example, the width D may be the shortest distance between two side surfaces of the conductive layer 255 on the opening 290 side in a cross-sectional view, or the shortest distance between two side surfaces of the insulating layer 281 on the opening 290 side. Furthermore, for example, the width D may be the shortest distance between the side surface of the conductive layer 240a on the opening 290 side and the side surface of the conductive layer 240b on the opening 290 side in a cross-sectional view.

[0189] When the opening 290 is formed by photolithography, the width D of the opening 290 is limited by the exposure limit of photolithography. The width D of the opening 290 is set depending on the film thickness of each of the insulating layer 225, the oxide semiconductor layer 230a, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.

[0190] The width D of the opening 290 is greater than the distance Hab. More specifically, the width D of the opening 290 is preferably greater than the sum of twice the film thickness of the insulating layer 225 and the distance Hab. This allows the oxide semiconductor layer 230a and the oxide semiconductor layer 230b to be provided within the opening 290. Here, the film thickness of the insulating layer 225 refers to the width of at least a portion of the insulating layer 225 in the A1-A2 direction. Furthermore, the width D of the opening 290 is more preferably greater than the sum of twice the film thickness of the insulating layer 225, twice the film thickness of the oxide semiconductor layer 230a, and the distance Hab. This prevents the film thickness of the oxide semiconductor layer 230a from becoming thin (reduced), thereby ensuring the area of ​​the channel formation region in a plan view. Here, the film thickness of the oxide semiconductor layer 230a refers to the width of at least a portion of the oxide semiconductor layer 230a located in the opening 290 in the A1-A2 direction.

[0191] Furthermore, it is preferable that the distance Hab is small. By reducing the distance Hab, the channel width W can be increased. Furthermore, miniaturization or high integration of the semiconductor device can be achieved. The distance Hab is, for example, preferably 10 nm or more and 60 nm or less, more preferably 10 nm or more and 50 nm or less, even more preferably 10 nm or more and 40 nm or less, and even more preferably 10 nm or more and 30 nm or less. Furthermore, the distance Hab is, for example, preferably 5 nm or more and 50 nm or less, more preferably 5 nm or more and 40 nm or less, and even more preferably 5 nm or more and 30 nm or less.

[0192] The channel length of the transistor 200a is the distance between the source region and the drain region. For example, when the conductive layer 255 functions as a first gate electrode, the channel length of the transistor 200a is the length of a region of the oxide semiconductor layer 230a that faces the conductive layer 255 with the insulating layer 225 sandwiched therebetween, in a cross-sectional view. In other words, it can be said that the channel length of the transistor 200a is determined by the thickness of the conductive layer 255. When the conductive layer 260 and the conductive layer 255 are connected to each other, the channel length of the transistor 200a is the length of a region of the oxide semiconductor layer 230a that is sandwiched between the conductive layer 260 and the conductive layer 255, in a cross-sectional view. In other words, it can be said that the channel length of the transistor 200a is determined by the thickness of the conductive layer 255.

[0193] Furthermore, when the conductive layer 260 functions as a first gate electrode, it can be said that the channel length of the transistor 200a is determined by the thickness of the insulating layer 280, the thickness of the conductive layer 255, the thickness of the insulating layer 281, the thickness of the conductive layer 240a, and the like on the conductive layer 220a in a cross-sectional view.

[0194] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200a can be set by the thickness of the conductive layer 255 or the like. Therefore, the channel length of the transistor 200a can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200a, thereby improving its frequency characteristics.

[0195] Note that the channel length of the transistor 200a is determined by the film thickness of the conductive layer 255 and the like, and therefore does not affect the area occupied by the transistor 200a, for example, the area of ​​the transistor 200a in a plan view. By setting the channel length of the transistor 200a to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the opening 290 and the like.

[0196] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0197] The channel length of the transistor 200a is preferably at least shorter than the channel width W of the transistor 200a. The channel length L of the transistor 200a is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200a. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0198] Note that the channel width W of the transistor 200a may be equal to or less than the channel length of the transistor 200a. With such a structure, miniaturization or high integration of a semiconductor device can be achieved.

[0199] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the insulating layer 225 is provided concentrically and the oxide semiconductor layer 230a is provided in an arc shape. Furthermore, the insulating layer 250 and the conductive layer 260 are provided along the shapes of the insulating layer 225 and the oxide semiconductor layer 230a. As a result, the distance between the conductive layer 255 and the oxide semiconductor layer 230a and the distance between the conductive layer 260 and the oxide semiconductor layer 230a become approximately uniform, and therefore a gate electric field can be applied to the oxide semiconductor layer 230a approximately uniformly.

[0200] In this embodiment, the opening 290 is circular in plan view, but the present invention is not limited to this. In plan view, the opening 290 can be, for example, a circle or an approximately circle such as an oval, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0201] <Constituent Materials of Semiconductor Device> Materials that can be used for the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked-layer structure. Note that hereinafter, the transistors 200a and 200b may be collectively referred to as transistors 200. The oxide semiconductor layers 230a and 230b may be collectively referred to as oxide semiconductor layers 230. The conductive layers 220a and 220b may be collectively referred to as conductive layers 220. The conductive layers 240a and 240b may be collectively referred to as conductive layers 240.

[0202] [Oxide Semiconductor Layer] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0203] 25A shows an example of a three-layer structure of the oxide semiconductor layer 230. The oxide semiconductor layer 230a shown in Fig. 25A can have a three-layer structure of an oxide semiconductor layer 230a1, an oxide semiconductor layer 230a2 on the oxide semiconductor layer 230a1, and an oxide semiconductor layer 230a3 on the oxide semiconductor layer 230a2.

[0204] For an oxide semiconductor layer that can be used for the oxide semiconductor layers 230a1 to 230a3, the description in Embodiment 2 can be referred to.

[0205] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0206] The transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the oxide semiconductor layer 230 including a channel formation region. When a metal oxide functioning as a semiconductor is used for the oxide semiconductor layer 230, the transistor 200 can be referred to as an OS transistor.

[0207] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0208] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0209] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0210] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0211] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0212] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0213] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0214] Further, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 5.

[0215] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 280, insulating layer 281, insulating layer 288, insulating layer 180, insulating layer 250, insulating layer 225, insulating layer 130, insulating layer 287, insulating layer 105, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0216] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0217] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0218] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0219] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0220] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0221] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0222] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0223] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0224] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0225] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0226] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystalline structure, as this will result in the manifestation of ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0227] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0228] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0229] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also included are nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Also included are nitride oxides such as silicon nitride oxide.

[0230] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0231] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0232] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0233] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0234] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0235] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0236] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0237] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0238] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0239] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0240] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0241] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0242] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 and can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0243] The concentration of impurities such as hydrogen or water in the insulating layer 210 is preferably reduced, which can prevent impurities such as hydrogen or water from entering a channel formation region of the oxide semiconductor layer 230.

[0244] 8B, 12B, 25A, etc. show examples in which the insulating layer 210 has a single-layer structure. The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0245] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0246] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the oxide semiconductor layer 230.

[0247] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least some of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0248] Note that the thickness of the insulating layer 280 on the conductive layer 220 a or 220 b affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately according to the design value of the channel length of the transistor 200 .

[0249] The insulating layer 280 can have a stacked structure of two or more layers. For example, the insulating layer 280 can have a three-layer structure. In this case, it is preferable to use the above-mentioned material with a low relative dielectric constant as the second layer located between the first layer and the third layer, and to use barrier insulating layers against oxygen as the first layer and the third layer. This can suppress oxidation of the conductive layer 220 and the conductive layer 255 and prevent high resistance.

[0250] For example, it is preferable to use a silicon nitride film or an aluminum oxide film as the first layer and the third layer of the insulating layer 280, and to use a silicon oxide film as the second layer of the insulating layer 280. Note that each of the first layer and the third layer of the insulating layer 280 may have a stacked structure of two or more layers.

[0251] The insulating layer 281 can be made of an insulating material that can be used for the insulating layer 280 .

[0252] The insulating layer 281 can have a stacked structure of two or more layers. For example, the insulating layer 281 can have a three-layer structure, similar to the insulating layer 280. It is preferable to use the above-mentioned material with a low relative dielectric constant for the second layer, and to use barrier insulating layers against oxygen for the first and third layers. This can suppress oxidation of the conductive layer 255 and the conductive layer 240 and prevent high resistance.

[0253] For example, it is preferable to use a silicon nitride film or an aluminum oxide film as the first layer and the third layer of the insulating layer 281, and to use a silicon oxide film as the second layer of the insulating layer 281. Note that each of the first layer and the third layer of the insulating layer 281 may have a stacked structure of two or more layers.

[0254] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0255] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0256] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. In this way, oxygen can be supplied from the insulating layer 250 to the oxide semiconductor layer 230, and oxygen vacancies in the oxide semiconductor layer 230 can be reduced. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0257] The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0258] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized. For example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer and a silicon nitride film can be used as the second insulating layer.

[0259] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0260] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0261] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0262] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including the fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0263] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0264] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0265] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0266] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0267] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0268] Note that the insulating layer 250 having a four-layer structure may not include the second insulating layer. For example, an insulating layer having a barrier property against oxygen can be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant can be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side can be used.

[0269] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0270] The insulating layer 225 can be made of an insulating material that can be used for the insulating layer 250 .

[0271] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor layer. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor layer.

[0272] Therefore, a barrier insulating layer against hydrogen is preferably used as the insulating layer 225 provided outside the oxide semiconductor layer 230. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used as the insulating layer 225, and a silicon nitride film is more preferably used.

[0273] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, by using a silicon nitride film for the insulating layer 225, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, which can prevent oxygen vacancies from being formed in the oxide semiconductor layer 230. Furthermore, by using a silicon nitride film for the insulating layer 225, excessive oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Therefore, the channel formation region of the oxide semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200. Furthermore, the insulating layer 225 may be in contact with the side surface of the conductive layer 240a in the opening 290. In this case, by using a silicon nitride film for the insulating layer 225, it is possible to prevent the side surface of the conductive layer 240a in the opening 290 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200.

[0274] The silicon nitride film of the insulating layer 225 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 225 on the side surface of the opening 290 and form an insulating layer 225 with a uniform thickness.

[0275] The insulating layer 225 may be made of the above-mentioned material that can have ferroelectricity.

[0276] The insulating layer 225 can have a stacked structure of two or more layers. It is preferable that the first layer provided in contact with the side surface of the insulating layer 280 in the opening 290 be a barrier insulating layer against hydrogen, and the second layer provided in contact with the oxide semiconductor layer 230 be an insulating layer having a function of capturing or fixing hydrogen. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved. For example, it is preferable that a silicon nitride film be used for the first layer, and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film be used for the second layer. In this case, the first layer contains silicon and nitrogen, and the second layer contains one or both of hafnium and aluminum, and oxygen.

[0277] Alternatively, an insulating layer including a region containing excess oxygen can be used as the second layer. With such a structure, one or both of oxygen vacancies and hydrogen in the oxide semiconductor layer 230 can be reduced. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced. For example, a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film is preferably used for the second layer. In this case, the second layer contains oxygen and one or both of silicon and aluminum.

[0278] As described above, by wrapping the oxide semiconductor layer 230 in a ring shape with a barrier insulating layer against hydrogen and providing an insulating layer having a function of capturing or fixing hydrogen or an insulating layer including a region containing excess oxygen near the oxide semiconductor layer 230, it is possible to reduce one or both of oxygen vacancies and impurities in the oxide semiconductor layer 230. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0279] The insulating layer 225 can have a four-layer structure including a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. For example, it is preferable that one of the first to fourth insulating layers is a barrier insulating layer against hydrogen, another is an insulating layer having a function of capturing or fixing hydrogen, another is an insulating layer having a region containing excess oxygen, and the others are insulating layers having a barrier property against oxygen. With such a structure, a decrease in on-state current or a decrease in field-effect mobility of the transistor 200 can be suppressed.

[0280] Note that the stacked structure of the first to fourth insulating layers in the insulating layer 225 can be referred to the stacked structure of the first to fourth insulating layers in the insulating layer 250. Note that the stacked order in the insulating layer 225 is preferably the reverse of that in the insulating layer 250. For example, when the insulating layer 225 has a three-layer structure, the insulating layer 225 can have a three-layer structure including a second insulating layer in contact with the conductive layer 255, a first insulating layer on the second insulating layer, and a third insulating layer on the first insulating layer. In this case, the third insulating layer is in contact with the oxide semiconductor layer 230.

[0281] The semiconductor device of one embodiment of the present invention may include an insulating layer over the transistor 200. Specifically, an insulating layer may be provided over the conductive layer 260 and the insulating layer 250.

[0282] The insulating layer is preferably a barrier insulating layer against hydrogen. For example, a barrier insulating layer against hydrogen is preferably used as the insulating layer 105. With such a structure, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0283] The insulating layer 130 is provided on the conductive layers 115a and 115b. The insulating layer 130 is provided so as to contact the upper and side surfaces of the conductive layers 115a and 115b. In other words, the insulating layer 130 is preferably structured to cover the side edges of the conductive layers 115a and 115b. This can prevent the conductive layers 115a and 115b from shorting out with the conductive layer 120.

[0284] It is preferable to use a material with a high relative dielectric constant for the insulating layer 130. By using a material with a high relative dielectric constant for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current and also ensure sufficient capacitance of the capacitive element 100a.

[0285] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a layered structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. Using a stack of insulating layers with a relatively high dielectric strength, such as aluminum oxide, improves the dielectric strength and suppresses electrostatic breakdown of the capacitor element 100a.

[0286] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, refer to the description in Embodiment 1.

[0287] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nanometers, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less). Furthermore, for example, the film thickness is preferably 8 nm or more and 12 nm or less. By using a ferroelectric layer that can be thinned, a semiconductor device can be formed by combining the capacitive element with a semiconductor element such as a miniaturized transistor.

[0288] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 nm, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element can be reduced.

[0289] Yttrium can also be added to metal oxides containing either or both of hafnium and zirconium. For example, adding yttrium to hafnium zirconium oxide can enhance ferroelectricity.

[0290] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as a capacitance element, the memory device described in this embodiment functions as a ferroelectric memory.

[0291] The conductive layer 120 is provided in contact with a part of the upper surface of the insulating layer 130. The side edge of the conductive layer 120 is located outside the side edges of the conductive layers 115a and 115b.

[0292] Each of the insulating layers 287a and 287b can be formed as a single layer or a stacked layer using the insulating material described above.

[0293] The insulating layer 287a and the insulating layer 287b are preferably formed using a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 260, the conductive layer 215a, and the conductive layer 215b, thereby preventing the resistance from increasing. For example, a silicon nitride film is preferably used for the insulating layer 287a and the insulating layer 287b.

[0294] Since the insulating layer 288 and the insulating layer 180 function as interlayer films, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulating layer 288 and the insulating layer 180 can be formed as a single layer or a stack using the above-mentioned insulating materials. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 288 and the insulating layer 180.

[0295] [Conductive Layer] For the conductive layers (conductive layer 220a, conductive layer 220b, conductive layer 240a, conductive layer 240b, conductive layer 260, conductive layer 255, conductive layer 115a, conductive layer 115b, conductive layer 120, conductive layer 215a, conductive layer 215b, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0296] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0297] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0298] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0299] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0300] The conductive layers 220a, 220b, 240a, and 240b are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers.

[0301] By using a conductive material containing oxygen for the conductive layer 220a and the conductive layer 220b, the conductive layer can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240a and the conductive layer 240b, the conductive layer can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, this is preferable because the conductive layer 220a and the conductive layer 220b can maintain their conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220a, the conductive layer 220b, the conductive layer 240a, and the conductive layer 240b.

[0302] When the conductive layer 220a, the conductive layer 220b, the conductive layer 240a, and the conductive layer 240b each have a stacked structure, the contact resistance between the conductive layer and the oxide semiconductor layer 230 can be reduced by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230.

[0303] The conductive layer 220a shown in FIG. 8B and other figures has a two-layer structure including a conductive layer 220a1 and a conductive layer 220a2 on the conductive layer 220a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 220a2 and a material having higher conductivity than the conductive layer 220a2 for the conductive layer 220a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 220a2 and tungsten for the conductive layer 220a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 220a1. Using an oxide conductor for the conductive layer 220a2, which is mainly in contact with the oxide semiconductor layer 230a, can reduce contact resistance with the oxide semiconductor layer 230a. Furthermore, using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 220a can increase the conductivity of the conductive layer 220a.

[0304] Note that the conductive layer 220a1 may be formed using a conductive material containing oxygen, and the conductive layer 220a2 may be formed using a material having higher conductivity than the conductive layer 220a1. In this case, the conductive layer 220a is formed using a material having higher conductivity in a layer closest to the channel formation region of the oxide semiconductor layer 230a. Therefore, the current path between the source and drain can be shortened, and the on-state current of the transistor 200a can be increased.

[0305] Note that one or both of the conductive layer 220a1 and the conductive layer 220a2 may have a stacked structure of two or more layers. For example, it is preferable that the conductive layer 220a1 has a two-layer structure, with a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion used for the lower layer, a material with high conductivity used for the upper layer, and a conductive material containing oxygen (more preferably, an oxide conductor) used for the conductive layer 220a2. Specifically, it is preferable that titanium nitride be used for the lower layer of the conductive layer 220a1, tungsten be used for the upper layer, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) be used for the conductive layer 220a2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230a. Furthermore, an oxide conductor is used for the layer closest to the channel formation region of the oxide semiconductor layer 230a. Compared to tungsten, an oxide conductor has lower contact resistance with the oxide semiconductor layer 230a, which shortens the current path between the source and drain and increases the on-state current of the transistor 200a. With this structure, the conductive layer 220a can maintain conductivity even when in contact with the oxide semiconductor layer 230a. Furthermore, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220a can be suppressed by the insulating layer 210. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as the upper layer of the conductive layer 220a1, the conductivity of the conductive layer 220a can be increased.

[0306] The conductive layer 240a shown in FIG. 8B and other figures has a two-layer structure including a conductive layer 240a1 and a conductive layer 240a2 on the conductive layer 240a1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a2 and a material having higher conductivity than the conductive layer 240a2 for the conductive layer 240a1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240a2 and tungsten for the conductive layer 240a1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240a1. Using an oxide conductor for the conductive layer 240a2, which is mainly in contact with the oxide semiconductor layer 230a, can reduce contact resistance with the oxide semiconductor layer 230a. Furthermore, using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240a can increase the conductivity of the conductive layer 240a.

[0307] Note that the conductive layer 240a1 may be formed using a conductive material containing oxygen, and the conductive layer 240a2 may be formed using a material having higher conductivity than the conductive layer 240a1. In this case, an oxide conductor is used for the conductive layer 240a that is closest to the channel formation region of the oxide semiconductor layer 230a. Therefore, the current path between the source and drain can be shortened, and the on-state current of the transistor 200a can be increased.

[0308] Although the conductive layer 220a and the conductive layer 240a have been described, the same applies to the conductive layer 220b and the conductive layer 240b.

[0309] The conductive layer 255 has a region that functions as a first gate wiring. The conductive layer 255 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 255 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 255.

[0310] The conductive layer 255 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0311] The conductive layer 260 can be made of any conductive material that can be used for the conductive layer 255 .

[0312] The conductive layer 260 can have a stacked structure of two or more layers. For example, it is preferable that the conductive layer 260 has a two-layer structure, with a titanium nitride film used as the lower layer and a tungsten film used as the upper layer. Alternatively, it is preferable that a tantalum nitride film is used as the lower layer and a copper film is used as the upper layer. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0313] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0314] The conductive layers 115a and 115b are preferably formed using a single layer or a stacked layer of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can prevent the conductive layers 115a and 115b from being oxidized. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can prevent the conductive layers 115a and 115b from being oxidized.

[0315] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0316] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0317] <Method for Manufacturing Semiconductor Device> An example of a method for manufacturing the semiconductor device shown in FIGS. 12A to 13A will be described with reference to FIGS. 18A to 24. FIG.

[0318] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0319] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0320] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0321] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0322] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0323] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0324] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0325] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0326] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0327] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0328] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0329] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0330] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0331] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed using immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0332] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0333] First, an insulating layer 210 is formed on a substrate (not shown), and a conductive layer 220 a and a conductive layer 220 b are formed on the insulating layer 210 .

[0334] Subsequently, an insulating layer 280 is formed over the conductive layer 220a, the conductive layer 220b, and the insulating layer 210. Subsequently, a conductive layer 255 is formed over the insulating layer 280, and an insulating layer 281 is formed over the conductive layer 255.

[0335] Next, a conductive film 240f that will become the conductive layer 240a and the conductive layer 240b is formed over the insulating layer 281. Next, an opening 290 is formed in the conductive film 240f, the insulating layer 281, the conductive layer 255, and the insulating layer 280 (FIGS. 18A to 18C). Here, FIG. 18A is a top view, and FIGS. 18B and 18C are cross-sectional views corresponding to the dashed dotted lines C1-C2 and C3-C4 shown in FIG. 18A, respectively.

[0336] The opening 290 is formed so as to expose at least a portion of the upper surface of each of the conductive layer 220a, the conductive layer 220b, and the insulating layer 210. At this time, recesses are preferably provided in the conductive layer 220a2 and the conductive layer 220b2 at positions overlapping with the opening 290. By forming the opening 290, it is preferable that the bottom and side surfaces of the recesses in the conductive layer 220a2 and the conductive layer 220b2 are exposed. Furthermore, a recess may be provided in the insulating layer 210 between the conductive layer 220a and the conductive layer 220b at a position overlapping with the opening 290.

[0337] Subsequently, heat treatment may be performed. By performing the heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 and the like can be reduced before the oxide semiconductor layers 230a and 230b are formed.

[0338] Subsequently, the insulating layer 225 is formed. The insulating layer 225 is provided in contact with the side surfaces of the recesses of the conductive layer 220a2 and the conductive layer 220b2, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 255, the side surfaces of the insulating layer 281, and the side surfaces of the conductive film 240f.

[0339] Next, oxide semiconductor layers 230a and 230b are formed. The oxide semiconductor layer 230a is provided in contact with the bottom and side surfaces of the recesses of the conductive layer 220a, the exposed upper surface of the insulating layer 210, the side surfaces of the insulating layer 225, and the side surfaces and upper surfaces of the conductive film 240f. The oxide semiconductor layer 230b is provided in contact with the bottom and side surfaces of the recesses of the conductive layer 220b, the exposed upper surface of the insulating layer 210, the side surfaces of the insulating layer 225, and the side surfaces and upper surfaces of the conductive film 240f.

[0340] Next, the conductive film 240f is processed to form the conductive layers 240a and 240b. Next, the insulating layer 250 is formed so as to cover the opening 290.

[0341] Microwave plasma treatment is preferably performed after the insulating layer 250 is formed. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the oxide semiconductor layer can be reduced. Furthermore, a crystalline region of the oxide semiconductor layer may grow.

[0342] Next, a conductive film to be the conductive layer 260 is formed over the insulating layer 250. Next, an insulating layer 287a is formed over the conductive film, and the conductive film is processed using the insulating layer 287a as a mask to form the conductive layer 260 (FIGS. 19A to 19C). Here, FIG. 19A shows a top view, and FIGS. 19B and 19C show cross-sectional views corresponding to the dashed dotted lines C1-C2 and C3-C4 shown in FIG. 19A, respectively.

[0343] Next, an insulating film to be the insulating layer 287b is formed over the insulating layer 287a and the insulating layer 250. The method for forming the insulating film to be the insulating layer 287a can be referred to for the method for forming the insulating film to be the insulating layer 287a. The insulating film is then processed by anisotropic etching to form the insulating layer 287b on the sidewalls of the conductive layer 260 and the insulating layer 287a (FIGS. 20A to 20C). Here, FIG. 20A shows a top view, and FIGS. 20B and 20C show cross-sectional views corresponding to the dashed dotted lines C1-C2 and C3-C4 shown in FIG. 20A, respectively.

[0344] Here, as an example, silicon nitride and silicon oxide on the silicon nitride are used for the insulating layer 287 a, and silicon nitride can be used for the insulating layer 287 b. With this structure, even if the etching time is extended in etching to form the insulating layer 287 b as a sidewall insulating layer, the insulating layer 287 a on the conductive layer 260 can be prevented from disappearing.

[0345] By increasing the etching time when forming the insulating layer 287b, unnecessary sidewall insulating layers formed in areas with small steps, such as the sidewalls of the conductive layers 240a and 240b, can be removed, and the insulating layer 287b can be selectively formed on the sidewalls of the conductive layer 260.

[0346] Next, the insulating layer 180 and the insulating layer 250 are removed by etching in a region overlapping with the conductive layer 260 in a plan view, a region located outside the conductive layer 260 and overlapping with the conductive layer 240a, and a region located outside the conductive layer 260 and overlapping with the conductive layer 240b ( FIGS. 21A , 21B , and 22 ). An opening 190 is formed in the insulating layer 180. Here, FIG. 21A shows a top view, and FIGS. 21B and 22 are cross-sectional views corresponding to the dashed-dotted lines C1-C2 and C3-C4 shown in FIG. 21A , respectively. The etching process is preferably performed under conditions that result in a low etching rate for the insulating layer 287. At this time, the region of the insulating layer 250 covered by the insulating layer 287 remains without being removed. Since the conductive layer 260 is covered by the insulating layer 287, it remains without being removed by the etching process. Furthermore, the region of the insulating layer 250 that is covered with the insulating layer 287 remains without being removed. It can be said that the insulating layer 287 functions as an etching stopper.

[0347] Also, Figure 21B shows an example in which the upper conductive layers (conductive layer 240a2, conductive layer 240b2) are removed in the areas of conductive layer 240a that are not covered by insulating layer 287 and in the areas of conductive layer 240b that are not covered by insulating layer 287.

[0348] Next, a conductive film 115f is formed in contact with the top surface of the insulating layer 180, the sidewall of the opening 190 of the insulating layer 180, the top surface of the insulating layer 287a, the top and side surfaces of the insulating layer 287b, the side surfaces of the insulating layer 250, the side surfaces of the conductive layer 240a2, the top surface of the conductive layer 240a1, the side surfaces of the conductive layer 240a2, and the top surface of the conductive layer 240a1 ( FIGS. 23A to 24 ). Here, FIG. 23A shows a top view, and FIGS. 23B and 24 are cross-sectional views corresponding to the dashed dotted lines C1-C2 and C3-C4 shown in FIG. 23A , respectively.

[0349] Subsequently, the conductive layers 115a and 115b are formed by removing a portion of the conductive film 115f, thereby exposing the upper surface of the insulating layer 287 in a region located between the conductive layers 115a and 115b in a plan view.

[0350] The region of the conductive film 115f located on the insulating layer 180 can be removed by planarization treatment using a chemical mechanical polishing (CMP) method, etch-back treatment using a dry etching method, or the like. Alternatively, wet etching may be used. These methods may also be combined.

[0351] In addition, when the conductive film 115 f is processed, it is preferable to process the conductive film 115 f so that the height of the top ends of the conductive layers 115 a and 115 b is lower than the height of the top surface of the insulating layer 180 .

[0352] Subsequently, an insulating layer 130 is formed over the conductive layer 115a, the conductive layer 115b, the insulating layer 287, and the insulating layer 180, and a conductive layer 120 is formed over the insulating layer 130, thereby manufacturing the semiconductor device shown in FIGS. 12A to 13A.

[0353] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0354] Embodiment 2 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. As the oxide semiconductor layer of one embodiment of the present invention, a layer containing a metal oxide can be used as a single layer or a stacked layer. Note that in an oxide semiconductor layer with a stacked structure, it may be difficult to identify boundaries between stacked films, as described later.

[0355] [Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0356] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Zn oxide, IAZO). Examples of usable metal oxides include indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), gallium tin oxide (Ga—Sn oxide), and aluminum tin oxide (Al—Sn oxide) can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, and the like can be used as the metal oxide according to one embodiment of the present invention.

[0357] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0358] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0359] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0360] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0361] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0362] A structural example of an oxide semiconductor layer capable of increasing the field-effect mobility of a transistor will be described. For example, it is preferable to use indium oxide or a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the oxide semiconductor layer has indium oxide and IGZO on the indium oxide. In addition, it is preferable to use IGZO containing nitrogen as the oxide semiconductor layer. For example, it is preferable to use IGZO containing nitrogen during or after film formation. ２ By performing O plasma treatment, IGZO containing nitrogen can be formed. For the oxide semiconductor layer, at least one of indium oxide, In—Ga oxide, In—Zn oxide, and IGZTO is preferably used.

[0363] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0364] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0365] Note that the crystallinity of the metal oxide included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0366] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0367] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution TEM image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0368] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is to be formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is to be formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the oxide semiconductor layer is to be formed.

[0369] When the oxide semiconductor layer has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0370] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0371] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0372] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0373] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to a surface on which the oxide semiconductor layer is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the oxide semiconductor layer has crystallinity.

[0374] [Composition of Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the oxide semiconductor layer, the on-state current of a transistor can be increased and frequency characteristics can be improved. For example, indium oxide is preferably used for the oxide semiconductor layer.

[0375] Furthermore, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, the metal oxide becomes a highly crystalline metal oxide, for example, a metal oxide having a CAAC structure. For example, an In—Zn oxide can be used for the oxide semiconductor layer. Specifically, a metal oxide having a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout can be used. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0376] Furthermore, the metal oxide according to one embodiment of the present invention can contain an element M. When the metal oxide contains the element M, oxygen vacancies can be suppressed from being formed in the metal oxide. Thus, the reliability of a transistor including an oxide semiconductor layer can be improved.

[0377] For example, the oxide semiconductor layer can be made of an In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereof can be used. Alternatively, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used.

[0378] The oxide semiconductor layer can be made of an In—Zn oxide containing an element M. Specifically, a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a composition thereof, an atomic ratio of In:M:Zn=1:1:1.2 or a composition thereof, an atomic ratio of In:M:Zn=1:1:0.5 or a composition thereof, an atomic ratio of In:M:Zn=1:1:2 or a composition thereof, an atomic ratio of In:M:Zn=4:2:3 or a composition thereof, an atomic ratio of In:M:Zn=1:3:2 or a composition thereof, or an atomic ratio of In:M:Zn=1:3:4 or a composition thereof can be used.

[0379] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0380] Furthermore, when forming a metal oxide containing multiple metal elements, such as In—Ga—Zn oxide, by atomic layer deposition (ALD), the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element may not match the atomic ratio of each metal element in the formed metal oxide.

[0381] The composition of the metal oxide used in the oxide semiconductor layer can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0382] The oxide semiconductor layer of one embodiment of the present invention may have a stacked structure of two or more layers. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the second layer preferably has a different composition from the first layer. When the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the second layer preferably has a different composition from the first layer and the third layer. Note that the first layer can have the same composition as the third layer. Alternatively, the first layer and the third layer can have different compositions.

[0383] The first to third layers may each be made of the metal oxides described above.

[0384] The second layer can be made of, for example, indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Zn=1:1 or a composition thereabout, an atomic ratio of In:Zn=2:1 or a composition thereabout, or an atomic ratio of In:Zn=4:1 or a composition thereabout can be used. For example, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereabout, an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereabout, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a composition thereabout can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used. Increasing the In content in the second layer can increase the on-current and improve the frequency characteristics.

[0385] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0386] By sandwiching the second layer between the first layer and the third layer, carriers trapped at and near the interface of the second layer can be reduced. Furthermore, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This allows for a buried channel transistor in which the channel is moved away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the effects of interface states that may form on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving transistor reliability.

[0387] For example, a band diagram of the oxide semiconductor layer 230a including the oxide semiconductor layers 230a1 to 230a3 and their vicinity shown in FIG. 25B is as shown in FIG. 31. In FIG. 31, the vertical axis represents energy, and the horizontal axis represents the film thickness direction at the center of the channel formation region. FIG. 31 also shows the valence band maximum (VBM) and the conduction band minimum (CBM) of the oxide semiconductor layer 230a1, the oxide semiconductor layer 230a2, the oxide semiconductor layer 230a3, the insulating layer 225, and the insulating layer 250 when no voltage is applied between the gate and the source. In FIG. 31, the vacuum level Vac is indicated by a dashed line.

[0388] Note that the energy of the upper end of the valence band and the energy of the lower end of the conduction band vary depending on the constituent elements and compositions of the oxide semiconductor layer 230a1, the oxide semiconductor layer 230a2, the oxide semiconductor layer 230a3, the insulating layer 225, and the insulating layer 250. Therefore, the relationship in height between the upper ends of the valence bands and the relationship in height between the lower ends of the conduction bands will be mainly described using the band diagram in FIG. 31 .

[0389] Depending on the constituent elements and compositions of the oxide semiconductor layers 230a1 to 230a3, the oxide semiconductor layer 230a2 may be sandwiched between the oxide semiconductor layers 230a1 and 230a3, whose conduction band minimums are closer to the vacuum level than the oxide semiconductor layer 230a2, as shown in FIG. 31 . This structure can realize a buried channel. That is, this structure forms a path through which more current (electrons are illustrated as carriers in FIG. 31 ) flows in the oxide semiconductor layer 230a2. Therefore, an increase in on-state current or improvement in reliability can be achieved.

[0390] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide having a higher Ga content than the second layer. Specifically, the first and third layers can each be made of a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can sometimes position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0391] Furthermore, increasing the Ga content in the first layer and the third layer can improve the barrier properties of the first layer and the third layer against hydrogen. Therefore, hydrogen diffusion from below the first layer or above the third layer to the second layer can be suppressed. Furthermore, increasing the Ga content in the first layer and the third layer can reduce impurities such as hydrogen or water contained in the oxide semiconductor layer due to heat or the like applied after the formation of the oxide semiconductor layer. Note that the same effect may be achieved by using a metal oxide having a lower In content than the second layer for the first layer and the third layer.

[0392] For example, the third layer preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, in which the third layer contains indium and gallium.

[0393] Furthermore, increasing the Ga content in the first layer and the third layer can improve the oxygen barrier properties of the first layer and the third layer. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0394] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As described above, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0395] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0396] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer. Alternatively, one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0397] The first layer, the second layer, and the third layer may each have a plurality of layers having the above-described compositions stacked together. For example, the first layer may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content. For example, the third layer may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0398] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0399] The oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by two different deposition methods. For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming a metal oxide by a first deposition method and a second deposition method.

[0400] The oxide semiconductor layer of one embodiment of the present invention can have a two-layer structure including a first layer and a second layer over the first layer. In the case where the oxide semiconductor layer has a two-layer structure, the oxide semiconductor layer can be manufactured by forming the first layer over a surface to be formed by a first film formation method and then forming the second layer thereover by a second film formation method.

[0401] The first deposition method is preferably a deposition method that causes less damage to the surface on which the oxide semiconductor layer is formed than the second deposition method. This can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is formed. Furthermore, impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, which can further increase the crystallinity of the oxide semiconductor layer.

[0402] Examples of the first film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that cause little damage to the surface on which the film is formed. A wet method can also be used as the first film formation method. The wet method is one of the film formation methods that cause little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0403] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the second film formation method.

[0404] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0405] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the second film formation method using a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the crystallization of the metal oxide may be inhibited by the inclusion of impurities such as silicon into the metal oxide. Furthermore, there is a concern that the use of an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when a heat treatment, which will be described later, is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0406] Therefore, as described above, by forming a metal oxide by the first film formation method before forming a metal oxide by the second film formation method, impurities can be prevented from being mixed into the oxide semiconductor layer. Furthermore, alloying with a layer on which the metal oxide is to be formed can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor layer can be further increased.

[0407] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the component contained in the first layer and the component contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, for example, when the indium content in the second layer is higher than the indium content in the first layer, the indium content in the mixed layer is equal to or greater than the indium content in the first layer and equal to or less than the indium content in the second layer.

[0408] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and by using the ALD method as the film formation method for the first layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, and the like with a high aspect ratio.

[0409] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. The crystallinity of the first layer may be increased by forming a second layer with high crystallinity on the first layer with low crystallinity or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which the oxide semiconductor layer is formed.

[0410] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to have crystallinity. Note that, when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide contained in the oxide semiconductor layer.

[0411] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0412] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0413] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0414] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0415] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a formation surface by an ALD method.

[0416] When an oxide semiconductor layer is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ ) or the like is used as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0417] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge excess reactant, reaction products, etc. from the reaction chamber.

[0418] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0419] The second layer is preferably formed by sputtering.

[0420] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0421] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0422] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0423] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0424] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the thickness of the alloyed region formed at the interface between the layer to be formed and the metal oxide can be reduced to an extent that it cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0425] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0426] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0427] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0428] For example, when SIMS analysis is performed on an oxide semiconductor layer formed on a silicon oxide film that is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0×10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0429] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0430] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer.

[0431] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0432] Furthermore, the oxide semiconductor layer of one embodiment of the present invention can have a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer.

[0433] When the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can be manufactured by forming a first layer on a surface to be formed by a first film formation method, forming a second layer by a second film formation method, and then forming a third layer by the first film formation method.

[0434] Even when the first layer and the third layer are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, the oxide semiconductor layer can have a structure in which the entire oxide semiconductor layer including the first layer and the third layer has the CAAC structure by crystal growth using the second layer as a nucleus. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the first layer and the third layer and the second layer.

[0435] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor layer can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0436] The first and third layers may be made of a metal oxide having the same composition as that of the second layer. Using the same composition may make it easier for the first and third layers to become CAAC after heat treatment.

[0437] Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0438] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0439] When the oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor layer, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0440] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0441] As described above, in the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first and third layers here) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown by solid-phase growth using the second layer as a nucleus or seed, thereby forming an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a deposition method, i.e., a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC).

[0442] In the oxide semiconductor layer, a region having a CAAC structure is preferably present widely throughout the layer. The region having the CAAC structure in the first layer is crystallinely connected to the region having the CAAC structure in the second layer. The region having the CAAC structure in the third layer is crystallinely connected to the region having the CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Furthermore, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor layer may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor layer may be expressed as a single layer.

[0443] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0444] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0445] In addition, when the oxide semiconductor layer has a three-layer structure, the oxide semiconductor layer can also be manufactured in such a manner that a first layer is formed on a surface to be formed by a first film formation method, a second layer is formed by the first film formation method, and a third layer is formed by the second film formation method.

[0446] As described above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, using a metal oxide with a high In content in the second layer in contact with the third layer can form a crystal that reflects the crystal orientation of the third layer.

[0447] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to have crystals that reflect the orientation of the crystals of the third layer. In this case, for example, in cross-sectional observation of the oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the second layer.

[0448] The crystal structure of the second layer is not particularly limited as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0449] In the above structure, typically, the first layer is a layer containing gallium oxide or a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout; the second layer is a layer containing indium oxide or a metal oxide containing a trace amount of the aforementioned element M; and the third layer is a layer containing a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

[0450] When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be improved. Furthermore, impurities (typically, moisture, etc.) that are introduced into the interface between the first layer and the second layer and the vicinity thereof can be reduced.

[0451] One or more of the first to third layers may have a stack of layers with different compositions. For example, the first layer may be formed by forming a layer containing a metal oxide with a high Ga content by the first film formation method, and then forming a layer containing a metal oxide with a higher In content than the first layer by the first film formation method.

[0452] After forming the layer by the first film formation method, it is preferable to perform microwave plasma treatment.

[0453] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0454] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the oxide semiconductor layer 230 can be reduced. Examples of impurities include hydrogen and carbon. Although the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0455] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0456] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0457] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0458] The shorter the processing time of the microwave plasma treatment, the more the oxidation of the conductive layer 220a, the conductive layer 220b, the conductive layer 240a, the conductive layer 240b, etc. can be suppressed. Also, the productivity increases. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0459] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. By the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the hydrogen impurities can be removed from the oxide semiconductor layer. ＯH can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0460] Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor will be described. First, activated species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the activated species and oxygen in the oxide semiconductor layer. Nuclei or seeds are formed. Lateral growth of the nuclei or seeds is also induced. It is preferable that the activated species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor.

[0461] On the other hand, a reaction occurs between part of oxygen present in the oxide semiconductor layer before the microwave plasma treatment and hydrogen in the oxide semiconductor layer, in other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove hydrogen from the oxide semiconductor layer. ２ The hydrogen concentration in the oxide semiconductor layer can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor layer can be further reduced by increasing the temperature during the microwave plasma treatment.

[0462] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0463] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0464] The crystallinity of the layer formed by the first film formation method can be increased, which can further increase the crystallinity of a layer formed over the layer, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0465] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer is preferably in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0466] After the oxide semiconductor layer is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer. The heat treatment here is not limited to heat treatment. For example, heat applied during a manufacturing process may be used.

[0467] The heat treatment temperature can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer (in other words, the crystalline molecules formed using the ALD method) formed using the first film formation method.

[0468] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0469] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer formed by the first film formation method. Furthermore, if the region is formed only below the third layer after the ALD film formation, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0470] Furthermore, it is preferable that at least a portion of the first layer or the second layer formed using the first film formation method is converted into CAAC by the heat treatment process. It is expected that the CAAC conversion is more likely to occur when the mixed layer formed in the first layer or the second layer during the formation of the layer formed using the second film formation method serves as a nucleus or seed. It is preferable that the region in the first layer or the second layer that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface on which it is formed.

[0471] Furthermore, because the CAAC is formed from the top to the bottom of the first layer or the second layer, the CAAC can be formed up to the vicinity of the layer regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the crystallinity of the first layer or the second layer can be increased. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC is formed has an amorphous structure.

[0472] As described above, by performing microwave plasma treatment and / or heat treatment, the crystallinity of the entire oxide semiconductor layer can be improved. Furthermore, impurities in the oxide semiconductor layer can be reduced. Crystal growth can be performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, thereby further improving the crystallinity.

[0473] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0474] Note that one or both of the microwave plasma treatment and the heat treatment may be performed directly on the oxide semiconductor layer, or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0475] Before forming the first layer or after forming the first layer or the second layer by the first film formation method, treatment for supplying oxygen to the first layer or the second layer may be performed, whereby oxygen can be supplied to the oxide semiconductor layer by heat or the like applied after the treatment.

[0476] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere, plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere, and the like. Alternatively, oxygen may be supplied to the first layer or the second layer formed by the first film formation method by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately after deposition, or may be left as it is. When the deposited oxide film is left as it is, the oxide film can be used as a layer (second layer or third layer) provided on the first layer or second layer. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing a compound gas containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0477] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor layer, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0478] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0479] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0480] The oxide semiconductor layer of one embodiment of the present invention can be formed by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor layer of one embodiment of the present invention can be formed without using the second film formation method. For example, by performing one or both of microwave plasma treatment and heat treatment after forming a first layer by the first film formation method, the crystallinity of the first layer can be increased. Therefore, the crystallinity of a second layer formed on the first layer by the first film formation method can be increased using the first layer as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the second layer, the crystallinity of the oxide semiconductor layer can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0481] As described above, even in a manufacturing method that does not use the second film formation method, the first layer formed by the first film formation method can be used as a nucleus or seed to cause solid-phase growth of the oxide semiconductor thereover, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method can also be referred to as an AG CAAC.

[0482] When the oxide semiconductor layer has a stacked structure of two or more layers, it can also be formed by forming a metal oxide using one type of film formation method. When the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the oxide semiconductor layer can be formed by, for example, forming the first layer and the second layer in this order by a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. For example, when the oxide semiconductor layer has a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer, the first layer to the third layer can also be formed by a sputtering method. Furthermore, some of the first layer to the third layer can also be formed by ALD. For example, one or both of the second layer and the third layer may be formed by ALD.

[0483] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of this embodiment can be used as a semiconductor layer of a transistor.

[0484] The oxide semiconductor layer in this embodiment can be used as the oxide semiconductor layer 230 or the like included in each transistor described in Embodiment 1. The layer that is a surface to be formed corresponds to the insulating layer 280 or the like described in Embodiment 1. For example, the first layer can be used as the oxide semiconductor layer 230a1, the second layer can be used as the oxide semiconductor layer 230a2, and the third layer can be used as the oxide semiconductor layer 230a3.

[0485] The oxide semiconductor layer of this embodiment preferably has a CAAC structure, in which metal atoms are arranged in layers in a direction parallel or substantially parallel to a surface on which the oxide semiconductor layer is formed.

[0486] It is estimated that an oxide semiconductor layer having a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. That is, it is estimated that in an oxide semiconductor layer having a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0487] In the semiconductor device described in the above embodiment, metal atoms are arranged in a layered manner in a direction parallel or substantially parallel to the surface on which the oxide semiconductor layer 230 is formed. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel or substantially parallel to the surface on which the oxide semiconductor layer 230 is formed. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0488] When the oxide semiconductor layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. In a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 20 nm, further preferably 3 nm to 15 nm, further preferably 5 nm to 12 nm, and further preferably 5 nm to 10 nm. The average thickness of the oxide semiconductor layer in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0489] The first layer preferably has a thickness of 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm. The first layer is further preferably 0.5 nm to 3 nm.

[0490] The first layer preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, or more preferably 0.5 nm to 3 nm, and even more preferably 0.5 nm to 2 nm.

[0491] The second layer preferably has a thickness of, for example, 200 nm or less. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0492] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0493] For the preferred range of the thickness of the third layer, see the description of the thickness of the first layer.

[0494] [Impurities in Oxide Semiconductor Layer] Here, the influence of each impurity in the oxide semiconductor layer will be described.

[0495] As described in the above embodiment, in a transistor including an oxide semiconductor in a semiconductor layer, oxygen vacancies (V Ｏ The presence of impurities such as hydrogen, carbon, and nitrogen can cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor layer is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor layer, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor layer refer to elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0496] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0497] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３The following applies.

[0498] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0499] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0500] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0501] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0502] 29 and 30. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0503] 26A shows the planar layout of the memory device shown in FIG. 8A, FIG. 12A, etc. The planar layout in FIG. 26A shows an area including 2×2 memory cells 150a and 2×2 memory cells 150b. Also shown are a conductive layer 255 functioning as a wiring WOL, a conductive layer 260 functioning as a wiring BGL, a conductive layer 240a functioning as a wiring BILa, a conductive layer 240b functioning as a wiring BILb, and an opening 290.

[0504] 26A , memory cell 150a is provided at the intersection of conductive layer 255 extending in the X direction and conductive layer 240a extending in the Y direction. Memory cell 150b is provided at the intersection of conductive layer 255 extending in the X direction and conductive layer 240b extending in the Y direction. As shown in FIG. 26A , the width of opening 290 can be made smaller than the width of the short side of conductive layer 255. In this way, memory cell 150a and memory cell 150b can be said to have a structure that allows for high integration and miniaturization.

[0505] FIG. 27 is a perspective view including a cross section corresponding to the three-dot chain line A1-A2 in the plan view shown in FIG. 26A.

[0506] 26A illustrates a configuration in which the conductive layer 260 extends in the Y direction, but the present invention is not limited to this. For example, as shown in FIG. 26B, the conductive layer 260 may extend in the X direction. This allows the conductive layer 260 to intersect with the conductive layer 240a or the conductive layer 240b, allowing the conductive layer 260 to function as a wiring WOL. In this case, the conductive layer 255 functions as a wiring BGL.

[0507] In the configuration shown in FIG. 26B, the conductive layer 255 may be provided extending in the Y direction.

[0508] In the structure shown in FIG. 26B , the top surfaces of the openings 290 and 190 each have a circular shape. Although FIG. 26B shows conductive layers 215a and 215b, when using the memory device shown in FIG. 12A or the like, the conductive layers 240a and 115a may overlap, and the conductive layer 115a may contact the top surface of the conductive layer 240a without using the conductive layer 215a. Alternatively, the conductive layers 240b and 115b may overlap, and the conductive layer 115b may contact the top surface of the conductive layer 240b without using the conductive layer 215b. The center of the circle of the opening 190 is shifted in the Y direction from the center of the circle of the opening 290. This allows the conductive layer 115a to overlap with a region of the conductive layer 240a (conductive layer 240b) that is not covered by the conductive layer 260.

[0509] 26B and the memory cell in the configuration of FIG. 28B described later can correspond to the circuit diagram shown in FIG. 28A. One of the conductive layer 255 and the conductive layer 260 can function as a wiring WOL, and the other can function as a wiring BGL. The conductive layer 220a can function as a wiring BILa, and the conductive layer 220b can function as a wiring BILb.

[0510] 28B illustrates an example in which the conductive layer 260 and the conductive layer 255 intersect with the Y direction at an angle greater than 0° and less than 90° in a plan view, and the transistor 200a of the memory cell 150a and the transistor 200b of the memory cell 150b are provided at the intersection of the conductive layer 260 and the conductive layer 220a (or the intersection of the conductive layer 255 and the conductive layer 220a) and the intersection of the conductive layer 260 and the conductive layer 220b (or the intersection of the conductive layer 255 and the conductive layer 220b). The angle at which the conductive layer 260 and the conductive layer 255 intersect with the Y direction is, for example, 15° to 75°.

[0511] Although the above description has been given of a configuration in which the memory cell 150a and the memory cell 150b each include a transistor and a capacitor, the present invention is not limited to this. The memory cell 150a and the memory cell 150b may include a transistor instead of a capacitor. In this case, the memory cell 150a and the memory cell 150b each include two transistors. Here, the upper transistor is referred to as the first transistor, and the lower transistor is referred to as the second transistor.

[0512] One of a source electrode and a drain electrode of the first transistor is connected to a gate electrode of the second transistor. The first transistor can be any of the transistors exemplified in Embodiment 1. The second transistor can be a planar transistor, a vertical transistor, a Fin transistor, a GAA transistor, or the like.

[0513] For the circuit configuration of a memory cell having a first transistor and a second transistor, refer to the circuit configuration example shown in Fig. 32D or 32E. For example, the first transistor corresponds to the transistor M2 shown in Fig. 32D or 32E, and the second transistor corresponds to the transistor M3 shown in Fig. 32D or 32E.

[0514] <Configuration Example 3 of Memory Device> The memory cell described in this embodiment can be used as a memory cell of a memory device. The transistor included in the memory cell is preferably an OS transistor. Because an OS transistor has a low off-state current, its use in a memory device allows stored data to be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, the memory device can be highly integrated and its power consumption can be reduced. Furthermore, the high frequency characteristics of an OS transistor enable high-speed reading and writing to and from the memory device.

[0515] A memory cell array can be configured by arranging memory cells in a three-dimensional matrix.

[0516] 29 shows an example in which n memory cells are stacked in layers (n is an integer of 3 or more) in the Z direction. The B1-B2 direction and the B1-B3 direction shown in Fig. 29 are cross sections corresponding to the dashed dotted lines shown in Fig. 28B. The B1-B3 direction shown in Fig. 29 is parallel to the Y direction, and the region shown between C1 and C3 includes the region in which the conductive layer 220 extends.

[0517] The memory device shown in FIG. 29 has n memory layers 160. Specifically, a memory layer 160[2] is provided on the memory layer 160[1], and (n-2) memory layers are further provided on the memory layer 160[2], with the memory layer 160[n] provided at the top. The number of memory cells included in one memory layer 160 is not particularly limited, and the memory layer 160 may have two or more memory cells. The conductive layers 245, 246, and 247 connect the memory cells included in the n memory layer 160 to a sense amplifier (not shown) provided below the n memory layer 160. In this case, the conductive layers 245, 246, and 247 function as part of the wiring BILa or the wiring BILb. In this way, by providing a memory device above or below the memory device, the memory capacity per unit area can be increased.

[0518] Note that the conductive layer 245, the conductive layer 246, the conductive layer 247, etc. may function as plugs or wirings for connecting circuit elements, wirings, electrodes, or terminals such as switches, transistors, capacitors, inductors, resistors, and diodes to memory cells.

[0519] 29 shows an example in which the conductive layer 245 is in contact with the bottom surface of the conductive layer 220 and the conductive layer 246 is in contact with the top surface of the conductive layer 220. The conductive layer 245 is disposed in an opening formed in the insulating layer 210 and the insulating layer thereunder, and is in contact with the bottom surface of the conductive layer 220. The conductive layer 246 is disposed in an opening formed in the insulating layer 280, the insulating layer 281, the insulating layer 250, the insulating layer 288, the insulating layer 105, the insulating layer 180, the insulating layer 130, and the insulating layer 181, and is in contact with the top surface of the conductive layer 220. Note that the conductive layers 245, 246, 247, and the like can be formed using a conductive material that can be used for the conductive layer 220.

[0520] Note that various modes are possible for the connection points between plugs such as the conductive layer 245 and the conductive layer 246 and each memory cell, and are not limited to the configuration shown in FIG. 29 . For example, the conductive layer 246 may be in contact with the top surface of the conductive layer 220a1. That is, the conductive layer 220a2 may have an opening at a position overlapping with the conductive layer 246. As the connection points between the memory cell and the plug, it is preferable that, among the layers constituting the conductive layer 220, a layer having low contact resistance with the conductive layer 246 be in contact with the conductive layer 246. It is also preferable that, among the layers constituting the conductive layer 220, a layer having low wiring resistance be in contact with the conductive layer 245 and the conductive layer 246.

[0521] 29, by stacking multiple memory cells, cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured. This allows for a larger memory capacity per unit area.

[0522] FIG. 30 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided.

[0523] In FIG. 30, a memory cell 150 a (a transistor 200 a and a capacitor 100 a ) and a memory cell 150 b (a transistor 200 b and a capacitor 100 b ) are provided above a transistor 300 .

[0524] The transistor 300 is one of the transistors included in the sense amplifier.

[0525] For the memory cell 150a and the memory cell 150b shown in FIG. 30, reference can be made to the descriptions of the memory cell 150a and the memory cell 150b shown in the previous embodiment and the memory cell 150a and the memory cell 150b shown in FIGS. 28B and 29B.

[0526] 30, the bit lines can be shortened by providing sense amplifiers so as to overlap memory cells 150a and 150b, thereby reducing the bit line capacitance and enabling high-speed operation of the memory device.

[0527] 30 can correspond to the semiconductor device 900 described in Embodiment 4. Specifically, the transistor 300 corresponds to a transistor included in the sense amplifier 927 in the semiconductor device 900. The memory cell 150a and the memory cell 150b correspond to the memory cell 950.

[0528] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0529] Here, in the transistor 300 shown in FIG. 30 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0530] Note that the transistor 300 illustrated in FIG. 30 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0531] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0532] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0533] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0534] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 30, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0535] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a semiconductor device or a memory device.

[0536] Conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, can be formed using a conductive material applicable to the conductive layer 240a and the conductive layer 240b. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0537] The conductive layer 220a of the transistor 200a is connected to the low-resistance region 314b functioning as a source or drain region of the transistor 300 through the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0538] The conductive layer 646 is embedded in an insulating layer 649 .

[0539] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0540] Embodiment 4 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0541] Fig. 31 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 31 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 31 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0542] The memory cell 950 can be any of the memory devices described in Embodiment 3 (such as the memory cell 150a and the memory cell 150b).

[0543] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0544] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0545] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0546] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0547] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0548] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0549] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0550] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0551] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 31, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0552] 32A to 32F, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0553] 32A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0554] The transistor M1 has a gate (sometimes referred to as a top gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0555] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to the wiring BIL, a gate of the transistor M1 is connected to the wiring WOL, a back gate of the transistor M1 is connected to the wiring BGL, and a second terminal of the capacitor CA is connected to the wiring CAL.

[0556] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0557] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0558] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 may be a memory cell in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell 950 may be a memory cell configured with a single-gate transistor, that is, a transistor M1 that does not have a back gate. For example, the memory cell 951 may not include the capacitor CA and the wiring CAL, and the first terminal of the transistor M1 may be electrically floating.

[0559] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely small off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951.

[0560] 32B shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0561] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0562] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0563] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0564] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0565] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 32C . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0566] 32D is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 32E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0567] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0568] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0569] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, each of which uses an OS transistor as the transistor M2, are one embodiment of an NOSRAM.

[0570] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0571] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0572] 32F shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0573] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, the gate of the transistor M4 is connected to the wiring WOL, and the back gate of the transistor M4 is connected to the wiring BGL. The second terminal of the capacitor CC is connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0574] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0575] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0576] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0577] Note that at least the transistor M4 is preferably an OS transistor.

[0578] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0579] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0580] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the s...

Claims

a first insulating layer, a first transistor, a second transistor, and a second insulating layer on the first insulating layer, a first capacitance element, a second capacitance element, a third insulating layer, and a fourth insulating layer; the first capacitive element is located on the first transistor; the second capacitive element is located on the second transistor; the first transistor includes a first conductive layer, a first oxide semiconductor layer, a fifth insulating layer, and a second conductive layer; the second transistor includes a third conductive layer, a second oxide semiconductor layer, the fifth insulating layer, and the second conductive layer; the first conductive layer and the third conductive layer are provided on the first insulating layer and spaced apart from each other; the third insulating layer has a first region provided in contact with an upper surface of the second conductive layer; the second insulating layer has a first opening; the first opening has a region overlapping with the first conductive layer, a region overlapping with the third conductive layer, and a region located between the first conductive layer and the third conductive layer and overlapping with the first insulating layer; the first oxide semiconductor layer and the second oxide semiconductor layer have regions provided along sidewalls of the first opening; the fifth insulating layer is located on the first conductive layer and the third conductive layer; the second conductive layer is located on the fifth insulating layer; the fifth insulating layer has a region overlapping with the sidewall of the first opening with the first oxide semiconductor layer sandwiched therebetween, and a region overlapping with the sidewall of the first opening with the second oxide semiconductor layer sandwiched therebetween; the first capacitance element has a fourth conductive layer, a sixth insulating layer, and a fifth conductive layer; the second capacitive element has a sixth conductive layer, the sixth insulating layer, and the fifth conductive layer; the fourth conductive layer and the sixth conductive layer are provided on the third insulating layer and spaced apart from each other; the fifth conductive layer has a second region overlapping the fourth conductive layer with the sixth insulating layer therebetween, and a third region overlapping the sixth conductive layer with the sixth insulating layer therebetween; the second region is located on the fourth conductive layer; the third region is located on the sixth conductive layer; the fourth insulating layer has a second opening; the fourth conductive layer and the sixth conductive layer each have a region provided along a sidewall of the second opening, The semiconductor device, wherein the first opening and the second opening have an overlapping region in a plan view. 　 In claim 1, the third insulating layer has a fourth region provided in contact with a side surface of the second conductive layer, the fourth conductive layer has a region overlapping a side surface of the second conductive layer with the fourth region of the third insulating layer sandwiched therebetween, the sixth conductive layer has a region overlapping a side surface of the second conductive layer with the fourth region of the third insulating layer sandwiched therebetween. 　 In claim 1, the first transistor has a seventh conductive layer on the second insulating layer; the first oxide semiconductor layer has a region in contact with an upper surface of the first conductive layer and a region in contact with an upper surface of the seventh conductive layer; the second transistor has an eighth conductive layer on the second insulating layer; the second oxide semiconductor layer has a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the eighth conductive layer; the fourth conductive layer has a region overlapping with the seventh conductive layer in a plan view, The sixth conductive layer has a region that overlaps with the eighth conductive layer in a plan view. 　 In claim 3, the fourth conductive layer has a region in contact with an upper surface of the seventh conductive layer and a region overlapping a side surface of the second conductive layer with the third insulating layer interposed therebetween; the sixth conductive layer has a region in contact with an upper surface of the eighth conductive layer and a region overlapping a side surface of the second conductive layer with the third insulating layer sandwiched therebetween. 　 In claim 3, a ninth conductive layer and a tenth conductive layer; the fourth conductive layer and the seventh conductive layer are connected via the ninth conductive layer, the sixth conductive layer and the eighth conductive layer are connected via the tenth conductive layer; the ninth conductive layer has a region in contact with an upper surface of the seventh conductive layer and a region overlapping a side surface of the second conductive layer with the third insulating layer interposed therebetween; the tenth conductive layer has a region in contact with an upper surface of the eighth conductive layer and a region overlapping a side surface of the second conductive layer with the third insulating layer interposed therebetween. 　 a first insulating layer; a first transistor, a second transistor, and a second insulating layer on the first insulating layer; a third insulating layer on the second insulating layer; a first capacitance element on the first transistor; and a second capacitance element on the second transistor; the first transistor has a first semiconductor layer, a fourth insulating layer, a first conductive layer, a second conductive layer on the first insulating layer, and a third conductive layer on the third insulating layer; the second transistor has a second semiconductor layer, a fifth insulating layer, the first conductive layer, a fourth conductive layer on the first insulating layer, and a fifth conductive layer on the third insulating layer; the first conductive layer is located between the second insulating layer and the third insulating layer; the second conductive layer and the fourth conductive layer are provided on the first insulating layer and spaced apart from each other; the second insulating layer, the first conductive layer, and the third insulating layer each have an opening; the opening of the second insulating layer and the opening of the first conductive layer overlap each other in a plan view; the opening in the third insulating layer and the opening in the first conductive layer overlap each other in a plan view; the first semiconductor layer faces side surfaces of the openings of the second insulating layer, the first conductive layer, and the third insulating layer, with the fourth insulating layer sandwiched therebetween; the first semiconductor layer has a region in contact with an upper surface of the second conductive layer and a region in contact with an upper surface of the third conductive layer; the second semiconductor layer faces side surfaces of the openings of the second insulating layer, the first conductive layer, and the third insulating layer, with the fifth insulating layer sandwiched therebetween; the second semiconductor layer has a region in contact with an upper surface of the fourth conductive layer and a region in contact with an upper surface of the fifth conductive layer; the first capacitance element has a sixth conductive layer, a seventh conductive layer, and a sixth insulating layer; the second capacitive element has an eighth conductive layer, the seventh conductive layer, and the sixth insulating layer; a sixth insulating layer having a region located between the sixth conductive layer and the seventh conductive layer, and a region located between the eighth conductive layer and the seventh conductive layer; 　 In claim 6, a seventh insulating layer on the first transistor and on the second transistor; the seventh insulating layer has a second opening; the sixth conductive layer and the eighth conductive layer each have a region provided along a sidewall of the second opening, The semiconductor device, wherein the opening and the second opening have an overlapping region in a plan view.

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