Semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The semiconductor device comprises a transistor. The transistor has a lower electrode and an upper electrode. A first interlayer film is provided between the lower electrode and the upper electrode. The first interlayer film has a groove that reaches the lower electrode. A gate electrode, a gate insulating layer, and a metal oxide layer functioning as a semiconductor layer of the transistor each have region positioned in the groove. The gate insulating layer has ferroelectricity. A second interlayer film is provided on the gate electrode, and a bit line is provided on the second interlayer film. The bit line is connected to the upper electrode. The groove and the gate electrode extend in a first direction. The bit line extends in a second direction which is perpendicular or substantially perpendicular to the first direction.

Description

Semiconductor Devices

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing units (CPU), and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories of various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics is being actively carried out. For next-generation ferroelectric memories, ferroelectric HfO ２ Research on Hf-based materials (Non-Patent Document 2),０．５ Zr ０．５ O ２ Research on ferroelectricity of thin films (Non-Patent Document 3), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 4), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) and CMOS using hafnium oxide (Non-Patent Document 5).

[0006] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011 Zhen Fan, et al. , “Ferroelectric HfO▲2▼-based materials for next-generation ferroelectric memories”, JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016Jun Okuno, et al. , "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf 0.5 Zr 0.5 O 2 ", VLSI 2020. Akira Toriumi, "Ferroelectricity of HfO 2 thin film", The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. T. Francois, et al. , “Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”, IEDM 2019

[0007] An object of one embodiment of the present invention is to provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a highly reliable transistor, a semiconductor device, or a memory device.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device with a high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device or a memory device including a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, the semiconductor device, or the memory device.

[0008] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0009] One embodiment of the present invention provides a transistor and a first insulating layer. The transistor includes a metal oxide layer, a first conductive layer, a second conductive layer, a third conductive layer, and a second insulating layer. The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer. The first insulating layer has a groove that reaches the first conductive layer. The metal oxide layer has a region that contacts a top surface of the second conductive layer, a region that contacts a side surface of the first insulating layer in the groove, and a region that contacts the first insulating layer in the groove. The second insulating layer has a region that overlaps with a side surface of the first insulating layer within the groove via a metal oxide layer, and a region that overlaps with the first conductive layer within the groove via the metal oxide layer, and the third conductive layer has a region that overlaps with a side surface of the first insulating layer within the groove via the second insulating layer and the metal oxide layer, and a region that overlaps with the first conductive layer within the groove via the second insulating layer and the metal oxide layer, and the second insulating layer has ferroelectricity.

[0010] Alternatively, in the above aspect, the semiconductor device has a third insulating layer and a fourth conductive layer, the third insulating layer is located on the third conductive layer and the second insulating layer, the fourth conductive layer is located on the third insulating layer, the fourth conductive layer is electrically connected to the second conductive layer, the groove portion extends in a first direction in a planar view, and the fourth conductive layer extends in a second direction in a planar view, the second direction being perpendicular or approximately perpendicular to the first direction.

[0011] Alternatively, in the above aspect, the third conductive layer may extend in the first direction in plan view. The second insulating layer may contain, for example, hafnium and zirconium. The third conductive layer may contain, for example, titanium and nitrogen. The metal oxide layer functioning as a semiconductor layer preferably contains at least one of indium and zinc.

[0012] One embodiment of the present invention can provide a transistor, a semiconductor device, or a memory device that can be miniaturized or highly integrated. One embodiment of the present invention can provide a highly reliable transistor, a semiconductor device, or a memory device. One embodiment of the present invention can provide a semiconductor device or a memory device with low power consumption. One embodiment of the present invention can provide a semiconductor device or a memory device with high operating speed. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with favorable electrical characteristics. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with high on-state current. One embodiment of the present invention can provide a semiconductor device or a memory device including a transistor with low parasitic capacitance. One embodiment of the present invention can provide a manufacturing method of the above transistor, semiconductor device, or memory device.

[0013] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0014] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIG. 1B is a circuit diagram illustrating an example of a semiconductor device. FIG. 2 is a circuit diagram illustrating an example of a semiconductor device. FIGS. 3A to 3C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 4A to 4C are perspective views illustrating an example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views illustrating an example of a semiconductor device. FIG. 6 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 7A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 7B and 7C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 8A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 8B and 8C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 9A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 9B and 9C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 10B and 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11B and 11C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12B and 12C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13B and 13C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14B and 14C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15B and 15C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16B and 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17B and 17C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 18 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 19 is a cross-sectional view illustrating an example of a semiconductor device. FIG. 20 is a graph illustrating an example of hysteresis characteristics. FIG. 21 is a diagram illustrating the crystal structure of hafnium oxide.22A and 22B are diagrams illustrating a model of the orthorhombic crystal structure of HfZrOx. FIGS. 23A and 23B are equivalent circuit diagrams of a memory cell. FIG. 23C is a diagram illustrating the Id-Vg characteristics of a transistor. FIG. 24A is a timing chart illustrating the operation of a memory cell. FIG. 24B is a circuit diagram illustrating the operation of a memory cell. FIG. 25A is a timing chart illustrating the operation of a memory cell. FIG. 25B is a circuit diagram illustrating the operation of a memory cell. FIG. 26A is a timing chart illustrating the operation of a memory cell. FIGS. 26B and 26C are circuit diagrams illustrating the operation of a memory cell. FIG. 27 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 28A to 28G are diagrams illustrating a circuit configuration example of a memory cell. FIGS. 29A and 29B are perspective views illustrating a configuration example of a semiconductor device. FIG. 30 is a block diagram illustrating a CPU. FIGS. 31A and 31B are perspective views of a semiconductor device. FIGS. 32A and 32B are perspective views of a semiconductor device. Fig. 33 is a conceptual diagram explaining the hierarchy of a storage device. Figs. 34A and 34B are configuration examples of electronic components. Figs. 35A to 35C are configuration examples of mainframe computers. Fig. 36A is a configuration example of space equipment. Fig. 36B is a configuration example of a storage system.

[0015] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0016] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0017] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0018] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0019] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0020] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an "OS transistor." Also, a transistor having silicon for a channel formation region may be referred to as a "Si transistor."

[0021] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0022] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0023] Note that impurities in a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen deficiency (V) in the metal oxide. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0024] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0025] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0026] In this specification, the term "content" refers to the ratio of a component contained in a film. For example, if a metal oxide layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide layer is A, then the number of atoms of each of metal elements X, Y, and Z is A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0027] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0028] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0029] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0030] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0031] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0032] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0033] Unless otherwise specified, in this specification, the off-state current refers to a leakage current between the source and drain of a transistor when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage Vth (or higher than Vth for a p-channel transistor).

[0034] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0035] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0036] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0037] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0038] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0039] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other, i.e., directions that are perpendicular to each other. In this specification and the like, the X direction may be referred to as the row direction, and the Y direction may be referred to as the column direction.

[0040] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0041] 1A is a plan view illustrating an example of a semiconductor device of one embodiment of the present invention. The semiconductor device illustrated in FIG. 1A includes a transistor 200 that functions as a memory cell 150. Note that some elements are omitted in the plan view of FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views.

[0042] 1B is an equivalent circuit diagram of the semiconductor device illustrated in FIG. 1A. As illustrated in FIG. 1B, in the semiconductor device of one embodiment of the present invention, transistors 200 functioning as memory cells 150 are arranged in a matrix. Therefore, the semiconductor device of one embodiment of the present invention can function as a memory device.

[0043] An FeFET (Ferroelectric Field Effect Transistor) using a material capable of having ferroelectricity for the gate insulating film is used as the transistor 200. By using an FeFET as the transistor 200, one memory element can be realized with one transistor 200. Therefore, the memory density of the memory device can be increased.

[0044] 1A and 1B show memory cells 150 arranged in three rows and three columns. In Fig. 1B, the memory cells 150 in the first row and first column, the second row and second column, the third row and first column, the second row and second column, the third row and third column, the first row and first column, the second row and second column, and the third row and third column are shown as memory cell 150[1,1], memory cell 150[1,2], memory cell 150[1,3], memory cell 150[2,1], memory cell 150[2,2], memory cell 150[2,3], memory cell 150[3,1], memory cell 150[3,2], and memory cell 150[3,3], respectively.

[0045] One of the source and the drain of the transistor 200 functioning as the memory cell 150 is connected to a wiring SL. The other of the source and the drain of the transistor 200 is connected to a wiring BL. A gate of the transistor 200 is connected to a wiring WL.

[0046] The wiring BL functions as a bit line, the wiring WL functions as a word line, and the wiring SL functions as a power supply line. Here, memory cells 150 in the same column are connected to the same wiring BL and wiring SL. In FIG. 1B , the wiring BL connected to the memory cell 150[1,1], the memory cell 150[2,1], and the memory cell 150[3,1] is referred to as wiring BL[1]. The wiring BL connected to the memory cell 150[1,2], the memory cell 150[2,2], and the memory cell 150[3,2] is referred to as wiring BL[2]. The wiring BL connected to the memory cell 150[1,3], the memory cell 150[2,3], and the memory cell 150[3,3] is referred to as wiring BL[3].

[0047] Similarly, the wiring SL connected to the memory cell 150[1,1], the memory cell 150[2,1], and the memory cell 150[3,1] is referred to as wiring SL[1]. The wiring SL connected to the memory cell 150[1,2], the memory cell 150[2,2], and the memory cell 150[3,2] is referred to as wiring SL[2]. The wiring SL connected to the memory cell 150[1,3], the memory cell 150[2,3], and the memory cell 150[3,3] is referred to as wiring SL[3].

[0048] The memory cells 150 in the same row are connected to the same wiring WL. Here, the wiring WL connected to the memory cell 150[1,1], the memory cell 150[1,2], and the memory cell 150[1,3] is referred to as wiring WL[1]. The wiring WL connected to the memory cell 150[2,1], the memory cell 150[2,2], and the memory cell 150[2,3] is referred to as wiring WL[2]. The wiring WL connected to the memory cell 150[3,1], the memory cell 150[3,2], and the memory cell 150[3,3] is referred to as wiring WL[3].

[0049] 1A and 1B show a case where the extension directions of the wiring WL and the wiring BL intersect, the extension directions of the wiring WL and the wiring SL intersect, and the extension directions of the wiring BL and the wiring SL are the same. However, as shown in FIG. 2, the extension directions of the wiring BL and the wiring SL can intersect. In this case, memory cells 150 in the same row are connected to the same wiring SL. In FIG. 2, the wiring SL connected to the memory cell 150[1,1], the memory cell 150[1,2], and the memory cell 150[1,3] is referred to as wiring SL[1]. The wiring SL connected to the memory cell 150[2,1], the memory cell 150[2,2], and the memory cell 150[2,3] is referred to as wiring SL[2]. The wiring SL connected to the memory cell 150[3,1], the memory cell 150[3,2], and the memory cell 150[3,3] is referred to as wiring SL[3].

[0050] Fig. 3A is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Fig. 1A, Fig. 3B is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Fig. 1A, and Fig. 3C is a cross-sectional view of the portion indicated by the dashed line B1-B2 in Fig. 1A.

[0051] 4A, 4B, and 4C are perspective views illustrating an example of a semiconductor device according to one embodiment of the present invention. Parts of the configuration illustrated in FIG. 4A are removed in FIG. 4B and FIG. 4C. FIG. 4B includes an example cross-sectional configuration taken along dashed lines A1-A2 in FIG. 1A and FIG. 3A. FIG. 4C includes an example cross-sectional configuration taken along dashed lines B1-B2 in FIG. 1A and FIG. 3C.

[0052] The semiconductor device shown in FIGS. 1A to 4C includes an insulating layer 180 on a substrate (not shown), a conductive layer 120 on the insulating layer 180, an insulating layer 280 on the conductive layer 120, a transistor 200, an insulating layer 285 on the transistor 200, and a conductive layer 245 on the transistor 200 and the insulating layer 285.

[0053] The conductive layer 120 functions as a wiring SL. The conductive layer 245 extends in the X direction and functions as a wiring BL. The insulating layer 180, the insulating layer 280, and the insulating layer 285 function as interlayer films.

[0054] The transistor 200 includes a conductive layer 120, a conductive layer 240 over an insulating layer 280, a metal oxide layer 230 over the conductive layer 120 and the conductive layer 240, an insulating layer 250 over the metal oxide layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is provided over the conductive layer 120.

[0055] The metal oxide layer 230 functions as a semiconductor layer of the transistor 200. The conductive layer 260 functions as a gate electrode of the transistor 200. The insulating layer 250 functions as a gate insulating layer of the transistor 200. The conductive layer 120 functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 240 functions as the other of the source electrode and the drain electrode of the transistor 200. Here, the conductive layer 260 is provided to extend in the Y direction. The conductive layer 260 functions as a wiring WL.

[0056] As shown in Figures 1A, 3A, 3B, etc., the insulating layer 280 has a groove 290. The groove 290 has a region that penetrates the conductive layer 240 and the insulating layer 280 and reaches the conductive layer 120. The groove 290 extends in a direction parallel to the extension direction of the conductive layer 260. That is, the groove 290 extends in the Y direction, similar to the conductive layer 260. As described above, the conductive layer 245 extends in the X direction. As a result, the conductive layer 245 intersects with the groove 290 and the conductive layer 260 in a planar view, for example, perpendicularly or approximately perpendicularly to them.

[0057] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0058] At least a portion of the components of the transistor 200 is disposed within the groove 290. Specifically, the metal oxide layer 230, the insulating layer 250, and the conductive layer 260 are disposed such that at least a portion of each of them is located within the groove 290. Note that the transistors 200 included in the memory cells 150 in the same column have regions located within the same groove 290.

[0059] Each transistor 200 has two conductive layers 240 that are provided to face each other across a groove 290 in a plan view. One conductive layer 240 is shared between two transistors 200 adjacent to each other in the X direction. This allows the other of the sources and drains of the two transistors 200 to be connected to each other.

[0060] The metal oxide layer 230 has a region in contact with the top surface of the conductive layer 120 within the groove 290, a region in contact with the side surface of the conductive layer 240, a region in contact with the side surface of the groove 290, and a region in contact with the top surface of the conductive layer 240 outside the groove 290. The region of the metal oxide layer 230 in contact with the conductive layer 120 functions as one of the source region and the drain region of the transistor 200. The region of the metal oxide layer 230 in contact with the conductive layer 240 functions as the other of the source region and the drain region of the transistor 200. The region of the metal oxide layer 230 along the side surface of the groove 290 functions as the channel formation region of the transistor 200. In other words, the region of the metal oxide layer 230 along the side surface of the insulating layer 280 functions as the channel formation region of the transistor 200.

[0061] 3A shows an example in which the metal oxide layer 230 is shared among a plurality of transistors 200 adjacent to each other in the X direction, the metal oxide layer 230 may be separated among the transistors 200. In other words, the metal oxide layer may be provided in an island shape.

[0062] The insulating layer 250 is provided in the groove portion 290 so as to cover the metal oxide layer 230. The insulating layer 250 has a recess at a position overlapping the groove portion 290. Note that although an example in which the insulating layer 250 is shared by all the transistors 200 is shown in FIGS. 3A to 3C , the insulating layer 250 does not have to be shared by the transistors 200 adjacent to each other in the X direction, for example. For example, the insulating layer 250 can be processed so that its shape in plan view is the same as or approximately the same as the conductive layer 260.

[0063] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region in the groove 290 that faces the metal oxide layer 230 with the insulating layer 250 sandwiched therebetween.

[0064] As described above, the metal oxide layer 230 is provided in the groove 290. Furthermore, in the transistor 200, one of the source electrode and the drain electrode (here, the conductive layer 120) is located at the bottom, and the other of the source electrode and the drain electrode (here, the conductive layer 240) is located at the top. In other words, the source electrode and the drain electrode of the transistor 200 are located at different positions in the Z direction. The channel of the transistor 200 is formed along the sidewall of the groove 290. It can also be said that the channel of the transistor 200 is formed along the side surface of the insulating layer 280. Therefore, the transistor 200 has a configuration in which the drain current flows mainly in the vertical direction. That is, the channel length direction of the transistor 200 mainly includes a component along the Z direction. Such a transistor is also called a "vertical channel transistor," "vertical channel transistor," "vertical transistor," or "VFET (Vertical Field Effect Transistor)."

[0065] With the above configuration, a channel formation region, a source region, and a drain region can be formed in the groove 290. As a result, the transistor 200, which is a vertical transistor, can occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Using a vertical transistor in a semiconductor device allows for miniaturization or high integration.

[0066] Furthermore, it is preferable to use an oxide semiconductor for the semiconductor layer of a vertical transistor. For example, when silicon, a typical semiconductor material, is used, impurities that function as donors or acceptors must be doped into the semiconductor layer to form source and drain regions. When silicon is used for the semiconductor layer of a vertical transistor, it is difficult to dope impurities into the semiconductor layer with high precision because the channel formation region is formed vertically relative to the substrate surface and the source and drain regions are at different heights. On the other hand, when an oxide semiconductor is used, low-resistance regions that function as source or drain regions can be formed without doping with such impurities. Therefore, using an oxide semiconductor for the semiconductor layer can reduce the number of manufacturing steps for a transistor. This allows transistors to be manufactured with a high yield. This can increase the productivity of transistors.

[0067] The insulating layer 285 is located on the conductive layer 260 and the insulating layer 250. Portions of the insulating layer 285, the insulating layer 250, and the metal oxide layer 230 are removed to provide an opening 270 that reaches the conductive layer 240. A conductive layer 244 is provided in the opening 270. For example, the conductive layer 244 is provided so as to be embedded in portions of the insulating layer 285, the insulating layer 250, and the metal oxide layer 230. The conductive layer 244 may have a region in contact with the conductive layer 240 within the opening 270. Note that, for example, when the metal oxide layer 230 and the insulating layer 250 are not shared between multiple transistors 200 adjacent in the X direction, the opening 270 may not be provided in the metal oxide layer 230 and the insulating layer 250.

[0068] The conductive layer 245 is provided over the insulating layer 285 and the conductive layer 244, and has a region in contact with the top surface of the conductive layer 244. This allows the conductive layer 245 to be connected to the conductive layer 244. The conductive layer 240 and the conductive layer 245 are connected to each other through the conductive layer 244. As described above, the conductive layer 245 is provided extending in the X direction. The conductive layer 245 functions as a source wiring or a drain wiring. Specifically, when the conductive layer 240 functions as a source electrode, the conductive layer 245 functions as a source wiring, and when the conductive layer 240 functions as a drain electrode, the conductive layer 245 functions as a drain wiring. By providing the conductive layer 245 extending in the X direction, the conductive layers 240 of the multiple transistors 200 arranged in the X direction can be connected to each other. Note that it is preferable that the top surfaces of the conductive layer 244 and the insulating layer 285 are aligned or approximately aligned when viewed from the X direction or the Y direction.

[0069] FIG. 5A is an expanded view of transistor 200 shown in FIG. 3A.

[0070] The channel length L of the transistor 200 is the distance between the source region and the drain region in the metal oxide layer 230. The channel length L of the transistor 200 can also be referred to as the distance in the Z direction from the top surface of the conductive layer 120 to the bottom surface of the conductive layer 240 (see FIG. 5A).

[0071] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the thickness of the insulating layer 280, etc. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0072] Note that the channel length L of the transistor 200 is determined by the film thickness of the insulating layer 280 and the like. Therefore, the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the groove 290 and the like.

[0073] The channel length L of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0074] 5A shows an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. Also, an example in which the conductive layer 120 has a two-layer structure including a conductive layer 120_1 and a conductive layer 120_2 over the conductive layer 120_1. Furthermore, an example in which the conductive layer 260 has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1 is shown.

[0075] 5A illustrates a configuration in which the upper surface of the conductive layer 120 has a recess. Specifically, the upper surface of the conductive layer 120_2 has a recess. The bottom surface of the recess corresponds to a part of the bottom surface of the groove 290. The side surface of the recess corresponds to a part of the sidewall of the groove 290.

[0076] Therefore, the bottom of the groove 290 includes the bottom surface of the recess of the conductive layer 120_2. The sidewall of the groove 290 includes the side surface of the recess of the conductive layer 120_2 and the side surface of the insulating layer 280. It can also be said that the recess of the conductive layer 120_2 is provided at a position overlapping with the groove 290.

[0077] By providing a recess at a position where the conductive layer 120_2 overlaps with the groove 290, the positions of the bottom surfaces of the insulating layer 250 and the conductive layer 260 in the groove 290 when viewed from the X direction or the Y direction can be lower than the position of the top surface of the conductive layer 120_2 in contact with the insulating layer 280, as compared to when the conductive layer 120_2 does not have the recess. Here, the position of each surface can be determined as a distance or height from a reference surface where the transistor is to be formed. Note that the surface used as the reference is not limited to the surface where the transistor is to be formed. For example, the top surface of a substrate on which the semiconductor device is provided may be used as the reference surface.

[0078] By reducing the height of the bottom surface of the conductive layer 260, a gate electric field can be easily applied to the channel formation region of the metal oxide layer 230. This can improve the electrical characteristics of the transistor 200. In addition, a gate electric field can be easily applied to a region of the metal oxide layer 230 in contact with the conductive layer 120_2. This can increase the on-state current of the transistor 200. Furthermore, regardless of whether the conductive layer 120 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved.

[0079] 5A also shows an example in which the opening 270 is provided not only in the insulating layer 285, the insulating layer 250, and the metal oxide layer 230, but also in the conductive layer 240_2. For example, FIG. 5A also shows an example in which the opening 270 reaches the conductive layer 240_1. In this case, the conductive layer 244 can have a region in contact with the top surface of the conductive layer 240_1 and the side surface of the conductive layer 240_2. By having the conductive layer 244 in contact with the top surface of the conductive layer 240_1, the contact resistance per unit area between the conductive layer 240 and the conductive layer 244 can be reduced, even if the contact resistance per unit area between the conductive layer 240_2 and the conductive layer 244 is greater than the contact resistance per unit area between the conductive layer 240_1 and the conductive layer 244. Furthermore, since the conductive layer 244 is in contact with the top surface of the conductive layer 240_1 and the side surface of the conductive layer 240_2, the contact area between the conductive layer 240 and the conductive layer 244 is larger than when the conductive layer 244 is in contact only with the top surface of the conductive layer 240_2. This reduces the contact resistance between the conductive layer 240 and the conductive layer 244. Note that the opening 270 does not need to penetrate the conductive layer 240_2. In this case, the bottom of the opening 270 reaches the top surface of the conductive layer 240_2. When the opening 270 does not penetrate the conductive layer 240_2, it may be easier to form the opening 270 than when the opening 270 penetrates the conductive layer 240_2.

[0080] 5A , the opening 270 includes an opening in the insulating layer 285, an opening in the insulating layer 250, an opening in the metal oxide layer 230, and an opening in the conductive layer 240_2. Note that the shape and size of the opening 270 in a plan view may differ depending on the layer. Furthermore, when the shape of the opening 270 in a plan view is circular, the openings in each layer may or may not be concentric.

[0081] Furthermore, after forming the conductive film that will become the conductive layer 260, a planarization process such as chemical mechanical polishing (CMP) may be performed. Planarization can remove portions of the conductive film, the insulating layer 250, and the metal oxide layer 230, thereby forming the conductive layer 260 and reducing surface irregularities. The planarization process can make the positions of the top surfaces of the conductive layer 240, the conductive layer 260, the insulating layer 250, and the metal oxide layer 230 coincident or approximately coincident in the Z direction (see FIG. 6 ). That is, the distances (heights) from the surface of the substrate (not shown) to the top surfaces of the conductive layer 240, the conductive layer 260, the insulating layer 250, and the metal oxide layer 230 can be made coincident or approximately coincident. Reducing surface irregularities through the planarization process can improve the coverage of subsequently formed insulating layers, conductive layers, and the like. Therefore, the thicknesses of subsequently formed insulating layers, conductive layers, and the like can be reduced, thereby improving the productivity of semiconductor devices. Furthermore, since the conductive layer 240 and the conductive layer 260 do not overlap each other in a plan view, the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced, thereby increasing the operating speed of the memory cell 150. Therefore, the operating speed of the semiconductor device including the memory cell 150 can be increased.

[0082] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0083] [Metal Oxide Layer] As described above, the metal oxide layer 230 has a channel formation region. The metal oxide layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The metal oxide layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0084] The crystallinity of the semiconductor material used for the metal oxide layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0085] The transistor 200 preferably includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in the metal oxide layer 230 including a channel formation region. When a metal oxide that functions as a semiconductor is used for the metal oxide layer 230, the transistor 200 can be referred to as an OS transistor.

[0086] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0087] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0088] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the metal oxide layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0089] For a metal oxide layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 3. Detailed description thereof will be omitted here.

[0090] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0091] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0092] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0093] In addition, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 6.

[0094] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 180, insulating layer 280, insulating layer 250, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layers included in the semiconductor device.

[0095] For example, as transistors become more miniaturized or highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0096] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide (also called gallium oxide), hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0097] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0098] In order for the transistor 200 to function as an FeFET, a material that can have ferroelectricity is used for the insulating layer 250 that functions as a gate insulating layer.

[0099] Examples of materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials that can have ferroelectricity include materials in which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials that can have ferroelectricity include materials in which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ (X is a real number greater than 0), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or a piezoelectric ceramic having a perovskite structure such as barium titanate (BST), strontium titanate (X), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may also be used.

[0100] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al １−ａ Sc ａ N ｂ(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1. Hereinafter, this may be referred to simply as "AlScN"), Al-Ga-Sc nitride, Ga-Sc nitride, etc. may be used. Ferroelectric materials include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Metal oxides containing element M1 and nitrogen may also be ferroelectric even without element M2. Furthermore, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above-mentioned metal nitrides. The element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Since the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, which is a Group 15 element, the metal nitrides may be referred to as Group 13-15 ferroelectrics, Group 13 nitride ferroelectrics, etc.

[0101] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0102] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0103] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. For example, the insulating layer 250 can have a layered structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0104] Metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved. Representative examples of metal oxides containing hafnium and zirconium include HfZrO Ｘ Also, HfZrO Ｘ It is also possible to use a metal oxide in which Y (yttrium) is added to HfZrO. Ｘ By adding Y (yttrium) to the above, the ferroelectricity can be enhanced.

[0105] In this specification and the like, a material that can have ferroelectricity may be referred to as a "ferroelectric material." A layer of a ferroelectric material may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. A device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device in this specification and the like.

[0106] It is believed that ferroelectricity is exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. It is also believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. It is particularly preferable for an insulating layer to contain crystals having an orthorhombic crystal structure, as this will exhibit ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0107] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0108] As described above, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even when it is a thin film of a few nanometers, and is therefore preferable for the insulating layer 250. The film thickness of the insulating layer 250 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm or more and 9 nm or less).

[0109] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 250. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ (0.01 μm ２ ) or less, or 1000 nm ２ (0.001 μm ２ ) or less, the ferroelectric layer may still have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the transistor 200 can be reduced.

[0110] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a ferroelectric material as a dielectric. A nonvolatile memory element using a ferroelectric material is sometimes called a "ferroelectric memory." The transistor 200 according to one aspect of the present invention functions as a ferroelectric memory.

[0111] Furthermore, when a ferroelectric material is used for the insulating layer 250 that functions as a gate insulating layer of the transistor 200, an unintended current (leakage current) may easily flow between the conductive layer 260 and the metal oxide layer 230. In order to prevent an increase in the leakage current, it is preferable that the insulating layer 250 be a stack of multiple layers, and that a paraelectric material be used for the layer in contact with the metal oxide layer 230.

[0112] 5B , it is preferable to form an insulating layer 250_1 using a paraelectric material on the metal oxide layer 230, and then form an insulating layer 250_2 using a ferroelectric material on the insulating layer 250_1. When an oxide semiconductor is used as the metal oxide layer 230, it is preferable to use an insulating material containing oxygen for the insulating layer 250_1. For example, it is preferable to use silicon oxide, silicon oxynitride, or the like for the insulating layer 250_1.

[0113] A transistor using a metal oxide for a semiconductor layer can have stable electrical characteristics by surrounding the semiconductor layer with an insulating layer that has a function of suppressing permeation of impurities and oxygen. The insulating layer that has a function of suppressing permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing permeation of impurities and oxygen can be made of oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; nitrides such as aluminum nitride and silicon nitride; or nitride oxides such as silicon nitride oxide.

[0114] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also included are nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Also included are nitride oxides such as silicon nitride oxide.

[0115] Furthermore, an insulating layer such as a gate insulating layer that is in contact with a metal oxide layer or that is provided near the metal oxide layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with a metal oxide layer or is located near the metal oxide layer, oxygen vacancies in the metal oxide layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0116] An insulating layer in contact with a metal oxide layer or an insulating layer provided near the metal oxide layer is preferably a barrier insulating layer against hydrogen, since the insulating layer has a barrier property against hydrogen, which can suppress diffusion of hydrogen into the metal oxide layer.

[0117] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0118] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0119] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0120] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0121] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0122] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２ The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0123] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0124] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0125] The insulating layer 180, the insulating layer 280, and the insulating layer 285 function as interlayer films, and therefore, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer films, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 180, the insulating layer 280, and the insulating layer 285.

[0126] The concentration of impurities such as hydrogen or water in the insulating layer 280 is preferably reduced. This can prevent impurities such as hydrogen or water from entering the channel formation region of the metal oxide layer 230.

[0127] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least a portion of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the metal oxide layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0128] Note that the thickness of the insulating layer 280 on the conductive layer 120 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0129] It is preferable to use a barrier insulating layer against hydrogen as the insulating layer 250. When the insulating layer 250 provided on the metal oxide layer 230 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen contained in the conductive layer 260 into the metal oxide layer 230. For example, a silicon nitride film has a high barrier property against hydrogen and is therefore suitable as the insulating layer 250.

[0130] Furthermore, since the insulating layer 250 is in contact with the metal oxide layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the metal oxide layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the metal oxide layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0131] Furthermore, it is preferable to use an insulating layer having a region containing excess oxygen as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the metal oxide layer 230, thereby reducing oxygen vacancies in the metal oxide layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable as the insulating layer 250 because it has a structure that is stable against heat.

[0132] 3A and 5A show examples in which the insulating layer 250 has a single-layer structure. The insulating layer 250 can have a laminated structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include the function of extracting hydrogen from the metal oxide layer 230, the function of suppressing diffusion of hydrogen into the metal oxide layer 230, and the function of exhibiting ferroelectricity.

[0133] For example, the insulating layer 250 can have a two-layer structure consisting of a first insulating layer and a second insulating layer on the first insulating layer. In this case, the first insulating layer contacts the metal oxide layer 230. For example, it is preferable to use an insulating layer having the function of capturing or fixing hydrogen, or an insulating layer having the function of supplying oxygen to the metal oxide layer 230, as the first insulating layer, and an insulating layer having the function of exhibiting ferroelectricity as the second insulating layer. This configuration can reduce the hydrogen concentration in the metal oxide layer 230 and supply oxygen to the metal oxide layer 230. Therefore, a highly reliable transistor can be realized. Additionally, the transistor 200 can function as an FeFET. For example, a silicon oxide film or a silicon oxynitride film can be used as the first insulating layer, and a film containing ferroelectric materials such as hafnium oxide and zirconium oxide can be used as the second insulating layer. Furthermore, it is preferable that the first insulating layer has a region containing excess oxygen.

[0134] Furthermore, an insulating layer having a barrier property against oxygen can be used as the first insulating layer. When the first insulating layer has a barrier property against oxygen, oxygen can be prevented from being released from the metal oxide layer 230. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200.

[0135] The thickness of the second insulating layer made of a ferroelectric material is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, in order to apply a sufficient electric field to the second insulating layer made of a ferroelectric material when writing data to the transistor 200 functioning as a memory cell, the thickness of the first insulating layer is preferably thinner than the thickness of the second insulating layer made of a ferroelectric material. For example, the thickness of the first insulating layer is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0136] When forming a plurality of insulating films by laminating them, it is preferable to use the atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the insulating layers are formed using the ALD process. By forming at least two or more insulating layers using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layers. Furthermore, it is possible to increase productivity by continuously forming two or more films, for example, two or more insulating layers, using the ALD process.

[0137] [Conductive Layer] The conductive layers (conductive layer 120, conductive layer 240, conductive layer 260, conductive layer 244, conductive layer 245, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0138] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In-Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0139] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0140] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0141] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0142] A conductive material with high conductivity, such as tungsten, can be used for the conductive layer 120. By using such a conductive material with high conductivity, the conductivity of the conductive layer 120 can be improved, and the conductive layer 120 can function sufficiently as the wiring SL.

[0143] The conductive layer 120 and the conductive layer 240 are each conductive layers in contact with the metal oxide layer 230. Therefore, for the conductive layer 120 and the conductive layer 240, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120 and the conductive layer 240.

[0144] By using a conductive material containing oxygen for the conductive layer 120, the conductive layer 120 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, it is preferable to use, for example, ITO, ITSO, In—Zn oxide, or the like for each of the conductive layer 120 and the conductive layer 240.

[0145] When the conductive layer 120 and the conductive layer 240 each have a stacked structure, the contact resistance between the conductive layer 120 and the metal oxide layer 230 and between the conductive layer 240 and the metal oxide layer 230 can be reduced by using a conductive material containing oxygen in the layer of the stacked structure that has the largest contact area with the metal oxide layer 230.

[0146] For example, the conductive layer 120 shown in FIG. 5A has a two-layer structure including a conductive layer 120_1 and a conductive layer 120_2 over the conductive layer 120_1. In this case, for example, a conductive material containing oxygen is preferably used for the conductive layer 120_2. Furthermore, a material having higher conductivity than the conductive layer 120_2 is preferably used for the conductive layer 120_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 120_2 and tungsten for the conductive layer 120_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 120_1. By using an oxide conductor for the conductive layer 120_2 that is mainly in contact with the metal oxide layer 230, the contact resistance with the metal oxide layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 120, the conductivity of the conductive layer 120 can be increased.

[0147] Note that a conductive material containing oxygen can be used for the conductive layer 120_1, and a material having higher conductivity than the conductive layer 120_1 can be used for the conductive layer 120_2. In this case, the material with higher conductivity is used for the layer of the conductive layer 120 that is closest to the channel formation region of the metal oxide layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0148] For example, the conductive layer 240 shown in FIG. 5A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, a conductive material containing oxygen is preferably used for the conductive layer 240_2. Furthermore, a material having higher conductivity than the conductive layer 240_2 is preferably used for the conductive layer 240_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240_2 and tungsten for the conductive layer 240_1. Ruthenium, titanium nitride, tantalum nitride, or the like may also be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the metal oxide layer 230, the contact resistance with the metal oxide layer 230 can be reduced. Furthermore, by using a material having higher conductivity than an oxide conductor for the layers constituting the conductive layer 240, the conductivity of each conductive layer 240 can be increased.

[0149] Note that the conductive layer 240_1 may be formed using a conductive material containing oxygen, and the conductive layer 240_2 may be formed using a material having higher conductivity than the conductive layer 240_1. In this case, an oxide conductor is used for the conductive layer 240 that is closest to the channel formation region of the metal oxide layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0150] The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 260. As described above, examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0151] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0152] 5A shows an example in which the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. By using a conductive material having a function of suppressing oxygen diffusion as the conductive layer 260_1, for example, release of oxygen from the metal oxide layer 230 can be suppressed, and formation of oxygen vacancies in the metal oxide layer 230 can be suppressed.

[0153] Furthermore, by using a conductive material that is resistant to oxidation as the conductive layer 260_1, it is possible to prevent the conductive layer 260_1 from being oxidized and its conductivity from being reduced due to, for example, the release of oxygen from the metal oxide layer 230 or the release of oxygen from the insulating layer 250.

[0154] The material used for the conductive layer 260_2 preferably has higher conductivity than the material used for the conductive layer 260_1, for example. In addition, by increasing the thickness of the conductive layer 260_2, the current flowing through the conductive layer 260_2 can be increased.

[0155] By using a deposition method with high coverage for the conductive layer 260_1, the conductive layer 260_1 can be suitably formed along the sidewall of the groove 290.

[0156] The conductive layer 260_1 can be, for example, a conductive material containing nitrogen, a conductive material containing oxygen, or the like. Alternatively, the conductive layer 260_1 can be, for example, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed.

[0157] For example, a conductive material containing the above-mentioned metal element and nitrogen can be used as the conductive layer 260_1, such as tantalum nitride, titanium nitride, ruthenium nitride, a nitride containing molybdenum, a nitride containing tungsten, titanium, and aluminum, or a nitride containing tantalum and aluminum.

[0158] Furthermore, for example, a conductive material containing the above-mentioned metal element and oxygen can be used as the conductive layer 260_1, such as ruthenium oxide, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel.

[0159] Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used.

[0160] Furthermore, as the conductive layer 260_1, a material containing titanium, tantalum, ruthenium, or one or more selected from these metal elements is preferable because it is a conductive material that is resistant to oxidation, a conductive material that has the function of suppressing oxygen diffusion, or a material that maintains conductivity even after absorbing oxygen.

[0161] The conductive layer 260_2 can be formed using, for example, any of the above metal elements, alloys containing the above metal elements, alloys of a combination of the above metal elements, etc. For example, tungsten can be used.

[0162] When the transistor 200 is made to function as an FeFET, the conductive layer 260_1 in contact with the insulating layer 250, which is a ferroelectric, is preferably made of a material that easily generates polarization in the insulating layer 250. For example, titanium nitride, tantalum nitride, or the like is preferably used for the conductive layer 260_1.

[0163] The conductive layer 260_1 may further have a stacked structure. The conductive layer 260_2 may further have a stacked structure. When the conductive layer 260_1 has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260_1 may be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention may be stacked. When the conductive layer 260_2 has a stacked structure, for example, a plurality of materials that can be used for the conductive layer 260_2 may be stacked. Alternatively, a plurality of materials selected from the materials that can be used for the conductive layer of one embodiment of the present invention may be stacked.

[0164] The conductive layer 244 and the conductive layer 245 can be formed using a material that can be used for the conductive layer 240. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 244 and the conductive layer 245. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0165] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0166] <Example of Manufacturing Method of Semiconductor Device> Next, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. Note that, with regard to materials and forming methods of elements, descriptions of parts similar to those described above may be omitted.

[0167] Unless otherwise specified, A in each figure indicates a plan view, B in each figure indicates a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A of each figure, and C in each figure indicates a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A of each figure.

[0168] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, etc.

[0169] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0170] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0171] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0172] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0173] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method according to one embodiment of the present invention uses the ALD method, but employs one or both of a high substrate temperature during film formation and an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be lower than when the ALD method is used without these.

[0174] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0175] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0176] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0177] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0178] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0179] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0180] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0181] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0182] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0183] An example of a method for manufacturing the semiconductor device shown in FIGS. 1A, 3A, and 3B will be described below.

[0184] 7A, 7B, and 7C, an insulating layer 180 is formed over a substrate (not shown), and a conductive layer 120 is formed over the insulating layer 180. For example, a first conductive film that will become the conductive layer 120_1 is formed, a second conductive film that will become the conductive layer 120_2 is formed over the first conductive film, and the first conductive film and the second conductive film are processed to form the conductive layer 120 having the conductive layer 120_1 and the conductive layer 120_2.

[0185] Subsequently, the insulating layer 280 is formed on the conductive layer 120, and the conductive film 240f is formed on the insulating layer 280. As the conductive film 240f, for example, a conductive film 240f1 on the insulating layer 280 and a conductive film 240f2 on the conductive film 240f1 are formed.

[0186] 8A, 8B, and 8C, the conductive film 240f and the insulating layer 280 are processed to form a groove 290 that reaches the conductive layer 120. In this embodiment, the groove 290 is formed to extend in the Y direction.

[0187] The groove 290 is formed so as to expose a part of the conductive layer 120_2. At this time, it is preferable that a recess is provided in the conductive layer 120_2 at a position overlapping with the groove 290. Furthermore, by adjusting the conditions for forming the groove 290, a recess can be formed in the conductive layer 120_2.

[0188] Anisotropic etching is preferably used for etching the conductive film 240f and the insulating layer 280 to form the groove 290. In particular, dry etching is preferable because it is easy to achieve anisotropic etching and is suitable for fine processing.

[0189] Subsequently, heat treatment is preferably performed at a temperature of, for example, 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0190] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-described heat treatment, impurities such as hydrogen or water contained in the insulating layer 280 or the like can be reduced before the formation of the metal oxide layer 230.

[0191] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb (0.001 ppm) or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being absorbed into the insulating layer 280 and the like as much as possible.

[0192] 9A, 9B, and 9C, a metal oxide film 230f is formed to cover the groove portion 290 and later become the metal oxide layer 230. The metal oxide film 230f is provided in contact with the bottom and side surfaces of the recessed portion of the conductive layer 120_2, the side surfaces of the insulating layer 280, the side surfaces of the conductive layer 240f1, the side surfaces of the conductive layer 240f2, and the top surface of the conductive layer 240f2.

[0193] The description in Embodiment 3 can be referred to for a method for forming the metal oxide film 230f.

[0194] In this embodiment, the metal oxide film 230f is formed by depositing a first metal oxide film, a second metal oxide film, and a third metal oxide film in this order. For example, the first metal oxide film is formed as an In—Ga—Zn oxide film by thermal ALD, the second metal oxide film is formed as an indium oxide film by thermal ALD, and the third metal oxide film is formed as an In—Ga—Zn oxide film by sputtering.

[0195] It is preferable that the first metal oxide film and the second metal oxide film are successively formed without being exposed to the atmosphere. By successively forming the first metal oxide film and the second metal oxide film without being exposed to the atmosphere, productivity can be improved. Furthermore, impurities (typically, moisture, etc.) introduced into the interface between the first metal oxide film and the second metal oxide film and the vicinity thereof can be reduced.

[0196] After the second metal oxide film is formed, a process of supplying oxygen to the second metal oxide film may be performed. This allows oxygen to be supplied to the metal oxide layer 230 by heat or the like applied after the process. The details of the process of supplying oxygen can be found in the above description.

[0197] Next, it is preferable to perform heat treatment. The temperature of the heat treatment is preferably 100° C. or higher and 650° C. or lower, more preferably 250° C. or higher and 600° C. or lower, and even more preferably 350° C. or higher and 550° C. or lower. For details of the heat treatment, refer to the above description.

[0198] The gas used in the heat treatment is preferably highly purified. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being taken into the metal oxide film 230f as much as possible.

[0199] The heat treatment reduces impurities such as carbon, hydrogen, and water in the metal oxide film 230f. Reducing the impurities in the film in this manner improves the crystallinity of the metal oxide film 230f, resulting in a denser, more compact structure. This increases the crystalline regions in the metal oxide film 230f, reducing in-plane variations in the crystalline regions in the metal oxide film 230f. This reduces in-plane variations in the electrical characteristics of the transistor.

[0200] For example, it is preferable to form an insulating layer containing excess oxygen as the insulating layer 280 and supply oxygen contained in the insulating layer 280 to the channel formation region of the metal oxide film 230f by the heat treatment. Ｏ H can be reduced.

[0201] Furthermore, oxygen has a function of trapping electrons, which makes it easier for negative charges to be generated, thereby shifting the threshold voltage of the transistor in the positive direction and enabling a normally-off transistor to be realized.

[0202] Note that microwave plasma treatment may be performed after the formation of the second metal oxide film or the third metal oxide film. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the metal oxide film 230f can be reduced. Furthermore, crystalline regions of the metal oxide film 230f may grow. Note that details of the microwave plasma treatment will be described in Embodiment 3.

[0203] 10A, 10B, and 10C, the metal oxide film 230f and the conductive film 240f are processed to form the metal oxide layer 230 and the conductive layer 240 (conductive layer 240_1 and conductive layer 240_2). Specifically, the metal oxide layer 230 is formed from the metal oxide film 230f. Furthermore, the conductive layer 240_2 is formed from the conductive film 240f2, and the conductive layer 240_1 is formed from the conductive film 240f1. As shown in FIG. 10B, the metal oxide layer 230 can be formed to extend in the X direction.

[0204] The metal oxide film 230f and the conductive film 240f can be processed using the same mask. In this case, the number of manufacturing steps of the semiconductor device can be reduced compared to when the metal oxide film 230f and the conductive film 240f are processed using different masks. Note that the metal oxide film 230f and the conductive film 240f may be processed using different masks. In this case, for example, the area of ​​the metal oxide layer 230 in a plan view can be made smaller than the area of ​​the conductive layer 240.

[0205] 11A, 11B, and 11C, an insulating layer 250 is formed on the metal oxide film 230f. The insulating layer 250 is formed in a groove 290 having a large aspect ratio. Therefore, the insulating layer 250 is preferably formed using a film formation method with good coverage, and more preferably formed using a CVD method, an ALD method, or the like.

[0206] In this embodiment, a film of HfZrOx, which is a ferroelectric material, is formed as the insulating layer 250. Note that, as shown in Fig. 5B , when a stack of an insulating layer 250_1 and an insulating layer 250_2 is used as the insulating layer 250, a film of silicon oxynitride is formed on the metal oxide film 230f as the insulating layer 250_1, and a film of HfZrOx, which is a ferroelectric material, is formed on the insulating layer 250_1 as the insulating layer 250_2.

[0207] After the insulating layer 250 is formed, it is preferable to perform a heat treatment to enhance the crystallinity of the ferroelectric material HfZrOx. The temperature of the heat treatment is preferably 300° C. or higher and 600° C. or lower, and more preferably 400° C. or higher and 500° C. or lower. Note that the heat treatment can also be performed after the conductive layer 260 is formed.

[0208] Microwave plasma treatment is preferably performed after the insulating layer 250 is formed. Microwave plasma treatment is preferably performed at least one of after the insulating layer 250_1 and after the insulating layer 250_2 is formed. In particular, microwave plasma treatment is preferably performed in an atmosphere containing oxygen. By performing the microwave plasma treatment, the concentration of impurities such as hydrogen or water contained in the metal oxide layer 230 can be reduced. Furthermore, a crystalline region of the metal oxide layer 230 may grow. Details of the microwave plasma treatment will be described in Embodiment 3.

[0209] After the insulating layer 250_1 is formed, treatment for supplying oxygen to the insulating layer 250_1 may be performed. In this manner, oxygen can be supplied to the metal oxide layer 230. Note that the above description can be referred to for details of the treatment for supplying oxygen.

[0210] 12A, 12B, and 12C, a conductive film 260f, which will later become the conductive layer 260, is formed on the insulating layer 250. Specifically, the conductive film 260f is formed so as to have a region located inside the groove portion 290. As the conductive film 260f, for example, a conductive film 260f1 is formed on the insulating layer 250, and a conductive film 260f2 is formed on the conductive film 260f1.

[0211] In this embodiment, in order to make the transistor 200 function as an FeFET, a titanium nitride film is formed as the conductive layer 260f1 in contact with the ferroelectric insulating layer 250. Also, a tungsten film is formed as the conductive film 260f2.

[0212] 13A, 13B, and 13C, the conductive film 260f is processed to form the conductive layers 260 (conductive layers 260_1 and 260_2). Specifically, the conductive layer 260_2 is formed from the conductive film 260f2, and the conductive layer 260_1 is formed from the conductive film 260f1. The conductive layers 260 are formed to extend in the Y direction.

[0213] 14A, 14B, and 14C, an insulating layer 285 is formed over the conductive layer 260 and the insulating layer 250. Then, as shown in FIGS. 15A, 15B, and 15C, an opening 270 is formed that penetrates the insulating layer 285, the insulating layer 250, the metal oxide layer 230, and the conductive layer 240_2 and reaches the conductive layer 240_1.

[0214] 16A, 16B, and 16C, a conductive layer 244 is formed in the opening 270. For example, a conductive film that becomes the conductive layer 244 is formed on the insulating layer 285 so as to have a region located inside the opening 270. Then, a planarization process is performed on the conductive film to expose the top surface of the insulating layer 285, thereby forming the conductive layer 244 in the opening 270. CMP process is suitable as the planarization process. In the planarization process, at least the region of the conductive film that overlaps with the top surface of the insulating layer 285 is removed. Therefore, when viewed from the X direction and the Y direction, the position of the top surface of the insulating layer 285 and the position of the top surface of the conductive layer 244 coincide or approximately coincide.

[0215] By forming the conductive layer 244 using CMP treatment, the number of masks can be reduced compared to, for example, forming the conductive layer 244 by etching. In this manner, the transistor 200 is formed.

[0216] 17A , 17B, and 17C , a conductive layer 245 is formed on the insulating layer 285 and the conductive layer 244. The conductive layer 245 contacts the upper surface of the conductive layer 244. The conductive layer 245 also contacts the upper surface of the insulating layer 285. The conductive layer 245 is formed to extend in the X direction.

[0217] In this manner, the semiconductor device shown in FIGS. 1A, 3A, and 3B can be manufactured.

[0218] <Structure Example 2 of Semiconductor Device> In a semiconductor device of one embodiment of the present invention, for example, a plurality of transistors can be stacked on top of each other. The semiconductor device illustrated in FIG. 18 includes n-layer (n is an integer of 2 or more) memory layers 170 stacked in the Z direction. The memory layers 170 include memory cells 150 each including a transistor 200. In FIG. 18 , the first memory layer 170 is denoted as memory layer 170[1], the second memory layer 170 is denoted as memory layer 170[2], and the n-th memory layer 170 is denoted as memory layer 170[n].

[0219] Specifically, memory layer 170[2] is provided on memory layer 170[1], and another memory layer 170 is provided on memory layer 170[2], with memory layer 170[n] provided on the topmost level.

[0220] The number of memory cells 150 included in one memory layer 170 is not particularly limited, and one memory layer 170 may have two or more memory cells 150. Each of the memory cells 150 included in the n-th memory layer 170 is connected to a sense amplifier (not shown) provided below the n-th memory layer 170 via a conductive layer 256, a conductive layer 257, etc. In this case, the conductive layer 256, the conductive layer 257, etc. function as part of the wiring BL shown in FIG. 1B together with the conductive layer 245. By stacking a plurality of memory cells 150 in this way, the storage capacity per unit area can be increased.

[0221] 18, the conductive layers 245 provided in the memory layers 170[1] to 170[n] are distinguished by being referred to as conductive layers 245[1] to 245[n], respectively. The conductive layers 256 provided in the memory layers 170[1] to 170[n] are distinguished by being referred to as conductive layers 256[1] to 256[n], respectively. The conductive layers 257 provided in the memory layers 170[1] to 170[n] are distinguished by being referred to as conductive layers 257[1] to 257[n], respectively.

[0222] Note that the conductive layers 256 , 257 , and the like can also function as plugs or wirings for connecting a circuit element such as a transistor, a wiring, an electrode, or a terminal to the memory cell 150 .

[0223] 18 shows an example in which the conductive layer 257 is provided on the same formation surface as the conductive layer 120. The conductive layer 257 can be formed in the same process and made of the same material as the conductive layer 120. FIG. 18 shows an example in which the conductive layer 257 has a two-layer stacked structure of a first conductive layer and a second conductive layer over the first conductive layer.

[0224] 18 shows an example in which the conductive layer 256 is disposed in an opening formed in the second conductive layer of the conductive layer 257, the insulating layer 280, and the insulating layer 285. The conductive layer 256 can be in contact with the top surface of the first conductive layer of the conductive layer 257 and the bottom surface of the conductive layer 245. As described above, the conductive layers 245[1] to 245[n] can be connected to each other. Here, when the contact resistance between the first conductive layer of the conductive layer 257 and the conductive layer 256 is lower than the contact resistance between the second conductive layer of the conductive layer 257 and the conductive layer 256, it is preferable to also provide an opening in which the conductive layer 256 is disposed in the second conductive layer of the conductive layer 257, as shown in FIG. 18. Note that the conductive layer 256 can be formed using a conductive material or the like that can be used for the conductive layer 244.

[0225] 18, by stacking a plurality of memory cells 150, the memory cells 150 can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured. This allows for a larger storage capacity per unit area.

[0226] FIG. 19 shows an example of a cross-sectional configuration of a semiconductor device in which a memory layer 170 having memory cells 150 is provided on a layer in which a driver circuit including a sense amplifier is provided.

[0227] In FIG. 19, a memory cell 150 including a transistor 200 is provided above a transistor 300 .

[0228] The transistor 300 is one of the transistors included in the driver circuit.

[0229] 19, the bit line connected to the drive circuit can be shortened by providing the drive circuit so as to overlap with the memory cell 150. This reduces the wiring resistance and parasitic capacitance of the bit line, enabling high-speed operation of the semiconductor device.

[0230] 19 can correspond to the semiconductor device 900 described in Embodiment 4. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0231] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0232] Here, in the transistor 300 shown in FIG. 19 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Although the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0233] Note that the transistor 300 illustrated in FIG. 19 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0234] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0235] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0236] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0237] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in FIG. 19 , an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0238] The insulating layers 352, 354, and the like that function as interlayer films can be formed using the insulating layers that can be used in the above-described semiconductor devices.

[0239] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 240 can be used. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0240] The conductive layer 245 is connected to the low-resistance region 314b which functions as a source or drain region of the transistor 300 through the conductive layer 256, the conductive layer 257, the conductive layer 356, the conductive layer 330, and the conductive layer 328. For the conductive layer 256 and the conductive layer 257, the description of FIG. 18 can be referred to.

[0241] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0242] Embodiment 2 In this embodiment, an operation example of a transistor 200 functioning as a memory cell will be described.

[0243] [Hysteresis Characteristics of Ferroelectrics] Ferroelectrics have hysteresis characteristics. Before describing an example of the operation of the transistor 200, the hysteresis characteristics of ferroelectrics will be described. FIG. 20 is a diagram showing an example of the hysteresis characteristics of a ferroelectric. The hysteresis characteristics can be measured using a capacitive element (also called a "ferroelectric capacitor") that uses a ferroelectric. In FIG. 20, the horizontal axis represents the voltage (electric field) applied to the ferroelectric. This voltage is the potential difference between one electrode and the other electrode of the ferroelectric capacitor. The electric field strength can be found by dividing this potential difference by the thickness of the ferroelectric.

[0244] In Fig. 20, the vertical axis represents the polarization of the ferroelectric. When the polarization is positive, it indicates that the positive charge in the ferroelectric is biased toward one electrode of the capacitance element, and the negative charge is biased toward the other electrode of the capacitance element. On the other hand, when the polarization is negative, it indicates that the negative charge in the ferroelectric is biased toward one electrode of the capacitance element, and the positive charge is biased toward the other electrode of the capacitance element.

[0245] Furthermore, the polarization shown on the vertical axis of the graph in Figure 20 may be positive when negative charges are biased toward one electrode side of the capacitance element and positive charges are biased toward the other electrode side of the capacitance element, and negative when positive charges are biased toward one electrode side of the capacitance element and negative charges are biased toward the other electrode side of the capacitance element.

[0246] 20, the hysteresis characteristics of a ferroelectric material can be expressed by a curve 51 and a curve 52. The voltages at the intersections of the curves 51 and 52 are called the saturated polarization voltage +VSP (also called "+VSP") and the saturated polarization voltage -VSP (also called "-VSP"). +VSP and -VSP can be said to have opposite polarities.

[0247] When a voltage equal to or less than -VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is increased, the polarization of the ferroelectric changes according to curve 51. On the other hand, when a voltage equal to or greater than +VSP is applied to a ferroelectric, and then the voltage applied to the ferroelectric is decreased, the polarization of the ferroelectric changes according to curve 52. Note that +VSP may be called a "positive saturation polarization voltage" or a "first saturation polarization voltage." Also, -VSP may be called a "negative saturation polarization voltage" or a "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0248] When the polarization of a ferroelectric changes according to curve 51, the voltage at which the polarization becomes 0 is called the coercive voltage +Vc. When the polarization of a ferroelectric changes according to curve 52, the voltage at which the polarization becomes 0 is called the coercive voltage -Vc. The values ​​of +Vc and -Vc are between +VSP and -VSP. Note that +Vc may be called the "positive coercive voltage" or "first coercive voltage," and -Vc may be called the "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first coercive voltage and the second coercive voltage may be the same or different.

[0249] Furthermore, when no voltage is applied to the ferroelectric (when the voltage is 0 V), the maximum value of polarization is called "residual polarization +Pr" or "residual polarization Pr1," and the minimum value is called "residual polarization -Pr" or "residual polarization Pr2." Furthermore, the absolute value of the difference between remanent polarization +Pr and remanent polarization -Pr is called "residual polarization 2Pr." The larger the remanent polarization 2Pr, the greater the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. The larger the remanent polarization 2Pr, the more preferable it is.

[0250] Here, the crystal structure of hafnium oxide that functions as a ferroelectric will be described with reference to FIG. 21. FIG. 21 is a model diagram illustrating the crystal structure of hafnium oxide. Hafnium oxide is known to have a variety of crystal structures, such as the cubic system (cubic, space group: Fm-3m) shown in FIG. 21, the tetragonal system (tetragonal, space group: P4 ２ / nmc), orthorhombic, space group: Pbc2 ２ ), and monoclinic, space group: P2 １ / c). Furthermore, as shown in Figure 21, each of the above-mentioned crystal structures can undergo a phase change. For example, by doping hafnium oxide with zirconium to form a composite material, it is possible to change the crystal structure of hafnium oxide, which is mainly monoclinic, into a crystal structure mainly orthorhombic.

[0251] When the above-mentioned composite material is formed by alternately depositing hafnium oxide and zirconium oxide in a composition ratio of approximately 1:1 using an ALD method or the like, the composite material has an orthorhombic crystal structure. Alternatively, the composite material has an amorphous structure. The amorphous structure can then be converted into an orthorhombic crystal structure by subjecting the composite material to a heat treatment or the like. Note that the orthorhombic crystal structure may change to a monoclinic crystal structure. When imparting ferroelectricity to the above-mentioned composite material, an orthorhombic crystal structure is preferable to a monoclinic crystal structure.

[0252] Here, a model of the orthorhombic crystal structure of HfZrOx will be described with reference to FIGS. 22A and 22B.

[0253] 22A and 22B show HfZrOx, where Hf ０．５ Zr ０．５ O ２ 22A and 22B are model diagrams of the crystal structure of HfO. In addition, the directions of the a-axis, b-axis, and c-axis are also shown in FIGS. 22A and 22B. ２ orthorhombic structure of Pca2 １ ) is a model in which the atomic arrangement has been optimized using first-principles calculations.

[0254] 22A and 22B, it can be seen that hafnium and zirconium are bonded to each other via oxygen, which can be achieved by alternately depositing hafnium and zirconium films by the ALD method.

[0255] In the orthorhombic structure, HfZrOx can have either the atomic arrangement shown in FIG. 22A or the atomic arrangement shown in FIG. 22B. Therefore, an externally applied electric field displaces some of the oxygen atoms in HfZrOx, causing polarization inside. Here, some of the oxygen atoms are displaced in the c-axis direction, and polarization also occurs in the c-axis direction. Furthermore, by changing the direction or strength of the electric field, some of the oxygen atoms in HfZrOx move, changing the sign of the polarization inside.

[0256] For example, when the remanent polarization is −Pr, the atoms in HfZrOx are arranged as shown in Fig. 22A. When the remanent polarization is +Pr, the atoms in HfZrOx are arranged as shown in Fig. 22B.

[0257] [Relationship Between Polarization of Ferroelectric and Id-Vg Characteristics] Next, the relationship between the polarization of the ferroelectric used in the gate insulating layer (insulating layer 250) and the Id-Vg characteristics of the transistor 200 will be described.

[0258] 23A and 23B are equivalent circuit diagrams of a FeFET transistor 200. In these figures, polarization of a ferroelectric insulating layer 250 (see FIG. 7A) is shown schematically.

[0259] 23C is a diagram illustrating the Id-Vg characteristics of the transistor 200 when the potential difference between the source and the drain (also referred to as "drain voltage" or "Vd") is constant. The horizontal axis of FIG. 23C represents the potential difference between the source and the gate (also referred to as "gate voltage" or "Vg"), and the vertical axis represents the current flowing between the source and the drain (also referred to as "drain current" or "Id").

[0260] In FIG. 23C, characteristic 291 indicates the Id-Vg characteristic of transistor 200 when no polarization occurs in insulating layer 250.

[0261] 23C, characteristic 292 indicates the Id-Vg characteristic when the polarization of insulating layer 250 is remanent polarization Pr1. Also, FIG. 23A is a schematic diagram showing the polarization of insulating layer 250 constituting transistor 200 in characteristic 292.

[0262] Because the remanent polarization Pr1 is positive, a positive voltage is generated on the semiconductor layer 230 side of the insulating layer 250. As a result, the Id-Vg characteristic of characteristic 291 shifts in the negative direction of Vg, becoming characteristic 292. That is, the threshold voltage of the transistor 200 shifts in the negative direction of Vg.

[0263] 23C, characteristic 293 indicates the Id-Vg characteristic when the polarization of insulating layer 250 is remanent polarization Pr2. FIG. 23B is a schematic diagram showing the polarization of insulating layer 250 constituting transistor 200 in characteristic 293.

[0264] Because the remanent polarization Pr2 is negative, a negative voltage is generated on the semiconductor layer 230 side of the insulating layer 250. As a result, the Id-Vg characteristic of the characteristic 291 shifts in the positive direction of Vg to become a characteristic 293. That is, the threshold voltage of the transistor 200 shifts in the positive direction of Vg.

[0265] 23A, 23B, and 23C, the Id-Vg characteristics of the transistor 200 can be changed depending on the polarization of the insulating layer 250, which is a ferroelectric layer. In other words, the threshold voltage of the transistor 200 can be controlled by controlling the polarization of the insulating layer 250. Therefore, the transistor 200 can function as a memory cell capable of holding binary data.

[0266] For example, when writing binary data of data "0" or "1" to the transistor 200 functioning as a memory cell, the polarization of the insulating layer 250 may be set to remanent polarization Pr1 when writing data "1" and to remanent polarization Pr2 when writing data "0". In this case, the Id-Vg characteristics of the transistor 200 in which data "1" has been written will be characteristic 292. The Id-Vg characteristics of the transistor 200 in which data "0" has been written will be characteristic 293.

[0267] Next, the erase operation, write operation, retention operation, and read operation of the transistor 200 functioning as a memory cell will be described. In this embodiment, the potential H is higher than the potential L. When the potential COM is set to a reference potential (0 V), the potential H is higher than the potential COM, and the potential L is lower than the potential COM. The potential difference between the potential H and the potential L is equal to or greater than VSP (the absolute value of −VSP or +VSP).

[0268] <Erase Operation> Before writing data to the transistor 200 functioning as a memory cell, the data must be erased. In this embodiment, the erase operation is an operation of writing data "0" to the transistor 200. That is, the polarization of the insulating layer 250 is set to a remanent polarization Pr2.

[0269] 24A is a timing chart illustrating an erase operation. FIG. 24B is a circuit diagram illustrating the state of the transistor 200 during period T11. In circuit diagrams and the like, a symbol indicating the potential of a wiring or the like may be written adjacent to the wiring to clearly show the potential of the wiring. A symbol indicating the potential may be enclosed in a box around a wiring in which a potential change has occurred. An arrow may be written to indicate the direction of current flow.

[0270] In a period T11, a potential L is supplied to the wiring WL, and a potential H is supplied to the wirings BL and SL. Then, −VSP is applied to the insulating layer 250. Then, in a period T12, 0 V is supplied to the wirings WL, BL, and SL. That is, the wirings WL, BL, and SL are set to the same potential.

[0271] During period T12, the polarization of the insulating layer 250 becomes a remnant polarization Pr2 (see FIG. 20). As described above, the remnant polarization Pr2 is negative, and therefore a negative voltage is generated on the semiconductor layer 230 side of the insulating layer 250. As a result, the Id-Vg characteristic of characteristic 291 shifts in the positive direction of Vg to become characteristic 293. That is, the threshold voltage of the transistor 200 shifts in the positive direction of Vg (see FIG. 23C).

[0272] In the period T13, a potential RL is supplied to the wiring WL. The potential RL will be described in detail in the description of the holding operation. Note that the period T12 may be omitted, and the period T13 may be performed after the period T11. After the period T11, a negative voltage is generated on the semiconductor layer 230 side of the insulating layer 250 even if the period T12 is omitted.

[0273] <Write Operation> Next, an operation of writing data "1" to the transistor 200 functioning as a memory cell will be described. Fig. 25A is a timing chart illustrating the write operation. Fig. 25B is a circuit diagram showing the state of the transistor 200 in a period T21.

[0274] After the erasing operation is performed in period T11, in period T21, a potential H is supplied to the wiring WL, and a potential L is supplied to the wiring BL and the wiring SL. Then, +VSP is applied to the insulating layer 250, and the polarization of the insulating layer 250 changes along the curve 51 (see FIG. 20). Subsequently, in period T22, 0 V is supplied to the wiring WL, the wiring BL, and the wiring SL. That is, the wiring WL, the wiring BL, and the wiring SL are set to the same potential.

[0275] During period T22, the polarization of the insulating layer 250 becomes a remnant polarization Pr1 (see FIG. 20). As described above, the remnant polarization Pr1 is positive, and therefore a positive voltage is generated on the semiconductor layer 230 side of the insulating layer 250. As a result, the Id-Vg characteristic of characteristic 291 shifts in the negative direction of Vg to become characteristic 292. That is, the threshold voltage of the transistor 200 shifts in the negative direction of Vg (see FIG. 23C).

[0276] In this way, data "1" can be written to the transistor 200. Furthermore, the polarization of the insulating layer 250 containing a ferroelectric is maintained even when power supply to the transistor 200 is cut off. Therefore, the data written to the transistor 200 is maintained even when power supply to the transistor 200 is cut off. Therefore, the transistor 200 functions as a nonvolatile memory cell.

[0277] The operation of writing data "0" to the transistor 200 is the same as the erase operation described above, so there is no need to perform the operation of writing data "0" after the erase operation.

[0278] <Retaining Operation> After writing data to the transistor 200, a potential RL is supplied to the wiring WL in a period T23. The potential RL is a potential at which the transistor 200 is turned off even when the Id-Vg characteristics of the transistor 200 are the characteristics 292 (see FIG. 23C ). Therefore, the potential RL may be a potential lower than the threshold voltage of the transistor 200 having the characteristics 292. Furthermore, to make it difficult for the polarization of the insulating layer 250 to change, the potential RL is set to a voltage equal to or higher than the coercive voltage −Vc.

[0279] After the write operation is completed, the potential of the wiring WL is preferably the potential RL until the read operation is performed. By keeping the potential of the wiring WL at the potential RL, the transistor 200 is reliably turned off, thereby reducing the power consumption of the transistor 200. Therefore, the power consumption of the memory cell is reduced. Furthermore, when a memory cell array is configured by arranging a plurality of transistors 200 in a matrix, interference with the read operation of other memory cells (transistors 200) can be prevented. Therefore, the reliability of the memory cell array can be improved.

[0280] It is also possible to omit the period T22 and perform the period T23 after the period T21.

[0281] <Read Operation> Next, a read operation of data held in the transistor 200 functioning as a memory cell will be described. Fig. 26A is a timing chart illustrating the read operation. Fig. 26B is a circuit diagram showing the state of the transistor 200 in a period T31. Fig. 26C is a circuit diagram showing the state of the transistor 200 in a period T32.

[0282] In this embodiment, a read operation of the transistor 200 holding data "1" will be described.

[0283] In a period T31, the wiring BL is precharged to a potential H. That is, after the potential of the wiring BL is set to the potential H, the wiring BL is set to a floating state (a state in which power is not supplied from anywhere). In addition, the potential COM is supplied to the wiring SL.

[0284] Subsequently, in a period T32, a potential RH, which is a read potential, is supplied to the wiring WL. The potential RH is equal to or higher than the threshold voltage of the transistor 200 having the characteristic 292 and lower than the threshold voltage of the transistor 200 having the characteristic 293. To prevent the polarization of the insulating layer 250 from changing, the potential RH is set to a voltage at which the voltage applied to the insulating layer 250 is equal to or lower than the coercive voltage +Vc.

[0285] When data "1" is held in the transistor 200, when the potential RH is supplied to the wiring WL, the transistor 200 is turned on, and a current Id1 flows between the source and drain of the transistor 200 (see FIGS. 23C and 26C). Therefore, the wirings BL and SL are brought into electrical continuity, and the potential of the floating wiring BL changes toward the potential COM.

[0286] When the potential of the wiring BL changes after the potential RH is supplied to the wiring WL, it can be determined that data "1" is written to the transistor 200. When it is determined that the potential of the wiring BL does not change even when the potential RH is supplied to the wiring WL, it can be determined that data "0" is written to the transistor 200.

[0287] After the read operation is completed, a potential RL is supplied to the wiring WL in a period T33. By setting the potential RH to a voltage that makes the voltage applied to the insulating layer 250 equal to or lower than the coercive voltage +Vc, the polarization of the insulating layer 250 is less likely to change. Therefore, nondestructive readout of the transistor 200 can be achieved.

[0288] The hysteresis characteristics of a ferroelectric material vary depending on the material, configuration, manufacturing method, etc. Therefore, the potential RH is preferably a voltage at which the voltage applied to the insulating layer 250 is 0.8 times or less, more preferably 0.6 times or less, of the coercive voltage +Vc. The potential RL is preferably a voltage at which the voltage applied to the insulating layer 250 is 0.8 times or more, more preferably 0.6 times or more, of the coercive voltage -Vc.

[0289] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0290] Embodiment 3 In this embodiment, a metal oxide layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention will be described. As the metal oxide layer, a layer containing metal oxide can be used as a single layer or a stacked layer. Note that in a metal oxide layer with a stacked structure, it may be difficult to identify the boundaries between stacked films, as described later.

[0291] [Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0292] Examples of metal oxides according to one embodiment of the present invention include indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), and indium aluminum zinc oxide (In-Al-Z). Examples of usable metal oxides include indium tin zinc oxide (In—Sn—Zn oxide, also referred to as IAZO), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, examples of usable metal oxides include gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), gallium tin oxide (Ga—Sn oxide), and aluminum tin oxide (Al—Sn oxide). Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Further, as the metal oxide according to one embodiment of the present invention, gallium oxide, zinc oxide, or the like can be used.

[0293] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0294] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0295] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0296] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0297] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0298] A structural example of a metal oxide layer that can increase the field-effect mobility of a transistor will be described. For example, it is preferable to use a stacked structure of indium oxide and IGZO. Specifically, it is preferable that the metal oxide layer has indium oxide and IGZO on the indium oxide. It is also preferable to use IGZO containing nitrogen as the metal oxide layer. For example, it is preferable to use IGZO containing nitrogen during or after film formation. ２ By performing O plasma treatment, IGZO containing nitrogen can be formed. Furthermore, it is preferable to use at least one of indium oxide, In—Ga oxide, In—Zn oxide, and IGZTO as the metal oxide layer.

[0299] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0300] The metal oxide layer according to one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the metal oxide layer, the density of defect states in the metal oxide layer can be reduced. Therefore, the reliability of a transistor including the metal oxide layer according to one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0301] Note that the crystallinity of the metal oxide contained in the metal oxide layer is not particularly limited. For example, the metal oxide layer may contain one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the metal oxide layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0302] The crystallinity of the metal oxide layer can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of these techniques may be used for analysis.

[0303] The metal oxide layer according to one embodiment of the present invention preferably has a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of a metal oxide layer having a CAAC structure is observed using a high-resolution TEM image (also called a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystalline portion. Therefore, a metal oxide layer having a CAAC structure can also be said to have a structure having a layered crystalline portion.

[0304] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface or surface on which the metal oxide layer is formed. In the CAAC structure, metal atoms are arranged in layers parallel to or approximately parallel to the surface on which the metal oxide layer is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal oxide layer is formed.

[0305] When the metal oxide layer has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the metal oxide layer observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which they are formed.

[0306] When electron diffraction is performed on a metal oxide layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0307] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0308] A cross-sectional TEM image of a metal oxide layer having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing on each region within the cross-sectional TEM image. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of the line segment connecting two spots observed in the created FFT pattern that have high brightness and are approximately equidistant from the center is taken as the crystal axis direction. Regions where the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0309] When a metal oxide layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity.

[0310] [Composition of Metal Oxide] The metal oxide according to one embodiment of the present invention preferably contains indium (In), and more preferably has a high In content. By using a metal oxide with a high In content for the metal oxide layer, the on-state current of the transistor can be increased, and the frequency characteristics can be improved. For example, indium oxide is preferably used for the metal oxide layer.

[0311] Furthermore, the metal oxide according to one embodiment of the present invention may contain zinc. When the metal oxide contains zinc, it becomes a highly crystalline metal oxide, for example, a metal oxide having a CAAC structure. For example, an In-Zn oxide can be used for the metal oxide layer. Specifically, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or a composition close thereto, a composition of In:Zn = 2:1 [atomic ratio] or a composition close thereto, or a composition of In:Zn = 4:1 [atomic ratio] or a composition close thereto can be used. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio.

[0312] Furthermore, the metal oxide according to one embodiment of the present invention can contain an element M. When the metal oxide contains the element M, oxygen vacancies can be suppressed from being formed in the metal oxide. Therefore, the reliability of a transistor including a metal oxide layer can be improved.

[0313] For example, the metal oxide layer can be made of In—Zn oxide containing a trace amount of element M. Specifically, metal oxides having a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a similar composition, In:Ga:Zn=2:0.1:1 (atomic ratio) or a similar composition, or In:Ga:Zn=1:0.1:1 (atomic ratio) or a similar composition can be used. Furthermore, metal oxides having a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a similar composition, In:Sn:Zn=2:0.1:1 (atomic ratio) or a similar composition, or In:Sn:Zn=1:0.1:1 (atomic ratio) or a similar composition can be used.

[0314] The metal oxide layer can be made of an In—Zn oxide containing element M. Specifically, metal oxides having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:1.2 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:0.5 (atomic ratio) or a composition close thereto, In:M:Zn=1:1:2 (atomic ratio) or a composition close thereto, In:M:Zn=4:2:3 (atomic ratio) or a composition close thereto, In:M:Zn=1:3:2 (atomic ratio) or a composition close thereto, or In:M:Zn=1:3:4 (atomic ratio) or a composition close thereto can be used.

[0315] When a metal oxide is formed by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% of that in the sputtering target.

[0316] Furthermore, when forming a metal oxide film containing multiple metal elements, such as In—Ga—Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not match.

[0317] The composition of the metal oxide used in the metal oxide layer can be analyzed using, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0318] The metal oxide layer according to one embodiment of the present invention may have a stacked structure of two or more layers. When the metal oxide layer has a two-layer structure of a first layer and a second layer on the first layer, the second layer preferably has a different composition from the first layer. When the metal oxide layer has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the second layer preferably has a different composition from the first layer and the third layer. The first layer may have the same composition as the third layer. Alternatively, the first layer and the third layer may have different compositions.

[0319] The first to third layers may each be made of the metal oxides described above.

[0320] The second layer can be made of, for example, indium oxide, In—Zn oxide, or In—Zn oxide containing a trace amount of element M. Specifically, a metal oxide having an atomic ratio of In:Zn=1:1 or a similar composition, an atomic ratio of In:Zn=2:1 or a similar composition, or an atomic ratio of In:Zn=4:1 or a similar composition can be used. For example, a metal oxide having an atomic ratio of In:Ga:Zn=4:0.1:1 or a similar composition, an atomic ratio of In:Ga:Zn=2:0.1:1 or a similar composition, or an atomic ratio of In:Ga:Zn=1:0.1:1 or a similar composition can be used. Alternatively, for example, a metal oxide having an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereof, an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereof, or an atomic ratio of In:Sn:Zn=1:0.1:1 or a composition thereof can be used. Increasing the In content in the second layer can increase the on-current and improve the frequency characteristics.

[0321] The conduction band minimums of the first and third layers are preferably located closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of the first and third layers is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is sandwiched between the first and third layers, whose conduction band minimums are located closer to the vacuum level, and can function mainly as a current path (channel).

[0322] By sandwiching the second layer between the first layer and the third layer, carriers trapped at and near the interface of the second layer can be reduced. Furthermore, the channel can be moved away from the surface of the gate insulating layer, reducing the effects of surface scattering. This allows for a buried channel transistor in which the channel is moved away from the insulating layer interface, thereby increasing field-effect mobility. Furthermore, the effects of interface states that may form on the back channel side can be reduced, suppressing light degradation of the transistor (e.g., negative bias light degradation), and improving transistor reliability.

[0323] When forming a buried channel using the first to third layers, for example, the first and third layers can be made of a metal oxide having a higher Ga content than the second layer. Specifically, the first and third layers can each be made of a metal oxide having an In:Ga:Zn=1:1:1 atomic ratio or a composition thereabout, a metal oxide having an In:Ga:Zn=1:3:2 atomic ratio or a composition thereabout, or a metal oxide having an In:Ga:Zn=1:3:4 atomic ratio or a composition thereabout. Alternatively, Ga-Zn oxide or gallium oxide can be used. Increasing the Ga content of the first and third layers can sometimes position the conduction band minimum of each of the first and third layers closer to the vacuum level than the conduction band minimum of the second layer.

[0324] Furthermore, by increasing the Ga content in the first layer and the third layer, the barrier properties against hydrogen of the first layer and the third layer can be improved. Therefore, it is possible to suppress the diffusion of hydrogen from below the first layer or above the third layer to the second layer. Furthermore, by increasing the Ga content in the first layer and the third layer, it is possible to reduce impurities such as hydrogen or water contained in the metal oxide layer due to heat or the like applied after the formation of the metal oxide layer. Note that a similar effect may be achieved by using a metal oxide having a lower In content for the first layer and the third layer compared to the second layer.

[0325] For example, the third layer preferably uses a metal oxide having an atomic ratio of In:Ga:Zn=1:1:1 or a similar composition, an atomic ratio of In:Ga:Zn=1:3:2 or a similar composition, or an atomic ratio of In:Ga:Zn=1:3:4 or a similar composition, in which the third layer contains indium and gallium.

[0326] Furthermore, increasing the Ga content in the first layer and the third layer can improve the oxygen barrier properties of the first layer and the third layer. This can suppress oxygen release from the second layer where the channel is formed, and can suppress the formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer. This can improve the electrical characteristics of the transistor.

[0327] Furthermore, by increasing the Ga content in the first layer, the resistivity of the first layer can be made higher than that of the second layer in some cases. When the first layer is provided on the back channel side, providing a layer with high resistivity as the first layer can suppress a negative shift in threshold voltage or a decrease in on-current. Therefore, the threshold voltage of the transistor is shifted positively, and the transistor can be made normally off. As described above, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.

[0328] The band gap of a metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Furthermore, a combination of these techniques can be used for analysis. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

[0329] The first layer and the third layer may be made of a metal oxide having a higher In content than the second layer. Alternatively, one of the first layer and the third layer may be made of a metal oxide having a higher In content than the second layer, and the other may be made of a metal oxide having a higher Ga content than the second layer.

[0330] The first layer, the second layer, and the third layer may each have a plurality of layers having the above-described compositions stacked together. For example, the first layer may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content. For example, the third layer may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0331] [Method for Forming Metal Oxide Layer] The metal oxide layer according to one embodiment of the present invention can be formed by a sputtering method, a CVD method, a vacuum evaporation method, an MBE method, a PLD method, an ALD method, or the like.

[0332] The metal oxide layer according to one embodiment of the present invention can be fabricated by forming a metal oxide using two different film formation methods. For example, the metal oxide layer according to one embodiment of the present invention can be fabricated by forming a metal oxide using a first film formation method and a second film formation method.

[0333] The metal oxide layer according to one embodiment of the present invention can have a two-layer structure including a first layer and a second layer formed on the first layer. When the metal oxide layer has a two-layer structure, the metal oxide layer can be manufactured by forming the first layer on a surface to be formed by a first film formation method and then forming the second layer thereon by a second film formation method.

[0334] The first film formation method preferably uses a film formation method that causes less damage to the surface to be formed than the second film formation method. This can suppress the formation of a mixed layer at the interface between the metal oxide layer and the layer on which the metal oxide layer is to be formed. Furthermore, since it can suppress the incorporation of impurities such as silicon into the second layer formed on the first layer, the crystallinity of the metal oxide layer may be increased.

[0335] Examples of the first film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo-assisted CVD, and MOCVD. The MBE method is a film formation method that grows a thin film having a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that cause little damage to the surface on which the film is formed. A wet method can also be used as the first film formation method. The wet method is one of the film formation methods that cause little damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0336] The second film formation method is preferably a method capable of forming a crystalline metal oxide film. It is particularly preferable that the metal oxide film formed in this case has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the second film formation method.

[0337] When a metal oxide is formed on a surface to be formed using the second film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0338] For example, when a sputtering method is used as the second film formation method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to the substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed using the second film formation method on a silicon-containing insulating layer, such as a silicon oxide film, as the formation surface, silicon may be mixed into the metal oxide. The inclusion of impurities such as silicon in the metal oxide may hinder the crystallization of the metal oxide. Furthermore, the use of a metal oxide layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when the heat treatment described below is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0339] Therefore, as described above, by forming a metal oxide layer using the first film formation method before forming a metal oxide layer using the second film formation method, it is possible to suppress the incorporation of impurities into the metal oxide layer. Furthermore, it is possible to suppress alloying with the layer on which the metal oxide layer is to be formed. Therefore, it is possible to improve the initial characteristics and reliability of the transistor. Furthermore, it is possible to further increase the crystallinity of the metal oxide layer.

[0340] A mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer contains the component contained in the first layer and the component contained in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer contains gallium and indium. Furthermore, for example, when the indium content in the second layer is higher than the indium content in the first layer, the indium content in the mixed layer is equal to or greater than the indium content in the first layer and equal to or less than the indium content in the second layer.

[0341] The ALD method is suitable as the first film formation method because it can suppress damage to the surface to be formed compared to the sputtering method. Furthermore, the ALD method is a film formation method with superior coverage compared to the sputtering method, and by using the ALD method as the film formation method for the first layer, the coverage of the metal oxide layer can be improved. Therefore, the metal oxide layer can be well coated on steps, openings, etc. with high aspect ratios.

[0342] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure. By forming a second layer having high crystallinity on the first layer having low crystallinity, or by applying a heat treatment after forming the second layer, the crystallinity of the first layer may be increased, with the second layer acting as a nucleus. This may increase the crystallinity of the entire metal oxide layer, including the vicinity of the interface with the surface on which it is formed.

[0343] The layer serving as the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that, depending on the transistor structure, the layer may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the surface to be formed does not need to have crystallinity. Note that, when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide of the metal oxide layer.

[0344] The first layer is preferably formed by ALD. Here, a method for forming an In-M-Zn oxide as the first layer by ALD will be described.

[0345] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0346] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0347] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0348] By repeating the above-described method, an In-M-Zn oxide can be formed as a metal oxide layer on a layer that is a surface to be formed by the ALD method.

[0349] When forming a metal oxide layer using the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H ２ O) and the like can be used. ３ ), oxygen (O ２ By using the above-mentioned oxidizing agent, the amount of hydrogen mixed into the metal oxide layer can be reduced.

[0350] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge the excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge the excess reactant, reaction products, etc. from the reaction chamber.

[0351] Furthermore, unless otherwise specified in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, it is understood that these are not limited to gaseous or molecular states, but also include plasma, radical, and ionic states.

[0352] The second layer is preferably formed by sputtering.

[0353] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0354] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0355] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, for film formation. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0356] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0357] By using the above-described manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the thickness can be made thin enough that the alloyed region formed at the interface between the layer to be formed and the metal oxide is difficult to observe. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0358] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry or energy dispersive X-ray spectroscopy (EDX).

[0359] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0360] In a metal oxide layer according to one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0361] Furthermore, for example, when SIMS analysis is performed on a metal oxide layer formed on a silicon oxide film, which is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum value of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases and the interface is defined as thickness t. The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0362] By reducing the thickness of the alloyed region, the thickness t can be set to a value within the above range.

[0363] By reducing the alloyed region, it becomes possible to form a CAAC structure near the surface on which the metal oxide layer is to be formed. Here, "near the surface on which the metal oxide layer is to be formed" refers to, for example, a region that is more than 0 nm but not more than 3 nm, preferably more than 0 nm but not more than 2 nm, more preferably 1 nm or more but not more than 2 nm, generally perpendicular to the surface on which the metal oxide layer is to be formed.

[0364] The CAAC structure near the surface to be formed can sometimes be confirmed by observation using a TEM. For example, in cross-sectional observation of a metal oxide layer using a high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed near the surface to be formed.

[0365] Furthermore, the metal oxide layer according to one embodiment of the present invention can have a three-layer structure including a first layer, a second layer on the first layer, and a third layer on the second layer.

[0366] When the metal oxide layer has a three-layer structure, the metal oxide layer can be produced by forming a first layer on a surface to be formed using a first film formation method, then forming a second layer using a second film formation method, and then forming a third layer using the first film formation method.

[0367] Even when the first and third layers are made of compositions that make it difficult to form a CAAC structure when a single layer is formed, the metal oxide layer can have a CAAC structure throughout the entire metal oxide layer, including the first and third layers, by crystal growth occurring with the second layer as a nucleus. Alternatively, the metal oxide layer can have a CAAC structure in a region that includes at least a portion of each of the first and third layers and the second layer.

[0368] In particular, even when the first layer and the third layer have a high In content, the metal oxide layer can have suitable crystallinity for use as a semiconductor layer of a transistor. In the metal oxide layer according to one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0369] The first and third layers may be made of a metal oxide having the same composition as that of the second layer. Using the same composition may make it easier for the first and third layers to become CAAC after heat treatment.

[0370] Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the metal oxide layer can have both high crystallinity and high coverage throughout the layer.

[0371] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0372] When the metal oxide layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the metal oxide layer, may be in contact with the gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on state.

[0373] The first layer and the third layer each have high crystallinity, using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during or after the deposition of the second layer. The crystallinity of the third layer may be increased by heat treatment during or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0374] As described above, in the method for forming a metal oxide layer according to one embodiment of the present invention, the second layer having a highly crystalline metal oxide (i.e., CAAC) can be used as a nucleus or seed to increase the crystallinity of the upper and lower metal oxides (here, the first layer and the third layer). This increases the crystallinity of the entire metal oxide. In other words, the second layer can be used as a nucleus or seed to cause solid-phase growth of the upper and lower metal oxides, thereby forming a highly crystalline metal oxide layer. A metal oxide layer formed using such a film formation method, i.e., a CAAC film, can be referred to as an axial growth CAAC (AG CAAC).

[0375] In the metal oxide layer, it is preferable that a region having a CAAC structure is widely present throughout the layer. The region having a CAAC structure in the first layer is crystallinely connected to the region having a CAAC structure in the second layer. The region having a CAAC structure in the third layer is crystallinely connected to the region having a CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Also, the boundary between the second layer and the third layer may not be observed. The metal oxide layer may be expressed as a single layer with no clearly observed interface. The metal oxide layer may be expressed as a single layer.

[0376] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or approximately parallel to the surface on which the metal oxide layer is formed are confirmed in cross-sectional observation using a high-resolution TEM. Furthermore, it is preferable that the c-axis of the CAAC structure in each of the first to third layers is parallel or approximately parallel to the normal direction of the surface on which the metal oxide layer is formed.

[0377] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0378] Furthermore, when the metal oxide layer has a three-layer structure, the metal oxide layer can also be produced by forming a first layer on a surface to be formed using a first film formation method, then forming a second layer using the first film formation method, and then forming a third layer using a second film formation method.

[0379] As described above, using a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, metal oxides with a high In content tend to have a cubic crystal structure. Therefore, using a metal oxide with a high In content in the second layer in contact with the third layer can form a crystal that reflects the crystal orientation of the third layer.

[0380] Furthermore, it is preferable that the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. This allows the second layer to form crystals that reflect the orientation of the crystals of the third layer. In this case, for example, when a cross-section of the metal oxide layer is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface on which the metal oxide layer is formed are observed in the second layer.

[0381] The crystal structure of the second layer is not particularly limited as long as the lattice mismatch between the crystals of the third layer and the crystals of the second layer is small. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0382] In the above structure, typically, the first layer is a layer containing a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or a composition thereabout, or gallium oxide; the second layer is a layer containing a metal oxide having a trace amount of the aforementioned element M or indium oxide; and the third layer is a layer containing a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition thereabout. In this case, the first layer contains gallium. Furthermore, when the first layer contains a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or a composition thereabout, the indium content in the first layer is lower than the gallium content. Furthermore, the indium content in the second layer is higher than the indium content in the third layer.

[0383] When the first layer and the second layer are formed using the first film formation method, it is preferable to form the first layer and the second layer successively without exposing them to the atmosphere. By forming the first layer and the second layer successively without exposing them to the atmosphere, productivity can be increased. Furthermore, impurities (typically, moisture, etc.) introduced into the interface between the first layer and the second layer and the vicinity thereof can be reduced.

[0384] One or more of the first to third layers may have a stack of layers with different compositions. For example, the first layer may be formed by forming a layer containing a metal oxide with a high Ga content by the first film formation method, and then forming a layer containing a metal oxide with a higher In content than the first layer by the first film formation method.

[0385] After forming the layer by the first film formation method, it is preferable to perform microwave plasma treatment.

[0386] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0387] By performing microwave plasma treatment in an atmosphere containing oxygen, the impurity concentration in the metal oxide layer 230 can be reduced. Examples of impurities include hydrogen and carbon. While the above example illustrates a configuration in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may enhance the crystallinity of the metal oxide layer.

[0388] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0389] When microwave plasma treatment is performed, the substrate may be heated. The substrate is preferably heated to a temperature above room temperature (e.g., 25°C), above 100°C, above 200°C, above 300°C, or above 400°C, and below 500°C or below 450°C. For example, the substrate is preferably heated to a temperature above room temperature and below 500°C, more preferably above 100°C and below 450°C, more preferably above 200°C and below 450°C, even more preferably above 300°C and below 450°C, and even more preferably above 400°C and below 450°C.

[0390] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. In the microwave plasma treatment using oxygen gas and argon gas, the main oxygen radical is triplet oxygen (O( ３ P ｊ )), singlet oxygen (O( １ D ２ )), and oxygen ions (O ２ ＋) can take three states. Note that oxygen ions act effectively in reducing the hydrogen concentration in the oxide film by microwave plasma processing. The amount of oxygen radicals in each state varies depending on the oxygen flow rate ratio or pressure in microwave plasma processing. For example, under conditions where the oxygen flow rate ratio is low and the pressure is low, the amount of oxygen ions tends to increase. On the other hand, if the oxygen flow rate ratio or pressure is excessively low, there is a concern that the control of the oxygen flow rate becomes unstable, making it difficult to stabilize the discharge, and that the oxide film may be etched. Therefore, for example, when the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0391] The shorter the processing time of the microwave plasma treatment, the more the oxidation of the conductive layer 120 or the conductive layer 240, etc. can be suppressed. Also, the productivity increases. Therefore, for example, the processing time of the microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0392] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the metal oxide layer. The action of plasma, microwaves, oxygen radicals, or the like can form defects in which hydrogen has entered oxygen vacancies in the metal oxide layer (hereinafter referred to as V Ｏ This splits the V (sometimes referred to as H) into oxygen vacancies and hydrogen, and the hydrogen impurities can be removed from the metal oxide layer. Ｏ In this case, the impurities such as carbon and hydrogen can be reduced. Furthermore, in some cases, carbon bonded to oxygen or hydrogen can also be removed. In this way, by performing microwave plasma treatment, impurities such as carbon and hydrogen can be reduced. Furthermore, by supplying the oxygen radicals to the oxygen vacancies formed in the metal oxide layer, the oxygen vacancies in the metal oxide layer can be further reduced.

[0393] Furthermore, microwave plasma treatment can improve the crystallinity of a layer formed using the first film formation method. Here, the principle by which microwave plasma treatment improves the crystallinity of a metal oxide will be explained. First, active species such as oxygen radicals excited by microwaves arrive at the metal oxide surface, and a substitution reaction occurs between the active species and oxygen in the metal oxide layer. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable for the active species excited by microwaves to contain oxygen (typically oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, improving the crystallinity of the metal oxide.

[0394] On the other hand, a reaction occurs between a part of the oxygen in the metal oxide layer that existed before the microwave plasma treatment and the hydrogen in the metal oxide layer, in other words, "2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder the improvement of crystallinity, it is preferable to remove it from the metal oxide layer. ２ The hydrogen concentration in the metal oxide layer can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the metal oxide layer can be further reduced by increasing the temperature during the microwave plasma treatment.

[0395] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0396] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0397] The crystallinity of the layer formed by the first deposition method can be improved, and the crystallinity of the layer formed thereon can be further improved, thereby increasing the crystallinity of the entire metal oxide layer.

[0398] Oxygen supplied into the metal oxide layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with an unpaired electron). The oxygen injected into the metal oxide layer is preferably in one or more of the above forms, and is particularly preferably in the form of an oxygen radical.

[0399] After the metal oxide layer is formed, it is preferable to perform heat treatment. The heat treatment can enhance the crystallinity of the metal oxide layer. The heat treatment here is not limited to heat treatment. For example, it may be heat applied during the manufacturing process.

[0400] The temperature of the heat treatment can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA (Rapid Thermal Anneal) apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair atomic-level crystalline gaps in the CAAC structure of the second layer formed using the second film formation method with the third layer formed using the first film formation method.

[0401] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using high-temperature gas.

[0402] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer formed by the first film formation method. Furthermore, if the region is formed only below the third layer after the ALD film formation, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0403] Furthermore, it is preferable that at least a portion of the first layer or the second layer formed using the first film formation method is converted into CAAC by the heat treatment process. It is expected that the CAAC conversion is more likely to occur when the mixed layer formed in the first layer or the second layer during the formation of the layer formed using the second film formation method serves as a nucleus or seed. It is preferable that the region in the first layer or the second layer that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface on which it is formed.

[0404] Furthermore, because the CAAC is formed from the top to the bottom of the first or second layer, the CAAC can be formed up to the vicinity of the layer, regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the crystallinity of the first or second layer can be increased. Therefore, the method for forming a metal oxide layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC is formed has an amorphous structure.

[0405] As described above, by performing one or both of microwave plasma treatment and heat treatment, the crystallinity of the metal oxide layer as a whole can be increased. Furthermore, impurities in the metal oxide layer can be reduced. By performing crystal growth in a state where the impurity concentration in the metal oxide layer is reduced, the crystallinity can be further improved.

[0406] By increasing the crystallinity of the metal oxide layer, an increase in the electrical resistance of the semiconductor layer of a transistor using the metal oxide layer can be suppressed, or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby realizing a transistor suitable for high-speed operation.Furthermore, the reliability of the transistor can be improved, and the on-state current can be increased.

[0407] Note that one or both of the microwave plasma treatment and the heat treatment may be performed directly on the metal oxide layer, or may be performed after an insulating film or the like is formed on the metal oxide layer.

[0408] Before forming the first layer or after forming the first layer or the second layer by the first film formation method, a treatment for supplying oxygen to the first layer or the second layer may be performed, whereby oxygen can be supplied to the metal oxide layer by heat or the like applied after the treatment.

[0409] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere, plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere, and the like. Alternatively, oxygen may be supplied to the first layer or the second layer formed by the first film formation method by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The deposited oxide film may be removed immediately after deposition, or may be left as it is. When the deposited oxide film is left as it is, the oxide film can be used as a layer (second layer or third layer) provided on the first layer or second layer. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２The atmosphere includes a gas containing a compound containing oxygen such as oxygen (O). The substrate temperature during the plasma treatment is set to be equal to or higher than room temperature (25° C.) and equal to or lower than 450° C.

[0410] The metal oxide layer according to one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the metal oxide layer, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0411] Furthermore, a metal oxide layer having a CAAC structure formed using the two types of film formation methods described above may have a higher dielectric constant, film density, and / or film hardness than a metal oxide layer having a CAAC structure formed using one type of film formation method.

[0412] By using a metal oxide layer having a CAAC structure formed by using the above-described two types of film formation methods in a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0413] Furthermore, the metal oxide layer according to one embodiment of the present invention can be formed by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the metal oxide layer according to one embodiment of the present invention can be formed without using the second film formation method. For example, after forming a first layer using the first film formation method, one or both of microwave plasma treatment and heat treatment can be performed to enhance the crystallinity of the first layer. Therefore, the crystallinity of a second layer formed on the first layer using the first film formation method can be enhanced using the first layer as a nucleus or seed. Furthermore, after forming the second layer, one or both of microwave plasma treatment and heat treatment can be performed to enhance the crystallinity of the metal oxide layer. Therefore, a CAAC structure can be formed in the metal oxide layer.

[0414] As described above, even in a manufacturing method that does not use the second film formation method, a metal oxide having high crystallinity can be formed by solid-phase growth of the upper metal oxide using the first layer formed by the first film formation method as a nucleus or seed. Metal oxides formed by such film formation methods can also be called AG CAAC.

[0415] When the metal oxide layer has a stacked structure of two or more layers, it can be formed by forming the metal oxide using one film formation method. When the metal oxide layer has a two-layer structure of a first layer and a second layer on the first layer, the metal oxide layer can be formed, for example, by forming the first layer and the second layer in this order using a sputtering method. Sputtering has a higher film formation rate than ALD, and therefore can improve productivity. Furthermore, when the metal oxide layer has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer to the third layer can also be formed using a sputtering method. Furthermore, a portion of the first layer to the third layer can also be formed by ALD. For example, one or both of the second layer and the third layer may be formed by ALD.

[0416] [Metal Oxide Layer of Transistor] The metal oxide layer of this embodiment can be used as a semiconductor layer of a transistor.

[0417] The metal oxide layer in this embodiment can be used as the metal oxide layer 230 or the like included in each transistor described in Embodiment 1. The layer that is the surface on which the metal oxide layer is formed corresponds to the insulating layer 280 or the like described in Embodiment 1.

[0418] The metal oxide layer of this embodiment preferably has a CAAC structure, in which metal atoms in the crystal portion are arranged in layers parallel or substantially parallel to the surface on which the layer is formed.

[0419] It is estimated that a metal oxide layer having a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. That is, it is estimated that a metal oxide layer having a CAAC structure allows current to flow more easily in the horizontal direction than in the vertical direction.

[0420] In the semiconductor device described in the above embodiment, the metal oxide layer 230 has metal atoms arranged in a layered manner in a direction parallel or approximately parallel to the surface on which the layer is formed. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel or approximately parallel to the surface on which the layer is formed. With this configuration, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0421] When the metal oxide layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the metal oxide layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, even more preferably 5 nm to 100 nm, still more preferably 10 nm to 100 nm, even more preferably 10 nm to 70 nm, even more preferably 15 nm to 70 nm, even more preferably 15 nm to 50 nm, and even more preferably 20 nm to 50 nm. Furthermore, in transistors used in smaller semiconductor devices, the thickness of the metal oxide layer 230 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, even more preferably 5 nm to 12 nm, and even more preferably 5 nm to 10 nm. Furthermore, the average thickness of the metal oxide layer in the channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0422] The first layer preferably has a thickness of 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm. The first layer is further preferably 0.5 nm to 3 nm.

[0423] The first layer preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably 0.1 nm to 2 nm, or more preferably 0.5 nm to 3 nm, and even more preferably 0.5 nm to 2 nm.

[0424] The second layer preferably has a thickness of, for example, 200 nm or less. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0425] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0426] For the preferred range of the thickness of the third layer, see the description of the thickness of the first layer.

[0427] [Impurities in Metal Oxide Layer] Here, the influence of each impurity in the metal oxide layer will be described.

[0428] As described in the above embodiment, in a transistor using a metal oxide for a semiconductor layer, oxygen vacancies (V Ｏ The presence of impurities such as hydrogen, carbon, and nitrogen can cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the metal oxide layer is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the metal oxide layer, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in the metal oxide layer refer to elements other than the main component constituting the metal oxide. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0429] When a metal oxide contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the metal oxide. Therefore, the carbon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10１９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0430] Furthermore, when nitrogen is contained in a metal oxide, electrons serving as carriers are generated, the carrier concentration increases, and the metal oxide is likely to become n-type. As a result, a transistor using a nitrogen-containing metal oxide as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in a metal oxide, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0431] Furthermore, hydrogen contained in metal oxide reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons, which serve as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons, which serve as carriers. Therefore, transistors using metal oxides containing hydrogen tend to exhibit normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the metal oxide. Specifically, the hydrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0432] Furthermore, when a metal oxide contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the metal oxide obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0433] By using a metal oxide with sufficiently reduced impurities for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0434] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0435] Embodiment 4 In this embodiment, a semiconductor device 900 that functions as a memory device will be described.

[0436] Fig. 27 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 27 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 27 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0437] The memory cell 150 according to one embodiment of the present invention can be applied to the memory cell 950 .

[0438] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0439] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0440] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0441] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0442] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0443] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0444] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0445] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0446] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this example, the high power supply voltage of the semiconductor device 900 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 27, the number of power domains to which VDD is supplied in the peripheral circuit 915 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0447] 28A to 28G, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0448] 28A shows an example of a circuit configuration of a DRAM memory cell. In this specification, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0449] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0450] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to the wiring BL, and a gate of the transistor M1 is connected to the wiring WL. A second terminal of the capacitor CA is connected to the wiring CAL.

[0451] The wiring BL functions as a bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0452] Data is written and read by applying a high-level potential to the wiring WL, turning on the transistor M1, and bringing the wiring BL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0453] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed.

[0454] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951.

[0455] 28B shows an example circuit configuration of a two-transistor, one-capacitor gain cell memory cell. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell memory cell in which the transistor M2 is an OS transistor is referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0456] A first terminal of transistor M2 is connected to a first terminal of capacitor CB, a second terminal of transistor M2 is connected to wiring WBL, and a gate of transistor M2 is connected to wiring WL. A second terminal of capacitor CB is connected to wiring CAL. A first terminal of transistor M3 is connected to wiring RBL, a second terminal of transistor M3 is connected to wiring SL, and a gate of transistor M3 is connected to the first terminal of capacitor CB.

[0457] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0458] Data is written by applying a high-level potential to the wiring WL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0459] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0460] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BL. An example circuit configuration of such a memory cell is shown in FIG. 28C . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BL.

[0461] 28D is an example in which the capacitance CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 28E is an example in which the capacitance CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0462] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0463] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0464] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0465] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0466] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0467] 28F shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0468] A first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, a second terminal of the transistor M4 is connected to the wiring BL, and a gate of the transistor M4 is connected to the wiring WL. A second terminal of the capacitor CC is connected to the first terminal of the transistor M5 and the wiring GNDL. A second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and a gate of the transistor M5 is connected to the first terminal of the capacitor CC. A second terminal of the transistor M6 is connected to the wiring BL, and a gate of the transistor M6 is connected to the wiring RWL.

[0469] The wiring BL functions as a bit line, the wiring WL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0470] Data is written by applying a high-level potential to the wiring WL, turning on the transistor M4, and establishing electrical continuity between the wiring BL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0471] Data is read by precharging the wiring BL to a predetermined potential, then electrically floating the wiring BL and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0472] Note that at least the transistor M4 is preferably an OS transistor.

[0473] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0474] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only n-channel transistors.

[0475] 28G shows an example of an SRAM using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 28G is a memory cell of an SRAM capable of backing up data.

[0476] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0477] A first terminal of transistor M7 is connected to wiring BL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. A gate of transistor M7 is connected to wiring WL. A first terminal of transistor M8 is connected to wiring BLB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. A gate of transistor M8 is connected to wiring WL.

[0478] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0479] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0480] A second terminal of the capacitor CD1 is connected to the wiring GNDL, and a second terminal of the capacitor CD2 is connected to the wiring GNDL.

[0481] The wirings BL and BLB function as bit lines, the wiring WL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0482] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0483] Data is written by applying a high-level potential to the wiring WL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BL, and the potential is written to the second terminal of the transistor M10.

[0484] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BL, i.e., the inverted signal of the signal input to the wiring BL, is output to the wiring BLB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0485] Data reading will now be described. First, the wiring BL and the wiring BLB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BLB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BL. Since the potentials of the wiring BL and the wiring BLB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively, the potential held in the memory cell can be read from the potential of the wiring BL or the wiring BLB.

[0486] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells or eliminates the need for refreshing the memory cells.

[0487] Note that Si transistors may be used as the transistors MS1 to MS4.

[0488] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 29A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 29B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0489] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0490] 30 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 30 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0491] The arithmetic device 960 shown in FIG. 30 has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0492] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0493] As will be described later, a memory array 920 can be provided by stacking it on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0494] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0495] The arithmetic device 960 shown in FIG. 30 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 30 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0496] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0497] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and performs read and write operations on the registers 996 depending on the state of the arithmetic unit 960.

[0498] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0499] In the arithmetic unit 960 shown in FIG. 30 , a register controller 997 selects a holding operation in the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells in the register 996 will hold data using flip-flops or capacitors. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 996. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply voltage to the memory cells in the register 996 can be stopped.

[0500] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 31A and 31B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 31B.

[0501] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0502] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also referred to as monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0503] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0504] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0505] 31B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0506] Although the number of memory arrays functioning as caches is three in this example, it is also possible to have one or two, or four or more.

[0507] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may function as part of the cache interface 989, or may be configured to be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured to be connected thereto.

[0508] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0509] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0510] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 32A shows a perspective view of a semiconductor device 970B.

[0511] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Fig. 32A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0512] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0513] Also, multiple memory arrays may be stacked. Figure 32B shows a perspective view of a semiconductor device 970C.

[0514] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0515] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0516] Embodiment 5 In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

[0517] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 33 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 33, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0518] In FIG. 33 , from the top layer of the triangle, there are shown memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs, and storage memories such as 3D NANDs and hard disks (also called HDDs: hard disk drives).

[0519] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0520] A cache memory has a function of duplicating and storing a portion of data stored in a DRAM. By duplicating frequently used data and storing it in the cache memory, the access speed to the data can be increased. A cache memory is required to have a smaller storage capacity than a DRAM, but a faster operating speed than a DRAM. Data rewritten in the cache memory is duplicated and supplied to the DRAM. Note that, although only the L3 cache is illustrated in FIG. 33 , the cache memory is not limited to this. For example, a memory device using a metal oxide according to one embodiment of the present invention is also suitable for a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of a cache.

[0521] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0522] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0523] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0524] A memory device (OS memory) using a metal oxide according to one embodiment of the present invention can retain data for a long period of time. Therefore, the memory device is suitable for the region of Target 1 shown in FIG. 33 . Note that, as indicated by diagonal hatching in FIG. 33 , Target 1 also includes a part of the cache (L1, L2, L3) and a part of the 3D NAND. In other words, Target 1 includes a boundary region between the DRAM and the 3D NAND, and a boundary region between the DRAM and the cache (L1, L2, L3). Furthermore, the memory device using a metal oxide according to one embodiment of the present invention has a high operating speed and can therefore achieve excellent write and read operations. Therefore, the memory device is suitable for the region of Target 2 shown in FIG. 33 .

[0525] For example, it is preferable to replace the DRAM shown in FIG. 33 with a memory device using metal oxide according to one embodiment of the present invention. Here, the DRAM requires a refresh operation and is a destructive readout memory device, so it consumes more power than other memory devices. Therefore, a configuration without a DRAM can reduce power consumption. This configuration can reduce power consumption to one-hundredth or one-thousandth or less of that of a configuration using a DRAM. Therefore, global warming can be mitigated by deploying information processing devices, including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like, to which such a configuration is applied worldwide.

[0526] As described above, the memory device using a metal oxide according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories in the boundary region between DRAMs and 3D NANDs.

[0527] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0528] Embodiment 6 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0529] [Electronic Component] FIG. 34A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 34A has semiconductor device 710 inside mold 711. FIG. 34A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0530] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0531] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0532] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0533] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0534] 34B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0535] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, an NPU, or an FPGA (Field Programmable Gate Array).

[0536] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0537] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0538] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0539] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0540] On the other hand, when electrically connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0541] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0542] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 34B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0543] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0544] 35A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0545] 35B shows a perspective view of an example of a computer 5620. The computer 5620 includes a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0546] Fig. 35C shows an example of a PC card 5621. The PC card 5621 is a processing board equipped with, for example, a CPU, a GPU, a storage device, etc. The PC card 5621 has a board 5622 and connection terminals 5623, 5624, 5625, electronic components 5626, 5627, 5628, and 5629, etc., which are mounted on the board 5622. Note that Fig. 35C illustrates components other than electronic components 5626, 5627, and 5628.

[0547] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0548] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0549] The electronic component 5626 has a terminal (not shown) for inputting and outputting signals, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0550] The electronic components 5627 and 5628 have multiple terminals, and can be mounted on wiring provided on the board 5622 by, for example, reflow soldering the terminals. Examples of the electronic component 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the electronic component 5627. For example, the electronic component 5628 includes a storage device. For example, the electronic component 700 can be used as the electronic component 5628.

[0551] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0552] [Space Equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0553] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The change in electrical characteristics of an OS transistor due to radiation exposure is small. That is, the OS transistor has high radiation resistance and is therefore suitable for environments where radiation may be incident. For example, the OS transistor is suitable for use in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification includes one or more of the thermosphere, the mesosphere, and the stratosphere.

[0554] Fig. 36A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 36A shows a planet 6804 in space as an example.

[0555] 36A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0556] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0557] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0558] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0559] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor is highly reliable and suitable even in an environment where radiation may be incident.

[0560] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0561] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0562] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0563] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0564] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0565] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0566] Fig. 36B shows a storage system applicable to a data center. The storage system 6000 shown in Fig. 36B has a plurality of servers 6001sb as hosts 6001 (illustrated as Host Computers). It also has a plurality of storage devices 6003md as storage 6003 (illustrated as Storage). The host 6001 and storage 6003 are shown connected via a storage area network 6004 (illustrated as SAN: Storage Area Network) and a storage control circuit 6002 (illustrated as Storage Controller).

[0567] The host 6001 corresponds to a computer that accesses data stored in the storage 6003. The hosts 6001 may be connected to each other via a network.

[0568] Although the storage 6003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 6003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0569] The cache memory described above is used in the storage control circuit 6002 and the storage 6003. Data exchanged between the host 6001 and the storage 6003 is stored in the cache memory in the storage control circuit 6002 and the storage 6003, and then output to the host 6001 or the storage 6003.

[0570] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0571] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention is expected to contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0572] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0573] 51: curve, 52: curve, 120: conductive layer, 120_1: conductive layer, 120_2: conductive layer, 150: memory cell, 170[1]: memory layer, 170[2]: memory layer, 170[n]: memory layer, 180: insulating layer, 200: transistor, 230: metal oxide layer, 230f: metal oxide film, 240: conductive layer, 240_1: conductive layer, 240_2: conductive layer, 240f: conductive film, 244: conductive layer, 245[1]: conductive layer, 245[n]: conductive layer, 245: conductive layer, 250: insulating layer, 250_1: insulating layer, 250_2: insulating layer, 256[1]: conductive layer, 256[n]: conductive conductive layer, 256: conductive layer, 257[1]: conductive layer, 257[n]: conductive layer, 257: conductive layer, 260: conductive layer, 260_1: conductive layer, 260_2: conductive layer, 260f: conductive film, 270: opening, 280: insulating layer, 285: insulating layer, 290: groove, 291: characteristic, 292: characteristic, 293: characteristic, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulation layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 9 25: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller,993: instruction decoder, 994: interrupt controller, 995: timing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: electronic component, 56 27: Electronic component, 5628: Electronic component, 5629: Connection terminal, 5630: Motherboard, 5631: Slot, 6000: Storage system, 6001: Host, 6001sb: Server, 6002: Storage control circuit, 6003: Storage, 6003md: Storage device, 6800: Artificial satellite, 6801: Airframe, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device,

Claims

a transistor and a first insulating layer; the transistor includes a metal oxide layer, a first conductive layer, a second conductive layer, a third conductive layer, and a second insulating layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer has a groove that reaches the first conductive layer; the metal oxide layer has a region in contact with an upper surface of the second conductive layer, a region in contact with a side surface of the first insulating layer within the groove, and a region in contact with the first conductive layer within the groove; The second insulating layer comprises: a region in the groove that overlaps with a side surface of the first insulating layer via the metal oxide layer, and a region in the groove that overlaps with the first conductive layer via the metal oxide layer, The third conductive layer comprises: a region in the groove that overlaps with a side surface of the first insulating layer via the second insulating layer and the metal oxide layer, and a region in the groove that overlaps with the first conductive layer via the second insulating layer and the metal oxide layer, The second insulating layer has ferroelectricity. 　 In claim 1, a third insulating layer and a fourth conductive layer; the third insulating layer is located on the third conductive layer and on the second insulating layer; the fourth conductive layer is located on the third insulating layer; the fourth conductive layer is electrically connected to the second conductive layer; The groove portion extends in a first direction in a plan view, the fourth conductive layer extends in a second direction in a plan view, The second direction is perpendicular or approximately perpendicular to the first direction. 　 In claim 2, The third conductive layer extends in the first direction in a plan view. 　 In claim 1 or claim 2, The second insulating layer comprises hafnium and zirconium. 　 In claim 1 or claim 2, The metal oxide layer contains at least indium. 　 In claim 1 or claim 2, The third conductive layer includes titanium and nitrogen.

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