Semiconductor device

Abstract

This semiconductor device (30) comprises: an active region; and a termination region that is disposed around the active region in plan view and has a corner portion. The active region and the termination region each have a first lifetime control layer (41) and a second lifetime control layer (42) in a drift layer. The corner portion of the termination region have a third lifetime control layer (43) that has a larger defect amount than the first lifetime control layer 41 of the active region and has a larger defect amount than the first lifetime control layer in the other portions of the termination region.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] In power semiconductors (e.g., diodes), reverse recovery current tolerance (recovery tolerance, RecSOA tolerance (Recovery Safe Operating Area tolerance)) is an important item that must be ensured sufficiently. In particular, when the element's breakdown voltage increases, an electric field concentrates at the corners of the semiconductor device, which causes a decrease in the RecSOA tolerance.

[0003] To prevent this, lifetime control (e.g., irradiation with light ions such as protons) can be performed to suppress the concentration of holes, thereby improving the RecSOA tolerance and reducing the recovery loss. However, it is known that this increases the forward voltage drop (VF) and leakage current.

[0004] Japanese Patent Application Laid-Open No. 2003-144222 discloses forming a region having a shorter lifetime than other regions locally in a portion other than the active region portion of a semiconductor device.

[0005] Patent Document 2 describes a diode in which light ions such as protons are irradiated in a pattern. Patent Document 2 also discloses a semiconductor device that can suppress an increase in forward voltage drop and reduce leakage current while maintaining a high reverse recovery current withstand capability by irradiating light ions in various patterns.

[0006] Japanese Patent Laid-Open No. 9-246570 Japanese Patent Laid-Open No. 2014-135476

[0007] In Patent Document 1, the local electric field concentration around the active region is alleviated during recovery, and therefore the recovery tolerance is increased.

[0008] In Patent Document 2, an optimum pattern is formed to suppress an increase in forward voltage drop and reduce leakage current while maintaining a high reverse recovery current withstand capacity.

[0009] However, as the breakdown voltage of elements increases, further performance is desired. Therefore, in semiconductor devices having a lifetime control region, it is necessary to further suppress electric field concentration and improve the RecSOA tolerance.

[0010] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device having a lifetime control region that can achieve an improvement in reverse recovery current resistance.

[0011] To achieve the above object, a semiconductor device of the present invention is a semiconductor device comprising an active region and a termination region arranged around the active region in a plan view and having a corner portion, wherein the active region and the termination region have a first lifetime control layer and a second lifetime control layer in a drift layer, and the corner portion of the termination region has a third lifetime control layer having a larger amount of defects than the first lifetime control layer in the active region and having a larger amount of defects than the first lifetime control layer in other parts of the termination region. Other aspects of the present invention will be described in the embodiments described later.

[0012] According to the present invention, it is possible to improve the reverse recovery current resistance in a semiconductor device having a lifetime control region.

[0013] It is a top view showing the semiconductor device according to the embodiment. It is a diagram showing the AA' cross section of Figure 1. It is a diagram showing the BB' cross section of Figure 1. It is a diagram showing a process flow of the semiconductor device according to the embodiment.

[0014] Hereinafter, modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the drawings as appropriate.

[0015] Fig. 1 is a top view showing a semiconductor device according to an embodiment. Fig. 2 is a view showing a cross section taken along line AA' in Fig. 1. Fig. 3 is a view showing a cross section taken along line BB' in Fig. 1. In this embodiment, a planar semiconductor device will be described.

[0016] 1 includes an active region 31 and a termination region 32 that is disposed around the active region 31 in a plan view and has corner portions. The corner portions become partial lifetime control regions 33, which will be described later. The active region 31 is a rectangle with four curvatures at its corners.

[0017] 2, the semiconductor device 30 in the AA' cross section has, in an active region 31, an n-type drift layer 1, a p-type semiconductor region 2 on the surface side of the n-type drift layer 1, and an anode electrode 20 on the surface side of the p-type semiconductor region 2. ＋ layer 3, n-type drift layer 1 and n ＋ an n-type buffer layer 4 provided between the n-type silicon dioxide layer 3 and the n-type silicon dioxide layer 4; ＋ The cathode electrode 10 is provided on the back surface side of the layer 3. The front surface side is the side on which the anode electrode 20 is provided, and the back surface side is the side on which the cathode electrode 10 is provided.

[0018] The semiconductor device 30 has, in the termination region 32, a plurality of p-type field rings 5 ​​(p-wells) that extend into the n-type drift layer 1 in the peripheral portion on the front surface side and surround the p-type semiconductor region 2. The p-type field rings 5 ​​are in contact with a field plate 6 via contact holes in the interlayer insulating film 7. The field plate 6 is a technology (structure) that increases the breakdown voltage of diodes and transistors. A portion of the anode electrode 20 and the field plate 6 are protected by an organic protective film 21 (e.g., polyimide).

[0019] The active region 31 and the termination region 32 have a first lifetime control layer 41 and a second lifetime control layer 42 in the n-type drift layer 1. The first lifetime control layer 41 and the second lifetime control layer 42 are low lifetime regions. The low lifetime regions are regions where lifetime control is performed, and have a shorter minority carrier lifetime than other regions in the n-type drift layer 1.

[0020] The first lifetime control layer 41 is a low lifetime region and is formed on the anode side of the n-type drift layer 1. The first lifetime control layer 41 is located closer to the p-type semiconductor region 2 than the center (center line 40) of the thickness of the semiconductor substrate. The thickness of the semiconductor substrate refers to the distance between the anode electrode 20 and the cathode electrode 10.

[0021] The second lifetime control layer 42 is a low lifetime region, and is formed on the cathode side of the n-type drift layer 1. The second lifetime control layer 42 is located n away from the center (center line 40) of the thickness of the semiconductor substrate. ＋ Located on layer 3 side.

[0022] In the B-B' cross section of semiconductor device 30 shown in Figure 3, the configuration of active region 31 is the same as in Figure 2, but the lifetime control layer of termination region 32 is different from that in Figure 2. That is, termination region 32 has a third lifetime control layer 43 and a second lifetime control layer 42 in n-type drift layer 1. The third lifetime control layer 43 is a low lifetime region.

[0023] The third lifetime control layer 43 is outside the active region 31, and particularly at the corners of the main pn junction having a curvature in a plan view as shown in FIG. 1 , an electric field concentrates during recovery, reducing the di / dt resistance. Therefore, by reducing the free carriers in the n-type drift layer 1 moving from the corners of the main pn junction having a curvature toward the periphery in the on-state, the electric field concentration during recovery can be alleviated and the di / dt resistance can be improved.

[0024] The third lifetime control layer 43 is a low lifetime region, and is formed on the anode side of the n-type drift layer 1. The third lifetime control layer 43 is located closer to the p-type semiconductor region 2 than the center (center line 40) of the thickness of the semiconductor substrate.

[0025] The semiconductor device 30 of this embodiment is a semiconductor device including an active region 31 and a termination region 32 arranged around the active region 31 in a plan view and having a corner portion. The active region 31 and the termination region 32 have a first lifetime control layer 41 and a second lifetime control layer 42 in the drift layer, and the corner portion of the termination region 32 has a third lifetime control layer 43 having a larger amount of defects than the first lifetime control layer 41 in the active region 31 and a larger amount of defects than the first lifetime control layer 41 in the other portion of the termination region 32. The other portion of the termination region 32 refers to the portion other than the corner portion. The amount of defects refers to the density (concentration) of defects. The amount of defects in the first lifetime control layer 41 in the active region 31 and the other portion of the termination region 32 is set appropriately.

[0026] The configuration and features of this embodiment will be further described. (1) The first lifetime control layer 41 and the third lifetime control layer 43 are formed by light ion irradiation from the front surface (anode electrode 20 side). Furthermore, they are formed at positions closer to the front surface (anode) than halfway through the thickness of the semiconductor substrate. (2) The second lifetime control layer 42 is formed by light ion irradiation from the back surface (cathode electrode 10 side). Furthermore, they are formed at positions closer to the back surface (cathode electrode 10) than halfway through the thickness of the semiconductor substrate. (3) Because defects also occur in the region irradiated with light ions (through which the ions have passed), it is desirable to irradiate the first lifetime control layer 41 and the third lifetime control layer 43 from the front surface and the second lifetime control layer 42 from the back surface. (4) The first lifetime control layer 41 mainly affects the peak current during recovery. The greater the amount of defects, the more the peak current is suppressed. The second lifetime control layer 42 mainly affects the tail current during recovery. The greater the defect amount, the more the tail current is suppressed. Because the above two layers have a defect layer in the active region, they affect VF and leakage current in a trade-off relationship with the above effects. (5) Because the third lifetime control layer 43 is only present in the termination region, its impact on the forward voltage drop (VF) and leakage current is minor (negligible). (6) The corner portions of the termination region 32 (partial lifetime control regions 33) are more susceptible to electric field concentration than the linear region or active region, making them more susceptible to RecSOA breakdown. Therefore, by shortening the lifetime of these portions (increasing the defect amount), hole concentration can be suppressed and the RecSOA's tolerance can be improved.

[0027] 1 to 3, a semiconductor device 30 will be described. The semiconductor device 30 has a first semiconductor region of a first conductivity type (e.g., n-type) and a second semiconductor region of a second conductivity type (e.g., p-type) provided in the first semiconductor region, and in the active region 31, a first lifetime control layer 41 and a second lifetime control layer 42 are provided in the first semiconductor region, in corner portions of the termination region 32, a third lifetime control layer 43 and the second lifetime control layer 42 are provided in the first semiconductor region, and in other portions of the termination region 32, the first lifetime control layer 41 and the second lifetime control layer 42 are provided in the first semiconductor region.

[0028] The first lifetime control layer 41 in the active region 31 is provided on the second semiconductor region side of the center of the first semiconductor region in the thickness direction of the first semiconductor region, and the second lifetime control layer 42 in the active region 31 is provided on the opposite side of the second semiconductor region from the center of the first semiconductor region in the thickness direction of the first semiconductor region.

[0029] The third lifetime control layer 43 in the termination region 32 is provided on the second semiconductor region side from the center of the first semiconductor region in the thickness direction of the first semiconductor region, and the second lifetime control layer 42 in the termination region 32 is provided on the opposite side of the second semiconductor region from the center of the first semiconductor region in the thickness direction of the first semiconductor region.

[0030] (Process Flow) FIG. 4 is a diagram showing a process flow S50 for the semiconductor device according to the embodiment. In FIG. 4, a method for forming a lifetime control layer will be described. Step S51: The surfaces of the anode electrode 20, the organic protective film 21, etc. are formed. Step S52: The back diffusion layer (n-type buffer layer 4, n ＋Step S53: A back electrode for the cathode electrode 10 is formed. Step S54: (A) Light ions are irradiated to form a front-side lifetime control layer (first lifetime control layer 41). For example, helium ions or protons are used for the light ion irradiation. Step S55: (B) Light ions are irradiated to form a back-side lifetime control layer (second lifetime control layer 42). Step S56: (C) Light ions are irradiated to form a front-side partial lifetime control layer (third lifetime control layer 43). At this time, for example, a metal mask is used to irradiate light ions from the front only onto the corner portions of the termination region 32 (partial lifetime control region 33 in FIG. 1 ), forming a layer with a high defect density only in the corner portions. Step S57: A recovery annealing process is performed. Specifically, crystal recovery and solid-phase diffusion are performed after ion implantation, and the process is completed.

[0031] The irradiation order of (A), (B), and (C) above does not matter, and for example, it is also possible to start with the partial irradiation of (C). In this way, by forming a lifetime control layer with a large amount of defects in the corner portion, it is possible to improve the RecSOA tolerance without changing the conventional characteristics (VF, recovery loss, leakage current).

[0032] Furthermore, since there is no need to form a complex pattern as in Patent Document 1, it is possible to form the pattern by simply adding ion irradiation using a metal mask (C) once in addition to the conventional ion irradiation, which makes it possible to prevent an increase in the number of processes.

[0033] Although this embodiment has been described using a diode, it can also be applied to other semiconductor devices having a pn junction, such as an IGBT, a MOSFET, a bipolar transistor, a thyristor, and the like.

[0034] 1 n-type drift layer (drift layer) 2 p-type semiconductor region 3 n ＋Layer 4 n-type buffer layer 5 p-type field ring 6 field plate 7 interlayer insulating film 10 cathode electrode 20 anode electrode 21 organic protective film 30 semiconductor device 31 active region 32 termination region 33 partial lifetime control region (corner portion) 40 center line 41 first lifetime control layer 42 second lifetime control layer 43 third lifetime control layer

Claims

1. A semiconductor device comprising an active region and a termination region arranged around the active region in a planar view and having a corner portion, wherein the active region and the termination region have a first lifetime control layer and a second lifetime control layer within a drift layer, and the corner portion of the termination region has a third lifetime control layer that has a larger amount of defects than the first lifetime control layer in the active region and that has a larger amount of defects than the first lifetime control layer in other parts of the termination region.

2. The semiconductor device according to claim 1, wherein the first lifetime control layer and the third lifetime control layer are located on the front surface side of the center of the thickness of the semiconductor substrate, and the second lifetime control layer is located on the back surface side of the center of the thickness of the semiconductor substrate.

3. The semiconductor device according to claim 1, characterized in that the semiconductor device has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided in the first semiconductor region, wherein in the active region, the first lifetime control layer and the second lifetime control layer are provided in the first semiconductor region, at corner portions of the termination region, the third lifetime control layer and the second lifetime control layer are provided in the first semiconductor region, and in other portions of the termination region, the first lifetime control layer and the second lifetime control layer are provided in the first semiconductor region.

4. The semiconductor device described in claim 3, characterized in that the first lifetime control layer in the active region is provided on the second semiconductor region side of the center of the first semiconductor region in the thickness direction of the first semiconductor region, and the second lifetime control layer in the active region is provided on the opposite side of the second semiconductor region from the center of the first semiconductor region in the thickness direction of the first semiconductor region.

5. The semiconductor device described in claim 3, characterized in that the third lifetime control layer in the termination region is provided on the second semiconductor region side of the center of the first semiconductor region in the thickness direction of the first semiconductor region, and the second lifetime control layer in the termination region is provided on the opposite side of the second semiconductor region from the center of the first semiconductor region in the thickness direction of the first semiconductor region.

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