Semiconductor device

Abstract

The present invention achieves both an increase in on-current and a decrease in off-leak current. A semiconductor device (1) comprises: a switch body (20); and a light-emitting element (10) that is electrically insulated from the switch body (20). The switch body (20) includes: a substrate (21); a channel layer (22) that is provided above the substrate (21) and that has a first band gap; a barrier layer (23) that is provided above the channel layer (22) and that has a second band gap greater than the first band gap; electrodes (24) and (25) that are provided above the barrier layer (23) and that are separated from each other; and a pn junction layer (26) that is provided above the barrier layer (23) and between the electrode (25) and at least a portion of the electrode (24) and that has a pn junction interface. The pn junction layer (26) includes a p-type layer (26p) and an n-type layer (26n). The electrode (24) is electrically connected to the n-type layer (26n).

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, relay devices using a light-receiving element have been known. For example, Patent Documents 1 to 3 disclose light-receiving elements having an AlGaN / GaN heterostructure. The light-receiving elements disclosed in Patent Documents 1 to 3 use a two-dimensional electron gas (2DEG) generated near the interface of the heterojunction as a channel. Controlling the generation of the 2DEG with light enables light detection or light-based control of conduction and non-conduction.

[0003] International Publication No. 2007 / 135739 Japanese Patent Application Laid-Open No. 2012-33773 Japanese Patent Application Laid-Open No. 2010-73744

[0004] Compared to conventional light receiving elements, there is a demand for both an increase in on-state current when the element is conductive and a reduction in off-state leakage current when the element is non-conductive.

[0005] The present disclosure provides a semiconductor device that can achieve both an increase in on-current and a reduction in off-leak current.

[0006] A semiconductor device according to one aspect of the present disclosure includes a switch body and a light-emitting element electrically insulated from the switch body. The switch body includes a substrate, a first nitride semiconductor layer provided above the substrate and having a first band gap, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a second band gap larger than the first band gap, a first electrode and a second electrode provided spaced apart from each other above the second nitride semiconductor layer, and a third nitride semiconductor layer having a p-n junction interface provided above the second nitride semiconductor layer between at least a portion of the first electrode and the second electrode. The third nitride semiconductor layer includes a first p-type nitride semiconductor layer and a first n-type nitride semiconductor layer. The first electrode is electrically connected to the first n-type nitride semiconductor layer.

[0007] According to the present disclosure, it is possible to achieve both an increase in on-current and a reduction in off-leak current.

[0008] FIG. 1 is a perspective view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view of another example of the semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view for explaining an OFF state of the semiconductor device according to the first embodiment. FIG. 5 is a cross-sectional view for explaining an ON state of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view for explaining an ON state of the semiconductor device according to a first modification of the first embodiment. FIG. 7 is a cross-sectional view showing a configuration of a semiconductor device according to a second modification of the first embodiment. FIG. 8 is a cross-sectional view of a switch main body included in a semiconductor device according to a third modification of the first embodiment. FIG. 9 is a cross-sectional view of a switch main body included in a semiconductor device according to a fourth modification of the first embodiment. FIG. 10 is a cross-sectional view of a switch main body included in a semiconductor device according to a fifth modification of the first embodiment. FIG. 11 is a cross-sectional view of a switch main body included in a semiconductor device according to a sixth modification of the first embodiment. FIG. 12 is a cross-sectional view of a switch main body included in a semiconductor device according to a seventh modification of the first embodiment. FIG. 13 is a cross-sectional view of a switch main body included in a semiconductor device according to an eighth modification of the first embodiment. FIG. 14 is a cross-sectional view of a switch main body included in a semiconductor device according to a second embodiment. FIG. 15 is a cross-sectional view of a switch main body included in a semiconductor device according to a third embodiment. Fig. 16 is a cross-sectional view of a switch main body included in a semiconductor device according to a fourth embodiment. Fig. 17 is a cross-sectional view of a switch main body included in a semiconductor device according to a fifth embodiment. Fig. 18 is a cross-sectional view of a switch main body included in a semiconductor device according to a sixth embodiment. Fig. 19 is a cross-sectional view of a switch main body included in a semiconductor device according to a seventh embodiment.

[0009] (Summary of the Present Disclosure) In a light-receiving element including a semiconductor, photoelectric conversion is carried out by utilizing the photovoltaic effect or the photoconductive effect.

[0010] The photovoltaic effect is an effect that occurs when light is incident near the pn junction interface between a p-type semiconductor layer and an n-type semiconductor layer. Specifically, when light having energy greater than the band gap energy of at least one of the p-type semiconductor layer and the n-type semiconductor layer is incident, electron-hole pairs are generated near the pn junction interface. The generated electron-hole pairs are separated into electrons and holes by the junction electric field of the pn junction and move. Specifically, the electrons move to the n-type semiconductor layer, and the holes move to the p-type semiconductor layer. As a result, a voltage (photovoltaic force) is generated across the pn junction, causing the p-type semiconductor layer to be higher than the n-type semiconductor layer.

[0011] The photoconductive effect is an effect that occurs when light is incident on a semiconductor layer. Here, the semiconductor layer is, for example, an n-type semiconductor layer, but it may also be an i-type semiconductor layer (intrinsic semiconductor layer) or a p-type semiconductor layer. Specifically, when light having energy greater than the band gap energy of a semiconductor layer to which an external voltage is applied is incident, electron-hole pairs are generated within the semiconductor layer. The generated electron-hole pairs are separated into electrons and holes and move depending on the applied voltage. Since more carriers flow within the semiconductor layer than when not irradiated with light, the current flowing within the semiconductor layer increases.

[0012] In the case of the photoconductive effect, the generated electrons and holes tend to disappear due to recombination. Therefore, they do not contribute much to increasing the current flowing under light irradiation, i.e., the on-current. In addition, the high contact resistance between the semiconductor layer and the electrode also hinders the increase in the on-current.

[0013] In contrast, the semiconductor devices disclosed in Patent Documents 1 to 3 attempt to increase the on-current by utilizing two-dimensional electron gas. However, simply utilizing two-dimensional electron gas is not effective in increasing the on-current. Furthermore, even if the on-current can be increased, the off-leak current also increases.

[0014] In the semiconductor device disclosed in Patent Document 1, a p-type layer is disposed on two undoped layers forming a heterojunction. A gate electrode having the same potential as the source electrode is disposed on the p-type layer. In this case, even when light is irradiated, the concentration of 2DEG generated directly below the p-type layer is low, so the on-current cannot be increased.

[0015] When the p-type layer is used in a floating state, the on-current can be easily increased. However, in this case, holes accumulated in the p-type layer during light irradiation cannot be completely removed, and the potential of the p-type layer increases. As a result, the 2DEG directly below the p-type layer is not sufficiently depleted, and a large off-leak current tends to flow.

[0016] Furthermore, in the semiconductor device disclosed in Patent Document 2, a floating p-type layer or gate electrode is disposed, which causes the same problems as those in the semiconductor device disclosed in Patent Document 1.

[0017] Furthermore, in the semiconductor device disclosed in Patent Document 3, an InGaN layer disposed at the interface of the heterojunction is used as a channel. However, the function of the InGaN layer as a channel cannot be sufficiently turned off, so a large off-leak current tends to flow.

[0018] As described above, the semiconductor elements disclosed in Patent Documents 1 to 3 cannot simultaneously increase the on-state current and reduce the off-state leakage current.

[0019] Therefore, the present disclosure provides a semiconductor device that can achieve both an increase in on-state current and a reduction in off-state leakage current.

[0020] A semiconductor device according to a first aspect of the present disclosure includes a switch body and a light-emitting element electrically insulated from the switch body. The switch body includes a substrate, a first nitride semiconductor layer provided above the substrate and having a first bandgap, a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a second bandgap larger than the first bandgap, a first electrode and a second electrode provided spaced apart from each other above the second nitride semiconductor layer, and a third nitride semiconductor layer having a p-n junction interface provided above the second nitride semiconductor layer between at least a portion of the first electrode and the second electrode. The third nitride semiconductor layer includes a first p-type nitride semiconductor layer and a first n-type nitride semiconductor layer. The first electrode is electrically connected to the first n-type nitride semiconductor layer.

[0021] As a result, a 2DEG is generated near the heterojunction interface between the first nitride semiconductor layer and the second nitride semiconductor layer due to spontaneous polarization and piezoelectric polarization. The 2DEG functions as a current path (channel) between the first electrode and the second electrode. In the semiconductor device according to this aspect, the provision of the first p-type nitride semiconductor layer increases the potential directly below the first p-type nitride semiconductor layer, causing the 2DEG to disappear and become depleted. In this state, the channel is blocked, and the switch body is therefore in a non-conducting state (off state).

[0022] When light is incident near the pn junction interface, a higher voltage is generated in the first p-type nitride semiconductor layer than in the first n-type nitride semiconductor layer due to the photovoltaic effect. As a result, the potential directly below the first p-type nitride semiconductor layer decreases, generating 2DEG, and the switch body enters a conductive state (ON state). In the ON state, the 2DEG and electrons generated by the photovoltaic effect can increase the ON current. Furthermore, since 2DEG is also generated directly below each of the first electrode and the second electrode, contact resistance is reduced. This also contributes to an increase in the ON current.

[0023] In the off state, since the first n-type nitride semiconductor layer is electrically connected to the first electrode, even if holes accumulate in the first p-type nitride semiconductor layer during light irradiation (on state), the accumulated holes can be released to the first electrode via the first n-type nitride semiconductor layer. This makes it possible to prevent the potential of the first p-type nitride semiconductor layer from increasing in the off state, so that the 2DEG directly below the first p-type nitride semiconductor layer is sufficiently depleted, thereby reducing the off-leakage current.

[0024] In this way, the semiconductor device according to this aspect can achieve both an increase in on-state current and a reduction in off-state leakage current.

[0025] In this specification, the pn junction interface refers to the contact surface when a p-type semiconductor layer and an n-type semiconductor layer are in direct contact with each other. The p-type semiconductor layer and the n-type semiconductor layer may be joined with an i-type semiconductor layer (intrinsic semiconductor layer) sandwiched therebetween. In this case, the pn junction interface can be considered as the range that maintains a predetermined width (thickness) from the contact surface between the p-type semiconductor layer and the i-type semiconductor layer to the contact surface between the n-type semiconductor layer and the i-type semiconductor layer. In addition, in this specification, a nitride semiconductor refers to a nitride semiconductor having a general composition formula of Al ｘ In ｙ Ga １－ｘ－ｙ N (0≦x≦1, 0≦y≦1, 0≦x+y≦1). When x = y = 0, it is GaN. When y = 0 and a certain value of x (0<x<1), it is expressed as AlGaN, and when x = 0 and a certain value of y (0<y<1), it is expressed as InGaN.

[0026] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, further comprising a recessed portion provided in the second nitride semiconductor layer, and the first p-type nitride semiconductor layer is provided so as to cover the recessed portion.

[0027] This allows the voltage generated by the photovoltaic effect to be concentrated at the bottom of the recess, thereby increasing the 2DEG concentration generated directly below the recess, thereby reducing the on-resistance and further increasing the on-current.

[0028] A semiconductor device according to a third aspect of the present disclosure is a semiconductor device according to the first or second aspect, wherein the pn junction interface extends further toward the second electrode than the end of the first electrode on the second electrode side.

[0029] This increases the amount of light absorbed by the third nitride semiconductor layer, thereby enhancing the effect of increasing the on-current due to electrons generated by the photovoltaic effect.

[0030] A semiconductor device according to a fourth aspect of the present disclosure is the semiconductor device according to any one of the first to third aspects, wherein the first n-type nitride semiconductor layer is in contact with the top surface of the first p-type nitride semiconductor layer and a side surface of the first p-type nitride semiconductor layer on the first electrode side.

[0031] This increases the area of ​​the pn junction interface, thereby enhancing the effect of increasing the on-current due to electrons generated by the photovoltaic effect. Furthermore, the increased area of ​​the pn junction interface increases the rate at which holes accumulated in the first p-type nitride semiconductor layer are released when irradiated with light (when the switch is on). This increases the switching speed of the switch itself.

[0032] A semiconductor device according to a fifth aspect of the present disclosure is a semiconductor device according to any one of the first to fourth aspects, wherein the first electrode is in contact with the top surface and side surfaces of the first n-type nitride semiconductor layer.

[0033] This allows the distance between the first electrode and the second electrode to be shortened, thereby realizing a miniaturized switch body.

[0034] A semiconductor device according to a sixth aspect of the present disclosure is a semiconductor device according to any one of the first to fifth aspects, further comprising an insulating film provided between the second nitride semiconductor layer and the third nitride semiconductor layer.

[0035] As a result, the switch body has a so-called MIS (Metal-Insulator-Semiconductor) structure, which makes it possible to reduce the off-leak current while also making it smaller.

[0036] A semiconductor device according to a seventh aspect of the present disclosure is a semiconductor device according to any one of the first to sixth aspects, wherein the first electrode extends toward the second electrode beyond the end of the first p-type nitride semiconductor layer on the second electrode side.

[0037] The semiconductor device has an npn transistor structure formed by a first n-type nitride semiconductor layer, a first p-type nitride semiconductor layer, and a 2DEG. In this case, if an electric field concentrates on the side surface of the first p-type nitride semiconductor layer due to a potential difference between the second electrode and the first electrode, a pseudo inversion channel may be formed near the side surface. In contrast, in the semiconductor device according to the seventh aspect, the first electrode extends toward the second electrode, making it difficult for an electric field to concentrate on the side surface of the first p-type nitride semiconductor layer. Therefore, an inversion channel is unlikely to be formed on the side surface of the first p-type nitride semiconductor layer, thereby reducing leakage current through the side surface.

[0038] A semiconductor device according to an eighth aspect of the present disclosure is the semiconductor device according to any one of the first to seventh aspects, wherein the first p-type nitride semiconductor layer includes a first region including a side surface on the second electrode side, and a second region different from the first region, and the acceptor concentration in the first region is higher than the acceptor concentration in the second region.

[0039] As a result, the acceptor concentration in the first region is high, so that an inversion channel is unlikely to be formed even if an electric field is concentrated in the first region, thereby reducing leakage current through the first region.

[0040] A semiconductor device according to a ninth aspect of the present disclosure is the semiconductor device according to any one of the first to eighth aspects, further comprising a protective film. The protective film includes a planar portion covering an upper surface of the second nitride semiconductor layer and a sidewall portion covering a side surface of the third nitride semiconductor layer. The thickness of the sidewall portion is greater than the thickness of the planar portion.

[0041] As a result, the sidewalls of the protective film are thick, making it difficult for an electric field to concentrate on the side surfaces of the first p-type nitride semiconductor layer, and therefore it is difficult for an inversion channel to form on the side surfaces of the first p-type nitride semiconductor layer, thereby reducing leakage current through the side surfaces.

[0042] A semiconductor device according to a tenth aspect of the present disclosure is the semiconductor device according to any one of the first to ninth aspects, further comprising a fourth nitride semiconductor layer having a p-n junction interface provided above the second nitride semiconductor layer and between the third nitride semiconductor layer and at least a part of the second electrode. The fourth nitride semiconductor layer includes a second p-type nitride semiconductor layer and a second n-type nitride semiconductor layer. The second electrode is electrically connected to the second n-type nitride semiconductor layer.

[0043] This allows for bidirectional switching.

[0044] A semiconductor device according to an eleventh aspect of the present disclosure is the semiconductor device according to any one of the first to tenth aspects, further comprising: a third electrode provided above the second nitride semiconductor layer and spaced apart from the first electrode so as to sandwich the first electrode between the second electrode and the third electrode; and a fifth nitride semiconductor layer having a p-n junction interface provided above the second nitride semiconductor layer between at least a portion of the first electrode and the third electrode. The fifth nitride semiconductor layer includes a third p-type nitride semiconductor layer and a third n-type nitride semiconductor layer. The first electrode is electrically connected to the third n-type nitride semiconductor layer.

[0045] This allows for bidirectional switching.

[0046] A semiconductor device according to a twelfth aspect of the present disclosure is the semiconductor device according to any one of the first to eleventh aspects, wherein the third nitride semiconductor layer further includes: a fourth n-type nitride semiconductor layer provided between the first p-type nitride semiconductor layer and the first n-type nitride semiconductor layer and in contact with the first p-type nitride semiconductor layer, and a fourth p-type nitride semiconductor layer provided between the first p-type nitride semiconductor layer and the first n-type nitride semiconductor layer and in contact with the first n-type nitride semiconductor layer, and the fourth p-type nitride semiconductor layer is in ohmic contact with the fourth n-type nitride semiconductor layer.

[0047] This increases the voltage generated by the photovoltaic effect, further increasing the 2DEG concentration directly below the first p-type nitride semiconductor layer, thereby reducing the on-resistance and further increasing the on-current.

[0048] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0049] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0050] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0051] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0052] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0053] In this specification, "thickness direction" refers to the thickness direction of the semiconductor device, and is the direction perpendicular to the main surface of the substrate. Furthermore, "plan view" refers to the view from a direction perpendicular to the main surface of the substrate, unless otherwise specified. In the case of a flat member such as a plate or layer, the "main surface" refers to the main surface of the member, for example, the surface with the largest area or the surface opposite to the surface with the largest area. The main surface is usually flat, but may include minute irregularities or curvatures.

[0054] In this specification, the term "major component" refers to the component that is contained in the largest proportion, expressed in mole percent, in a material.

[0055] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0056] First Embodiment [Configuration] First, the configuration of a semiconductor device according to a first embodiment will be described with reference to FIGS. 1 and 2. FIG.

[0057] 1 and 2 are a perspective view and a cross-sectional view, respectively, of a semiconductor device 1 according to this embodiment. Note that FIG. 2 illustrates a light-emitting element 10 and a switch body 20, and omits the illustration of a support substrate 30, a resin member 50, and the like. The positional relationship between the light-emitting element 10 and the switch body 20 shown in FIG. 2 is upside down compared to the positional relationship shown in FIG. 1. That is, "upward" in FIG. 2 refers to the direction from the light-emitting element 10 toward the switch body 20, and corresponds to "downward" in FIG. 1. In the following description, unless otherwise specified, the up-down direction is defined as shown in FIG. 2. That is, the direction from the light-emitting element 10 toward the switch body 20 is defined as "upward," and the opposite direction is defined as "downward."

[0058] The semiconductor device 1 according to this embodiment is a semiconductor relay that relays an input signal and outputs it to a predetermined circuit. Specifically, the semiconductor device 1 is an optically coupled semiconductor relay. A semiconductor relay is also called an SSR (Solid-State Relay).

[0059] 1 and 2 , the semiconductor device 1 includes a light-emitting element 10 and a switch body 20. The semiconductor device 1 also includes a support substrate 30, a plurality of terminals 41 a, 41 b, 41 c, 41 d, 45 a, and 45 b, external terminals 43 a, 43 b, and 43 c, wires 44 a and 44 b, and a resin member 50.

[0060] The light-emitting element 10 is an element that emits light. When the semiconductor device 1 is used as a semiconductor relay, an input signal is input to the light-emitting element 10. The light-emitting element 10 switches between emitting and not emitting light in response to the input signal. In this embodiment, the light-emitting element 10 emits light toward the switch body 20. The light-emitting element 10 is electrically insulated from the switch body 20. As will be described in detail later, the light-emitting element 10 emits light that is incident on a pn junction layer 26 provided in the switch body 20. At least a portion of the light may be incident on a channel layer 22 and a barrier layer 23 provided in the switch body 20.

[0061] For example, the light-emitting element 10 is an LED (Light Emitting Diode) element. The light emitted by the light-emitting element 10 may be ultraviolet light or visible light. The light-emitting element 10 may also be an organic EL (Electroluminescence) element or a semiconductor laser element. The specific configuration of the light-emitting element 10 will be described later.

[0062] The switch body 20 switches between conductive (ON) and non-conductive (OFF) states depending on the incident light. Specifically, in the switch body 20, the electrodes 24 and 25 shown in Fig. 2 are switched between conductive and non-conductive states depending on whether the light-emitting element 10 emits light or not. The specific configuration of the switch body 20 will be described later.

[0063] The support substrate 30 is an example of a support member that supports the switch body 20. The support substrate 30 is a ceramic substrate, a glass epoxy substrate, or the like, but is not limited to these.

[0064] As shown in FIG. 1 , conductive terminals 41 a, 41 b, 41 c, and 41 d are provided on the mounting surface (main surface on the switch body 20 side) of the support substrate 30. External terminals 43 a, 43 b, and 43 c are provided on the back surface (main surface opposite the mounting surface) of the support substrate 30. The external terminals 43 a, 43 b, and 43 c correspond to the terminals 41 a, 41 b, and 41 c, respectively, and are electrically connected to each other via vias (not shown) that penetrate the support substrate 30. In addition, an external terminal (not shown) corresponding to the terminal 41 d is provided on the back surface of the support substrate 30, and this external terminal and the terminal 41 d are connected via a via (not shown). The external terminal corresponding to the terminal 41 d and the external terminal 43 c are external input terminals of the semiconductor device 1. The external terminals 43 a and 43 b are external output terminals of the semiconductor device 1. An input signal is input to an external terminal corresponding to the terminal 41d and to an external terminal 43c, and an output signal corresponding to the input signal is output from the external terminals 43a and 43b.

[0065] For example, the switch body 20 is flip-chip mounted on the support substrate 30. Although not shown, the electrode 24 of the switch body 20 and the terminal 41a are electrically and mechanically connected via a bump. The electrode 25 of the switch body 20 and the terminal 41b are electrically and mechanically connected via a bump.

[0066] In this embodiment, as shown in FIG. 1 , the light-emitting element 10 is stacked on the main surface of the switch body 20. The light-emitting element 10 is provided with terminals 45a and 45b. The terminal 45a is connected to the terminal 41c by a wire 44a. The terminal 45b is connected to the terminal 41d by a wire 44b. Although not shown, the electrode 14 (see FIG. 2 ) of the light-emitting element 10 is electrically connected to the terminal 45a. The electrode 15 (see FIG. 2 ) of the light-emitting element 10 is electrically connected to the terminal 45b. As a result, an input signal input to the semiconductor device 1 is supplied to the light-emitting element 10.

[0067] The terminals, vias, and external terminals, as well as the bumps and wires provided on the support substrate 30, are each formed using a conductive material such as a metal. The metal used for the terminals, vias, and external terminals, as well as the bumps and wires, is, for example, copper, silver, gold, aluminum, or the like, but is not particularly limited.

[0068] The resin member 50 seals the light emitting element 10, the switch body 20, and at least a part of the support substrate 30. The resin member 50 is provided to protect the light emitting element 10 and the switch body 20. The resin member 50 can be made of a resin typically used for molding semiconductor elements.

[0069] Next, the specific configuration of the light emitting element 10 and the switch body 20 will be described with reference to FIG.

[0070] 2 , the light-emitting element 10 includes an n-type layer 11, an active layer 12, a p-type layer 13, and two electrodes 14 and 15. The n-type layer 11 is an example of an n-type nitride semiconductor layer, and is, for example, an n-type GaN layer with a thickness of 1 μm. The active layer 12 is an example of a nitride semiconductor layer located between the n-type layer 11 and the p-type layer 13, and has, for example, a multiple quantum well structure in which InGaN layers and GaN layers are alternately stacked. The p-type layer 13 is an example of a p-type nitride semiconductor layer, and is, for example, a p-type GaN layer with a thickness of 1 μm.

[0071] The GaN layer refers to a nitride semiconductor layer containing GaN as a main component. An n-type GaN layer and a p-type GaN layer are formed by adding an n-type impurity (donor) or a p-type impurity (acceptor) to the GaN layer. Examples of n-type impurities include Si and Ge. Examples of p-type impurities include Mg and Be. It is not necessary to add impurities to form an n-type or p-type GaN layer. For example, even if it is an undoped GaN layer, it is possible to form an n-type or p-type GaN layer by adding 10 １５ cm －３A GaN layer that maintains a carrier concentration of about 1000 nm can be used as an n-type GaN layer. Note that "undoped" is a term that means that the layer is not doped with n-type or p-type impurities, but does not mean that the layer is not doped with any impurities. In other words, a GaN layer doped with C or the like, or a GaN layer containing unavoidable impurities that are unavoidable during manufacturing, can also be considered "undoped."

[0072] The electrodes 14 and 15 receive power to cause the light-emitting element 10 to emit light. The electrodes 14 and 15 are each formed using a conductive material such as metal. As shown in FIG. 2 , the electrode 14 is connected to the p-type layer 13. The electrode 15 is connected to the n-type layer 11. The electrode 14 is also connected to a terminal 45a shown in FIG. 1 outside the light-emitting element 10. The electrode 15 is also connected to a terminal 45b shown in FIG. 1 outside the light-emitting element 10. An input signal is input to the electrodes 14 and 15 via the terminals 45a and 45b. When a current flows from the electrode 14 to the electrode 15, light is generated in the active layer 12. At least a portion of the generated light is incident on the switch body 20.

[0073] The light-emitting element 10 is electrically insulated from the switch body 20. In this embodiment, the light-emitting element 10 is provided below the substrate 21 of the switch body 20. Specifically, as shown in FIG. 2 , the light-emitting element 10 is bonded to the lower surface of the switch body 20 via an insulating layer 60. The insulating layer 60 is formed using an insulating resin material such as epoxy. The insulating layer 60 is translucent to the light emitted by the light-emitting element 10. By adjusting the material and thickness of the insulating layer 60, electrical insulation between the light-emitting element 10 and the switch body 20 can be easily ensured.

[0074] The insulating layer 60 does not have to be provided. Fig. 3 is a cross-sectional view of another example of the semiconductor device according to the present embodiment. As shown in Fig. 3, the light-emitting element 10 and the switch body 20 may be directly bonded to each other without providing the insulating layer 60. In this case, the substrate 21 of the switch body 20 is an insulating substrate having electrical insulation properties.

[0075] 2, the switch body 20 includes a substrate 21, a channel layer 22, a barrier layer 23, electrodes 24 and 25, a pn junction layer 26, and a protective film 27. Note that in Fig. 2, the cross-sectional views of the channel layer 22 and the barrier layer 23 of the switch body 20 are not shaded. This also applies to Fig. 3 and other cross-sectional views described later.

[0076] The substrate 21 is an insulating substrate having electrical insulation properties. The substrate 21 is, for example, a sapphire substrate, but is not limited to this. The substrate 21 may also be formed using SiC or the like.

[0077] The substrate 21 is a light-transmitting substrate that is transparent to the light from the light-emitting element 10. The substrate 21 has a single-layer structure and has a uniform refractive index inside. This makes it possible to suppress refraction and scattering of the light from the light-emitting element 10, and to allow the light to propagate efficiently to the pn junction layer 26. The substrate 21 may have a multi-layer structure.

[0078] The channel layer 22 is an example of a first nitride semiconductor layer having a first band gap, and is provided above the substrate 21. The channel layer 22 is, for example, an undoped GaN layer, but is not limited to this. The channel layer 22 may be formed using other nitride semiconductors such as InGaN or AlGaN. The channel layer 22 is formed using a film formation method such as epitaxial growth on the substrate 21. The thickness of the channel layer 22 is, for example, not limited to, 100 nm or more and 1000 nm or less. A buffer layer may be provided between the channel layer 22 and the substrate 21.

[0079] The barrier layer 23 is an example of a second nitride semiconductor layer having a second band gap larger than the first band gap, and is provided above the channel layer 22. In the present embodiment, the barrier layer 23 is in contact with the upper surface of the channel layer 22. The barrier layer 23 is, for example, an undoped AlGaN layer. The barrier layer 23 is formed continuously after the step of forming the channel layer 22 using a film formation method such as epitaxial growth. The thickness of the barrier layer 23 is, for example, not less than 5 nm and not more than 100 nm.

[0080] A heterojunction is formed between the barrier layer 23 and the channel layer 22, and 2DEG 28 is generated near the junction interface in the channel layer 22 due to spontaneous polarization and piezoelectric polarization. The 2DEG 28 functions as a current path when the switch body 20 is on. Note that, as long as the 2DEG 28 is generated in the channel layer 22, another layer may be provided between the channel layer 22 and the barrier layer 23.

[0081] The electrodes 24 and 25 are an example of a first electrode and a second electrode that are spaced apart from each other, and are provided above the barrier layer 23. In this embodiment, the electrodes 24 and 25 are each in contact with the upper surface of the barrier layer 23. The electrodes 24 and 25 are formed using a conductive material such as a metal. For example, the electrodes 24 and 25 have a layered structure including a Ti layer and an Al layer stacked on the upper surface of the Ti layer, but are not limited to this.

[0082] The pn junction layer 26 is an example of a third nitride semiconductor layer having a pn junction interface, and is provided above the barrier layer 23, between at least a part of the electrode 24 and the electrode 25. In the present embodiment, the pn junction layer 26 is provided between the electrode 25 and a portion where the electrode 24 is in contact with the barrier layer 23.

[0083] 2, the pn junction layer 26 includes a p-type layer 26p and an n-type layer 26n. The p-type layer 26p and the n-type layer 26n are stacked in this order from the barrier layer 23 side. The p-type layer 26p and the n-type layer 26n are in contact with each other, and the contact surface corresponds to the pn junction interface.

[0084] The p-type layer 26p is an example of a first p-type nitride semiconductor layer, and is provided above the barrier layer 23. In this embodiment, the p-type layer 26p is in contact with the upper surface of the barrier layer 23. The p-type layer 26p is a p-type GaN layer doped with p-type impurities such as Mg. The thickness of the p-type layer 26p is, for example, not less than 50 nm and not more than 300 nm, but is not limited to this. The impurity concentration of the p-type layer 26p is, for example, 1×10 １７ cm －３ 1x10 or more １９ cm －３The p-type layer 26p is not limited to a GaN layer, but may be formed using other nitride semiconductors such as AlGaN and InGaN.

[0085] The n-type layer 26n is an example of a first n-type nitride semiconductor layer, and is provided above the barrier layer 23. In this embodiment, the n-type layer 26n is in contact with the upper surface of the p-type layer 26p, but is not in contact with the barrier layer 23. The n-type layer 26n is an n-type GaN layer doped with n-type impurities such as Si. The thickness of the n-type layer 26n is, for example, not less than 50 nm and not more than 300 nm, but is not limited to this. The impurity concentration of the n-type layer 26n is, for example, 1×10 １７ cm －３ 1x10 or more １９ cm －３ As described above, the n-type layer 26n may be an undoped GaN layer that can be regarded as an n-type GaN layer. Furthermore, the n-type layer 26n is not limited to a GaN layer and may be formed using other nitride semiconductors such as AlGaN or InGaN.

[0086] The protective film 27 is a film that covers the upper surface of the barrier layer 23 and the side surfaces of the pn junction layer 26. In this embodiment, the protective film 27 contacts and covers the upper surface of the barrier layer 23, the side surfaces of the pn junction layer 26, and part of the upper surface of the pn junction layer 26, specifically part of the upper surface of the n-type layer 26n. The protective film 27 covers the side surfaces of the pn junction layer 26 on the electrode 25 side and the side surface opposite to the electrode 25. The protective film 27 is made of, for example, SiN or SiO ２ The protective film 27 may not be provided.

[0087] Electrode 24 is electrically connected to n-type layer 26n through an opening provided in protective film 27. In this embodiment, electrode 24 extends from the contact portion with barrier layer 23 toward electrode 25 so as to cover part of protective film 27, and is in contact with the upper surface of n-type layer 26n. As a result, the potential of n-type layer 26n is fixed to the potential of electrode 24.

[0088] [Operation] Next, the operation of the semiconductor device 1 according to this embodiment will be described with reference to Fig. 4 and Fig. 5. Fig. 4 and Fig. 5 are cross-sectional views for explaining the off state and the on state of the semiconductor device 1 according to this embodiment, respectively. Note that in Fig. 4 and Fig. 5, the light-emitting element 10 is simply represented by a circuit symbol.

[0089] In the semiconductor device 1, the electrode 24 and the electrode 25 are switched between conductive and non-conductive states depending on whether the light-emitting element 10 emits light or not. That is, the switch body 20 receives light from the light-emitting element 10 and switches between conductive (ON) and non-conductive (OFF) states between the electrode 24 and the electrode 25. In this embodiment, the switch body 20 is in a conductive state when it receives light and in a non-conductive state when it does not receive light. That is, the switch body 20 is a switching element controlled by light. The switch body 20 has a configuration similar to a transistor that functions as a switching element. Therefore, the electrode 24 can be referred to as a source electrode, and the electrode 25 can be referred to as a drain electrode. The pn junction layer 26 corresponds to the control terminal (gate) of the transistor. For example, a higher voltage than that of the electrode 24 is applied as a bias voltage to the electrode 25. The magnitude of the bias voltage is, for example, approximately 5 V to 10 V.

[0090] First, the off state will be described using Figure 4. In the off state, the light-emitting element 10 does not emit light. In the off state, the 2DEG 28 generated in the channel layer 22 disappears in the region below the p-type layer 26p. This is because the potential directly below the p-type layer 26p increases, causing depletion. As a result, the channel between the electrode 24 and the electrode 25 is blocked, and the switch body 20 becomes non-conductive (off).

[0091] Next, the on state will be described with reference to Fig. 5. In the on state, the light emitting element 10 emits light. Light from the light emitting element 10 passes through the channel layer 22 and the barrier layer 23 and reaches the pn junction layer 26, where it is absorbed. This is because the energy of the light from the light emitting element 10 and the band gap energy of each layer have the following relationship:

[0092] Specifically, the band gap energy of the channel layer 22 is larger than the energy of light from the light-emitting element 10. Furthermore, since the band gap of the barrier layer 23 is larger than the band gap energy of the channel layer 22, the band gap energy of the barrier layer 23 is also larger than the energy of light from the light-emitting element 10. As a result, the channel layer 22 and the barrier layer 23 are unable to generate electron-hole pairs due to insufficient energy of the light from the light-emitting element 10, and the light passes through the channel layer 22 and the barrier layer 23.

[0093] The bandgap energy of at least one of the p-type layer 26p and the n-type layer 26n is smaller than the energy of light from the light-emitting element 10. As a result, light from the light-emitting element 10 is absorbed by at least one of the p-type layer 26p and the n-type layer 26n, generating electron-hole pairs. Due to the photovoltaic effect, a higher voltage is generated in the p-type layer 26p than in the n-type layer 26n. As a result, the potential decreases directly below the p-type layer 26p, generating 2DEG 28. The channel between the electrode 24 and the electrode 25 is conductive due to the 2DEG 28, so the switch body 20 is conductive (ON).

[0094] In terms of the penetration depth of light, the thickness of the channel layer 22 is thinner than the penetration depth of light from the light emitting element 10. For example, the penetration depth d0 of light is expressed by the following formula (1).

[0095] (1) d0 = {1 + ln(1 - R)} / A A is the absorption coefficient of light. In the case of GaN, A > 100,000 [1 / cm]. R is the reflection coefficient of light. In the case of GaN, R can be considered to be substantially 0. Therefore, in the case of GaN, d0 is greater than 100 nm. By making the thickness of the channel layer 22 less than d0, light can be transmitted through the channel layer 22 and reach the pn junction layer 26.

[0096] In the on-state, the on-current can be increased by the 2DEG 28 and electrons generated in the pn junction layer 26 due to the photovoltaic effect. In addition, the 2DEG 28 is generated directly below each of the electrodes 24 and 25, reducing the contact resistance. This also increases the on-current.

[0097] In the on-state, holes may accumulate in the p-type layer 26p. If holes continue to remain in the p-type layer 26p after the light-emitting element 10 is turned off, the decrease in the potential of the p-type layer 26p is delayed, which causes off-leakage current. In contrast, in the present embodiment, the n-type layer 26n is electrically connected to the electrode 24. Therefore, even if holes accumulate in the p-type layer 26p during light irradiation (on-state), the accumulated holes can be released to the electrode 24 via the n-type layer 26n. This prevents the potential of the p-type layer 26p from increasing in the off-state, thereby reducing off-leakage current.

[0098] As described above, the semiconductor device 1 according to this embodiment can achieve both an increase in on-current and a reduction in off-leak current.

[0099] In the present embodiment, an example has been shown in which the light-emitting element 10 and the switch body 20 are bonded via the insulating layer 60 or directly bonded, but the present invention is not limited to this. The light-emitting element 10 and the switch body 20 may be provided spaced apart from each other. An optical element, such as a lens or a light-guiding member, for adjusting the optical path may be disposed between the light-emitting element 10 and the switch body 20.

[0100] In this way, when the light-emitting element 10 and the switch body 20 are disposed apart from each other and electrical insulation between them can be ensured, the substrate 21 does not have to be an insulating substrate, and may be a semiconductor substrate or a conductive substrate. The same applies to the case where electrical insulation between the light-emitting element 10 and the switch body 20 can be ensured by the insulating layer 60 shown in FIG.

[0101] Furthermore, the semiconductor device 1 may not necessarily include the support substrate 30, the terminals 41a, 41b, 41c, 41d, 43a, 43b, 43c, 45a, and 45b, the wires 44a and 44b, and the resin member 50. For example, instead of these components, the semiconductor device 1 may include a first frame member that supports the light-emitting element 10 and a second frame member that supports the switch body 20. The first frame member and the second frame member are each formed using a conductive material such as metal. The first frame member functions as part of a transmission path for an input signal to the light-emitting element 10, and the second frame member functions as part of a transmission path for an output signal from the switch body 20.

[0102] [Modifications] Next, a description will be given of several modifications of embodiment 1. The following description will focus on the differences from embodiment 1, and the description of commonalities will be omitted or simplified.

[0103] <Modification 1> In the semiconductor device according to Modification 1, the size of the band gap of the channel layer 22 is different from that of the first embodiment.

[0104] 6 is a cross-sectional view illustrating the on-state of the semiconductor device according to the first modification of the first embodiment. As shown in FIG. 6, the band gap energy of the channel layer 22 is smaller than the energy of the light from the light emitting element 10. Therefore, part of the light from the light emitting element 10 is absorbed by the channel layer 22, generating electron-hole pairs within the channel layer 22. This reduces the on-resistance. The size of the band gap of the channel layer 22 can be adjusted, for example, by adjusting the composition of the channel layer 22 or the amount of impurities added.

[0105] Another portion of the light from the light-emitting element 10 passes through the channel layer 22 and the barrier layer 23, reaches the pn junction layer 26, and is absorbed therein, similarly to the first embodiment. As a result, a 2DEG 28 is generated directly below the p-type layer 26p, and electrical conduction is established between the electrode 24 and the electrode 25, similarly to the first embodiment.

[0106] As described above, according to this modification, the light from the light-emitting element 10 can be photoelectrically converted in the channel layer 22, thereby improving the light utilization efficiency. Furthermore, the electron-hole pairs generated in the channel layer 22 can reduce the on-resistance, thereby increasing the on-current.

[0107] <Modification 2> A semiconductor device according to Modification 2 differs from that of the first embodiment in the position of the light emitting element 10.

[0108] 7 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 2 of Embodiment 1. As shown in Fig. 7, light-emitting element 10 is disposed above switch body 20, i.e., on the side of substrate 21 where electrodes 24 and 25 are provided.

[0109] The thickness of the pn junction layer 26 is thinner than the penetration depth d0 of light. This allows a portion of the light from the light emitting element 10 to pass through the pn junction layer 26 and reach the channel layer 22. The light that reaches the channel layer 22 generates electron-hole pairs in the channel layer 22, thereby reducing the on-resistance.

[0110] According to this modification, the substrate 21 does not need to transmit light. This broadens the range of materials that can be used for the substrate 21. For example, a reflective substrate that reflects light can be used as the substrate 21. In this case, light from the light-emitting element 10 that is not absorbed by the pn junction layer 26 and the channel layer 22 can be reflected by the substrate 21 and reabsorbed by the pn junction layer 26, the channel layer 22, etc. This improves the light utilization efficiency. Note that instead of a reflective substrate, a transparent substrate with a reflective layer provided on the back surface side can also be used as the substrate 21.

[0111] The thickness of the pn junction layer 26 may be greater than the penetration depth d0 of light. In this case, the light from the light emitting element 10 can be effectively used to generate electron-hole pairs in the pn junction layer 26.

[0112] <Modification 3> In the semiconductor device according to Modification 3, the length of the pn junction interface is different from that of the first embodiment.

[0113] 8 is a cross-sectional view of a switch body 120 included in a semiconductor device according to Modification 3 of Embodiment 1. As shown in Fig. 8, the switch body 120 includes a pn junction layer 126 instead of the pn junction layer 26 according to Embodiment 1. The pn junction layer 126 includes a p-type layer 126p and an n-type layer 126n.

[0114] The p-type layer 126p and the n-type layer 126n correspond to the p-type layer 26p and the n-type layer 26n, respectively, and are different in size. Specifically, the p-n junction interface, which is the contact surface between the p-type layer 126p and the n-type layer 126n, extends toward the electrode 25 beyond the end of the electrode 24 on the electrode 25 side. In other words, the shortest distance between the electrode 25 and the p-n junction interface is shorter than the shortest distance between the electrode 25 and the electrode 24.

[0115] This increases the area of ​​the pn junction interface, thereby increasing the efficiency of absorbing light from the light-emitting element 10. The number of electron-hole pairs generated in the pn junction layer 126 also increases, further increasing the on-current. Furthermore, the increased area of ​​the pn junction interface increases the rate at which holes accumulated in the p-type layer 126p are released when light is irradiated (when the device is on). This increases the switching speed of the switch body 120.

[0116] <Modification 4> A semiconductor device according to Modification 4 differs from that of the first embodiment in the shape of the pn junction interface.

[0117] 9 is a cross-sectional view of a switch body 220 included in a semiconductor device according to Modification 4 of Embodiment 1. As shown in Fig. 9, the switch body 220 includes a pn junction layer 226 instead of the pn junction layer 26 according to Embodiment 1. The pn junction layer 226 includes a p-type layer 26p and an n-type layer 226n.

[0118] The n-type layer 226n corresponds to the n-type layer 26n, but has a different shape. Specifically, the n-type layer 226n is in contact with an upper surface 26pa of the p-type layer 26p and a side surface 26pb of the p-type layer 26p facing the electrode 24. The n-type layer 226n is in contact with the upper surface of the barrier layer 23 on the electrode 24 side of the p-type layer 26p.

[0119] This increases the area of ​​the pn junction interface, thereby increasing the efficiency of absorbing light from the light-emitting element 10. The number of electron-hole pairs generated in the pn junction layer 226 also increases, further increasing the on-current. Furthermore, the increased area of ​​the pn junction interface increases the rate at which holes accumulated in the p-type layer 26p are released when irradiated with light (when the device is on). This increases the switching speed of the switch body 220.

[0120] The n-type layer 226n is not in contact with the side surface 26pc of the p-type layer 26p on the electrode 25 side. The n-type layer 226n is not in contact with the top surface of the barrier layer 23 on the electrode 25 side of the p-type layer 26p. If the n-type layer 226n covers the side surface 26pc, the n-type layer 226n and the 2DEG 28 on the electrode 25 side will come close to each other, causing a leakage current. Since the n-type layer 226n does not cover the side surface 26pc, the leakage current can be suppressed.

[0121] The "electrode 24 side" refers to a direction determined based on the positional relationship between electrode 24 and electrode 25, and specifically refers to the direction from electrode 25 toward electrode 24 (leftward in FIG. 9). The "electrode 25 side" refers to the opposite direction from electrode 24, i.e., the direction from electrode 24 toward electrode 25 (rightward in FIG. 9).

[0122] <Modification 5> A semiconductor device according to Modification 5 is different from Modification 4 of the first embodiment in the shape of the protective film.

[0123] 10 is a cross-sectional view of a switch body 320 included in a semiconductor device according to Modification 5 of Embodiment 1. As shown in Fig. 10, the switch body 320 includes a protective film 327 instead of the protective film 27 according to Modification 4 of Embodiment 1.

[0124] The protective film 327 corresponds to the protective film 27, but has a different shape. Specifically, the protective film 327 does not cover the side surface 226nb of the n-type layer 226n facing the electrode 24. The protective film 327 covers a part of the upper surface 226na of the n-type layer 226n and the side surface 226nc of the n-type layer 226n facing the electrode 25. In other words, the protective film 327 is not provided between the side surface 226nb of the n-type layer 226n and the electrode 24. The electrode 24 is in contact with the upper surface 226na and the side surface 226nb of the n-type layer 226n.

[0125] This eliminates the need for a portion of the protective film 327, thereby shortening the distance between the electrodes 24 and 25. This allows the switch body 320 to be made smaller.

[0126] <Modification 6> A semiconductor device according to Modification 6 is different from that of the first embodiment in the shape of the electrode connected to the n-type layer 26n.

[0127] 11 is a cross-sectional view of a switch body 420 included in a semiconductor device according to Modification 6 of Embodiment 1. As shown in Fig. 11, switch body 420 includes an electrode 424 instead of electrode 24 according to Embodiment 1.

[0128] The electrode 424 corresponds to the electrode 24, but has a different shape. Specifically, the electrode 424 extends toward the electrode 25 beyond the end of the p-type layer 26p on the electrode 25 side. In other words, the shortest distance between the electrode 25 and the electrode 424 is shorter than the shortest distance between the electrode 25 and the p-type layer 26p.

[0129] In the switch body 420, the n-type layer 26n, the p-type layer 26p, and the 2DEG 28 on the electrode 25 side form an npn transistor structure. In this case, the protective film 27 covering the side surface 26pc of the p-type layer 26p on the electrode 25 side can function as a gate insulating film when the electrode 25 is considered to be a gate electrode. In other words, a pseudo MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) structure is formed. If an electric field is concentrated near the side surface 26pc of the p-type layer 26p due to a potential difference between the electrode 25 and the electrode 424, an inversion channel can be formed in the region near the side surface 26pc. When an inversion channel is formed, a leakage current can flow through the inversion channel.

[0130] In contrast, in the switch body 420, the electrode 424 extends further toward the electrode 25 than the p-type layer 26p, so the electric field caused by the potential difference between the electrode 424 and the electrode 25 does not concentrate on the side surface 26pc. In other words, the electrode 424 functions as a so-called source field plate. This allows the off-leak current to be reduced in the switch body 420.

[0131] <Seventh Modification> The semiconductor device according to the seventh modification is different from the first embodiment in that a region with a high acceptor concentration is formed in the p-type layer.

[0132] 12 is a cross-sectional view of a switch body 520 included in a semiconductor device according to Modification 7 of Embodiment 1. As shown in Fig. 12, the switch body 520 includes a pn junction layer 526 instead of the pn junction layer 26 according to Embodiment 1. The pn junction layer 526 includes a p-type layer 526p and an n-type layer 26n.

[0133] The p-type layer 526p corresponds to the p-type layer 26p, and differs in that the concentration of p-type impurities (acceptor concentration) varies depending on the region. Specifically, the p-type layer 526p includes a first region 526pa and a second region 526pb. The first region 526pa is a region that includes the side surface 526pc on the electrode 25 side. The second region 526pb is a region different from the first region 526pa. Specifically, the second region 526pb is the main region of the p-type layer 526p, and is the entire region other than the first region 526pa.

[0134] The acceptor concentration of the first region 526pa is higher than that of the second region 526pb. For example, the acceptor concentration of the first region 526pa is more than twice as high as that of the second region 526pb. This makes it difficult for an inversion channel to form in the first region 526pa, even if an electric field concentrates on the side surface 526pc, as described in Modification 6. This reduces the off-leakage current of the switch body 520.

[0135] <Modification 8> In a semiconductor device according to Modification 8, the shape of the protective film is different from that of the first embodiment.

[0136] 13 is a cross-sectional view of a switch body 620 included in a semiconductor device according to Modification 8 of Embodiment 1. As shown in Fig. 13, the switch body 620 includes a protective film 627 instead of the protective film 27 according to Embodiment 1.

[0137] The protective film 627 corresponds to the protective film 27, but has a different shape. Specifically, the protective film 627 includes a plane portion 627a and sidewall portions 627b and 627c. The plane portion 627a is a portion that covers the upper surface of the barrier layer 23. The sidewall portions 627b and 627c are portions that cover the side surfaces of the pn junction layer 26. Specifically, the sidewall portion 627b covers the side surface 26b of the pn junction layer 26 on the electrode 24 side. The sidewall portion 627c covers the side surface 26c of the pn junction layer 26 on the electrode 25 side.

[0138] The thickness of each of the sidewall portions 627b and 627c is thicker than the thickness of the flat portion 627a. The thickness of the protective film 627 at a given position is expressed as the distance between the lower surface and the upper surface of the protective film 627 on a line that passes through the given position and is perpendicular to the lower surface and the upper surface of the protective film 627. For example, the thickness of the flat portion 627a is the distance between the upper surface of the barrier layer 23 and the upper surface of the flat portion 627a. The thickness of the sidewall portion 627c is the distance between the side surface 26c of the pn junction layer 26 and the portion of the upper surface of the sidewall portion 627c that is parallel to the side surface 26c (specifically, the inclined surface). The same applies to the sidewall portion 627b.

[0139] This makes it difficult for the electric field caused by the potential difference between electrode 24 and electrode 25 to concentrate on side surface 26c, thereby reducing the off-leak current in switch body 620. In this modification, the thickness of side wall portion 627b may be the same as the thickness of flat portion 627a.

[0140] Such a protective film 627 is formed by forming an insulating film and then thinning the thickness of the flat portion 627a by partially etching it, etc. Alternatively, the sidewall portions 627b and 627c may be formed thicker than the flat portion 627a by an anisotropic film forming method.

[0141] In order to reduce the off-leak current, the dielectric constant of the protective film 627 may be lowered overall. In this case, the thickness of the protective film 627 may be uniform overall, similar to the protective film 27. Alternatively, the dielectric constant of the side wall portion 627c may be lower than the dielectric constant of the flat portion 627a. The side wall portion 627c and the flat portion 627a may be formed using different materials.

[0142] Second Embodiment Next, a second embodiment will be described.

[0143] The second embodiment differs from the first embodiment in that a recess is provided in the barrier layer. The following description will focus on the differences from the first embodiment, and description of the commonalities will be omitted or simplified.

[0144] 14 is a cross-sectional view of a switch body 720 included in the semiconductor device according to embodiment 2. As shown in FIG.

[0145] The recessed portion 729 is formed by removing a portion of the barrier layer 23 by patterning and etching after the barrier layer 23 is formed. The patterning is performed, for example, by photolithography using a photoresist. The thickness of the barrier layer 23 is reduced in the region where the recessed portion 729 is provided. For example, the depth of the recessed portion 729 is at least half the thickness of the barrier layer 23 (the thickness of the portion where the recessed portion 729 is not provided), but is not limited to this.

[0146] In this embodiment, the p-type layer 26p is provided so as to cover the recessed portion 729. Specifically, the p-type layer 26p covers the bottom and side surfaces of the recessed portion 729, and also covers a portion of the upper surface of the barrier layer 23 that surrounds the recessed portion 729. For example, the p-type layer 26p is provided so as to completely fill the recessed portion 729.

[0147] The area of ​​the bottom surface of the recessed portion 729 is smaller than the area of ​​the pn junction interface. Therefore, the voltage generated by the photovoltaic effect can be concentrated at the bottom surface of the recessed portion 729, thereby increasing the concentration of 2DEG 28 generated directly below the recessed portion 729. This reduces the on-resistance and increases the on-current.

[0148] The recessed portion 729 of this embodiment may be provided in the switch body 120, 220, 320, 420, 520, or 620 according to each of the modifications of the first embodiment.

[0149] Third Embodiment Next, a third embodiment will be described.

[0150] The third embodiment differs from the first embodiment in that an insulating film is provided between the barrier layer and the p-type layer. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0151] 15 is a cross-sectional view of a switch body 820 included in the semiconductor device according to embodiment 3. The switch body 820 includes an insulating film 827 provided between the barrier layer 23 and the pn junction layer 26.

[0152] The insulating film 827 is in contact with the upper surface of the barrier layer 23. In this embodiment, the p-type layer 26p is provided in contact with the upper surface of the insulating film 827, but is not in contact with the barrier layer 23. The insulating film 827 is made of, for example, SiN or SiO ２ The film may be a single layer or a laminated film such as the above.

[0153] The insulating film 827 functions as a gate insulating film when the pn junction layer 26 is regarded as a control terminal (gate). In this way, the switch body 820 has a so-called MIS (Metal-Insulator-Semiconductor) structure, which enables miniaturization while reducing off-leak current.

[0154] The insulating film 827 of the present embodiment may be provided in the switch body 120, 220, 320, 420, 520, or 620 according to each modification of the first embodiment. The insulating film 827 may also be provided in the switch body 720 according to the second embodiment. In this case, the curved insulating film 827 is formed along the bottom and side surfaces of the recessed portion 729.

[0155] (Fourth embodiment) Next, a fourth embodiment will be described.

[0156] The fourth embodiment differs from the first embodiment in that two pn junction layers are provided, and the switch body has a so-called common-drain double-gate structure. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0157] 16 is a cross-sectional view of a switch body 920 included in a semiconductor device according to embodiment 4. The switch body 920 includes an electrode 925 and a protective film 927 instead of the electrode 25 and the protective film 27 according to embodiment 1. Furthermore, the switch body 920 includes a pn junction layer 926.

[0158] The electrode 925 corresponds to the electrode 25, and is different from the electrode 25 in that it is electrically connected to an n-type layer 926n of the pn junction layer 926. The protective film 927 corresponds to the protective film 27, and is different from the electrode 25 in that it further covers a part of the upper surface of the pn junction layer 926 and the side surface of the pn junction layer 926.

[0159] The pn junction layer 926 is an example of a fourth nitride semiconductor layer having a pn junction interface, and is provided above the barrier layer 23, between the pn junction layer 26 and at least a part of the electrode 925. In the present embodiment, the pn junction layer 926 is provided between the pn junction layer 26 and a portion where the electrode 925 is in contact with the barrier layer 23.

[0160] 16, the pn junction layer 926 includes a p-type layer 926p and an n-type layer 926n. The p-type layer 926p and the n-type layer 926n are stacked in this order from the barrier layer 23 side. The p-type layer 926p and the n-type layer 926n are in contact with each other, and the contact surface corresponds to the pn junction interface.

[0161] The p-type layer 926p is an example of a second p-type nitride semiconductor layer, and is provided above the barrier layer 23. In the present embodiment, the p-type layer 926p is in contact with the upper surface of the barrier layer 23. The p-type layer 926p is a p-type GaN layer doped with p-type impurities such as Mg. The p-type layer 926p has the same configuration as the p-type layer 26p, for example.

[0162] The n-type layer 926n is an example of a second n-type nitride semiconductor layer, and is provided above the barrier layer 23. In the present embodiment, the n-type layer 926n is in contact with the upper surface of the p-type layer 926p, but is not in contact with the barrier layer 23. The n-type layer 926n is an n-type GaN layer doped with n-type impurities such as Si. The n-type layer 926n has, for example, the same configuration as the n-type layer 26n.

[0163] The electrode 925 is electrically connected to the n-type layer 926n through an opening provided in the protective film 927. In this embodiment, the electrode 925 extends from the contact portion with the barrier layer 23 toward the electrode 24 so as to cover part of the protective film 927, and is in contact with the upper surface of the n-type layer 926n. This fixes the potential of the n-type layer 926n to the potential of the electrode 925.

[0164] The pn junction layer 926 has the same configuration as the pn junction layer 26. Therefore, when light from the light emitting element 10 is not incident, the 2DEG 28 disappears directly below the pn junction layer 926. In other words, the switch body 920 can be made non-conductive (off).

[0165] When light from the light-emitting element 10 is incident near the pn junction interface of the pn junction layer 926, a higher voltage is generated in the p-type layer 926p than in the n-type layer 926n due to the photovoltaic effect. As a result, the potential drops directly below the pn junction layer 926, generating 2DEG 28. The channel between the electrode 24 and the electrode 925 is made conductive by the 2DEG 28, so the switch body 920 becomes conductive (ON).

[0166] As described above, in the switch body 920 according to this embodiment, the pn junction layers 26 and 926 can each function as a gate. That is, the switch body 920 has a double-gate structure. By changing the polarity of the bias voltage applied between the electrode 24 and the electrode 925, a current can flow in both directions. That is, the switch body 920 is capable of bidirectional switching.

[0167] The configurations applicable to the pn junction layer 26 and the electrode 24 described in the first embodiment and its modifications, and the second and third embodiments, are also applicable to the pn junction layer 926 and the electrode 925, respectively. For example, a recessed portion may be provided at a position overlapping the pn junction layer 926 in a planar view, and the p-type layer 926p may be provided to cover the recessed portion. Furthermore, for example, the n-type layer 926n may cover the side surface of the p-type layer 926p on the electrode 925 side. An insulating film may be provided between the p-type layer 926p and the barrier layer 23. Furthermore, for example, the electrode 925 may extend toward the electrode 24 beyond the end of the p-type layer 926p on the electrode 24 side.

[0168] Fifth Embodiment Next, a fifth embodiment will be described.

[0169] The fifth embodiment differs from the first embodiment in that two pn junction layers are provided, and the switch body has a so-called source common double gate structure. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0170] 17 is a cross-sectional view of a switch body 1020 included in a semiconductor device according to embodiment 5. The switch body 1020 includes an electrode 1024 and a protective film 1027 instead of the electrode 24 and the protective film 27 according to embodiment 1. The switch body 1020 further includes an electrode 1025 and a pn junction layer 1026.

[0171] The electrode 1024 corresponds to the electrode 24, and differs in that it is electrically connected not only to the n-type layer 26n of the pn junction layer 26 but also to the n-type layer 1026n of the pn junction layer 1026. The protective film 1027 corresponds to the protective film 27, and differs in that it further covers part of the upper surface of the pn junction layer 1026 and the side surface of the pn junction layer 1026.

[0172] The electrode 1025 is an example of a third electrode, and is provided above the barrier layer 23 at a distance from the electrode 1024 so as to sandwich the electrode 1024 between the electrode 1025 and the barrier layer 23. In this embodiment, the electrode 1025 is in contact with the upper surface of the barrier layer 23. The electrode 1025 is formed using a conductive material such as a metal. For example, the electrode 1025 has a layered structure including a Ti layer and an Al layer stacked on the upper surface of the Ti layer, but is not limited to this.

[0173] The pn junction layer 1026 is an example of a fifth nitride semiconductor layer having a pn junction interface, and is provided above the barrier layer 23, between at least a part of the electrode 1024 and the electrode 1025. In the present embodiment, the pn junction layer 1026 is provided between the electrode 1025 and a portion where the electrode 1024 is in contact with the barrier layer 23.

[0174] 17, the pn junction layer 1026 includes a p-type layer 1026p and an n-type layer 1026n. The p-type layer 1026p and the n-type layer 1026n are stacked in this order from the barrier layer 23 side. The p-type layer 1026p and the n-type layer 1026n are in contact with each other, and the contact surface corresponds to the pn junction interface.

[0175] The p-type layer 1026p is an example of a third p-type nitride semiconductor layer, and is provided above the barrier layer 23. In the present embodiment, the p-type layer 1026p is in contact with the upper surface of the barrier layer 23. The p-type layer 1026p is a p-type GaN layer doped with p-type impurities such as Mg. The p-type layer 1026p has, for example, the same configuration as the p-type layer 26p.

[0176] The n-type layer 1026n is an example of a third n-type nitride semiconductor layer, and is provided above the barrier layer 23. In the present embodiment, the n-type layer 1026n is in contact with the upper surface of the barrier layer 23. The n-type layer 1026n is an n-type GaN layer doped with n-type impurities such as Si. The n-type layer 1026n has, for example, the same configuration as the n-type layer 26n.

[0177] The electrode 1024 is electrically connected to the n-type layer 1026n through an opening provided in the protective film 1027. In this embodiment, the electrode 1024 extends from the contact portion with the barrier layer 23 to both the electrode 25 side and the electrode 1025 side so as to cover part of the protective film 1027, and is in contact with the upper surface of the n-type layer 26n and the upper surface of the n-type layer 1026n, respectively. As a result, the potential of each of the n-type layers 26n and 1026n is fixed to the potential of the electrode 1024.

[0178] The pn junction layer 1026 has the same configuration as the pn junction layer 26. Therefore, when light from the light emitting element 10 is not incident, the 2DEG 28 disappears directly below the pn junction layer 1026. In other words, the switch body 1020 can be made non-conductive (off).

[0179] When light from the light-emitting element 10 is incident near the pn junction interface of the pn junction layer 1026, a higher voltage is generated in the p-type layer 1026p than in the n-type layer 1026n due to the photovoltaic effect. As a result, the potential drops directly below the pn junction layer 1026, generating 2DEG 28. The channel between the electrode 1024 and the electrode 1025 is made conductive by the 2DEG 28, so the switch body 1020 becomes conductive (ON).

[0180] In this way, in the switch body 1020 according to this embodiment, the pn junction layers 26 and 1026 can each function as a gate. That is, the switch body 1020 has a double-gate structure. That is, the switch body 1020 is capable of bidirectional switching.

[0181] The configurations applicable to the pn junction layer 26 and the electrode 24 described in the first embodiment and its modifications, and the second to fourth embodiments, are also applicable to the pn junction layer 1026 and the electrode 1024, respectively. For example, a recessed portion may be provided at a position overlapping the pn junction layer 1026 in a planar view, and the p-type layer 1026p may be provided to cover the recessed portion. Furthermore, for example, the n-type layer 1026n may cover the side surface of the p-type layer 1026p facing the electrode 1024. An insulating film may be provided between the p-type layer 1026p and the barrier layer 23. Furthermore, for example, the electrode 1024 may extend toward the electrode 1025 beyond the end of the p-type layer 1026p facing the electrode 1025.

[0182] Sixth Embodiment Next, a sixth embodiment will be described.

[0183] The sixth embodiment differs from the first embodiment in that the pn junction layer has a plurality of pn junction interfaces. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0184] 18 is a cross-sectional view of a switch body 1120 included in a semiconductor device according to embodiment 6. The switch body 1120 includes a pn junction layer 1126 instead of the pn junction layer 26 of the switch body 20.

[0185] The pn junction layer 1126 corresponds to the pn junction layer 26, and differs in that it has a plurality of pn junction interfaces. Specifically, the pn junction layer 1126 has a p-type layer 26p, an n-type layer 1126n, a p-type layer 1126p, and an n-type layer 26n. A stacked structure of the n-type layer 1126n and the p-type layer 1126p is provided between the p-type layer 26p and the n-type layer 26n.

[0186] The n-type layer 1126n is an example of a fourth n-type nitride semiconductor layer, and is provided between the p-type layer 26p and the n-type layer 26n and is in contact with the p-type layer 26p. The n-type layer 1126n is an n-type GaN layer doped with n-type impurities such as Si. The n-type layer 1126n has, for example, the same configuration as the n-type layer 26n.

[0187] The p-type layer 1126p is an example of a fourth p-type nitride semiconductor layer, and is provided between the p-type layer 26p and the n-type layer 26n and in contact with the n-type layer 26n. The p-type layer 1126p is a p-type GaN layer doped with p-type impurities such as Mg. The p-type layer 1126p has, for example, the same configuration as the p-type layer 26p.

[0188] In this embodiment, the p-type layer 1126p is in ohmic contact with the n-type layer 1126n. For example, by adjusting the impurity concentration of each layer near the junction interface between the p-type layer 1126p and the n-type layer 1126n, the depletion layer formed near the junction interface between the p-type layer 1126p and the n-type layer 1126n is thinned. This allows for substantial ohmic contact to be achieved by utilizing the tunnel effect.

[0189] The pn junction layer 1126 includes two junction interfaces: a pn junction interface between the p-type layer 26p and the n-type layer 1126n, and a pn junction interface between the p-type layer 1126p and the n-type layer 26n. In other words, the pn junction layer 1126 has a pnpn structure. This increases the voltage generated when light is incident on the pn junction layer 1126. This further increases the concentration of the 2DEG 28 directly below the p-type layer 26p, thereby reducing the on-resistance and further increasing the on-current.

[0190] The pn junction layer 1126 may include three or more pn junction interfaces. The pn junction layer 1126 according to this embodiment can also be used in place of the pn junction layers 26, 126, 226, 526, 926, and 1026 described in the first embodiment, its modifications, and the second to fifth embodiments.

[0191] Seventh Embodiment Next, a seventh embodiment will be described.

[0192] The seventh embodiment differs from the first embodiment in that the p-type layer and the n-type layer of the pn junction layer are arranged side by side rather than stacked. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0193] 19 is a cross-sectional view of a switch body 1220 included in a semiconductor device according to embodiment 7. The switch body 1220 includes a pn junction layer 1226 instead of the pn junction layer 26 of the switch body 20.

[0194] The pn junction layer 1226 corresponds to the pn junction layer 26, but has a different shape of the pn junction interface. Specifically, the pn junction layer 1226 has a p-type layer 1226p and an n-type layer 1226n. The p-type layer 1226p and the n-type layer 1226n are arranged side by side in the horizontal direction above the barrier layer 23. Specifically, the p-type layer 1226p and the n-type layer 1226n are arranged side by side in contact with the upper surface of the barrier layer 23. The n-type layer 1226n does not contact the upper surface of the p-type layer 1226p, but only the side surface. Therefore, the pn junction interface is formed to extend upward from the upper surface of the barrier layer 23.

[0195] In the pn junction layer 1226, the potential directly below the p-type layer 1226p increases, so that the 2DEG 28 disappears directly below the p-type layer 1226p when no light is incident from the light emitting element 10. In other words, the switch body 1220 can be made non-conductive (off).

[0196] When light from the light-emitting element 10 is incident near the pn junction interface of the pn junction layer 1226, a higher voltage is generated in the p-type layer 1226p than in the n-type layer 1226n due to the photovoltaic effect. As a result, the potential drops directly below the p-type layer 1226p, generating 2DEG 28. The channel between the electrode 24 and the electrode 25 is made conductive by the 2DEG 28, so the switch body 1220 becomes conductive (ON).

[0197] In this way, also in this embodiment, it is possible to achieve both an increase in on-current and a reduction in off-leak current.

[0198] While the semiconductor device according to one or more aspects has been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0199] For example, in the above-described embodiment, an example was shown in which the first electrode extends to cover the pn junction layer and contacts the first n-type nitride semiconductor layer included in the pn junction layer, but this is not limiting. For example, the semiconductor device may include an electrode (potential fixed electrode) that contacts the first n-type nitride semiconductor layer but is different from the first electrode. The potential fixed electrode and the first electrode may be electrically connected via a conductive via and a wiring. In this manner, the first electrode does not have to be in contact with the first n-type nitride semiconductor layer. The same applies to the first electrode (electrode 1024 in FIG. 17 ) and the third n-type nitride semiconductor layer (n-type layer 1026 n). The same applies to the second electrode (electrode 925 in FIG. 16 ) and the second n-type nitride semiconductor layer (n-type layer 926 n).

[0200] In addition, for example, in the above embodiment, an example was shown in which the switch body is conductive when emitting light and non-conductive when not emitting light, but the reverse is also possible. Specifically, the switch body may be non-conductive (off) when the light-emitting element is emitting light and conductive (on) when the light-emitting element is not emitting light.

[0201] Furthermore, the semiconductor devices according to the embodiments and modifications may be used for purposes other than relay devices, and may be used as various switching devices.

[0202] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0203] The present disclosure can be used as a semiconductor device that can achieve both an increase in on-current and a reduction in off-leakage current, and can be used, for example, in a relay device.

[0204] REFERENCE SIGNS LIST 1 semiconductor device 10 light-emitting element 11, 26n, 126n, 226n, 926n, 1026n, 1126n, 1226n n-type layer 12 active layer 13, 26p, 126p, 526p, 926p, 1026p, 1126p, 1226p p-type layer 14, 15, 24, 25, 424, 925, 1024, 1025 electrode 20, 120, 220, 320, 420, 520, 620, 720, 820, 920, 1020, 1120, 1220 switch body 21 substrate 22 channel layer 23 barrier layer 26, 126, 226, 526, 926, 1026, 1126, 1226 pn junction layer 26pa, 226na upper surface 26b, 26c, 26pb, 26pc, 226nb, 226nc, 526pc side surface 27, 327, 627, 927, 1027 protective film 28 2DEG 30 supporting substrate 41a, 41b, 41c, 41d, 45a, 45b terminals 43a, 43b, 43c external terminals 44a, 44b wires 50 resin member 60 insulating layer 526pa first region 526pb second region 627a plane portion 627b, 627c side wall portion 729 recessed portion 827 insulating film

Claims

1. A semiconductor device comprising: a switch body; and a light-emitting element electrically insulated from the switch body, wherein the switch body comprises: a substrate; a first nitride semiconductor layer provided above the substrate and having a first band gap; a second nitride semiconductor layer provided above the first nitride semiconductor layer and having a second band gap larger than the first band gap; a first electrode and a second electrode provided spaced apart from each other above the second nitride semiconductor layer; and a third nitride semiconductor layer having a pn junction interface provided above the second nitride semiconductor layer between at least a portion of the first electrode and the second electrode, wherein the third nitride semiconductor layer includes a first p-type nitride semiconductor layer and a first n-type nitride semiconductor layer, and the first electrode is electrically connected to the first n-type nitride semiconductor layer.

2. The semiconductor device according to claim 1, further comprising a recessed portion provided in said second nitride semiconductor layer, said first p-type nitride semiconductor layer being provided so as to cover said recessed portion.

3. The semiconductor device according to claim 1 or 2, wherein the pn junction interface extends toward the second electrode beyond the end of the first electrode on the second electrode side.

4. The semiconductor device according to claim 1 or 2, wherein the first n-type nitride semiconductor layer is in contact with an upper surface of the first p-type nitride semiconductor layer and a side surface of the first p-type nitride semiconductor layer facing the first electrode.

5. The semiconductor device according to claim 1 or 2, wherein the first electrode is in contact with an upper surface and a side surface of the first n-type nitride semiconductor layer.

6. The semiconductor device according to claim 1 or 2, further comprising an insulating film provided between the second nitride semiconductor layer and the third nitride semiconductor layer.

7. The semiconductor device according to claim 1 or 2, wherein the first electrode extends toward the second electrode beyond an end of the first p-type nitride semiconductor layer on the second electrode side.

8. The semiconductor device according to claim 1 or 2, wherein the first p-type nitride semiconductor layer includes a first region including a side surface on the second electrode side, and a second region different from the first region, and the acceptor concentration of the first region is higher than the acceptor concentration of the second region.

9. The semiconductor device according to claim 1 or 2, further comprising a protective film, the protective film including a planar portion covering an upper surface of the second nitride semiconductor layer and a sidewall portion covering a side surface of the third nitride semiconductor layer, the thickness of the sidewall portion being greater than the thickness of the planar portion.

10. The semiconductor device according to claim 1 or 2, further comprising a fourth nitride semiconductor layer having a pn junction interface provided above the second nitride semiconductor layer and between the third nitride semiconductor layer and at least a portion of the second electrode, the fourth nitride semiconductor layer including a second p-type nitride semiconductor layer and a second n-type nitride semiconductor layer, and the second electrode being electrically connected to the second n-type nitride semiconductor layer.

11. The semiconductor device according to claim 1 or 2, comprising: a third electrode provided above the second nitride semiconductor layer and spaced apart from the first electrode so as to sandwich the first electrode between the second electrode and the third electrode; and a fifth nitride semiconductor layer having a pn junction interface provided above the second nitride semiconductor layer between at least a portion of the first electrode and the third electrode, wherein the fifth nitride semiconductor layer includes a third p-type nitride semiconductor layer and a third n-type nitride semiconductor layer, and the first electrode is electrically connected to the third n-type nitride semiconductor layer.

12. The semiconductor device according to claim 1 or 2, wherein the third nitride semiconductor layer further includes: a fourth n-type nitride semiconductor layer provided between the first p-type nitride semiconductor layer and the first n-type nitride semiconductor layer and in contact with the first p-type nitride semiconductor layer; and a fourth p-type nitride semiconductor layer provided between the first p-type nitride semiconductor layer and the first n-type nitride semiconductor layer and in contact with the first n-type nitride semiconductor layer, and the fourth p-type nitride semiconductor layer is in ohmic contact with the fourth n-type nitride semiconductor layer.

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