Optical semiconductor element, optical semiconductor element array, and method for manufacturing optical semiconductor element

Abstract

The present invention includes: a semiconductor substrate; a first semiconductor layer which is doped to have a first conductivity type; an active layer which performs light emission; a second semiconductor layer which is doped to have a second conductivity type; a passivation film which has electrical insulation properties; a first electrode pad and a second electrode pad, which are superposed on the upper surface of the passivation film, with the first electrode pad being electrically connected to the second semiconductor layer via an opening that is provided in the passivation film; and a waveguide which includes the active layer, has a light exit surface on one of end surfaces that surround the active layer, and extends from the light exit surface to an end surface that is opposite to the light exit surface. An electrode contact region that has a depth reaching the first semiconductor layer or the semiconductor substrate from the upper surface is provided. In the electrode contact region, the second electrode pad is connected to the first semiconductor layer or the semiconductor substrate by means of an electrode which is formed on a forward tapered surface having a height difference in a direction that is parallel to the waveguide.

Description

Optical semiconductor element, optical semiconductor element array, and method for manufacturing optical semiconductor element

[0001] The present invention relates to an optical semiconductor element, an optical semiconductor element array, and a method for manufacturing an optical semiconductor element.

[0002] Patent Document 1 describes the configuration of an optical semiconductor device that includes a first conductivity type buffer layer formed in an island shape on a semi-insulating semiconductor substrate, a mesa stripe of a laminate consisting of an active layer formed on the first conductivity type buffer layer, a second conductivity type cladding layer, and a second conductivity type electrode layer, a high-resistance semiconductor buried layer that is buried up to the top surface of the mesa stripe except for a portion of the first conductivity type buffer layer, a first electrode connected to the top surface of the mesa stripe, and a second electrode that is drawn from the first conductivity type buffer layer exposed in a groove formed in the high-resistance semiconductor buried layer to the top surface of the high-resistance semiconductor buried layer.

[0003] Patent Document 2 discloses an optical semiconductor device that includes a first mesa stripe including a laminated structure in which at least a semiconductor active layer and a second conductivity type semiconductor layer having an opposite conductivity type to the first conductivity type are sequentially laminated on a first conductivity type semiconductor layer provided on a semiconductor substrate, a first terrace structure with inclined side surfaces and a high-resistance semiconductor layer embedding the side surfaces of the first mesa stripe, a second mesa stripe that is independent and parallel to the first mesa stripe and has the same laminated structure as the first mesa stripe, and a second terrace structure with inclined side surfaces and a high-resistance semiconductor layer embedding the side surfaces of the second mesa stripe, and a first electrode connected to the second conductivity type semiconductor layer of the first mesa stripe on a flat surface of the first terrace structure, and a second electrode connected to the first conductivity type semiconductor layer exposed between the first terrace structure and the second terrace structure and extending to a flat portion of the second terrace structure.

[0004] Patent No. 3230785 Patent No. 5691741

[0005] However, in the above-mentioned conventional technology, when constructing a flip-chip mounted laser array, two pad electrodes are arranged in the arrangement direction of the laser array. Furthermore, even when the two pad electrodes are arranged perpendicular to the arrangement direction of the laser array, the wiring leading to the n-type electrode is oriented in the arrangement direction of the laser array, which causes a decrease in the integration density of the optical semiconductor element. Furthermore, because the buried layer of the waveguide is not doped, there are still issues regarding heat dissipation during integration.

[0006] Therefore, there was a need for a technology that could improve the integration density of laser arrays using a simple process by arranging two electrodes that can be flip-chip mounted and an extraction electrode that connects the semiconductor layer on the substrate side of the active layer to the electrode so that they are perpendicular to the arrangement direction of the laser array.

[0007] The present invention has been made in view of the above, and an object of the present invention is to provide an optical semiconductor element, an optical semiconductor element array, and a method for manufacturing a semiconductor element that can improve the integration density of a laser array through a simple process.

[0008] In order to solve the above-mentioned problems and achieve the above-mentioned object, an optical semiconductor element according to the present invention includes a semiconductor substrate, a first semiconductor layer stacked on the semiconductor substrate and doped to a first conductivity type, an active layer that is provided on the first semiconductor layer and that emits light, a second semiconductor layer that is provided above the first semiconductor layer and the active layer and doped to a second conductivity type, an electrically insulating passivation film that is provided on the second semiconductor layer, and a first electrode pad and a second electrode pad stacked on an upper surface of the passivation film, the active layer has a light emission surface at one of the end faces surrounding the active layer, and the active layer has a waveguide extending from the emission surface toward the end face opposite to the emission surface, the waveguide including the active layer is provided with an electrode contact region having a depth reaching the first semiconductor layer or the semiconductor substrate from the upper surface, and in the electrode contact region, the second electrode pad is connected to the semiconductor substrate or the first semiconductor layer by an electrode formed on a forward tapered surface having a height difference in a direction parallel to the waveguide.

[0009] In the optical semiconductor element according to one aspect of the present invention, in the above invention, the upper surfaces of the first electrode pads and the second electrode pads are positioned on approximately the same plane.

[0010] An optical semiconductor element according to one aspect of the present invention is characterized in that, in the above invention, metal wiring extending from the first electrode pad and the second electrode pad is provided at the end of the upper surface in a plan view.

[0011] An optical semiconductor element according to one aspect of the present invention is characterized in that, in the above invention, it has a thyristor structure in which layers of different conductivity types are alternately stacked in the semiconductor layer excluding the vertical direction of the waveguide.

[0012] An optical semiconductor element array according to one aspect of the present invention is an optical semiconductor element array in which a plurality of optical semiconductor elements according to the above invention are arranged, characterized in that an electrical isolation trench is provided with a depth that reaches from the upper surface of the passivation film to the first semiconductor layer or the semiconductor substrate, and the plurality of optical semiconductor elements are arranged in a state in which the second semiconductor layer is electrically isolated by the electrical isolation trench.

[0013] In the optical semiconductor element array according to one aspect of the present invention, the first semiconductor layer is electrically isolated by the electrical isolation trench.

[0014] In the optical semiconductor element array according to one aspect of the present invention, the electrical isolation trench and the electrode contact region are in contact with each other in a plan view.

[0015] An optical semiconductor element array according to one aspect of the present invention is characterized in that, in the above invention, the depth from the upper surface to the electrode contact region is approximately equal to the depth from the upper surface to the electrical isolation groove.

[0016] a second semiconductor layer doped with a second conductivity type formed above the first semiconductor layer; an electrically insulating passivation film formed on the second semiconductor layer; a first electrode pad and a second electrode pad formed on an upper surface of the passivation film, the first electrode pad and the second electrode pad being electrically connected to the second semiconductor layer; a light emission surface formed on one of end surfaces surrounding the active layer; and a waveguide including the active layer extending toward an end surface opposite to the emission surface. The method for manufacturing an optical semiconductor element according to one aspect of the present invention is characterized in that an electrode contact region is formed to a depth reaching the first semiconductor layer or the semiconductor substrate from the upper surface, and the second electrode pad is formed so as to be connected to the semiconductor substrate or the first semiconductor layer by an electrode formed on a forward tapered surface having a height difference in the electrode contact region in a direction parallel to the waveguide.

[0017] According to the present invention, it is possible to improve the integration density of a laser array through a simple process.

[0018] FIG. 1 is an exemplary and schematic plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line II-II. FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line III-III. FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line VI-VI. FIG. 5 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along line V-V. FIG. 6 is an exemplary and schematic plan view showing a wafer on which a semiconductor device portion according to an embodiment of the present invention is formed.

[0019] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that in all the drawings of the following embodiments, the same or corresponding parts are designated by the same reference numerals. The configurations of the following embodiments, as well as the actions and results (effects) brought about by the configurations, are merely examples. The present invention can be realized by configurations other than those disclosed in the following embodiments. Furthermore, according to the present invention, it is possible to obtain at least one of the various effects and derivative effects obtained by the configurations. In this specification, ordinal numbers are used for convenience to distinguish directions, members, parts, etc., and do not indicate priority or order.

[0020] In each figure, the X direction is represented by an arrow X, the Y direction is represented by an arrow Y, and the Z direction is represented by an arrow Z. The X direction, Y direction, and Z direction intersect with each other and are perpendicular to each other. In the following, the X direction will be referred to as the short direction or width direction, the Y direction as the long direction or extension direction, and the Z direction as the stacking direction or height direction. Each figure is a schematic diagram for the purpose of explanation, and the scale and ratio of each figure do not necessarily match those of the actual product.

[0021] First, an optical semiconductor element according to one embodiment of the present invention will be described. Fig. 1 shows a top view of the optical device according to this embodiment. Figs. 2, 3, 4, and 5 show cross-sectional views taken along lines II-II, III-III, IV-IV, and V-V in Fig. 1, respectively.

[0022] As shown in FIGS. 1 to 5, an optical semiconductor device 1A according to one embodiment of the present invention includes a semiconductor substrate 30, a first semiconductor layer stacked on the semiconductor substrate 30 and made of a lower cladding layer 31 doped to a first conductivity type, for example, n-type, an active layer 34 provided on the lower cladding layer 31 and emitting light, a second semiconductor layer provided above the lower cladding layer 31 and the active layer 34 and including an upper cladding layer 35 doped to a second conductivity type, for example, p-type, and a contact layer 36, an electrically insulating passivation film 12 provided on the contact layer 36, a p-side electrode pad 10 serving as a first electrode electrically connected to a p-side electrode 11 on the upper surface of the passivation film 12, and an n-side electrode 2 serving as a second electrode. 1, and an n-side electrode pad 20, which is a second electrode pad electrically connected to the p-side electrode pad 10, is laminated on the n-side electrode pad 20. The p-side electrode pad 10 is electrically connected to the contact layer 36 via a connection hole 12a provided in the passivation film 12. The p-side electrode pad 10 has a light emission surface on one of the end faces surrounding the active layer 34, and is provided with a waveguide L including the active layer 34, extending from the emission surface toward the end face opposite to the emission surface. An n-side electrode contact region 2, which is an electrode contact region, is provided at a depth reaching from the upper surface to the lower cladding layer 31, which is the first semiconductor layer, or the semiconductor substrate 30. In the n-side electrode contact region 2, the n-side electrode pad 20 is composed of an n-side electrode 21 formed on a forward tapered surface having a difference in height in a direction parallel to the active layer 34 that constitutes the waveguide L.

[0023] Furthermore, the optical semiconductor element array 1 according to one embodiment of the present invention is an optical semiconductor element array 1 in which a plurality of the above-described optical semiconductor elements 1A are arranged, and an electrical isolation groove 40 is provided to a depth that reaches from the upper surface of the passivation film 12 to the lower clad layer 31, which is the first semiconductor layer, or the semiconductor substrate 30, and the plurality of optical semiconductor elements 1A are arranged with the lower clad layer 31 electrically isolated by the electrical isolation groove 40.

[0024] As shown in Figures 2, 3, and 4, the optical semiconductor device 1A according to this embodiment has a structure in which a lower cladding layer 31, which also serves as a buffer layer and is made of a stacked structure of n-type InP layers and n-type InGaAsP layers, an active layer 34 containing n-type InGaAsP, an upper cladding layer 35 containing p-type InP, and a contact layer 36 containing p-type InGaAsP are stacked on a semiconductor substrate 30 made of n-type InP. That is, the optical semiconductor device 1A has a thyristor structure in which layers of different conductivity types are alternately stacked in the semiconductor layers excluding the direction perpendicular to the waveguide L (X direction). The upper cladding layer 35 may also have a diffraction grating layer made of a p-type InGaAsP layer along the active layer 34 along the longitudinal direction (Y direction) of the optical semiconductor device 1A. The upper cladding layer 35 including the diffraction grating layer, the active layer 34, and the lower cladding layer 31 are processed into a mesa shape.

[0025] The mesa structure including the active layer 34 is buried between a lower blocking layer 32 made of p-type InP and an upper blocking layer 33 made of n-type InP, which constitute the second semiconductor layer. The lower blocking layer 32 and the upper blocking layer 33 function as current blocking layers. That is, the active layer 34, which is processed into a mesa stripe shape, functions as an optical waveguide and has a buried waveguide structure (BH waveguide structure). A main convex portion is formed to include the mesa structure of the active layer 34. A p-side electrode 11 is provided on the contact layer 36 in the main convex portion, and is connected to the contact layer 36 through a connection hole 12a serving as an opening. A p-side electrode pad 10 is provided at a position extending in the array direction (X direction).

[0026] 1 to 4, in plan view, an emission surface for emitting laser light is provided on one of the end faces surrounding the top surface. A waveguide L is provided in the main convex portion including the active layer 34 toward the end face opposite to this emission surface. An electrical isolation groove 40 is formed in a direction parallel to the waveguide L (Y direction) and reaches the lower cladding layer 31 or the semiconductor substrate 30. An n-side electrode 21 is formed at a position where a portion of the bottom surface of the electrical isolation groove 40 extends in the array arrangement direction (X direction).

[0027] 1 and 5, the p-side electrode pad 10 and the n-side electrode pad 20 have their upper surfaces at approximately the same height from the active layer 34, with the active layer 34 as the reference. In other words, the p-side electrode pad 10 and the n-side electrode pad 20 are formed so that their upper surfaces are on approximately the same plane. The main convex portion constitutes a light-emitting portion that emits laser light when a current is injected.

[0028] An n-side electrode contact region 2 is provided in the upper surface, having a depth reaching the lower cladding layer 31 or semiconductor substrate 30, which is a first semiconductor layer. A contact region 21a is formed in the n-side electrode contact region 2 at a position extending in a direction (Y direction) perpendicular to the array arrangement direction (X direction), where the lower cladding layer 31 or semiconductor substrate 30 and the n-side electrode 21 are electrically connected. That is, the n-side electrode pad 20 extending in the Y direction and the n-side electrode 21 are electrically connected to the lower cladding layer 31 or semiconductor substrate 30 in the contact region 21a. The n-side electrode contact region 2 and the n-side electrode pad 20 are configured to be connected in the contact region 21a by the n-side electrode 21 formed on a forward tapered surface having a height difference in a direction (Y direction) parallel to the active layer 34 constituting the waveguide L.

[0029] Furthermore, the electrical isolation groove 40 electrically isolates at least the lower blocking layer 32 and the upper cladding layer 35, which serve as second semiconductor layers, between adjacent optical semiconductor elements 1A. That is, the electrical isolation groove 40 may be etched to a depth partway through the lower cladding layer 31, or may be etched to a depth that reaches the semiconductor substrate 30. If a semi-insulating layer (not shown) is further included below the lower cladding layer 31, the electrical isolation groove 40 may be etched to a depth that reaches the semi-insulating layer and the n-side electrode 21 may be contacted to a depth that reaches the lower cladding layer 31, thereby electrically isolating the n-side region as well.

[0030] Furthermore, when the semiconductor substrate 30 is a semi-insulating substrate or a semiconductor substrate made of a different conductivity type (e.g., p-type) from the lower cladding layer 31 serving as the first semiconductor layer, the electrical isolation groove 40 may be formed up to or even deeper than the lower cladding layer 31. In this case, the lower cladding layer 31 serving as the first semiconductor layer of adjacent optical semiconductor elements 1A in the laser array is separated from the lower blocking layer 32 and upper cladding layer 35 serving as the second semiconductor layers, thereby cutting off unnecessary current paths and improving the carrier injection efficiency, which is more preferable.

[0031] (Method of Manufacturing Optical Semiconductor Device) Next, an example of a method of manufacturing an optical semiconductor device configured as described above will be described. That is, first, on a semiconductor substrate 30 made of InP, a lower cladding layer 31 having a stacked structure including an n-type InP layer, an active layer 34 having a stacked structure including a GaInAsP layer, an upper cladding layer 35 having a stacked structure including a p-type InP layer, and a diffraction grating layer made of a GaInAsP layer are successively grown by crystal growth.

[0032] Next, an insulating layer made of, for example, silicon nitride (SiN) is grown on the substrate on which the diffraction grating layer has been formed. A resist film is then formed on the grown insulating layer. Next, a diffraction grating pattern is formed on the resist film using an electron beam lithography system, and the insulating layer is etched to transfer the diffraction grating pattern. After removing the resist film, the diffraction grating layer is etched using, for example, a dry etching system to form the diffraction grating. Next, the insulating layer is removed, and a layer in which the diffraction grating layer will be embedded is crystal-grown.

[0033] The resist film is patterned so as to leave the mesa region of the active layer 34, and then the insulating layer is removed by etching from areas other than the active layer mesa region. After removing the remaining resist film, the active layer 34 is etched to form a mesa stripe shape.

[0034] Next, a buried active layer mesa structure is formed by sequentially growing a lower blocking layer 32 made of p-type InP and an upper blocking layer 33 made of n-type InP. As a result, the active layer 34 is processed into a mesa stripe shape, forming a buried waveguide structure that functions as an optical waveguide. Next, after removing the insulating layer, an upper cladding layer 35 made of p-type InP and a contact layer 36 having a stacked structure including a p-type GaInAsP layer are sequentially grown by crystal growth.

[0035] Next, a resist film is formed on the crystal-grown contact layer 36 and patterned into the shape of the electrical isolation groove 40. Subsequently, parts of the contact layer 36, upper cladding layer 35, upper blocking layer 33, and lower blocking layer 32 are removed by etching to form the electrical isolation groove 40 and the n-side electrode contact region 2. At this time, by selecting an anisotropic etchant such as hydrochloric acid (HCl), a tapered surface having a difference in height from the bottom of the n-side electrode contact region 2 toward the contact layer 36 is formed.

[0036] Next, an insulating film made of, for example, SiN is formed on the entire surface, and then a resist film is formed on the insulating film, and the surfaces in contact with the p-side electrode 11 and the n-side electrode 21 are patterned. Subsequently, the insulating film is etched using the patterned resist film as a mask, and then the resist film is removed.

[0037] Next, the p-side electrode 11 having a layered structure containing Au / AuZn is formed on the contact layer 36 along the waveguide by, for example, a vapor deposition lift-off method. Subsequently, the n-side electrode 21 having a layered structure containing AuGe / Ni / Au is formed on the n-side electrode contact region 2 by, for example, a vapor deposition lift-off method.

[0038] Next, the p-side electrode pad 10 and the n-side electrode pad 20 are formed together by plating the upper layers of the p-side electrode 11 and the n-side electrode 21 with gold (Au). As shown in FIG. 1 , in order to enable the p-side electrode pad 10 and the n-side electrode pad 20 to be integrally formed by plating, convex patterns 10a and 20a are formed on the adjacent optical semiconductor element 1A in the direction perpendicular to the arrangement direction (Y direction) so that the p-side electrode pad 10 and the n-side electrode pad 20 are continuous with each other. The convex pattern 10a is made of metal wiring extending from the p-side electrode pad 10, and the convex pattern 20a is made of metal wiring extending from the n-side electrode pad 20. In other words, prior to the stage of separating and cutting the optical semiconductor elements 1A, the convex patterns 10a and 20a connect the p-side electrode pad 10 and the n-side electrode pad 20, making plating possible.

[0039] Thereafter, the semiconductor substrate 30 is polished to a predetermined thickness. Next, a heat treatment is performed at, for example, about 400° C. This forms an ohmic connection between the p-side electrode 11 and the contact layer 36, which is a semiconductor layer in contact with the p-side electrode 11. Also, an ohmic connection is formed between the n-side electrode 21 and the lower cladding layer 31, which is a semiconductor layer in contact with the n-side electrode 21, or the semiconductor substrate 30.

[0040] Fig. 6 is a plan view showing a semiconductor wafer 100 on which optical semiconductor elements 1A are arranged along a predetermined direction as described above. As shown in Fig. 6, the surface of the semiconductor wafer 100 is a (100) plane, with the longitudinal direction (Y direction) of the multiple optical semiconductor elements 1A being the <011> crystal orientation, and the arrangement direction perpendicular to the longitudinal direction (X direction) being the <01-1> crystal orientation. The semiconductor wafer 100 on which multiple optical semiconductor elements 1A are formed is cleaved to form end faces, and a low-reflection coating is applied to the output side and a high-reflection coating is applied to the opposite side, thereby forming the optical semiconductor element 1A shown in Fig. 1.

[0041] According to the embodiment of the present invention described above, the two flip-chip mountable p-side electrode pads 10 and n-side electrode pad 20, and the extraction electrode for connecting the lower cladding layer 31, which is a semiconductor layer closer to the semiconductor substrate 30 than the active layer 34, to the n-side electrode 21, can be arranged along the direction (Y direction) perpendicular to the arrangement direction (X direction) of the laser array, making it possible to improve the integration degree of the laser array through a simple process.

[0042] Although one embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical concept of the present invention are possible. Configurations that appropriately combine the above-described components are also included in the present invention. Furthermore, further effects and modifications can be easily derived by those skilled in the art. Therefore, the broader aspects of the present invention are not limited to the above-described embodiment, and various modifications are possible. For example, the numerical values ​​and materials listed in the above-described embodiment are merely examples, and different numerical values ​​and materials may be used as necessary. The present invention is not limited by the description and drawings that form a part of the disclosure of the present invention according to this embodiment.

[0043] The present invention can be used in an optical semiconductor element, an optical semiconductor element array, and a method for manufacturing an optical semiconductor element.

[0044] REFERENCE SIGNS LIST 1 Optical semiconductor element array 1A Optical semiconductor element 2 N-side electrode contact region 10 P-side electrode pad 10a, 20a Convex pattern 11 P-side electrode 12 Passivation film 12a Contact hole 20 N-side electrode pad 21 N-side electrode 21a Contact region 30 Semiconductor substrate 31 Lower cladding layer 32 Lower blocking layer 33 Upper blocking layer 34 Active layer 35 Upper cladding layer 36 Contact layer 40 Electrical isolation groove 100 Semiconductor wafer L Waveguide

Claims

1. A substrate; a first semiconductor layer stacked on the substrate and doped to a first conductivity type; an active layer formed on the first semiconductor layer and emitting light; a second semiconductor layer formed above the first semiconductor layer and the active layer and doped to a second conductivity type; an electrically insulating passivation film formed on the second semiconductor layer; a first electrode pad and a second electrode pad stacked on the upper surface of the passivation film, the first electrode pad being electrically connected to the second semiconductor layer through an opening formed in the passivation film; a light emission surface being on one of the end surfaces surrounding the active layer; a waveguide including the active layer extending from the emission surface to an end surface opposite the emission surface; an electrode contact region having a depth reaching from the upper surface to the first semiconductor layer or the substrate; and in the electrode contact region, the second electrode pad is connected to the substrate or the first semiconductor layer by an electrode formed on a forward tapered surface having a height difference in a direction parallel to the waveguide. An optical semiconductor element characterized by:

2. The optical semiconductor element according to claim 1, wherein the upper surfaces of the first electrode pads and the second electrode pads are located on approximately the same plane.

3. The optical semiconductor element according to claim 2, characterized in that metal wiring extending from the first electrode pad and the second electrode pad is provided at the end of the upper surface in a plan view.

4. An optical semiconductor element according to any one of claims 1 to 3, characterized in that it has a thyristor structure in which layers of different conductivity types are alternately stacked in the semiconductor layer excluding the vertical direction of the waveguide.

5. An optical semiconductor element array in which a plurality of the optical semiconductor elements according to claim 1 are arranged, wherein an electrical isolation groove is provided from the upper surface of the passivation film to a depth that reaches the first semiconductor layer or the substrate, and the plurality of optical semiconductor elements are arranged in a state in which the second semiconductor layer is electrically isolated by the electrical isolation groove.

6. The optical semiconductor element array according to claim 5, wherein the first semiconductor layer is electrically isolated by the electrical isolation groove.

7. The optical semiconductor element array according to claim 5, wherein the electrical isolation grooves and the electrode contact regions are in contact with each other in a plan view.

8. The optical semiconductor element array according to claim 5, wherein the depth from said upper surface to said electrode contact region is approximately equal to the depth from said upper surface to said electrical isolation groove.

9. A method for manufacturing an optical semiconductor device comprising: a first semiconductor layer doped to a first conductivity type formed on a substrate; an active layer serving as a light emitting portion formed on the first semiconductor layer; a second semiconductor layer doped to a second conductivity type formed above the first semiconductor layer and the active layer; an electrically insulating passivation film formed on the second semiconductor layer; a first electrode pad electrically connected to the second semiconductor layer and a second electrode pad formed on the upper surface of the passivation film; a light emission surface formed on one of the end faces surrounding the active layer; and a waveguide including the active layer extending toward the end face opposite the emission surface, the method comprising: forming an electrode contact region deep enough to reach the first semiconductor layer or the substrate from the upper surface; and forming the second electrode pad in the electrode contact region so as to connect to the substrate or the first semiconductor layer by an electrode formed on a forward tapered surface having a difference in height in the direction parallel to the waveguide.

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