Semiconductor device and production method for semiconductor device

Abstract

Provided is a semiconductor device that makes it easy to ensure broad contact between a sintered metal and a joint boundary surface. A semiconductor device according to the present invention comprises a first member that is made of metal and a second member that includes a semiconductor chip. The first member and the second member are joined by sintering. Recesses and protrusions are formed at at least one joint boundary surface of the first member and the second member such that the interval of the recesses and protrusions is no more than 10 μm.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] There is a need to improve the power cycle life of high-heat-resistant power semiconductor modules used in electric railways, electric vehicles, and industrial applications. To meet this need, an effective solution is to use sintered bonding, which has excellent heat resistance, to bond the semiconductor chip to the substrate instead of the conventional solder bonding.

[0003] Techniques relating to sinter bonding are, for example, found in Patent Document 1 and Patent Document 2. Figure 5 and paragraphs 0040 to 0044 of Patent Document 1 describe a technique in which dimples that exert an anchor effect are formed on the surface of a substrate using a laser, a paste-like sinterable metal bonding material is printed, the printed sinterable metal bonding material is dried, a semiconductor element is mounted on the dried sinterable metal bonding material and temporarily fixed thereon, and then the substrate and semiconductor element are bonded together using the sinterable metal bonding material by heating under pressure.

[0004] Furthermore, Patent Document 2 describes that by mixing flake particles, it is possible to suppress volume shrinkage during bonding and perform sintering without pressure.

[0005] International Publication No. 2019 / 087920 Specification Japanese Patent Application Laid-Open No. 2021-64612

[0006] In solder bonding, the solder metal melts and spreads across the bonding interface, ensuring contact at the interface during bonding. On the other hand, in sinter bonding, the sintered metal does not melt but is bonded by diffusion in powder form, making it more difficult to ensure contact at the interface than with solder.

[0007] In response to this, a common technique is to apply pressure to press the chip or wiring onto the powder to ensure contact at the interface, as described in Patent Document 1. Another example is disclosed in Patent Document 2, which discloses a technique in which flake-shaped particles are mixed to suppress volumetric shrinkage during bonding, making it easier to ensure contact even without applying pressure.

[0008] However, even when pressure is applied, it may not be easy to ensure uniform contact with the solid powder. Also, due to concerns about damage to the chip, it is not possible to apply an unlimited amount of pressure.

[0009] Furthermore, even if volumetric shrinkage is suppressed by combining particles when no pressure is applied, it is still difficult to ensure contact at the interface compared to solder, in which the metal melts and actively spreads, or sintering technology, in which pressure is used to suppress some variation and ensure contact.

[0010] In order to solve the above-mentioned problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can easily ensure large contact between the sintered metal and the interface to be joined.

[0011] The above and other objects of the present invention and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012] The first semiconductor device of the present invention comprises a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering bonding, and irregularities are formed at the joining interface of at least one of the first member and the second member, with the spacing between the irregularities being 10 μm or less.

[0013] A second semiconductor device of the present invention comprises a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering bonding, and the joining interface of at least one of the first member and the second member being composed of crystal grains having a grain size of 10 μm or less.

[0014] The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a first member made of metal and a second member including a semiconductor chip are joined by sinter bonding, in which irregularities with a spacing of 10 μm or less are formed at the joining interface of at least one of the first member and the second member, and then sintered metal is supplied to the joining interface where the irregularities have been formed, thereby performing sinter bonding.

[0015] According to the present invention, the bonding interface has fine irregularities with intervals of 10 μm or less, or the bonding interface is composed of crystal grains with a grain size of 10 μm or less, which promotes atomic diffusion during sinter bonding, activates interdiffusion between the sintered metal and the bonding interface, and makes the bonding contact denser. This results in a bonding layer that is less likely to peel and has good thermal conductivity.

[0016] Problems, configurations, and effects other than those described above will become clear from the following description of the embodiments.

[0017] 1 is a schematic cross-sectional view showing the structure of a semiconductor module of Example 1. FIG. 1 is a cross-sectional view showing an example of the structure of a bonded interface of the semiconductor module of Example 1. FIG. 2 is a schematic view illustrating diffusion during sinter bonding. A and B are cross-sectional views showing diffusion at an interface during general sinter bonding. A and B are cross-sectional views showing diffusion at an interface during sinter bonding in a semiconductor device of the present invention. A is an SEM image of the surface state after etching a Ni film. A is an SEM image of a cross-section when sinter bonding is performed on a normal Ni film. B is an SEM image of a cross-section when sinter bonding is performed on a Ni film with unevenness. A cross-sectional view showing the phenomenon explained by Wenzel's equation. A cross-sectional view of a sinter bonded portion of a conventional semiconductor module. A cross-sectional view of a sinter bonded portion of a semiconductor module of Example 2. A and B are cross-sectional views showing a method for manufacturing a semiconductor module of Example 3.

[0018] The following describes embodiments and examples of the present invention using text and drawings. However, the structures, materials, and other specific configurations shown in the present invention are not limited to the embodiments described here, and can be appropriately combined or improved within the scope of the present invention. Furthermore, elements not directly related to the present invention are omitted from the illustrations.

[0019] A first semiconductor device of the present invention includes a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering. Furthermore, in the first semiconductor device of the present invention, unevenness is formed on the joining interface of at least one of the first member and the second member, and the interval between the unevennesses is 10 μm or less.

[0020] A second semiconductor device of the present invention includes a first member made of metal and a second member including a semiconductor chip, the first member and the second member being joined by sintering bonding, and the second semiconductor device of the present invention has a joining interface of at least one of the first member and the second member being composed of crystal grains with a grain size of 10 μm or less.

[0021] The semiconductor device manufacturing method of the present invention is a method for manufacturing a semiconductor device in which a first member made of metal and a second member including a semiconductor chip are bonded by sinter bonding. The semiconductor device manufacturing method of the present invention includes forming irregularities with a spacing of 10 μm or less at the bonded interface of at least one of the first member and the second member, and then supplying a sintered metal to the bonded interface where the irregularities have been formed, thereby performing sinter bonding.

[0022] According to the first semiconductor device and the method for manufacturing the semiconductor device of the present invention, the interface between at least one of the first and second members is provided with irregularities spaced 10 μm or less, which promotes atomic diffusion during sinter bonding, activates interdiffusion between the sintered metal and the interface between the members, and densely bonds the junctions, thereby providing a bonding layer that is resistant to peeling and has good thermal conductivity.

[0023] According to the second semiconductor device of the present invention, the interface between at least one of the first and second members is composed of crystal grains with a grain size of 10 μm or less. The small grain size of the crystal grains increases the number of crystal grain boundaries. This promotes atomic diffusion during sinter bonding, activating interdiffusion between the sintered metal and the interface, resulting in a denser bonded contact. This results in a bonded layer that is resistant to peeling and has good thermal conductivity.

[0024] The first semiconductor device can be configured such that the spacing between the projections and recesses is 0.1 μm or less. In this configuration, since the particles of typical sintered metals have submicron diameters, the projections and recesses are provided near all particles near the bonding interface on average. This further improves the quality of the sintered bond.

[0025] In the first semiconductor device, the depth of the recesses and protrusions may be 0.1 μm or more. In this configuration, the depth of the recesses and protrusions is 0.1 μm or more, which makes it easier to form a dense region of sintered metal.

[0026] In the first semiconductor device described above, the opening diameter of the asperities may be 10 μm or less. In this configuration, since the opening diameter of the asperities is 10 μm or less, particles of the sintered metal are less likely to enter the asperities, and the difference in thickness of the sintered metal between inside and outside the asperities can be reduced, allowing the pressure during sinter bonding to be transmitted uniformly.

[0027] In the first semiconductor device described above, the opening diameter of the asperities can be 0.01 μm or less. In this configuration, since the opening diameter of the asperities is 0.01 μm or less, even if the sintered metal particles have a submicron diameter, the asperities are less likely to penetrate, so that the difference in thickness of the sintered metal between inside and outside the asperities is almost eliminated, and pressure during sintering bonding can be uniformly transmitted.

[0028] In the first semiconductor device described above, the unevenness may be formed along the grain boundaries of the component. In this configuration, the unevenness allows the sintered metal to easily penetrate into the grain boundaries of the component. This makes it easier to improve the quality of the sintered bond.

[0029] In the first semiconductor device described above, the region where the irregularities are formed may be configured to extend outward from the sinter-bonded region. In this configuration, the irregularities are formed in the region extending outward from the sinter-bonded region, so that when the sintered metal paste is heated to remove the solvent, the irregularities in the region extending outward from the sinter-bonded region can be used to make it easier to remove the solvent.

[0030] In the first semiconductor device described above, the sintered metal used to sinter-bond the first and second members can be copper. In this configuration, the diffusion rate of copper is low, so sintering of the sintered bonding layer due to self-heating during operation of the semiconductor device after manufacture is unlikely to occur. Therefore, even if the sintered density of the sintered bonding layer is low upon completion of bonding of the first and second members, the reliability of the semiconductor device after manufacture can be maintained.

[0031] In the first semiconductor device, the bonded interface with the uneven surface can be formed with crystal grains of 10 μm or less in diameter. In this configuration, the small grain size of the crystal grains increases the number of crystal grain boundaries, promoting atomic diffusion during sinter bonding. This activates interdiffusion between the sintered metal and the bonded interface, resulting in a dense bonded contact point. This results in a bonded layer that is resistant to peeling and has good thermal conductivity.

[0032] In the above-described method for manufacturing a semiconductor device, a pressure of 0.01 MPa to 1.00 MPa may be applied during sinter bonding, or bonding may be performed without applying pressure. In this configuration, bonding is performed with a small pressure or without applying pressure, which can prevent damage to the semiconductor chip, etc.

[0033] The first and second semiconductor devices each include a first member made of metal and a second member including a semiconductor chip, and the first and second members are joined by sintering. The first and second semiconductor devices each further include wiring connected to the semiconductor chip, forming, for example, a semiconductor module.

[0034] In the semiconductor device and the method for manufacturing the semiconductor device described above, the first member made of metal can be a metal wiring (wiring layer or wiring film), a metal plate, or the like. For example, the metal of the wiring layer can be, for example, Cu or Al. In addition, a coating of Ni, Au, Ag, Pd, or the like may be formed on the surface of the metal of the wiring layer. Furthermore, the first member may be configured with only one layer, or may be configured with multiple layers stacked. In either configuration, the surface that comes into contact with the sintered metal of the sintered bond is the bonded interface.

[0035] In the semiconductor device and the method for manufacturing the semiconductor device described above, the second member including the semiconductor chip may have a structure in which a bonded material is formed on the outermost surface of the lower surface of the semiconductor chip. The semiconductor chip may be made of various semiconductor materials such as silicon or SiC. The bonded material may be made of metals such as Ni, Cu, Au, Ag, and Pd. The second member may have only one layer, or may have multiple layers stacked together. In either structure, the surface that comes into contact with the sintered metal of the sintered bond is the bonded interface.

[0036] In the above-described semiconductor device and method for manufacturing the semiconductor device, metal powder such as Ag powder or Cu powder can be used as the sintered metal for sinter-bonding.

[0037] In the above-described semiconductor device and method for manufacturing the semiconductor device, the irregularities can be formed by etching, laser processing, ion milling, or the like.

[0038] Regarding the combination of the materials to be joined and the sintered metal, Au or Ag is often selected as the material to be joined for Ag powder, and Ni or Cu is often selected as the material to be joined for Cu powder, but the combinations are not limited to these.

[0039] In the first semiconductor device and semiconductor device manufacturing method described above, the irregularities are formed at the interface between both or one of the first and second members. The spacing between the irregularities is 10 μm or less. Here, the "spacing" of the irregularities in the present invention refers to the distance between the centers of the recesses of adjacent irregularities for multiple irregularities. The smaller the spacing between the irregularities, the more desirable it is. However, if the spacing is, for example, 0.1 μm or less, considering that the particles of typical sintered metals are submicron in diameter, the irregularities are provided near all particles on average near the bonding interface, making it easier to improve quality. On the other hand, from the perspective of thermal resistance, even on a slightly larger scale, if the bonding is dense, sufficient heat dissipation paths can be ensured, so the spacing of 10 μm or less is desirable.

[0040] Furthermore, if the opening diameter of the irregularities is large, particles of the sintered metal before sintering will easily penetrate into the irregularities. In this case, the difference in thickness of the sintered metal between inside and outside the irregularities will be large, causing the amount of shrinkage during sintering to vary depending on the location, making it difficult to uniformly transmit pressure. Therefore, an opening diameter that makes it difficult for particles to penetrate is desirable, and if the sintered metal particles are submicron in diameter, it is desirable for the opening diameter of the irregularities to be 0.01 μm or less. However, considering the possibility of containing coarse particles on the order of microns in diameter, the opening diameter of the irregularities may be approximately 10 μm or less.

[0041] Furthermore, if the depth of the irregularities (depth of the openings) is, for example, about 0.1 μm, it is easy to form a dense region of sintered metal, but this is not necessarily the case.

[0042] For example, Japanese Patent Application Laid-Open No. 2020-68360 discloses a technique for etching a metal plate to deepen the grain boundaries of the metal plate when joining a metal plate and an electronic component with a bonding material, thereby increasing the surface area and providing an anchor effect to enhance adhesive strength. However, this technique describes that the opening width of the etched recesses is approximately 3 μm to 10 μm, the recess depth is 2 μm to 20 μm, and the crystal grain size of the metal plate is 100 μm to 600 μm. Considering that the size of sintered particles is generally submicron, this technique involves holes several tens of times deeper than the particle size, spaced apart by a large distance of 100 μm to 600 μm, which is not scalable for the purpose of the present invention, which is to achieve an overall uniform interface by promoting diffusion.

[0043] Furthermore, according to the present invention, the bonding quality at the interface can be improved, and therefore the pressure applied during sintering can be reduced accordingly. Therefore, the technology of the present invention is particularly effective when used in combination with a process using a minute pressure of 0.01 MPa to 1.00 MPa or a pressureless process that does not use pressure, as opposed to sinter bonding, which generally requires a pressure of the order of 10 MPa.

[0044] In addition, the aforementioned silver or copper powder is generally used as the sintered metal. Here, because the diffusion rate of copper is slower than that of silver, sintering of the sintered bonding layer due to self-heating is less likely to occur during operation of the manufactured semiconductor device. Therefore, even if the sintered density of the sintered bonding layer is low upon completion of bonding of the first and second members, the reliability of the manufactured semiconductor device can be maintained. For this reason, using copper as the sintered metal rather than silver allows for a lower pressure during sintering than conventional methods, ensuring the reliability of the manufactured semiconductor module even if the sintered density of the sintered bonding layer is low. Therefore, the technology of the present invention is particularly effective when copper is used as the sintered metal and when used in conjunction with a process using a low pressure.

[0045] Specific examples of the semiconductor device of the present invention will be described below with reference to the drawings. In each of the following examples, the semiconductor device of the present invention includes a semiconductor chip and a wiring layer, and the semiconductor chip and wiring layer are bonded by sintering to form a semiconductor module. In each of the drawings and examples, the same or similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0046] Example 1 A semiconductor module of Example 1 will be described with reference to Figures 1 to 7. Figure 1 is a schematic cross-sectional view showing the structure of the semiconductor module of Example 1.

[0047] As shown in FIG. 1, the semiconductor module 20 of this embodiment includes a semiconductor chip 1, a sintered metal layer 2, a substrate 3, a base plate 4, a sintered metal layer 5 under the substrate, wires 6, terminals 7, a case 8, a sealing resin 9, and a lid 10.

[0048] The substrate 3 includes an insulating substrate 3c, a wiring layer 3a provided on the front side of the insulating substrate 3c, and a backside metal layer 3b provided on the backside of the insulating substrate 3c. The wiring layer 3a is composed of multiple wiring patterns. The wiring layer 3a may be made of a conductive metal such as copper. The backside metal layer 3b may be made of copper.

[0049] The semiconductor chip 1 is bonded to the wiring layer 3a via a sintered metal layer 2. The semiconductor chip 1 may be, for example, a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a diode. The sintered metal layer 2 may be, for example, a sintered copper layer or a sintered silver layer. In FIG. 1 , two semiconductor chips 1 are sinter-bonded to the wiring layer 3a via the sintered metal layer 2.

[0050] The base plate 4 functions as a heat dissipation member. The base plate 4 and the backside metal layer 3b of the substrate 3 are joined via the under-substrate sintered metal layer 5 below the substrate 3. The case 8 is adhered to the base plate 4, for example, with an adhesive (not shown).

[0051] The wires 6 are conductive wires that electrically connect the semiconductor chips 1 to each other, the wiring layers 3a to each other, or between the semiconductor chip 1 and the wiring layer 3a. One end of the terminals 7 is connected to the wiring layer 3a, and a portion of the other end is drawn out to the outside of the case 8 to function as an external connection terminal.

[0052] For example, silicone gel, epoxy resin, etc. can be used as the sealing resin 9. A lid 10 is placed on the sealing resin 9, and the lid 10 is bonded to the case 8 via an adhesive (not shown).

[0053] FIG. 2 is a cross-sectional view showing an example of the structure of the bonded interface of the semiconductor module 20 of Example 1. In Example 1, particularly on the surface of the semiconductor chip 1 and the surface of the wiring layer 3a, which form the bonded interfaces of the semiconductor module 20, fine irregularities 11 and 12 are provided as shown in FIG. 2. In FIG. 2, the semiconductor chip 1 has a first layer 1A including semiconductor elements made of silicon or SiC and other electrode films, and a second layer 1B on the outermost surface on which a bonded material such as Ni is exposed. The fine irregularities 11 are formed on the underside of the second layer 1B. Furthermore, the fine irregularities 12 are formed on the upper side of the wiring layer 3a on which a bonded material such as Cu is exposed.

[0054] In Figure 2, fine irregularities 11, 12 are formed on both the second layer 1B of the semiconductor chip 1 and the wiring layer 3a, but it is also possible to configure the structure so that irregularities are formed on only one of the second layer 1B and the wiring layer 3a.

[0055] In addition to the above-mentioned Ni, Cu, Au, Ag, Pd, etc. can be used as the bonding material for the outermost surface of the second layer 1B of the semiconductor chip 1. Furthermore, Ag powder or Cu powder can be used as the sintered metal for sinter bonding. Regarding the combination of the sintered metal and the outermost bonding material, Au or Ag is often selected for the outermost surface for Ag powder, and Ni or Cu is often selected for the outermost surface for Cu powder, but the combinations are not limited to these.

[0056] Furthermore, for example, a semiconductor chip 1 such as a power semiconductor element or a wiring layer 3a made of metal wiring may have a layer structure formed by plating or the like, and in such a case, unevenness is provided at least on the bonding interface on the outermost surface of the layer structure.

[0057] The semiconductor module 20 of Example 1 can be manufactured, for example, as described below. First, fine irregularities are formed on the outermost surface of at least one of the semiconductor chip 1 and the wiring layer 3a. The fine irregularities can be formed by etching, laser processing, ion milling, or the like. Next, a paste supplying process is performed in which a paste of a sintering material that will become the sintered metal layer 2 is supplied to the wiring layer 3a using printing or a dispenser. This is followed by a pre-drying process in which the paste is heated to remove the solvent components contained in the paste. However, this pre-drying process can be omitted in some cases, and the solvent components can be removed by heating in the sintering process. Next, a chip mounting process is performed in which the semiconductor chip 1 is mounted on the sintering material. Finally, a sintering process is performed in which heat and pressure are applied to perform sinter bonding. Note that, depending on the bonding material used, pressure may not be applied during sinter bonding.

[0058] Here, we will explain atomic diffusion in sinter bonding. Sinter bonding can be considered a phenomenon in which atoms constituting the sintered metal and the atoms constituting the materials to be bonded gradually become one by mutual exchange through diffusion. There are three main modes of atomic diffusion. The first is surface diffusion. Surface diffusion is the fastest because it moves along the outermost surface where there are few obstacles. Next, there is grain boundary diffusion, which moves along grain boundaries. Although not as fast as surface diffusion, grain boundary diffusion is the second fastest because it moves through grain boundaries where other atoms are relatively sparse. The last is volume diffusion. Volume diffusion is the slowest because atoms move inside dense particles. In this way, sintering is a phenomenon that progresses through three diffusion modes.

[0059] FIG. 3 is a schematic diagram illustrating diffusion during sinter bonding. FIG. 3 shows the diffusion state when two sintered metals 21 and 22 are sinter-bonded, with the atoms 23 constituting the sintered metals 21 and 22 diffusing in the three modes described above. Arrows 31 indicate surface diffusion, in which atoms diffuse along the outermost surfaces of the particles of the sintered metals 21 and 22. Arrows 32 indicate grain boundary diffusion, in which atoms diffuse along the grain boundaries 24 of the particles of the sintered metals 21 and 22. Arrows 33 indicate volume diffusion, in which atoms diffuse along the interiors of the particles of the sintered metals 21 and 22. As shown in the upper diagram of FIG. 3 , the atoms 23 of the sintered metals 21 and 22 diffuse through surface diffusion 31, grain boundary diffusion 32, and volume diffusion 33, and the two sintered metals 21 and 22 are bonded at the grain boundaries 23, as shown in the lower diagram of FIG. 3 .

[0060] Next, the bonding mechanism between the sintered metal and the bonded interface in a typical sinter-bonding process, which serves as a comparison with the present invention, will be described with reference to Figures 4A and 4B. Figures 4A and 4B are cross-sectional views showing diffusion at the interface during typical sinter-bonding. Figures 4A and 4B show the changes that occur when a member 14 having a grain boundary 24 is sinter-bonded to a sintered metal 13. The lower surface of the member 14 forms the bonded interface with the sintered metal 13.

[0061] When the sintering temperature is reached by heating, as shown in FIG. 4A , atoms 23 constituting the sintered metal 13 diffuse into the bonded interface through the contact points between the particles of the sintered metal 13 and the bonded interface of the component 14. Surface diffusion 31 is the fastest diffusion mode, so it is dominant. However, some atoms 23 penetrate deep into the component 14 through grain boundaries 24 included in the bonded interface. Although volume diffusion also progresses slightly, it is slower than other modes and therefore is not dominant. As a result, the sintered metal 13 spreads thinly at the bonded interface with the component 14, as shown in FIG. 4B , while some penetrates deep into the component 14. This is believed to result in a bonded interface with a certain degree of strength. At the same time, atoms constituting the bonded interface also diffuse into the particles of the sintered metal 13, but this diffusion is not shown for simplicity.

[0062] In contrast, the bonding mechanism between the sintered metal and the bonded interface in the sinter-bonding process of the semiconductor device of the present invention will be described with reference to Figures 5A and 5B. Figures 5A and 5B are cross-sectional views showing diffusion at the interface during sinter-bonding in the semiconductor device of the present invention. Figures 5A and 5B, like Figures 4A and 4B, show changes that occur when a member 14 having a grain boundary 24 is sinter-bonded to a sintered metal 13. The lower surface of the member 14 forms the bonded interface with the sintered metal 13.

[0063] As shown in FIG. 5A , the surface of the bonded interface of the component 14 near the grain boundary 24 is processed to have irregularities 15 in the depth direction. The irregularities 15 shown in FIG. 5A are formed along the grain boundary 24 so that they are deepest near the grain boundary 24 of the component 14. The component 14 in the state shown in FIG. 5A can be produced, for example, by selectively etching the bonded interface of the component 14 to deepen the area near the grain boundary 24. When the bonded interface has such an irregularity, upon heating to a sintering temperature, the atoms 23 constituting the sintered metal 13 can penetrate to a certain extent in the depth direction of the component 14 through the surface of the irregularities 15 at the fastest speed of surface diffusion 31, as shown in FIG. 5A . Furthermore, when the irregularities 15 are deep near the grain boundary 24 as shown in FIG. 5A , the atoms 23 constituting the sintered metal 13 can penetrate deeper into the component 14 at the speed of grain boundary diffusion 32 because the irregularities 15 are connected to the grain boundary 24. This allows the sintered metal 13 to penetrate a considerable amount in the depth direction of the component 14. This also means that the amount of contact between the sintered metal 13 and the interface to be joined of the member 14 increases, and the interdiffusion between the sintered metal 13 and the interface to be joined of the member 14 also becomes active, and as shown in Fig. 5B, the atoms that constitute the interface to be joined (trapezoidal portion 25 surrounded by the dashed line in Fig. 5B) that were present near the tip of the unevenness 15 eventually scatter. In this way, a sintered metal layer with a certain thickness is obtained, as shown by the arrow in Fig. 5B.

[0064] The examples shown in FIGS. 5A and 5B show examples in which irregularities 15 are formed by deeply digging near the grain boundaries 24. However, even if fine irregularities are simply provided rather than near the grain boundaries, the effect of penetration in the depth direction by surface diffusion can be obtained, and therefore, although the effect is somewhat inferior, the effect of improving reliability can be obtained compared to the case without processing.

[0065] The method for processing the recesses and projections is not limited to etching, and any method that can process the recesses and projections to the desired size, such as laser processing or ion milling, may be used.

[0066] Assuming the above mechanism, the results of an actual prototype are shown below. The prototype this time was configured to bond sintered copper to a Ni film.

[0067] Here, the surface state of the Ni film after etching was observed using a SEM (scanning electron microscope). Figure 6 shows an SEM image of the surface state after etching the Ni film as an observation result. As shown in Figure 6, it can be seen that grooves with contour-like shapes are formed on the surface. This is presumed to be due to, for example, the grain boundaries being selectively and deeply processed by etching.

[0068] 7A and 7B show the results of sinter-bonding a normal Ni film and the film shown in FIG. 6 , comparing the interface structures. FIG. 7A is an SEM image of a cross section of a normal Ni film sinter-bonded. FIG. 7B is an SEM image of a cross section of a Ni film sinter-bonded with a textured surface. Comparing FIGS. 7A and 7B reveals that the bonded interface with the textured surface has a denser contact point between the sintered copper and Ni. This demonstrates that an interface structure with excellent heat dissipation and resistance to peeling has been obtained.

[0069] In the semiconductor module 20 of this embodiment, fine irregularities are formed at the interface to be bonded on either or both of the semiconductor chip 1 and the wiring layer 3a, which are sinter-bonded by the sintered metal layer 2. These fine irregularities promote atomic diffusion during sinter bonding, activating interdiffusion between the sintered metal and the interface to be bonded, and resulting in a dense bonded contact point. This results in a bonding layer that is resistant to peeling and has good thermal conductivity.

[0070] Next, a semiconductor module of Example 2 will be described. The semiconductor module of Example 2 also has the same configuration as the semiconductor module 20 of Example 1 shown in Fig. 1. Furthermore, as will be described in detail later, the semiconductor module of Example 2 is configured such that the fine irregularities formed at the bonded interface extend to an area outside the sinter-bonded area.

[0071] Before describing the configuration of the semiconductor module of Example 2, the wettability of the solvent used to apply the sintered metal to the interface to be sintered will be described.

[0072] Generally, a rough surface with irregularities has the property of enhancing wettability compared to a flat surface, which can be expressed by the Wenzel equation shown in the following formula (1).

[0073] cosθw = rcosθ (1) (θw: contact angle on rough surface, θ: contact angle on flat surface, r: area ratio of rough surface to flat surface)

[0074] Figure 8 is a cross-sectional view illustrating the phenomenon explained by Wenzel's equation. The top two figures in Figure 8 show the phenomenon in the case of a hydrophilic surface, and the bottom two figures in Figure 8 show the phenomenon in the case of a hydrophobic surface. In the top and bottom figures in Figure 8, the left figure shows the case where the surface is flat, and the right figure shows the case where the surface is roughened by unevenness. Note that the right figure omits the illustration of the unevenness of the rough surface.

[0075] As shown in the upper part of Figure 8, on a hydrophilic surface (θ<90°) with good wettability, the rough surface on the right side has a smaller contact angle (θw<θ) than the flat surface on the left side, making the rough surface more likely to wet. On the other hand, as shown in the lower part of Figure 8, on a hydrophobic surface (θ>90°) with poor wettability, the rough surface on the right side has a larger contact angle (θw>θ) than the flat surface on the left side, making the rough surface less likely to wet.

[0076] Next, a conventional semiconductor module, in which the interface to be sintered is a flat surface, will be compared with a semiconductor module of Example 2, in which the interface to be sintered is a rough surface having irregularities. FIG. 9 is a cross-sectional view of a sintered bonded portion of a conventional semiconductor module, in which the interface to be sintered is a flat surface. FIG. 10 is a cross-sectional view of a sintered bonded portion of a semiconductor module of Example 2, in which the interface to be sintered is a rough surface having irregularities. FIGS. 9 and 10 show, from left to right, the changes in state when a first member (e.g., the wiring layer 3 a shown in FIG. 1 ) 43 and a second member (e.g., including the semiconductor chip 1 shown in FIG. 1 ) are sintered and bonded using sintered metal powder 41. In FIGS. 9 and 10 , the leftmost figure shows a state in which a paste containing sintered metal powder 41 dispersed in a solvent 42 is supplied onto a first member 43, and a second member 44 is placed on the paste.

[0077] In the conventional semiconductor module shown in Figure 9, the solvent 42 evaporates when heated during the sinter-bonding process, and as shown in the center diagram, the evaporated solvent 42 escapes by filtering through the gaps in the sintered metal powder 41. However, the solvent 42 can only escape through the gaps in the sintered metal powder 41, and the gaps in the sintered metal powder 41 are narrow. For this reason, if heating is performed quickly to shorten the sinter-bonding process time, the remaining solvent 42 that has not been completely removed will gasify, increasing the internal pressure, causing the sintered metal powder 41 to be ejected and forming voids. When voids are formed in the sinter-bonded portion, the strength of the sintered bond weakens and the reliability of the bond decreases.

[0078] In the semiconductor module of Example 2 shown in FIG. 10 , asperities 45 and 46 are formed at the joining interfaces of a first member 43 and a second member 44, respectively, which strengthens the wetting power of the solvent 42 and allows the solvent 42 to be actively discharged along the surfaces of the asperities 45 and 46, thereby preventing the solvent 42 from remaining.

[0079] 10, the area where the irregularities 45, 46 are provided is extended outward from the area where the sinter-bonding paste is supplied and sinter-bonded. This makes it easier for the solvent 42 to be discharged than when the area where the irregularities 45, 46 are provided is the same size as the area where the sinter-bonding paste is supplied.

[0080] In the configuration of Example 2, it is more preferable that the solvent 42 to be dried and the surface having the irregularities 45, 46 be made of the easily wettable materials described in Figure 8. This allows the solvent to be actively expelled from the bonding surface while remaining liquid along the surface, allowing the solvent to be expelled and dried more quickly than with a flat surface. This configuration not only promotes diffusion at the bonding interface, but also prevents unbonded joints and reduced bonding strength due to residual solvent, thereby further improving product reliability.

[0081] The above describes a technique for improving the quality of the bonded interface by providing irregularities at the bonded interface and promoting diffusion in the depth direction at the interface. A similar approach can be considered by utilizing grain refinement technology to create a state with many grain boundaries at the interface, rather than providing minute irregularities on the surface. An example of this method is described below as Example 3.

[0082] A semiconductor module of Example 3 will be described with reference to Figures 11A and 11B. The semiconductor module of Example 3 also has the same configuration as the semiconductor module 20 of Example 1 shown in Figure 1. Figures 11A and 11B are cross-sectional views showing a manufacturing method for the semiconductor module of Example 3.

[0083] 11A and 11B, in the semiconductor module of Example 3, the intervals between the grain boundaries 24 of the member 14 joined to the sintered metal 13 are shortened to increase the number of grain boundaries 24. In order to increase the number of grain boundaries 24 in this manner, a technique for refining crystal grains is used. In this example, any method may be used as the technique for refining crystal grains.

[0084] In this embodiment, by increasing the number of grain boundaries 24 of the member 14, the number of paths through which the sintered metal 13 can penetrate by grain boundary diffusion 32 in the depth direction of the member 14 increases, as shown in Fig. 11B, thereby improving the quality of the bonded interface. More specifically, if the size of the crystal grains after refinement is 10 µm or less and the bonded interface is composed of crystal grains of 10 µm or less, the effect of improving the quality of the bonded interface is enhanced.

[0085] It is also possible to combine a configuration in which the crystal grains at the bonded interface are refined, as in the semiconductor module of Example 3, with a configuration in which fine irregularities are formed at the bonded interface, as in the semiconductor modules of Examples 1 and 2.

[0086] The present invention is not limited to the configurations described in the above-mentioned embodiments and examples, and various modifications are possible within the scope of the technical concept of the present invention. In addition, some or all of the configurations described in each example may be combined and applied.

[0087] 1 Semiconductor chip, 1A First layer, 1B Second layer, 2 Sintered metal layer, 3 Substrate, 3a Wiring layer, 3b Backside metal layer, 3c Insulating substrate, 4 Base plate, 5 Under-substrate sintered metal layer, 6 Wire, 7 Terminal, 8 Case, 9 Sealing resin, 10 Lid, 11, 12, 15, 45, 46 Concave and convex, 13, 21, 22 Sintered metal, 14 Member, 20 Semiconductor module, 23 Atom, 24 Grain boundary, 31 Surface diffusion, 32 Grain boundary diffusion, 33 Volume diffusion, 41 Sintered metal powder, 42 Solvent, 43 First member, 44 Second member

Claims

1. A semiconductor device comprising: a first member made of metal; and a second member including a semiconductor chip; the first member and the second member being joined by sintering; and at least one of the first member and the second member having an uneven surface at the interface to be joined, the uneven surface having an interval of 10 μm or less.

2. The semiconductor device according to claim 1, wherein the interval between the projections and recesses is 0.1 μm or less.

3. The semiconductor device according to claim 1, wherein the depth of said irregularities is 0.1 μm or more.

4. The semiconductor device according to claim 1, wherein the opening diameter of said irregularities is 10 μm or less.

5. The semiconductor device according to claim 1, wherein the opening diameter of said irregularities is 0.01 μm or less.

6. The semiconductor device according to claim 1, wherein the irregularities are formed along the grain boundaries of the material.

7. The semiconductor device according to claim 1, wherein the region where the irregularities are formed extends outward beyond the sinter-bonded region.

8. The semiconductor device according to claim 1, wherein the sintered metal used to sinter-bond said first member and said second member is copper.

9. The semiconductor device according to claim 1, wherein the interface to be bonded, on which the irregularities are formed, is composed of crystal grains having a grain size of 10 μm or less.

10. A semiconductor device comprising: a first member made of metal; and a second member including a semiconductor chip; wherein the first member and the second member are joined by sintering; and the joined interface of at least one of the first member and the second member is composed of crystal grains with a grain size of 10 μm or less.

11. A method for manufacturing a semiconductor device in which a first member made of metal and a second member including a semiconductor chip are bonded by sinter bonding, comprising the steps of: forming irregularities with an interval of 10 μm or less on the bonding interface of at least one of the first member and the second member; and then supplying sintered metal to the bonding interface where the irregularities have been formed, thereby performing sinter bonding.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the sinter-bonding is carried out with a pressure of 0.01 MPa to 1.00 MPa applied, or with no pressure applied.

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