Silicon carbide semiconductor device

Abstract

This silicon carbide semiconductor device comprises a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, and having, in a plan view perpendicular to the first main surface, an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region. The silicon carbide substrate comprises a first semiconductor region having a first conductive type, a plurality of second semiconductor regions provided in the first semiconductor region and having a second conductive type, and a third semiconductor region provided in the active region, having the second conductive type, forming the first main surface, and being ring-shaped in the plan view. A portion of the plurality of second semiconductor regions is electrically connected to the third semiconductor region. The plurality of second semiconductor regions are arranged, along a first axis parallel to the first main surface, in the active region, the first termination region, and the second termination region, and extend along a second axis that is parallel to the first main surface and perpendicular to the first axis. A first width of the second semiconductor regions in the second termination region is smaller than a second width of the second semiconductor regions in the first termination region.

Description

Silicon carbide semiconductor device

[0001] The present disclosure relates to silicon carbide semiconductor devices.

[0002] This application claims priority based on Japanese Application No. 2024-021704 filed on February 16, 2024, and incorporates by reference all of the contents of the aforementioned Japanese application.

[0003] Conventionally, semiconductor devices having a superjunction structure have been disclosed.

[0004] Japanese Patent Application Publication No. 2003-273355

[0005] a third semiconductor region having the second conductivity type and configured as an annular third semiconductor region in the plan view, the third semiconductor region having the second conductivity type and constituting the first main surface; a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including, in a plan view perpendicular to the first main surface, an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region; a first semiconductor region having a first conductivity type, the first semiconductor region having a first conductivity type, a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region, the third semiconductor region having the second conductivity type and constituting the first main surface, the third semiconductor region having an annular shape in the plan view, the third semiconductor region having the second conductivity type provided within the active region, the third semiconductor region having the second conductivity type and constituting the first main surface; a first width of the second semiconductor region in the second termination region being smaller than a second width of the second semiconductor region in the first termination region;

[0006] FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of the silicon carbide semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing the configuration of an active region of the silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing the configuration of the vicinity of the boundary between the active region and a termination region of the silicon carbide semiconductor device according to an embodiment. FIG. 5 is a schematic diagram showing an enlargement of a portion of FIG. 1. FIG. 6 is a cross-sectional view (part 1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIG. 7 is a cross-sectional view (part 2) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. FIG. 8 is a cross-sectional view (part 3) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment.

[0007] [Problem to be Solved by the Present Disclosure] In conventional semiconductor devices, it is difficult to further improve the breakdown voltage.

[0008] An object of the present disclosure is to provide a silicon carbide semiconductor device that can improve breakdown voltage.

[0009] [Effects of the Present Disclosure] According to the present disclosure, it is possible to improve the breakdown voltage.

[0010] The embodiments for carrying out the invention are described below.

[0011] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, identical or corresponding elements will be denoted by the same reference numerals, and the same description will not be repeated. In the crystallographic descriptions in this specification, individual orientations are denoted by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually expressed by placing a "-" (bar) above a number, but in this disclosure, a negative sign is placed before the number. In the following description, an XYZ Cartesian coordinate system is used, but this coordinate system is defined for the purpose of explanation and does not limit the orientation of a silicon carbide semiconductor device. An XY plane view is referred to as a planar view, and the +Z direction from an arbitrary point may be referred to as upward, upper side, or top, and the -Z direction may be referred to as downward, lower side, or bottom.

[0012] [1] a third semiconductor region having the second conductivity type and configured to form the first main surface; a third semiconductor region having the second conductivity type and configured to form the first main surface; a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate including, in a plan view perpendicular to the first main surface, a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region; and a third semiconductor region having the second conductivity type and configured to form the first main surface and configured to be annular in the plan view, the third semiconductor region having the second conductivity type and configured to form the first main surface; a first width of the second semiconductor region in the second main surface; a second width of the second semiconductor region in the second main surface;

[0013] The first width of the second semiconductor region in the second termination region is smaller than the second width of the second semiconductor region in the first termination region. Therefore, compared to when the first width is equal to the second width, depletion is more likely to be promoted near the second semiconductor region that contacts the third semiconductor region, and the electric field applied to the second semiconductor region that contacts the third semiconductor region is alleviated. Therefore, the breakdown voltage can be improved.

[0014] [2] In [1], the third width of the second semiconductor region in the active region may be smaller than the second width. In this case, the breakdown voltage in the active region becomes lower than the breakdown voltage in the first termination region, and the avalanche current generated when avalanche breakdown occurs is more likely to disperse within the active region. This improves the avalanche breakdown capability.

[0015] [3] In [1] or [2], the first width may be smaller than a third width of the second semiconductor region in the active region. In this case, the avalanche resistance can also be improved.

[0016] [4] In any one of [1] to [3], any of the plurality of second semiconductor regions may be provided in the active region, the first termination region, and the second termination region, in which case electric field concentration near the second semiconductor region is likely to be alleviated.

[0017] [5] In any one of [1] to [4], the plurality of second semiconductor regions may be provided at a constant pitch along the first axis. In this case, high uniformity in breakdown voltage within the silicon carbide semiconductor device can be easily obtained.

[0018] [6] In any one of [1] to [5], the second semiconductor region may have a lower end surface facing the second major surface, and the distance between the first major surface and the lower end surface may be equal to or greater than half the thickness of the first semiconductor region. In this case, a high breakdown voltage can be easily obtained even if the concentration of the first impurity in the first semiconductor region is relatively high in the active region. Therefore, the on-resistance can be easily reduced.

[0019] [Embodiments of the Present Disclosure] An embodiment of the present disclosure relates to a so-called vertical MOS (metal oxide semiconductor) field effect transistor (FET) using silicon carbide. This MOS FET is an example of a silicon carbide semiconductor device. FIG. 1 is a schematic diagram showing an overview of a silicon carbide substrate in a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a diagram showing the configuration of an interlayer insulating film and a first main surface in an active region of a silicon carbide semiconductor device according to an embodiment. FIG. 3 is a cross-sectional view showing the configuration of an active region of a silicon carbide semiconductor device according to an embodiment. FIG. 4 is a cross-sectional view showing the configuration near the boundary between the active region and a termination region of a silicon carbide semiconductor device according to an embodiment. FIG. 5 is a schematic diagram showing an enlarged portion of FIG. 1. FIG. 2 corresponds to region II in FIG. 1. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. 2. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 1. A barrier metal film 84 is omitted from FIG. 4. FIG. 5 corresponds to region V in FIG.

[0020] As shown in Figures 1 to 5, the silicon carbide semiconductor device 100 according to the embodiment has a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60, a drain electrode 70, and a barrier metal film 84.

[0021] The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The first main surface 1 and the second main surface 2 are parallel to the XY plane, and the first main surface 1 is in the +Z direction when viewed from the second main surface 2. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on the silicon carbide single crystal substrate 50. The silicon carbide epitaxial layer 40 constitutes the first main surface 1, and the silicon carbide single crystal substrate 50 constitutes the second main surface 2. The silicon carbide single crystal substrate 50 and the silicon carbide epitaxial layer 40 are made of, for example, hexagonal silicon carbide of polytype 4H. The silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen (N) and has an n-type conductivity (first conductivity type).

[0022] 1 and 5 , silicon carbide substrate 10 has active region 110, first termination region 121, and second termination region 122. Active region 110 has, for example, a square shape with rounded corners in a plan view perpendicular to first main surface 1. Active region 110 may also have a rectangular shape with rounded corners in a plan view. First termination region 121 surrounds active region 110 in a plan view. First termination region 121 is provided around active region 110 in a plan view. Second termination region 122 surrounds first termination region 121 in a plan view. Second termination region 122 is provided around first termination region 121 in a plan view.

[0023] The first main surface 1 is a {0001} plane or a {0001} plane tilted at an off angle of 8 degrees or less in the off direction. Preferably, the first main surface 1 is a (000-1) plane or a (000-1) plane tilted at an off angle of 8 degrees or less in the off direction. The first main surface 1 may be a (0001) plane or a (0001) plane tilted at an off angle of 8 degrees or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 degree or more, or 2 degrees or more. The off angle may be 6 degrees or less, or 4 degrees or less.

[0024] The silicon carbide epitaxial layer 40 has a drift region 11 , a body region 12 , a source region 13 , a p-type region 14 for superjunction, a contact region 16 , a junction termination structure (JTE) 17 , and a contact region 18 .

[0025] Drift region 11 contains n-type impurities such as nitrogen or phosphorus (P) and has n-type conductivity. Drift region 11 is provided on silicon carbide single crystal substrate 50.

[0026] The body region 12 contains p-type impurities such as aluminum (Al) and has p-type conductivity. The body region 12 is located within the active region 110. The body region 12 is provided on the drift region 11. The lower end surface of the body region 12 and the upper end surface of the drift region 11 are in contact with each other.

[0027] The source region 13 contains n-type impurities such as nitrogen or phosphorus and has n-type conductivity. The source region 13 is located within the active region 110. The source region 13 is provided on the body region 12. The source region 13 is separated from the drift region 11 by the body region 12. The source region 13 constitutes the first main surface 1.

[0028] A plurality of gate trenches 5 defined by side surfaces 3 and bottom surfaces 4 are provided on the first major surface 1. The gate trenches 5 are formed in the active region 110. The gate trenches 5 extend, for example, along the Y axis. A plurality of gate trenches 5 are also provided along the X axis at regular intervals (first pitch P1). The side surfaces 3 penetrate the source region 13, the body region 12, and a portion of the drift region 11, and reach the drift region 11. The bottom surfaces 4 are continuous with the side surfaces 3. The bottom surfaces 4 are located in the drift region 11. For example, the bottom surfaces 4 are parallel to the first major surface 1 and the second major surface 2. In a cross-sectional view perpendicular to the Y axis, an angle θ1 of the side surfaces 3 with respect to an imaginary plane 30 including the bottom surfaces 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. The side surfaces 3 preferably have a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility.

[0029] The contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 18 is located within the active region 110. The contact region 18 penetrates the source region 13 and is in contact with the body region 12. The contact region 18 constitutes the first main surface 1. In a plan view perpendicular to the first main surface 1, the contact region 18 is located between gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 and the source regions 13 may be alternately provided along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis. The contact regions 18 may be provided intermittently along the Y-axis between two gate trenches 5 adjacent to each other along the X-axis.

[0030] A plurality of gate trenches 5 may be arranged at regular intervals along the Y axis. When a plurality of gate trenches 5 are arranged at regular intervals along the Y axis, a part of the contact region 18 may be located between adjacent gate trenches 5 along the Y axis. A plurality of gate trenches 5 may be provided in an array.

[0031] The contact region 16 contains p-type impurities such as aluminum and has p-type conductivity. The contact region 16 is located within the active region 110. The contact region 16 is formed simultaneously with the contact region 18, is made of the same material as the contact region 18, and has the same depth as the contact region 18. The contact region 16 also constitutes the first main surface 1. In a plan view, the contact region 16 is provided in an annular shape, and a plurality of gate trenches 5 and a gate electrode 82 (described below) are located inside the contact region 16. The outer edge of the contact region 16 is the boundary between the active region 110 and the first termination region 121. In this disclosure, the term "annular" includes a shape that is a single closed curve other than a circular annular shape or an elliptical annular shape, such as a rounded rectangular shape. The contact region 16 is an example of a third semiconductor region.

[0032] JTE 17 contains p-type impurities such as aluminum at an effective concentration lower than that of contact region 16, and has p-type conductivity. JTE 17 is provided in an annular shape so as to be in contact with contact region 16. In a plan view, contact region 16 is located inside JTE 17. JTE 17 is located within first termination region 121. JTE 17 may be located not only in first termination region 121 but also in second termination region 122. JTE 17 also constitutes first main surface 1. JTE 17 is provided inside the outer edge of silicon carbide substrate 10, and first main surface 1 at the outer edge of silicon carbide substrate 10 is constituted by drift region 11.

[0033] The p-type region 14 contains p-type impurities such as aluminum and has p-type conductivity. The p-type region 14 is located in the active region 110, the first termination region 121, and the second termination region 122. The p-type region 14 is provided within the drift region 11. The p-type region 14 may extend along the Y-axis. A plurality of p-type regions 14 are aligned along the X-axis. A plurality of p-type regions 14 may be provided at a constant pitch along the X-axis. A plurality of p-type regions 14 may be provided in a stripe pattern. The effective concentration of the p-type impurity in the p-type region 14 is, for example, 1×10 １６ cm －３ 5x10 or more １７ cm －３ The p-type region 14 is an example of a second semiconductor region. The X-axis is an example of a first axis, and the Y-axis is an example of a second axis.

[0034] As shown in FIGS. 1 and 5, the plurality of p-type regions 14 are roughly divided into three types of p-type regions 14A, 14B, and 14C.

[0035] P-type region 14A is provided in active region 110, first termination region 121, and second termination region 122. The +Y side end and the −Y side end of p-type region 14A are located within second termination region 122. The portion of p-type region 14A within active region 110 may be located between gate trenches 5 adjacent along the X axis, or may be located below contact region 16. A portion of p-type region 14A within first termination region 121 overlaps with JTE 17 in plan view, and the remaining portion within first termination region 121 is separated from JTE 17 in plan view.

[0036] P-type region 14B is provided in first termination region 121 and second termination region 122. In plan view, p-type region 14B is on the +X side or the −X side of active region 110. The +Y side end and the −Y side end of p-type region 14B are located within second termination region 122. The portion of p-type region 14B within first termination region 121 may overlap with JTE 17 in plan view, or may be separated from JTE 17 in plan view.

[0037] The p-type region 14C is provided in the second termination region 122. In plan view, the p-type region 14C is on the +X side or the −X side of the first termination region 121. The entire p-type region 14C is located within the second termination region 122.

[0038] As shown in FIG. 3 , a portion of the p-type region 14A is located between adjacent gate trenches 5 along the X-axis in a plan view perpendicular to the first main surface 1. A p-type region 14S, which is part of the p-type region 14A and located between adjacent gate trenches 5 along the X-axis, is spaced apart from the gate trench 5. The body region 12 is exposed at the side surface 3 of the gate trench 5. The p-type region 14S is located farther from the gate trench 5 along the X-axis than the body region 12. The p-type region 14S is located below the body region 12 and is in contact with the body region 12. The p-type region 14S overlaps the contact region 18 in a plan view perpendicular to the first main surface 1. The contact region 18 may penetrate the body region 12, and the p-type region 14S may be in contact with the body region 12 and the contact region 18. The contact region 18, the body region 12, and the p-type region 14S are electrically connected to one another.

[0039] 4, a p-type region 14T that is part of p-type region 14A and is located below contact region 16 is in contact with contact region 16. A p-type region 14U that is part of p-type region 14B and is located below JTE 17 is in contact with JTE 17.

[0040] Thus, p-type regions 14A, 14B and 14C include portions within second termination region 122, p-type regions 14A and 14B include portions within first termination region 121, and p-type region 14A includes portions within active region 110.

[0041] 5, a first width W1 of p-type region 14 in second termination region 122 is smaller than a second width W2 of p-type region 14 in first termination region 121. A third width W3 of p-type region 14 in active region 110 is equal to second width W2.

[0042] The p-type region 14 has a lower end surface 14G facing the second main surface 2. For example, the distance between the first main surface 1 and the lower end surface 14G is 1 μm or more. The p-type region 14 can be formed, for example, by channeling implantation of p-type impurities into an n-type epitaxial layer.

[0043] In active region 110, drift region 11 is exposed to side surface 3 and contacts body region 12 and p-type region 14. In first termination region 121 and second termination region 122, drift region 11 forms first main surface 1 outside JTE 17 in plan view. Drift region 11 may contact silicon carbide single crystal substrate 50. The effective concentration of n-type impurities in drift region 11 is, for example, 1×10 １６ cm －３ 5x10 or more １７ cm －３ The drift region 11 may include a current spreading region having a particularly high concentration of n-type impurities within the active region 110. The drift region 11 is an example of a first semiconductor region.

[0044] Along the Z axis, silicon carbide single crystal substrate 50 and drift region 11 are present between bottom surface 4 and second main surface 2, and the conductivity type of silicon carbide substrate 10 between bottom surface 4 and second main surface 2 is n-type.

[0045] The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 contacts the side surface 3 and the bottom surface 4. The gate insulating film 81 contacts the drift region 11 at the bottom surface 4. The gate insulating film 81 contacts the source region 13, the body region 12, and the drift region 11 at the side surface 3. The gate insulating film 81 may contact the source region 13 at the first main surface 1.

[0046] The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. The gate electrode 82 is disposed inside the gate trench 5. The gate electrode 82 faces the side surface 3 and the bottom surface 4. A portion of the gate electrode 82 may face the first main surface 1. The gate electrode 82 extends along the Y-axis. In a plan view perpendicular to the first main surface 1, the gate electrode 82 may overlap with multiple gate trenches 5.

[0047] A gate insulating film 81 is also provided on the contact region 16, and an electrode film 85 is formed thereon. The electrode film 85 is formed simultaneously with the gate electrode 82 and is made of the same material as the gate electrode 82.

[0048] The interlayer insulating film 83 covers the gate electrode 82. The interlayer insulating film 83 is in contact with the gate electrode 82 and the gate insulating film 81. The interlayer insulating film 83 is, for example, an oxide film. The interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A portion of the interlayer insulating film 83 may be provided inside the gate trench 5. The upper surface of the interlayer insulating film 83 may be a curved surface whose curvature changes continuously. The upper surface of the interlayer insulating film 83 may be a curved surface that is convex in the +Z direction above the gate trench 5.

[0049] Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals along the X-axis. The contact holes 90 are arranged so that the gate trench 5 is located between adjacent contact holes 90 along the X-axis. The contact holes 90 extend along the Y-axis. Through the contact holes 90, the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81.

[0050] Above the contact region 16, an interlayer insulating film 83 is provided on the gate insulating film 81 and the electrode film 85. A contact hole 91 is formed in the interlayer insulating film 83, reaching the electrode film 85, and a contact hole 92 is formed in the interlayer insulating film 83 and the gate insulating film 81, reaching the contact region 16. The silicon carbide semiconductor device 100 has a gate runner 63 and a source runner 64. The gate runner 63 and the source runner 64 are formed simultaneously with the source electrode 60 and are made of the same material as the source electrode 60. The gate runner 63 is electrically connected to the gate electrode 82 and the electrode film 85. The source runner 64 is electrically connected to the source electrode 60 and the contact region 16. In a plan view, the source runner 64 is provided in an annular shape, and the outer edge of the source runner 64 may coincide with the outer edge of the contact region 16. The gate runner 63 is provided between the source electrode 60 and the source runner 64.

[0051] The barrier metal film 84 covers the upper surface of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81. The barrier metal film 84 is in contact with the interlayer insulating film 83 and the gate insulating film 81. The barrier metal film 84 is made of a material containing, for example, titanium nitride (TiN).

[0052] The source electrode 60 is in contact with the first main surface 1. The source electrode 60 includes a contact electrode 61 provided in a contact hole 90 and a source wiring 62. The contact electrode 61 is in contact with the source region 13, the contact region 16, and the contact region 18 on the first main surface 1. The contact electrode 61 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 forms an ohmic junction with the source region 13, the contact region 16, and the contact region 18. The source wiring 62 covers the upper surface and side surfaces of the barrier metal film 84 and the upper surface of the contact electrode 61. The source wiring 62 is in contact with the barrier metal film 84 and the contact electrode 61. The source wiring 62 is made of a material containing, for example, aluminum.

[0053] Silicon carbide semiconductor device 100 further has silicon nitride film 87 and polyimide film 88. Silicon nitride film 87 covers the upper surface and side surfaces of interlayer insulating film 83, and polyimide film 88 covers the upper surface and side surfaces of silicon nitride film 87. An opening exposing a portion of source electrode 60 is formed in silicon nitride film 87 and polyimide film 88, and a source plating film 86 is formed inside this opening. Silicon nitride film 87 and polyimide film 88 also have an opening (not shown) exposing a portion of a gate electrode (not shown) connected to gate runner 63, and a gate plating film (not shown) is formed inside this opening.

[0054] The drain electrode 70 is in contact with the second main surface 2. The drain electrode 70 is in contact with the silicon carbide single crystal substrate 50 at the second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing nickel silicide, for example. The drain electrode 70 may also be made of a material containing titanium, aluminum, and silicon. The drain electrode 70 is in ohmic contact with the silicon carbide single crystal substrate 50.

[0055] A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single crystal substrate 50 and drift region 11. Also, a passivation film covering a part of source electrode 60 may be provided.

[0056] The effective concentration of p-type impurities in the contact regions 16 and 18 may be higher than the effective concentration of p-type impurities in the body region 12. For example, the effective concentration of p-type impurities in the contact regions 16 and 18 may be, for example, 1×10 １８ cm －３ 1x10 or more ２０ cm －３ The effective concentration of p-type impurities in the body region 12 is 5×10 １７ cm －３ 1x10 or more １８ cm －３ The following is the result.

[0057] The effective concentration of n-type impurities in the source region 13 may be higher than the effective concentration of p-type impurities in the body region 12. The effective concentration of n-type impurities in the source region 13 may be, for example, 1×10 １９ cm －３ That's about it.

[0058] In the present disclosure, the effective concentration of a first conductivity type impurity is the concentration obtained by subtracting the concentration of a second conductivity type impurity from the concentration of the first conductivity type impurity, and the effective concentration of a second conductivity type impurity is the concentration obtained by subtracting the concentration of the first conductivity type impurity from the concentration of the second conductivity type impurity. The effective concentrations can be measured using, for example, a scanning capacitance microscope (SCM).

[0059] Drift region 11 has n-type conductivity, and body region 12 and p-type region 14 have p-type conductivity, so the boundary between drift region 11 and body region 12 and the boundary between drift region 11 and p-type region 14 are clear.

[0060] Next, a description will be given of a method for manufacturing silicon carbide semiconductor device 100. Figures 6 to 8 are cross-sectional views showing a method for manufacturing silicon carbide semiconductor device 100 according to an embodiment.

[0061] First, as shown in Fig. 6, a silicon carbide single crystal substrate 50 is prepared. Next, a silicon carbide epitaxial layer 40 is formed on the silicon carbide single crystal substrate 50. For example, the silicon carbide single crystal substrate 50 contains n-type impurities such as nitrogen and has n-type conductivity. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth with the addition of n-type impurities such as nitrogen.

[0062] 7 , ions are implanted into silicon carbide epitaxial layer 40 to form p-type region 14. The ion implantation for forming p-type region 14 involves channeling implantation of p-type impurities such as aluminum. At this time, the upper end surface of p-type region 14 may be exposed from the upper surface of silicon carbide epitaxial layer 40.

[0063] 8 , ions are implanted into silicon carbide epitaxial layer 40 to form body region 12, source region 13, contact region 16, JTE 17, and contact region 18. The remaining portion of silicon carbide epitaxial layer 40 becomes drift region 11.

[0064] Next, a plurality of gate trenches 5 are formed. Next, a gate insulating film 81, a gate electrode 82, an electrode film 85, an interlayer insulating film 83, a barrier metal film 84, a silicon nitride film 87, a polyimide film 88, and a plating film 86 are formed (see FIGS. 3 and 4).

[0065] In this manner, silicon carbide semiconductor device 100 can be manufactured.

[0066] In silicon carbide semiconductor device 100, as described above, first width W1 of p-type region 14 in second termination region 122 is smaller than second width W2 of p-type region 14 in first termination region 121. Therefore, compared to when first width W1 is equal to second width W2, depletion is more likely to be promoted in the vicinity of p-type region 14 in contact with contact region 16, and the electric field applied to p-type region 14 in contact with contact region 16 is alleviated. Therefore, the breakdown voltage can be improved.

[0067] The third width W3 of the p-type region 14 in the active region 110 may be smaller than the second width W2. If the third width W3 is smaller than the second width W2, the breakdown voltage in the active region 110 becomes lower than the breakdown voltage in the first termination region 121, and the avalanche current generated when avalanche breakdown occurs is more likely to disperse within the active region 110. This improves the avalanche resistance. Similarly, the avalanche resistance can also be improved by making the first width W1 smaller than the third width W3.

[0068] Furthermore, although the distribution of impurity concentration in the p-type region 14 may deviate from the design value due to manufacturing errors, there is a wide tolerance (margin) within which a high breakdown voltage can be obtained even in such cases.

[0069] P-type region 14A is provided in active region 110, first termination region 121, and second termination region 122. This makes it easy to alleviate electric field concentration in the vicinity of p-type region 14A.

[0070] When multiple p-type regions 14 are provided at a constant pitch along the X-axis, it is easy to obtain high uniformity in the breakdown voltage within silicon carbide semiconductor device 100. When multiple p-type regions 14 extend along the Y-axis, it is easy to form p-type regions 14 uniformly.

[0071] When the distance between the first main surface 1 and the lower end surface 14G is equal to or greater than half the thickness of the drift region 11, a high breakdown voltage can be easily obtained even if the concentration of n-type impurities in the drift region 11 is relatively high within the active region 110. Therefore, the on-resistance can be easily reduced.

[0072] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0073] REFERENCE SIGNS LIST 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 Drift region (first semiconductor region) 12 Body region 13 Source region 14, 14A, 14B, 14C, 14S, 14T, 14U p-type region (second semiconductor region) 14G Lower end surface 16 Contact region (third semiconductor region) 18 Contact region 17 Junction termination structure 30 Virtual plane 40 Silicon carbide epitaxial layer 50 Silicon carbide single crystal substrate 60 Source electrode 61 Contact electrode 62 Source wiring 63 Gate runner 64 Source runner 70 Drain electrode 81 Gate insulating film 82 Gate electrode 83 Interlayer insulating film 84 Barrier metal film 85 Electrode film 86 Plating film 87 Silicon nitride film 88 Polyimide film 90, 91, 92 Contact holes 100 Silicon carbide semiconductor device 110 Active region 121 First termination region 122 Second termination region P1 First pitch W1 First width W2 Second width W3 Third width X X axis (first axis) Y Y axis (second axis) Z Z axis θ1 Angle

Claims

1. A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having, in a plan view perpendicular to the first main surface, an active region, a first termination region surrounding the active region, and a second termination region surrounding the first termination region, wherein the silicon carbide substrate has: a first semiconductor region having a first conductivity type; a plurality of second semiconductor regions having a second conductivity type provided within the first semiconductor region; and a third semiconductor region having the second conductivity type provided within the active region, constituting the first main surface and having an annular shape in the plan view, wherein some of the plurality of second semiconductor regions are electrically connected to the third semiconductor region, and the plurality of second semiconductor regions are aligned within the active region, the first termination region, and the second termination region along a first axis parallel to the first main surface, and extend along a second axis parallel to the first main surface and perpendicular to the first axis, a first width of the second semiconductor region in the second termination region that is smaller than a second width of the second semiconductor region in the first termination region; 2. The silicon carbide semiconductor device according to claim 1, wherein a third width of said second semiconductor region in said active region is smaller than said second width.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein said first width is smaller than a third width of said second semiconductor region within said active region.

4. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein any of the plurality of second semiconductor regions is provided in the active region, the first termination region, and the second termination region.

5. The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the plurality of second semiconductor regions are provided at a constant pitch along the first axis.

6. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the second semiconductor region has a lower end surface facing the second main surface, and the distance between the first main surface and the lower end surface is equal to or greater than 1 / 2 of the thickness of the first semiconductor region.

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