Synchronization signal processing device, video display system, and synchronization signal processing method

Abstract

A synchronization signal processing device (100) comprises a correction value control unit (10) and a synchronization generation unit (50). The correction value control unit (10) acquires an input synchronization signal that is a vertical synchronization signal for an input video, determines whether or not the cycle of the input synchronization signal is greater than or equal to a predetermined threshold value that is greater than the cycle corresponding to the refresh rate of an LCD panel (300) on which an output video is displayed, generates a set cycle on the basis of a cycle of 1 / N times the input synchronization signal (N = integer 2 or greater) when it is determined that the cycle of the input synchronization signal is greater than or equal to the predetermined threshold value, and generates a set cycle on the basis of the cycle of the input synchronization signal when it is determined that the cycle of the input synchronization signal is less than the predetermined threshold value. The synchronization generation unit (50) generates an output synchronization signal that is a vertical synchronization signal of the output video on the basis of the set cycle.

Description

Synchronous signal processing device, video display system, and synchronous signal processing method

[0001] The present disclosure relates to a synchronization signal processing device, a video display system, and a synchronization signal processing method.

[0002] Patent Document 1 discloses a technique for controlling a video synchronization signal.

[0003] Patent No. 6128901

[0004] For example, some cameras used in electronic mirrors change their exposure time depending on the ambient brightness, dynamically changing the vertical synchronization signal output from the camera. For example, some cameras dynamically change the vertical synchronization signal between 60 Hz and 30 Hz. In contrast, the technology disclosed in Patent Document 1 does not anticipate cases where the cycle of the vertical synchronization signal changes dynamically, and the display may not display correctly.

[0005] Therefore, the present disclosure provides a synchronization signal processing device and the like that enables a display device to display correctly even if the vertical synchronization signal of the input video changes dynamically.

[0006] The synchronization signal processing device according to the present disclosure comprises a correction value control unit and a synchronization generation unit, wherein the correction value control unit acquires an input synchronization signal that is a vertical synchronization signal of an input video, determines whether the period of the input synchronization signal is equal to or greater than a predetermined threshold value that is greater than a period corresponding to a refresh rate of a display on which an output video is displayed, and, if it is determined that the period of the input synchronization signal is equal to or greater than the predetermined threshold value, generates a set period based on a period that is 1 / N times (N is an integer greater than or equal to 2) the input synchronization signal, and, if it is determined that the period of the input synchronization signal is less than the predetermined threshold value, generates the set period based on the period of the input synchronization signal, and the synchronization generation unit generates an output synchronization signal that is a vertical synchronization signal of the output video based on the set period.

[0007] A video display system according to the present disclosure includes the above-described synchronization signal processing device, a video input section to which the input video is input, and a video output section to which the output video is output.

[0008] The synchronization signal processing method according to the present disclosure is a synchronization signal processing method executed by a synchronization signal processing device, and includes the steps of: acquiring an input synchronization signal, which is a vertical synchronization signal of an input video; determining whether the period of the input synchronization signal is equal to or greater than a predetermined threshold value that is greater than a period corresponding to a refresh rate of a display on which an output video is displayed; generating a set period based on a period that is 1 / N times (N is an integer of 2 or greater) of the input synchronization signal if it is determined that the period of the input synchronization signal is equal to or greater than the predetermined threshold value; generating the set period based on the period of the input synchronization signal if it is determined that the period of the input synchronization signal is less than the predetermined threshold value; and generating an output synchronization signal, which is a vertical synchronization signal of the output video, based on the set period.

[0009] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a computer-readable recording medium such as a CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0010] According to a synchronization signal processing device and the like according to an aspect of the present disclosure, the display can display correctly even if the vertical synchronization signal of the input video changes dynamically.

[0011] 1 is a block diagram showing an example of a video display system according to embodiment 1. FIG. 2 is a block diagram showing an example of a correction value control unit according to embodiment 1. FIG. 3 is a flowchart showing an example of the operation of the correction value control unit according to embodiment 1. FIG. 4 is a diagram for explaining the operation of the correction value control unit according to embodiment 1. FIG. 5 is a block diagram showing an example of a video display system according to embodiment 2. FIG. 6 is a block diagram showing an example of a correction value control unit according to embodiment 2. FIG. 7 is a block diagram showing an example of a correction value generation unit according to embodiment 2. FIG. 8 is a flowchart showing an example of the operation of the correction value control unit according to embodiment 2. FIG. 9 is a diagram for explaining the operation of the correction value control unit according to embodiment 2. FIG. 10 is a flowchart showing an example of a method for adjusting a phase difference in embodiment 2. FIG. 11 is a diagram for explaining a method for adjusting a phase difference in embodiment 2. FIG. 11 is a block diagram showing an example of a video display system according to a modified example of embodiment 2. FIG. 2 is a block diagram showing a first example of a correction value control unit according to embodiment 3. FIG. 3 is a block diagram showing a second example of a correction value control unit according to embodiment 3. FIG. 4 is a block diagram showing a third example of a correction value control unit according to embodiment 3. FIG. 5 is a flowchart showing an example of a synchronization signal processing method according to other embodiments.

[0012] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0013] The embodiments described below are all comprehensive or specific examples, and the numerical values, shapes, materials, components, arrangement and connection of the components, steps, and order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0014] (First Embodiment) A synchronous signal processing device and a video display system according to a first embodiment will be described below.

[0015] Fig. 1 is a block diagram showing an example of a video display system 1 according to embodiment 1. In addition to the video display system 1, Fig. 1 also shows a camera 200 and an LCD panel 300. The same applies to Figs. 5 and 12 described below.

[0016] Camera 200 captures an image and outputs the captured image to image display system 1. For example, when camera 200 is used in an electronic mirror, camera 200 changes the exposure time depending on the ambient brightness, dynamically changing the vertical synchronization signal output from camera 200. For example, camera 200 dynamically changes the vertical synchronization signal between 60 Hz and 30 Hz. Under the condition that the horizontal cycles of input and output are the same, an input image of 30 Hz is input to the effective area at the same speed as 60 Hz, but the vertical blanking is twice as long, resulting in one frame of 30 Hz image. Camera 200 is a camera that lengthens the vertical blanking as a means of changing the vertical cycle to 30 Hz, and the input image in the present disclosure is an input image from such a camera 200.

[0017] LCD panel 300 is an example of a display device that displays an output video that is input from camera 200 to video display system 1 and output from video display system 1. Specifically, the input video that is input from camera 200 to video display system 1 is output from video display system 1 to LCD panel 300 as an output video. For example, if the refresh rate of LCD panel 300 is 60 Hz and the vertical synchronization signal output from camera 200 changes from 60 Hz to 30 Hz, LCD panel 300 may not be able to display the video correctly.

[0018] Therefore, the following describes a synchronization signal processing device 100 and a video display system 1 that enable the LCD panel 300 to display correctly even if the vertical synchronization signal of the input video changes dynamically.

[0019] The video display system 1 includes a video input unit 110 , a memory 120 , a video output unit 130 and a synchronous signal processing device 100 .

[0020] The video input unit 110 is an interface that receives the video (input video) output from the camera 200. The video input unit 110 outputs the input video to the memory 120, and also outputs an input synchronization signal, which is a vertical synchronization signal for the input video, to the synchronization signal processing device 100.

[0021] The memory 120 is a frame memory that stores images. For example, the memory 120 has at least one bank configuration. When the input image and the output image are synchronized, the memory 120 only needs to have one bank configuration, and by starting output when the input image has been written to about halfway up the bank, it is possible to display the image without outputting the image that is being written. However, when the input image and the output image are not synchronized, the memory 120 may require two or more banks.

[0022] The video output unit 130 is an interface that outputs the video stored in the memory 120. The video output unit 130 outputs the video stored in the memory 120 to the LCD panel 300 as an output video.

[0023] The synchronous signal processing device 100 includes a correction value control unit 10, a PLL (Phase Locked Loop) 20, a pixel counter 30, a line counter 40, and a synchronization generation unit 50. Each component included in the synchronous signal processing device 100 may be configured with dedicated hardware or may be implemented by executing a software program appropriate for that component. Each component may be implemented by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory. For example, the synchronous signal processing device 100 may be a computer including a processor (microprocessor) and memory. The memory may be a read-only memory (ROM) or a random access memory (RAM), and may store a program executed by the processor. For example, the correction value control unit 10 and the synchronization generation unit 50 may be implemented by a processor executing a program stored in memory.

[0024] The correction value control unit 10 acquires an input synchronization signal and determines whether the period of the input synchronization signal is equal to or greater than a switching threshold value that is greater than a period corresponding to the refresh rate of the LCD panel 300 on which the output video is displayed. The switching threshold value is an example of a predetermined threshold value. If the correction value control unit 10 determines that the period of the input synchronization signal is equal to or greater than the switching threshold value, it generates a set period based on a period that is 1 / N times the period of the input synchronization signal (N is an integer greater than or equal to 2), and if it determines that the period of the input synchronization signal is less than the switching threshold value, it generates a set period based on the period of the input synchronization signal. Details of the operation of the correction value control unit 10 will be described later.

[0025] The PLL 20 generates a pixel clock for the pixel counter 30. The PLL 20 is an example of a synchronization control unit. For example, the correction value control unit 10 outputs a clock period generated based on a set period to the PLL 20, and the PLL 20 generates a pixel clock based on the clock period. For example, assume below that the input vertical frequency is 60 Hz, the number of output pixels is 1650 pixels, and the number of output lines is 750 lines. When the set period corresponds to the input vertical frequency of 60 Hz, and the number of pixels in the output video (number of horizontal pixels x number of vertical lines) is 1650 x 750, the PLL 20 generates a pixel clock of (60 x 1650 x 750) Hz.

[0026] Each time the pixel counter 30 counts the number of horizontal pixels in the output video, it outputs a signal to the line counter 40. For example, the pixel counter 30 counts 1650 pixels as one line of pixels and notifies the line counter 40 that it has counted one line of pixels.

[0027] Each time the line counter 40 counts lines equal to the number of vertical pixels in the output video, it outputs a signal to the synchronization generation unit 50. For example, the line counter 40 counts 750 lines as the lines for one frame, and notifies the synchronization generation unit 50 that it has counted the lines for one frame.

[0028] The synchronization generation unit 50 generates an output synchronization signal, which is a vertical synchronization signal for the output video, based on a set period. Specifically, the timing at which the line counter 40 counts the lines for one frame is at a frequency corresponding to the set period, and the synchronization generation unit 50 generates an output synchronization signal with a frequency corresponding to the set period. As described above, if the set period corresponds to 60 Hz, which is the input vertical frequency, the synchronization generation unit 50 generates an output synchronization signal of 60 Hz.

[0029] Here, the configuration of the correction value control unit 10 will be described in detail with reference to FIG.

[0030] FIG. 2 is a block diagram showing an example of the correction value control unit 10 according to the first embodiment.

[0031] The correction value control unit 10 includes, for example, a period measurement unit 11, a 1 / N calculation unit 12, and a selection unit 13.

[0032] The period measurement unit 11 records the time when the input synchronization signal is acquired, and measures the period of the input synchronization signal by calculating the difference between the time when the input synchronization signal is acquired this time and the time when the input synchronization signal was acquired last time.

[0033] The 1 / N calculation unit 12 multiplies the period of the input synchronization signal by 1 / N. When the camera 200 changes the vertical synchronization signal from 60 Hz to 30 Hz, N=2, and the 1 / N calculation unit 12 multiplies the period of the input synchronization signal by 1 / 2.

[0034] The selector 13 determines whether the period of the input synchronization signal is equal to or greater than the switching threshold, and selects either a period 1 / N times the period of the input synchronization signal or the period of the input synchronization signal according to the determination result.

[0035] Next, the operation of the correction value control unit 10 will be described in detail with reference to FIGS.

[0036] FIG. 3 is a flowchart showing an example of the operation of the correction value control unit 10 according to the first embodiment.

[0037] 4 is a diagram for explaining the operation of the correction value control unit 10 according to the first embodiment. Fig. 4 shows the timing of the period of the input synchronization signal (input vertical synchronization signal) and the timing when the period of the input synchronization signal is halved. The horizontal axis represents time.

[0038] First, the cycle measurement unit 11 determines whether an input Vsync (vertical synchronization) interrupt of the input video has occurred (step S11). That is, the cycle measurement unit 11 determines whether an input synchronization signal has been acquired. For example, as shown in FIG. 4, an input Vsync interrupt occurs at time t_vi1, and the next input Vsync interrupt occurs at time t_vi2.

[0039] When the period measurement unit 11 determines that an input Vsync interrupt has occurred (Yes in step S11), it measures the period of the input Vsync (i.e., the period of the input synchronization signal) and records the time when the input Vsync interrupt occurred (step S12). For example, if Tvi is the period of the input Vsync, t_now is the current time, and t_vi is the time when the previous input Vsync interrupt occurred, the period measurement unit 11 calculates t_now - t_vi to calculate the period Tvi of the input Vsync, and then, for measuring the next period, records the current time as the time when the input Vsync interrupt occurred by substituting t_now for t_vi. 4, if time t_vi1 is recorded as t_vi and an input Vsync interrupt occurs at time t_vi2, the current time t_now becomes time t_vi2, and Tvi can be measured as t_vi2-t_vi1. Also, time t_vi2 is recorded as the occurrence time t_vi of the input Vsync interrupt for measuring the next cycle.

[0040] The period of the input Vsync may be measured by calculating the average of the past several (e.g., eight) periods of the input Vsync, thereby making it possible to measure a stable period of the input Vsync.

[0041] If it is determined that an input Vsync interrupt has not occurred (No in step S11), the process in step S12 is skipped.

[0042] Next, the selection unit 13 determines whether the period Tvi of the input Vsync is equal to or greater than a threshold (switching threshold) (step S13). For example, if the refresh rate of the LCD panel 300 is 60 Hz, the period corresponding to that refresh rate is (1 / 60) sec, and the switching threshold is (1 / 40) sec, which is greater than (1 / 60) sec. If the camera 200 changes the vertical synchronization signal from 60 Hz to 30 Hz, the period of the input Vsync becomes (1 / 30) sec, which is greater than the switching threshold (1 / 40) sec. Therefore, in such a case, the selection unit 13 determines that the period of the input Vsync is equal to or greater than the switching threshold.

[0043] If the selector 13 determines that the period of the input Vsync is equal to or greater than the switching threshold (Yes in step S13), it generates a set period based on 1 / N times the period of the input Vsync (step S14). As described above, when the camera 200 changes the vertical synchronization signal from 60 Hz to 30 Hz, N=2. For example, as shown in FIG. 4 , an input Vsync interrupt should occur after (1 / 60) seconds have elapsed since time t_vi1, but does not. Therefore, the selector 13 generates a set period of (1 / 60) seconds, which is half the period of the input Vsync (1 / 30) seconds. In other words, the selector 13 generates a set period corresponding to 60 Hz, which was the period before the camera 200 changed the frequency of the vertical synchronization signal to 30 Hz. The set period is used as the reference for the output Vsync.

[0044] As described above, when the period of the input synchronization signal is equal to or greater than the switching threshold, i.e., when the period of the input synchronization signal changes dynamically (specifically, becomes larger), the set period is generated based on 1 / N times the period of the input synchronization signal. For example, when the refresh rate of the LCD panel 300 is 60 Hz and the period of the input synchronization signal doubles (i.e., the frequency changes from 60 Hz to 30 Hz), the set period is generated based on 1 / 2 the period of the input synchronization signal, so the frequency of the output synchronization signal can be maintained at 60 Hz. Therefore, the LCD panel 300 can display correctly even if the vertical synchronization signal of the input video changes dynamically. For example, video from a camera 200 that dynamically changes the output vertical synchronization signal between 60 Hz and 30 Hz depending on the ambient brightness can be displayed on an LCD panel 300 that cannot tolerate fluctuations in the vertical synchronization signal period.

[0045] There is a conventional technology that provides two or more banks of frame memory to support a camera 200 that dynamically changes the vertical synchronization signal between 60 Hz and 30 Hz. However, in this conventional technology, the input synchronization signal and the output synchronization signal are asynchronous, which can cause fluctuations in input / output latency and the occurrence of frames being displayed twice or missing. In contrast, the synchronization signal processing device 100 of the present disclosure is less likely to encounter such problems.

[0046] There is also a conventional technology that adjusts the number of output lines to accommodate cameras 200 that dynamically change the vertical synchronization signal between 60 Hz and 30 Hz. However, with this conventional technology, the number of lines increases or decreases with each vertical synchronization, which may result in incorrect display on some LCD panels 300. Furthermore, when the input synchronization signal becomes 30 Hz, the error in the output synchronization signal becomes larger compared to when the input synchronization signal is 60 Hz. In contrast, the synchronization signal processing device 100 of the present disclosure is less likely to encounter such problems.

[0047] Second Embodiment Next, a synchronous signal processing device and a video display system according to a second embodiment will be described.

[0048] FIG. 5 is a block diagram showing an example of a video display system 2 according to the second embodiment.

[0049] Video display system 2 differs from video display system 1 according to embodiment 1 in that video display system 2 includes a synchronous signal processing device 100a instead of synchronous signal processing device 100. Also, synchronous signal processing device 100a differs from synchronous signal processing device 100 according to embodiment 1 in that it includes a correction value control unit 10a instead of correction value control unit 10. The following description will focus on the differences, and a description of the same points will be omitted.

[0050] The correction value control unit 10a compares the phase difference between the phase of the input synchronization signal and the phase of the output synchronization signal with a target phase difference, and generates a correction value based on the comparison result so that the phase difference approaches the target phase difference, and further generates a setting period based on the correction value. The configuration of the correction value control unit 10a will be described in detail with reference to FIG.

[0051] 6 is a block diagram showing an example of a correction value control unit 10a according to embodiment 2. The correction value control unit 10a differs from the correction value control unit 10 according to embodiment 1 in that it further includes a phase measurement unit 14, a comparison unit 15, a correction value generation unit 16, and an adder 17.

[0052] The phase measurement unit 14 measures the phase difference between the phase of the input synchronizing signal and the phase of the output synchronizing signal. Hereinafter, the phase difference between the phase of the input synchronizing signal and the phase of the output synchronizing signal will be simply referred to as the "phase difference."

[0053] The comparison unit 15 compares the phase difference with a target phase difference. The delay of the output synchronization signal relative to the input synchronization signal must be fixed so as not to vary, and the target phase difference is appropriately set as the amount of delay to be fixed.

[0054] Based on the result of the comparison, the correction value generator 16 generates a correction value that brings the phase difference closer to the target phase difference. As will be described later, a set period is generated based on the correction value, an output synchronization signal is generated based on the set period, and the output synchronization signal is fed back to the correction value controller 10 a, so that a correction value that brings the phase difference closer to the target phase difference can be generated by feedback control.

[0055] FIG. 7 is a block diagram showing an example of the correction value generating unit 16 according to the second embodiment.

[0056] For example, the correction value generating unit 16 includes a multiplier 16 a, which generates a correction value by multiplying the difference between the phase difference and the target phase difference by a correction gain stored in a register, for example. This makes it possible to increase the correction value when the phase difference is far from the target phase difference, and decrease the correction value when the phase difference is close to the target phase difference, thereby generating a stable output synchronization signal.

[0057] The adder 17 generates a set period based on the correction value. Specifically, the adder 17 generates a set period to which the correction value has been added by adding the correction value to the set period generated by the selector 13. An output synchronization signal is generated based on the set period to which the correction value has been added, and the output synchronization signal is fed back, causing the phase difference to approach the target phase difference.

[0058] Next, the operation of the correction value control unit 10a will be described in detail with reference to FIGS.

[0059] FIG. 8 is a flowchart showing an example of the operation of the correction value control unit 10a according to the second embodiment.

[0060] 9 is a diagram for explaining the operation of the correction value control unit 10a according to the second embodiment. Fig. 9 shows the timing of the period of the input synchronization signal (input vertical synchronization signal), the position of the target phase difference, the timing of the period of the output synchronization signal (output vertical synchronization signal), and the output clock (pixel clock) of the PLL 20. The horizontal axis represents time.

[0061] First, the phase measurement unit 14 determines whether an output Vsync (vertical synchronization) interrupt for the output video has occurred (step S21). That is, the phase measurement unit 14 determines whether an output synchronization signal has been acquired. For example, as shown in FIG. 9 , an output Vsync interrupt occurs at time t_vo1, and the next output Vsync interrupt occurs at time t_vo2.

[0062] If it is determined that the output Vsync interrupt has not occurred (No in step S21), the process in step S21 is performed again. That is, the generation of the output Vsync interrupt is awaited.

[0063] When the phase measurement unit 14 determines that an output Vsync interrupt has occurred (Yes in step S21), it calculates the phase difference between the input and output Vsync signals (step S22). Specifically, the phase measurement unit 14 calculates the phase difference phase by subtracting the time t_vi at which the most recent input Vsync interrupt occurred from the time t_vo at which the most recent output Vsync interrupt occurred. For example, as shown in FIG. 9 , at time t_vo1, phase can be calculated as phase = t_vo1 - t_vi1, and at time t_vo2, phase can be calculated as phase = t_vo2 - t_vi2.

[0064] Next, the phase measurement unit 14 calculates a remainder of the calculated phase difference and the period selected by the selection unit 13 to calculate a new phase difference phase (step S23). The phase measurement unit 14 outputs the calculated new phase difference to the comparison unit 15.

[0065] Next, the comparison unit 15 calculates the difference between the target phase difference and the phase difference between the input and output Vsync (step S24). Specifically, the comparison unit 15 calculates the difference diff by subtracting the phase difference phase from the target phase difference target. For example, as shown in FIG. 9, the phase difference between the input and output Vsync at time t_vo1 can be calculated as diff=target-(t_vo1-t_vi1), and the phase difference between the input and output Vsync at time t_vo2 can be calculated as diff=target-(t_vo2-t_vi2).

[0066] Next, the correction value generator 16 calculates an adjustment value (i.e., a correction value) (step S25). Specifically, the multiplier 16a calculates the adjustment value adjust by multiplying the difference (diff) between the target phase difference and the phase difference between the input and output Vsync signals by the correction gain (gain).

[0067] Next, the adder 17 calculates the period of the target output Vsync (step S26). For example, as shown in Fig. 9, the adder 17 calculates and outputs the period Tvt (i.e., the set period) of the output Vsync by adding the adjustment value adjust at time t_vo1 to the period Tvi of the input Vsync at time t_vi1.

[0068] The PLL 20 calculates the output clock frequency (in other words, the frequency of the pixel clock) using the set period output from the adder 17. Specifically, the PLL 20 calculates the output clock frequency f_clko by (1 / Tvt) × (width of the output video (i.e., the number of horizontal pixels)) × (height of the output video (i.e., the number of vertical lines)).

[0069] The PLL 20 then changes the output clock frequency. This allows the period of the output Vsync to become the target period Tvt, that is, the next output Vsync interrupt to be generated so that the phase difference "phase" approaches the target phase difference "target." For example, as shown in FIG. 9, when the phase difference "phase" is smaller than the target phase difference "target," the output clock frequency is lowered, resulting in a larger period of the output Vsync. Therefore, the phase difference "phase" increases and approaches the target phase difference "target."

[0070] Next, a method for adjusting the phase difference, specifically, a method for calculating the adjustment value will be described with reference to FIGS. 10 and 11. FIG.

[0071] FIG. 10 is a flowchart showing an example of a method for adjusting a phase difference according to the second embodiment.

[0072] 11 is a diagram for explaining a method for adjusting a phase difference in the second embodiment. Fig. 11 shows the timing of the period of an input synchronization signal (input vertical synchronization signal). The horizontal axis represents time.

[0073] For example, the capture range and dead band are set to calculate an adjustment value such that the adjustment value increases as the difference between the phase difference and the target phase difference increases. As shown in Fig. 11, the capture range and dead band are periods centered on the timing when the target phase difference time has elapsed since the time when the input Vsync was generated, and the capture range is larger than the dead band.

[0074] First, the correction value generating unit 16 determines whether the phase difference is outside the capture range (step S31), that is, whether the phase difference is significantly different from the target phase difference.

[0075] If the correction value generator 16 determines that the phase difference is outside the capture range (Yes in step S31), it sets a fixed value (e.g., a value equivalent to 1 msec) as the adjustment value for the period of the output Vsync (step S32). In other words, if the phase difference is significantly different from the target phase difference, the adjustment value is calculated so that the phase difference approaches the target phase difference at a fixed value.

[0076] If the correction value generator 16 determines that the phase difference is within the capture range (No in step S31), it determines whether the phase difference is outside the dead zone (step S33), i.e., whether the phase difference has approached the target phase difference.

[0077] If the correction value generator 16 determines that the phase difference is outside the dead zone (Yes in step S33), it sets the adjustment value for the period of the output Vsync to the difference between the phase difference and the target phase difference multiplied by the correction gain (step S34). That is, the adjustment value is calculated so that the smaller the difference between the phase difference and the target phase difference, the smaller the adjustment value. Note that the smaller the difference between the phase difference and the target phase difference, the smaller the correction gain may be used. For example, within the capture range, a first adjustment range larger than the dead zone and a second adjustment range larger than the first adjustment range may be provided, and when the phase difference is within the first adjustment range, a smaller correction gain may be used than when the phase difference is within the second adjustment range. This allows the phase difference to gradually approach the target phase difference.

[0078] If the correction value generator 16 determines that the phase difference is within the dead zone (No in step S33), it sets the adjustment value of the period of the output Vsync to 0 (step S35). That is, the adjustment of the phase difference is terminated. Note that if the dead zone is not provided and adjustment is performed until the phase difference matches the target phase difference, the phase difference may oscillate around the target phase difference, making it difficult to converge the phase difference to the target phase difference. For this reason, if the dead zone is provided and the phase difference is within the dead zone, it is determined that the phase difference has almost reached the target phase difference.

[0079] As described above, when the phase difference between the input synchronizing signal and the output synchronizing signal varies, it is necessary to temporarily store an image corresponding to the variation, which increases the frame memory capacity. Therefore, by maintaining the phase difference at a target phase difference, the required frame memory capacity can be reduced. For example, the memory 120 can be configured with only two banks.

[0080] In the second embodiment, an example has been described in which the correction value control unit 10a outputs a set period to the PLL 20, and the PLL 20 generates a pixel clock based on the set period. In this case, display is possible even on an LCD panel 300 that cannot allow an increase or decrease in the number of pixels per line. However, an operation different from this example may also be performed. This will be described with reference to FIG. 12.

[0081] FIG. 12 is a block diagram showing an example of a video display system 2a according to a modification of the second embodiment.

[0082] In the video display system 2a, the operation of the correction value control unit 10a and the pixel counter 30 included in the synchronization signal processing device 100a is different from that of the video display system 2 according to embodiment 2. The following description will focus on the differences, and a description of the same points will be omitted.

[0083] The correction value control unit 10a outputs the horizontal synchronization period generated based on the set period to the pixel counter 30. For example, the correction value control unit 10a outputs a horizontal synchronization period that brings the phase difference closer to the target phase difference to the pixel counter 30. That is, in the second embodiment, an example has been described in which the phase difference is adjusted to bring the phase difference closer to the target phase difference by adjusting the clock period. However, as in this modification, the phase difference may be adjusted to bring the phase difference closer to the target phase difference by adjusting the horizontal synchronization period (i.e., the number of horizontal pixels). In this case, display is possible even on an LCD panel 300 that cannot tolerate frame-by-frame fluctuations in clock frequency.

[0084] Third Embodiment Next, a correction value control unit according to a third embodiment will be described with reference to FIGS. 13A to 13C.

[0085] FIG. 13A is a block diagram showing a first example of a correction value control unit 10b according to the third embodiment.

[0086] FIG. 13B is a block diagram showing a second example of the correction value control unit 10b according to the third embodiment.

[0087] FIG. 13C is a block diagram showing a third example of the correction value control unit 10b according to the third embodiment.

[0088] The correction value control unit 10b differs from the correction value control unit 10 according to the first embodiment in that it further includes an abnormality processing unit that determines whether the input synchronization signal is abnormal. The following description will focus on the differences, and a description of the same points will be omitted.

[0089] The abnormality processing unit of the correction value control unit 10b determines whether the input synchronization signal is abnormal, and if it is determined that the input synchronization signal is abnormal, performs processing to set the set period to a constant period. Details of the abnormality processing unit will be described below using a first example shown in Figure 13A, a second example shown in Figure 13B, and a third example shown in Figure 13C.

[0090] First, a first example will be described. As shown in Fig. 13A, the correction value control unit 10b may include a comparison unit 18a and a selection unit 19a as an abnormality processing unit.

[0091] The comparator 18a determines whether the period of the input synchronization signal is abnormal by determining whether it is equal to or greater than a designated period that is greater than the switching threshold. In the first example, the designated period is an example of the first period. For example, in the first example, if the switching threshold is (1 / 40) sec, the designated period is (1 / 8) sec, for example. The comparator 18a determines whether the period of the input synchronization signal is abnormally long, for example, whether the input synchronization signal has been lost.

[0092] If the selector 19a determines that the period of the input synchronization signal is equal to or greater than the specified period, it sets the set period to a predetermined period. The predetermined period is a period relative to the refresh rate of the LCD panel 300, such as 1 / 60 seconds. For example, if the input synchronization signal is lost, an output synchronization signal with a predetermined period is generated.

[0093] In this way, if the cycle of the input synchronization signal is equal to or greater than the specified cycle, for example, if the input synchronization signal is lost, it is possible to prevent the LCD panel 300 from becoming unable to display an image.

[0094] The comparator 18a may determine whether to ignore the input synchronization signal when the period of the input synchronization signal becomes equal to or greater than the specified period and then falls below the specified period. Ignoring the input synchronization signal means maintaining the currently set period. When the period of the input synchronization signal becomes equal to or greater than the specified period and then falls below the specified period, for example, the input synchronization signal disappears and then returns. This makes it possible to select the input synchronization signal to be resynchronized when the input synchronization signal disappears and then returns.

[0095] Next, a second example will be described. As shown in Fig. 13B, the correction value control unit 10b may include a comparison unit 18b and a selection unit 19b as an abnormality processing unit.

[0096] The comparator 18b determines whether the period of the input synchronization signal is abnormal by determining whether it is equal to or shorter than a designated period that is shorter than the period corresponding to the refresh rate of the LCD panel 300. In the second example, the designated period is an example of the second period. For example, in the second example, if the refresh rate of the LCD panel 300 is (1 / 60) sec, the designated period is (1 / 120) sec, for example. The comparator 18b determines whether the period of the input synchronization signal is abnormally short, for example, whether the input synchronization signal is generated frequently within a certain period due to cable insertion / removal or poor contact.

[0097] If the selector 19b determines that the period of the input synchronization signal is equal to or shorter than the specified period, it ignores the input synchronization signal. Ignoring the input synchronization signal means maintaining the currently set period. This allows the period of the output synchronization signal to be kept constant when the period of the input synchronization signal is equal to or shorter than the specified period, for example, when the input synchronization signal is generated frequently within a certain period due to cable insertion / removal or poor contact.

[0098] Next, a third example will be described. As shown in Fig. 13C, the correction value control unit 10b may include a comparison unit 18c as an abnormality processing unit.

[0099] If the comparator 18c determines that the input synchronization signal is abnormal, it notifies the external device of the abnormal state. For example, if the period of the input synchronization signal is longer than a specified period such as (1 / 8) sec, or if the period of the input synchronization signal is shorter than a specified period such as (1 / 120) sec, the comparator 18c notifies the external device of the abnormal state. This allows an abnormality such as loss or disruption of the input synchronization signal to be notified to the outside.

[0100] As described above, when an abnormality such as loss or disturbance of the input synchronization signal occurs, the period of the output synchronization signal can be kept constant and the abnormality can be notified to the outside.

[0101] The correction value control unit 10a according to the second embodiment may include the abnormality processing unit according to the third embodiment.

[0102] (Other Embodiments) As described above, the embodiments have been described as examples of the technology according to the present disclosure. However, the technology according to the present disclosure is not limited to these, and can be applied to embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate. For example, the following modifications are also included in one embodiment of the present disclosure.

[0103] For example, the present disclosure can be realized not only as a video display system and a synchronous signal processing device, but also as a synchronous signal processing method including steps (processing) performed by components that make up the synchronous signal processing device.

[0104] FIG. 14 is a flowchart showing an example of a synchronization signal processing method according to another embodiment.

[0105] The synchronization signal processing method is a synchronization signal processing method executed by a synchronization signal processing device, and as shown in FIG. 14 , includes the steps of: acquiring an input synchronization signal, which is a vertical synchronization signal of an input video (step S101); determining whether the period of the input synchronization signal is equal to or greater than a predetermined threshold value that is greater than a period corresponding to the refresh rate of a display on which an output video is displayed (step S102); generating a set period based on a period that is 1 / N times (N is an integer of 2 or greater) of the input synchronization signal if it is determined that the period of the input synchronization signal is equal to or greater than the predetermined threshold value (Yes in step S102); generating the set period based on the period of the input synchronization signal if it is determined that the period of the input synchronization signal is less than the predetermined threshold (No in step S102) (steps S103 and S104); and generating an output synchronization signal, which is a vertical synchronization signal of an output video, based on the set period (step S105).

[0106] For example, the present disclosure can be realized as a program for causing a computer (processor) to execute steps included in a synchronization signal processing method. Furthermore, the present disclosure can be realized as a non-transitory computer-readable recording medium, such as a CD-ROM, on which the program is recorded.

[0107] For example, when the present disclosure is realized as a program (software), each step is performed by running the program using hardware resources such as a computer's CPU, memory, input / output circuits, etc. In other words, each step is performed by the CPU acquiring data from memory or input / output circuits, etc., performing calculations, and outputting the calculation results to memory or input / output circuits, etc.

[0108] Some or all of the functions of the synchronous signal processing device according to the above embodiments are typically realized as an LSI, which is an integrated circuit. These may be individually integrated into single chips, or some or all of them may be integrated into a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized using a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after LSI manufacturing, or a reconfigurable processor that can reconfigure the connections and settings of circuit cells within the LSI, may also be used.

[0109] Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derived technologies, it is natural that each component included in the synchronous signal processing device may be integrated using that technology.

[0110] In addition, this disclosure also includes forms obtained by making various modifications to the embodiments that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions in each embodiment within the scope of the present disclosure.

[0111] (Additional Notes) The above description of the embodiments discloses the following techniques.

[0112] (Technology 1) A synchronization signal processing device comprising a correction value control unit and a synchronization generation unit, wherein the correction value control unit acquires an input synchronization signal that is a vertical synchronization signal of an input video, determines whether a period of the input synchronization signal is equal to or greater than a predetermined threshold value that is greater than a period corresponding to a refresh rate of a display on which an output video is displayed, generates a set period based on a period that is 1 / N times (N is an integer of 2 or greater) of the input synchronization signal if it is determined that the period of the input synchronization signal is equal to or greater than the predetermined threshold, and generates the set period based on the period of the input synchronization signal if it is determined that the period of the input synchronization signal is less than the predetermined threshold, and the synchronization generation unit generates an output synchronization signal that is a vertical synchronization signal of the output video based on the set period.

[0113] According to this, when the period of the input synchronization signal is equal to or greater than a predetermined threshold, i.e., when the period of the input synchronization signal changes dynamically (specifically, becomes larger), the set period is generated based on 1 / N times the period of the input synchronization signal. For example, when the refresh rate of a display device is 60 Hz and the period of the input synchronization signal doubles (i.e., the frequency changes from 60 Hz to 30 Hz), the set period is generated based on 1 / 2 the period of the input synchronization signal, so the frequency of the output synchronization signal can be maintained at 60 Hz. Therefore, the display can display correctly even if the vertical synchronization signal of the input video changes dynamically. For example, video from an in-vehicle camera that dynamically changes the output vertical synchronization signal between 60 Hz and 30 Hz depending on the ambient brightness can be displayed on a display device such as an LCD panel that cannot tolerate fluctuations in the vertical synchronization signal period.

[0114] There is a conventional technology that provides two or more banks of frame memory to support cameras that dynamically change the vertical synchronization signal between 60 Hz and 30 Hz. However, in this conventional technology, the input synchronization signal and the output synchronization signal are asynchronous, which can cause fluctuations in input / output latency and the occurrence of frames being displayed twice or missing. In contrast, the synchronization signal processing device of the present disclosure is less likely to encounter such problems.

[0115] There is also a conventional technology that adjusts the number of output lines to accommodate cameras that dynamically change the vertical synchronization signal between 60 Hz and 30 Hz. However, with this conventional technology, the number of lines increases or decreases with each vertical synchronization, which may result in incorrect display depending on the display. Furthermore, when the input synchronization signal is 30 Hz, the error in the output synchronization signal becomes larger compared to when it is 60 Hz. In contrast, the synchronization signal processing device disclosed herein is less likely to encounter such problems.

[0116] (Technology 2) The synchronization signal processing device described in Technology 1, wherein the correction value control unit compares the phase difference between the phase of the input synchronization signal and the phase of the output synchronization signal with a target phase difference, generates a correction value based on the result of the comparison so that the phase difference approaches the target phase difference, and further generates the setting period based on the correction value.

[0117] According to this, if the phase difference between the phase of the input synchronizing signal and the phase of the output synchronizing signal varies, it is necessary to temporarily store an image corresponding to the variation, which increases the capacity of the frame memory. Therefore, by maintaining the phase difference at the target phase difference, the required frame memory capacity can be reduced. For example, the frame memory can be configured with only one bank.

[0118] (Technology 3) The synchronization signal processing device according to Technology 2, further comprising a pixel counter and a synchronization control unit that generates a pixel clock for the pixel counter, wherein the synchronization control unit generates the pixel clock based on the set period.

[0119] This makes it possible to display even on a display device that cannot allow an increase or decrease in the number of pixels per line.

[0120] (Technology 4) The synchronization signal processing device according to Technology 2 further includes a pixel counter and a synchronization control unit that generates a pixel clock for the pixel counter, wherein the correction value control unit outputs a horizontal synchronization period generated based on the set period to the pixel counter, and the pixel counter counts the number of pixels based on the horizontal synchronization period.

[0121] This makes it possible to display even on a display device that cannot tolerate clock frequency fluctuations for each frame.

[0122] (Technology 5) The synchronization signal processing device according to any one of Technologies 2 to 4, wherein the correction value control unit generates the correction value by multiplying a difference between the phase difference and the target phase difference by a correction gain.

[0123] This allows the correction value to be increased when the phase difference is far from the target phase difference, and decreased when the phase difference is close to the target phase difference, thereby generating a stable output synchronization signal.

[0124] (Technology 6) A synchronization signal processing device described in any of Technologies 1 to 5, wherein the correction value control unit determines whether the input synchronization signal is abnormal, and if it determines that the input synchronization signal is abnormal, performs processing to set the set period to a constant period.

[0125] This makes it possible to maintain a constant period of the output synchronizing signal even when an abnormality such as loss or disruption of the input synchronizing signal occurs.

[0126] (Technology 7) The correction value control unit determines whether the input synchronization signal is abnormal by determining whether the period of the input synchronization signal is equal to or greater than a first period that is greater than the predetermined threshold, and if it determines that the period of the input synchronization signal is equal to or greater than the first period, sets the set period to a predetermined period.This is a synchronization signal processing device described in Technology 6.

[0127] According to this, when the period of the input synchronization signal is equal to or greater than the first period, for example, when the input synchronization signal is lost, it is possible to prevent the display device from becoming unable to display.

[0128] (Technology 8) A synchronization signal processing device described in Technology 7, wherein the correction value control unit determines whether to ignore the input synchronization signal when the period of the input synchronization signal becomes equal to or greater than the first period and then becomes less than the first period.

[0129] According to this, when the input synchronization signal is lost and then restored, it is possible to select the input synchronization signal to be resynchronized.

[0130] (Technology 9) The correction value control unit determines whether the input synchronization signal is abnormal by determining whether the period of the input synchronization signal is equal to or less than a second period that is smaller than the period corresponding to the refresh rate of the display, and ignores the input synchronization signal if it determines that the period of the input synchronization signal is equal to or less than the second period.

[0131] This allows the period of the output synchronization signal to be kept constant when the period of the input synchronization signal is equal to or shorter than the second period, for example, when the input synchronization signal occurs frequently within a certain period due to cable insertion / removal or poor contact.

[0132] (Technology 10) The synchronization signal processing device according to any one of Technologies 6 to 9, wherein the correction value control unit notifies an external device of the abnormal state when it determines that the input synchronization signal is abnormal.

[0133] This allows an abnormality such as loss or disturbance of the input synchronization signal to be notified to the outside.

[0134] (Technology 11) A video display system comprising: a synchronization signal processing device according to any one of technologies 1 to 10; a video input unit to which the input video is input; and a video output unit to which the output video is output.

[0135] This makes it possible to provide a video display system that allows the display to display video correctly even if the vertical synchronization signal of the input video changes dynamically.

[0136] (Technology 12) A synchronization signal processing method executed by a synchronization signal processing device, the synchronization signal processing method including the steps of: acquiring an input synchronization signal that is a vertical synchronization signal of an input video; determining whether a period of the input synchronization signal is equal to or greater than a predetermined threshold value that is greater than a period corresponding to a refresh rate of a display on which an output video is displayed; generating a set period based on a period that is 1 / N times (N is an integer of 2 or greater) of the input synchronization signal if it is determined that the period of the input synchronization signal is equal to or greater than the predetermined threshold value; generating the set period based on the period of the input synchronization signal if it is determined that the period of the input synchronization signal is less than the predetermined threshold value; and generating an output synchronization signal that is a vertical synchronization signal of the output video based on the set period.

[0137] This makes it possible to provide a synchronization signal processing method that enables the display to display correctly even if the vertical synchronization signal of the input video changes dynamically.

[0138] (Technology 13) The synchronization signal processing method described in Technology 12 further includes a step of comparing a phase difference between the phase of the input synchronization signal and the phase of the output synchronization signal with a target phase difference, and generating a correction value based on the result of the comparison so that the phase difference approaches the target phase difference, and in the step of generating the set period, the set period is further generated based on the correction value.

[0139] According to this, if the phase difference between the phase of the input synchronizing signal and the phase of the output synchronizing signal varies, it is necessary to temporarily store an image corresponding to the variation, which increases the capacity of the frame memory. Therefore, by maintaining the phase difference at the target phase difference, the required frame memory capacity can be reduced. For example, the frame memory can be configured with only one bank.

[0140] The present disclosure can be applied to a system that displays on a display an image from a camera that dynamically changes the output vertical synchronization signal.

[0141] 1, 2, 2a Video display system 10, 10a, 10b Correction value control unit 11 Period measurement unit 12 1 / N calculation unit 13, 19a, 19b Selection unit 14 Phase measurement unit 15, 18a, 18b, 18c Comparison unit 16 Correction value generation unit 16a Multiplier 17 Adder 20 PLL 30 Pixel counter 40 Line counter 50 Synchronization generation unit 100, 100a Synchronization signal processing device 110 Video input unit 120 Memory 130 Video output unit 200 Camera 300 LCD panel

Claims

1. A synchronization signal processing device comprising: a correction value control unit; and a synchronization generation unit, wherein the correction value control unit acquires an input synchronization signal which is a vertical synchronization signal of an input video; determines whether the period of the input synchronization signal is equal to or greater than a predetermined threshold which is greater than a period corresponding to a refresh rate of a display on which an output video is displayed; if it is determined that the period of the input synchronization signal is equal to or greater than the predetermined threshold, generates a set period based on a period which is 1 / N times (N is an integer of 2 or greater) of the input synchronization signal; if it is determined that the period of the input synchronization signal is less than the predetermined threshold, generates the set period based on the period of the input synchronization signal; and the synchronization generation unit generates an output synchronization signal which is a vertical synchronization signal of the output video based on the set period.

2. The synchronization signal processing device according to claim 1, wherein the correction value control unit compares the phase difference between the phase of the input synchronization signal and the phase of the output synchronization signal with a target phase difference, generates a correction value based on the result of the comparison such that the phase difference approaches the target phase difference, and further generates the set period based on the correction value.

3. The synchronous signal processing device according to claim 2, further comprising: a pixel counter; and a synchronization control unit that generates a pixel clock for said pixel counter, said synchronization control unit generating said pixel clock based on said set period.

4. A synchronization signal processing device according to claim 2, further comprising: a pixel counter; and a synchronization control unit that generates a pixel clock for said pixel counter, wherein said correction value control unit outputs a horizontal synchronization period generated based on said set period to said pixel counter, and said pixel counter counts the number of pixels based on said horizontal synchronization period.

5. The synchronous signal processing device according to any one of claims 2 to 4, wherein the correction value control unit generates the correction value by multiplying a difference between the phase difference and the target phase difference by a correction gain.

6. A synchronization signal processing device according to any one of claims 1 to 5, wherein the correction value control unit determines whether the input synchronization signal is abnormal, and if it determines that the input synchronization signal is abnormal, performs processing to set the set period to a constant period.

7. The synchronization signal processing device according to claim 6, wherein the correction value control unit determines whether the input synchronization signal is abnormal by determining whether the period of the input synchronization signal is equal to or greater than a first period that is greater than the predetermined threshold value, and if it determines that the period of the input synchronization signal is equal to or greater than the first period, it sets the set period to a predetermined period.

8. The synchronization signal processing device according to claim 7, wherein the correction value control unit determines whether to ignore the input synchronization signal when the period of the input synchronization signal becomes equal to or greater than the first period and then becomes less than the first period.

9. The synchronization signal processing device according to claim 6, wherein the correction value control unit determines whether the input synchronization signal is abnormal by determining whether the period of the input synchronization signal is equal to or shorter than a second period that is shorter than a period corresponding to a refresh rate of the display, and ignores the input synchronization signal if it determines that the period of the input synchronization signal is equal to or shorter than the second period.

10. The synchronization signal processing device according to any one of claims 6 to 9, wherein the correction value control unit notifies an external device of the abnormal state when it determines that the input synchronization signal is abnormal.

11. A video display system comprising: a synchronization signal processing device according to any one of claims 1 to 10; a video input section to which the input video is input; and a video output section to which the output video is output.

12. A synchronization signal processing method executed by a synchronization signal processing device, comprising the steps of: acquiring an input synchronization signal which is a vertical synchronization signal of an input video; determining whether the period of the input synchronization signal is equal to or greater than a predetermined threshold which is greater than a period corresponding to a refresh rate of a display on which an output video is displayed; generating a set period based on a period that is 1 / N times (N is an integer of 2 or greater) of the input synchronization signal if it is determined that the period of the input synchronization signal is equal to or greater than the predetermined threshold; and generating the set period based on the period of the input synchronization signal if it is determined that the period of the input synchronization signal is less than the predetermined threshold; and generating an output synchronization signal which is a vertical synchronization signal of the output video based on the set period.

13. The synchronization signal processing method according to claim 12, further comprising the step of comparing the phase difference between the phase of the input synchronization signal and the phase of the output synchronization signal with a target phase difference, and generating a correction value based on the result of the comparison such that the phase difference approaches the target phase difference, and in the step of generating the set period, the set period is further generated based on the correction value.

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