Semiconductor package

Abstract

The present invention provides a semiconductor package in which a crack is less likely to occur in a substrate after a thermal cycle test, even if the size of the semiconductor package is increased. This semiconductor package specifically comprises: a printed wiring board that includes a resin layer wherein the ratio (Z / X) of the thermal expansion coefficient Z in the thickness direction to the thermal expansion coefficient X in the plane direction is 1.6 or less; and a semiconductor element.

Description

Semiconductor Package

[0001] The present disclosure relates to semiconductor packages.

[0002] As demands for higher performance in electronic devices continue, the density of electronic components incorporated into electronic devices is becoming increasingly higher. Under these circumstances, the transition from the current FC-BGA (Flip Chip-Ball Grid Array) to next-generation 2.xD or 3D packages will enable the integration of multiple semiconductor chips, achieving even higher integration. In this case, the semiconductor chip itself, its wiring, and the spacing between terminals become finer, while the size of the semiconductor package increases. As the size of the semiconductor package increases, the substrate becomes more susceptible to warping due to changes in environmental temperature, etc. Warping of the substrate can lead to the problem of cracks. One conventional method for reducing substrate warpage is to bring the thermal expansion coefficient of the substrate closer to that of the silicon chip (see, for example, Patent Document 1).

[0003] JP 2015-189834 A

[0004] As a result of intensive research by the present inventors, it was found that when the size of a semiconductor package increases, it is difficult to effectively suppress the occurrence of cracks in the substrate after a change in environmental temperature by using a method of making the thermal expansion coefficient of the substrate closer to that of a silicon chip, and that there is room for further improvement. Therefore, there is a strong demand for the development of a semiconductor package in which cracks are less likely to occur in the substrate even when the size of the semiconductor package increases.

[0005] In view of the current situation, an object of the present disclosure is to provide a semiconductor package in which cracks are unlikely to occur in the substrate after a thermal cycle test, even if the size of the semiconductor package increases.

[0006] The present inventors have conducted extensive research to solve the above-mentioned problems and have found that the problems can be solved by the present embodiment described below. This embodiment includes the following items [1] to

[11] . [1] A semiconductor package comprising a printed wiring board including a resin layer having a ratio (Z / X) of a thermal expansion coefficient Z in the thickness direction to a thermal expansion coefficient X in the plane direction of 1.6 or less, and a semiconductor element. [2] The semiconductor package according to the above item [1], in which Z / X is 1.4 or less. [3] The semiconductor package according to the above item [1] or [2], in which Z / X is 1.2 or less. [4] The semiconductor package according to any one of the above items [1] to [3], in which the printed wiring board has a core layer containing a fiber base material inside the resin layer. [5] The semiconductor package according to the above item [4], in which the printed wiring board further includes a buildup layer. [6] The semiconductor package according to the above item [5], in which the total thickness of the core layer is 500 to 3,600 μm and the total thickness of the buildup layer is 20 to 350 μm. [7] The semiconductor package according to any one of [1] to [6] above, wherein the thermal expansion coefficient X in the planar direction is 1 to 100 ppm / °C. [8] The semiconductor package according to any one of [1] to [7] above, wherein the thermal expansion coefficient X in the planar direction is 10 to 30 ppm / °C. [9] The semiconductor package according to any one of [1] to [8] above, wherein the thermal expansion coefficient Z in the thickness direction is 100 ppm / °C or less.

[10] The semiconductor package according to any one of [1] to [9] above, wherein the thermal expansion coefficient Z in the thickness direction is 40 ppm / °C or less.

[11] The semiconductor package according to any one of [1] to

[10] above, wherein the size is 20 to 270 mm in length x 20 to 270 mm in width.

[0007] According to the present disclosure, it is possible to provide a semiconductor package in which cracks are unlikely to occur in the substrate after a thermal cycle test, even if the size of the semiconductor package increases.

[0008] 1 is a perspective view of an example of a resin layer included in a semiconductor package according to an embodiment of the present invention, and FIG. 2 is a schematic view for explaining a mechanism by which cracks occur in a resin layer, and FIG. 3 is a perspective view for explaining an observation position by an optical microscope during a thermal cycle test in Examples.

[0009] In the numerical ranges described in this disclosure, the upper or lower limit of the numerical range may be replaced with the values ​​shown in the examples. Furthermore, the lower and upper limits of a numerical range can be arbitrarily combined with the lower or upper limit of another numerical range. In the expression "AA to BB," the numerical values ​​AA and BB at both ends are included as the lower and upper limits, respectively, within the numerical range. In this disclosure, for example, the expression "10 or more" means 10 and a value greater than 10, and this also applies when the numerical values ​​are different. Furthermore, for example, the expression "10 or less" means a value less than 10 and a value greater than 10, and this also applies when the numerical values ​​are different.

[0010] Unless otherwise specified, each component and material exemplified in this disclosure may be used alone or in combination of two or more. In this disclosure, "resin component" refers to the solid content excluding the inorganic filler described below. In this disclosure, "solid content" refers to components other than the solvent, and components that are liquid at 25°C are also considered solid content. In this disclosure, when the term "layer" is used, such as a core layer and a build-up layer, this term includes not only solid layers, but also layers that are not solid but are at least partially island-shaped, have holes, and have unclear interfaces with adjacent layers. The solid layer refers to a sheet-like layer that has not been particularly processed. This embodiment also includes any combination of the items described in this disclosure.

[0011] In the present disclosure, the weight average molecular weight is a value measured in terms of polystyrene by gel permeation chromatography (GPC) using tetrahydrofuran as an eluent.

[0012] [Semiconductor Package] The semiconductor package of this embodiment includes a printed wiring board including a resin layer having a ratio (Z / X) of the thermal expansion coefficient Z in the thickness direction to the thermal expansion coefficient X in the plane direction of 1.6 or less, and a semiconductor element. An example of the "resin layer having a ratio (Z / X) of the thermal expansion coefficient Z in the thickness direction to the thermal expansion coefficient X in the plane direction of 1.6 or less" included in the semiconductor package of this embodiment is shown in Figure 1. For the resin layer 1, the thermal expansion coefficient X in the plane direction and the thermal expansion coefficient Z in the thickness direction were measured by using a 5 mm square resin layer as a test piece, mounting the test piece in a thermomechanical measurement device, and performing two consecutive thermomechanical analyses using a compression method under conditions of a temperature range of 30 to 260°C, a load of 0.4 N, and a heating rate of 10°C / min. The average thermal expansion coefficient from 30 to 120°C in the second measurement was used. More specifically, the method described in the Examples was adopted. Here, the printed wiring board preferably has a core layer containing a fiber substrate within the resin layer. In the core layer, the thermal expansion coefficient X and the thermal expansion coefficient Z of the resin layer are measured without including the fiber substrate. For example, a resin powder obtained by scraping the resin layer from the core layer is compression-molded at a temperature of 100 to 300°C (preferably 200 to 300°C) for 10 to 300 minutes under a pressure of 0.5 to 5 MPa to prepare a 5 mm square test piece, and the thermal expansion coefficient X and the thermal expansion coefficient Z can be measured using the test piece.

[0013] The thermal expansion coefficient X in the plane direction is preferably 1 to 100 ppm / °C, more preferably 5 to 50 ppm / °C, and even more preferably 10 to 30 ppm / °C. When the thermal expansion coefficient X in the plane direction is equal to or greater than the lower limit, the difference with the thermal expansion coefficient of the metal layer or wiring can be reduced, which tends to result in a crack suppression effect. When the thermal expansion coefficient X in the plane direction is equal to or less than the upper limit, which tends to result in a semiconductor package warping being suppressed. The thermal expansion coefficient Z in the thickness direction is preferably 100 ppm / °C or less, more preferably 50 ppm / °C or less, and even more preferably 40 ppm / °C or less. There is no particular restriction on the lower limit of the thermal expansion coefficient Z in the thickness direction, and it may be 5 ppm / °C or more, or 10 ppm / °C or more. When the thermal expansion coefficient Z in the thickness direction is equal to or less than the upper limit, the Z / X ratio can be reduced, which tends to result in a crack suppression effect.

[0014] In the resin layer, the ratio (Z / X) of the thermal expansion coefficient Z in the thickness direction to the thermal expansion coefficient X in the plane direction is 1.6 or less, thereby effectively suppressing the occurrence of cracks. The reason for this effect is considered as follows. As shown in FIG. 2 , when the thermal expansion coefficient X in the plane direction of the resin layer is small, the thermal contraction of the resin layer (core layer) during cooling is small, which increases the difference between the thermal contraction of the metal layer or wiring adjacent to the resin layer (core layer). This causes a force that warps the resin layer (core layer) in a direction that moves the top and bottom away from each other (i.e., in the thickness direction), resulting in accumulation of stress in the thickness direction within the core layer. Stress in the thickness direction can promote cleavage and cause cracks, but a small thermal expansion coefficient Z in the thickness direction reduces the amount of thickness-direction contraction during cooling, thereby alleviating the stress, thereby effectively suppressing the occurrence of cracks. In other words, it is preferable for the thermal expansion coefficient Z to be as small as possible relative to the thermal expansion coefficient X, and the equation expressing this relationship is Z / X≦1.6. From the viewpoint of the effect of suppressing crack generation, the Z / X ratio is preferably 1.5 or less, more preferably 1.4 or less, even more preferably 1.3 or less, and particularly preferably 1.2 or less. There is no particular restriction on the lower limit, but the Z / X ratio is usually 0.8 or more, and may be 0.9 or more, or may be 1.0 or more.

[0015] The core layer may have one fiber substrate, two or more fiber substrates, 2 to 30 fiber substrates, 5 to 30 fiber substrates, or 8 to 30 fiber substrates. Known fiber substrates used in various electrical insulating laminates are used as the fiber substrate. The fiber substrate is preferably a sheet-like fiber substrate. Examples of the material for the fiber substrate include inorganic fibers such as E-glass, D-glass, S-glass, and Q-glass (quartz glass); organic fibers such as polyimide, polyester, and tetrafluoroethylene; and mixtures thereof. These fiber substrates may be in the form of woven fabric, nonwoven fabric, roving, chopped strand mat, surfacing mat, or the like.

[0016] The resin layer and the core layer may be formed from a known thermosetting resin composition. For example, a core layer having a resin layer and a fiber substrate can be formed by using a prepreg obtained by impregnating a fiber substrate with the thermosetting resin composition and then drying it. From the viewpoint of easily satisfying the Z / X ratio, the thermosetting resin composition preferably contains a thermosetting resin; an inorganic filler; a curing accelerator; and the like. The thermosetting resin composition may further contain an acrylic polymer or a flame retardant.

[0017] Examples of the thermosetting resin include epoxy resins, phenolic resins, maleimide resins, modified polyphenylene ether resins, cyanate resins, isocyanate resins, benzoxazine resins, oxetane resins, amino resins (e.g., melamine resins), unsaturated polyester resins, allyl resins, dicyclopentadiene resins, and silicone resins. From the viewpoint of easily satisfying the Z / X ratio, the thermosetting resin preferably contains one or more resins selected from the group consisting of epoxy resins and maleimide resins. Furthermore, from the viewpoint of easily satisfying the Z / X ratio, the epoxy resin preferably contains a naphthalene skeleton-containing epoxy resin. The thermosetting resins may be used alone or in combination of two or more.

[0018] From the viewpoint of easily satisfying the Z / X ratio, the maleimide resin is preferably a "modified maleimide resin" obtained by reacting a maleimide resin with one or more compounds selected from the group consisting of monoamine compounds and diamine compounds. Examples of the monoamine compound include monoamine compounds having an acidic substituent, such as aminophenol, o-aminobenzoic acid, m-aminobenzoic acid, aminobenzoic acid, aminobenzenesulfonic acid, 3,5-dihydroxyaniline, and 3,5-dicarboxyaniline. Examples of the diamine compound include aromatic diamines in which an amino group is bonded to an aromatic hydrocarbon group, such as 4,4'-diaminodiphenylmethane, 4,4'-diaminodiphenylethane, 4,4'-diaminodiphenylpropane, 2,2'-bis(4,4'-diaminodiphenyl)propane, 3,3'-dimethyl-4,4'-diaminodiphenylmethane, 3,3'-diethyl-4,4'-diaminodiphenylmethane, 3,3'-dimethyl-4,4'-diaminodiphenylethane, 3,3'-diethyl-4,4'-diaminodiphenylethane, 4,4'-diaminodiphenylether, 4,4'-diaminodiphenylthioether, 3,3'-dihydroxy-4,4'-diaminodiphenylmethane, and 2,2',6,6'-tetramethyl-4,4'-diaminodiphenylmethane; and siloxane diamines. The maleimide resins may be used alone or in combination of two or more.

[0019] The weight-average molecular weight (Mw) of the acrylic polymer is not particularly limited, but may be 2,000,000 or less, 50,000 to 1,500,000, or 100,000 to 1,300,000. When a thermosetting resin composition contains a component (e.g., the acrylic polymer) having such a large Mw (e.g., 50,000 or more), cracks tend to occur in the substrate after a thermal cycle test. In this case, the effect of the present invention of suppressing cracking tends to be even more pronounced. The weight-average molecular weight (Mw) of the epoxy resin is not particularly limited, but may be 200 to 1,000, 250 to 950, or 300 to 900. The epoxy equivalent of the epoxy resin is preferably 50 to 5,000 g / eq, more preferably 60 to 2,000 g / eq, even more preferably 70 to 1,000 g / eq, and particularly preferably 80 to 500 g / eq. The epoxy equivalent can be measured according to the method specified in JIS K7236 (2009).

[0020] The inorganic filler is not particularly limited, but examples thereof include silica, alumina, titanium oxide, mica, beryllia, barium titanate, potassium titanate, strontium titanate, calcium titanate, aluminum carbonate, magnesium hydroxide, aluminum hydroxide, aluminum silicate, calcium carbonate, calcium silicate, magnesium silicate, silicon nitride, boron nitride, clay (calcined clay, etc.), molybdic acid compounds (zinc molybdate, etc.), talc, aluminum borate, silicon carbide, etc. One type of the inorganic filler may be used alone, or two or more types may be used in combination.

[0021] Examples of the curing accelerator include amine-based curing accelerators, imidazole-based curing accelerators, phosphorus-based curing accelerators, organometallic salts, acidic catalysts, and organic peroxides. Here, imidazole-based curing accelerators are not classified as amine-based curing accelerators. The curing accelerator preferably includes at least one selected from the group consisting of imidazole-based curing accelerators and organic peroxides, and more preferably includes an imidazole-based curing accelerator. The curing accelerators may be used alone or in combination of two or more.

[0022] When the thermosetting resin composition contains the thermosetting resin, the content (total amount) of the thermosetting resin may be 50 to 99 mass%, 70 to 99 mass%, 80 to 99 mass%, 80 to 97 mass%, or 85 to 95 mass% based on the resin components. When the content of the thermosetting resin is within the above range, the Z / X ratio tends to be more easily satisfied. Among the thermosetting resins, the content of the maleimide resin may be 50 to 85 mass%, 55 to 85 mass%, 65 to 80 mass%, or 65 to 75 mass% based on the resin components. Furthermore, among the thermosetting resins, the content of the epoxy resin may be 1 to 25 mass%, 3 to 20 mass%, or 5 to 15 mass%. When the thermosetting resin composition contains the acrylic polymer, the content of the acrylic polymer may be 1 to 50 mass%, 3 to 40 mass%, 5 to 30 mass%, 5 to 20 mass%, or 5 to 15 mass%, based on the resin components. When the content of the acrylic polymer is within the above range, the Z / X ratio tends to be easily satisfied. When the thermosetting resin composition contains the curing accelerator, the content of the curing accelerator may be 0.01 to 5 mass%, 0.05 to 3 mass%, 0.1 to 3 mass%, or 0.1 to 1.5 mass%, based on the resin components. When the thermosetting resin composition contains the inorganic filler, the content of the inorganic filler may be 50 to 300 parts by mass, 80 to 230 parts by mass, 100 to 200 parts by mass, 120 to 180 parts by mass, or 130 to 170 parts by mass, relative to 100 parts by mass of the resin component.

[0023] The thickness of the fiber substrate is not particularly limited, but may be 1 to 120 μm, 1 to 100 μm, 3 to 70 μm, 5 to 55 μm, 15 to 55 μm, or 25 to 55 μm.

[0024] The printed wiring board may further include a buildup layer. Typically, one or more buildup layers are present above and below the core layer. There may be 2 to 15 buildup layers above and below the core layer, 3 to 12 buildup layers, 3 to 10 buildup layers, or 4 to 8 buildup layers above and below the core layer. A metal layer or wiring may be formed between the core layer and the buildup layer. In the case of a buildup layer in which two or more layers overlap, a metal layer or wiring may be formed between the buildup layers. The metal for the metal layer and wiring is not particularly limited, but from the viewpoint of electrical conductivity, it may be copper, gold, silver, nickel, platinum, molybdenum, ruthenium, aluminum, tungsten, iron, titanium, chromium, or an alloy containing one or more of these metal elements. Copper and aluminum are preferred, and copper is more preferred.

[0025] The thickness of the entire core layer is not particularly limited and may be 500 to 3,600 μm, 700 to 2,200 μm, 900 to 1,700 μm, or 900 to 1,500 μm. The thickness of the entire build-up layer is not particularly limited and may be 20 to 350 μm, 50 to 300 μm, 70 to 250 μm, 100 to 250 μm, or 130 to 230 μm.

[0026] The printed wiring board may have a solder resist layer as an outermost layer. The solder resist layer may be formed from a known photosensitive resin composition. The thickness of the solder resist layer is not particularly limited, and may be 10 to 100 μm, 15 to 80 μm, 15 to 60 μm, or 15 to 40 μm.

[0027] The Z / X ratio tends to be easily adjusted to 1.6 or less (preferably within the above-mentioned numerical range) by adjusting the molding conditions of the core layer. For example, the Z / X ratio tends to be reduced by lowering the heating temperature during compression molding. The compression molding conditions are not particularly limited, but can be, for example, a temperature of 100 to 300°C (preferably 180 to 300°C) and a pressure of 1.0 to 5 MPa (preferably 1.5 to 5 MPa), and are preferably adjusted within this range. The molding time is not particularly limited, but is preferably 10 to 300 minutes.

[0028] In the semiconductor package of this embodiment, the printed wiring board and the semiconductor element are connected by solder bumps or the like. The space between the semiconductor element and the printed wiring board is preferably sealed with an underfill material. Examples of the semiconductor element include a semiconductor chip and a memory. The size of the semiconductor package of this embodiment is not particularly limited, and may be 20 to 270 mm long x 20 to 270 mm wide, 100 to 270 mm long x 100 to 270 mm wide, or 20 to 100 mm long x 20 to 100 mm wide.

[0029] The present embodiment will be specifically described below with reference to examples, although the present embodiment is not limited to the following examples.

[0030] (1. Method for Measuring Thermal Expansion Coefficient and Method for Calculating Z / X) The prepreg obtained in each example was kneaded and collected to obtain a B-stage resin powder, which was compression-molded at 250°C and 1 MPa for 80 minutes to produce a C-stage laminate, from which a 5 mm square test piece was cut. Using the test piece, thermomechanical analysis was performed using a thermomechanical measuring apparatus (TMA) [manufactured by TA Instruments Japan Co., Ltd., model number Q400] by the tensile method. After mounting the test piece in the apparatus, measurements were performed twice using the compression method under conditions of a temperature range of 30 to 260°C, a load of 0.4 N, and a heating rate of 10°C / min. The average linear thermal expansion coefficient from 30°C to 260°C in the second measurement was calculated. Note that Z / X was calculated by defining the thermal expansion coefficient in the plane direction of the test piece as the thermal expansion coefficient X and the thermal expansion coefficient in the thickness direction of the test piece as the thermal expansion coefficient Z.

[0031] (2. Method for Calculating Crack Occurrence Rate) Twelve sheets of the prepreg obtained in each example (for core layer; total thickness 1,200 μm) were stacked together, and one sheet of copper foil (thickness 12 μm) was placed on top and bottom, followed by compression molding at 250° C. and 3 MPa to produce a copper-clad laminate. Next, a build-up film (manufactured by Ajinomoto Co., Inc., product name "GX92", thickness 30 μm; hereinafter, sometimes referred to as "Bu") (for build-up layer) and copper foil (thickness 18 μm) were used on the top and bottom of the obtained copper-clad laminate to produce a printed wiring board substrate (60 mm × 60 mm rectangular in plan view, thickness 1.7 to 2.0 mm) having the following multilayer structure.

[0032] <Substrate structure> Copper foil / Bu / Bu / copper foil / Bu / Bu / copper foil / Bu / Bu / copper foil / Bu / Bu / copper foil / core layer / copper foil / Bu / Bu / copper foil / Bu / Bu / copper foil / Bu / Bu / copper foil / Bu / Bu / copper foil

[0033] Next, a silicon semiconductor chip (20 mm x 20 mm rectangular in plan view, 0.775 mm thick) was placed in the center of one surface of the printed wiring board substrate obtained above, with the circuit side facing downward, and the gap between the semiconductor chip and the substrate was sealed with a liquid sealant (Resonac Corporation, product name "CEL-C-3730 series") to obtain a semiconductor chip-mounted substrate for thermal cycle testing. The following thermal cycle test was carried out using this semiconductor chip-mounted substrate.

[0034] <Thermal Cycle Test> Five identical semiconductor chip-mounted substrates were prepared for the thermal cycle test. The five semiconductor chip-mounted substrates were subjected to a thermal cycle test in which heating and cooling were repeated under the following conditions: 5 minutes in a low-temperature chamber at -65°C, 5 minutes in a high-temperature chamber at 150°C, and a transfer time of 18 seconds between the low-temperature chamber and the high-temperature chamber. This test was performed for 500 cycles. The substrates were then removed, and predetermined positions on the substrates were observed with an optical microscope (magnification: 500x) to confirm the presence or absence of cracks. A perspective view illustrating the observation positions using the optical microscope is shown in Figure 3. The observation positions were eight positions on the substrate 1 shown in Figure 3, each of which was observed from two directions at the four corners of the substrate indicated by observation area 10 (hatched area). Each observation area was an area of ​​1,500 μm × 1,500 μm. The above eight locations were observed for each of the five substrates, and the ratio of locations where cracks were observed out of a total of 40 locations [number of locations where cracks were observed / 40 locations] was taken as the crack occurrence rate in the thermal cycle test.

[0035] Example 1 (Preparation of thermosetting resin composition) The components shown in Table 1 below were blended in the amounts shown, and the blended mixture was stirred and mixed in methyl ethyl ketone at room temperature (25°C) to produce a thermosetting resin composition with a solid content of 50 mass%. The numerical values ​​shown in the blended compositions in Table 1 below are in parts by mass.

[0036] The modified maleimide resin in Table 1 above is a modified maleimide resin obtained by adding 100 g of a siloxane modified at both ends with diamines (manufactured by Shin-Etsu Chemical Co., Ltd., product name: X-22-161A, amino group functional group equivalent: 800 g / mol) and 450 g of 2,2-bis[4-(4-maleimidophenoxy)phenyl]propane to 550 g of propylene glycol monomethyl ether, and then reacting them at 120° C. for 3 hours. The epoxy resin in Table 1 above is biphenylaralkyl epoxy resin "NC-3000" (manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent: 275 g / eq).

[0037] (Preparation of Prepreg) The thermosetting resin composition obtained by the above method was impregnated into glass cloth "T2118" (trade name, manufactured by Nitto Boseki Co., Ltd.), and then heated and dried at 120°C for 5 minutes to obtain a prepreg. Using the prepreg, test specimens and semiconductor chip mounting boards were prepared according to the above methods, and various evaluations were performed. The results are shown in Table 3.

[0038] Example 2 The prepreg described in Example 11 of WO 2012 / 099133 was prepared, and test specimens and semiconductor chip mounting substrates were produced using the prepreg according to the above-described methods, and each evaluation was performed. The results are shown in Table 3.

[0039] Example 3 The prepreg described in Example 7 of WO 2013 / 243676 was prepared, and test specimens and semiconductor chip mounting boards were produced using the prepreg according to the above-described methods, and each evaluation was performed. The results are shown in Table 3.

[0040] Comparative Example 1 (Preparation of Thermosetting Resin Composition) The components shown in Table 2 below were blended in the amounts shown, and the blended mixture was stirred and mixed in methyl ethyl ketone at room temperature (25°C) to produce a thermosetting resin composition with a solid content of 50 mass%. The numerical values ​​shown in the blended compositions in Table 2 below are in parts by mass.

[0041] The modified maleimide resin in Table 2 above is a modified maleimide resin obtained by adding 100 g of a siloxane modified at both ends with diamines (manufactured by Shin-Etsu Chemical Co., Ltd., product name: X-22-161A, amino group functional group equivalent: 800 g / mol) and 450 g of 2,2-bis[4-(4-maleimidophenoxy)phenyl]propane to 550 g of propylene glycol monomethyl ether, and then reacting them at 120° C. for 3 hours. The epoxy resin in Table 2 above is biphenylaralkyl epoxy resin "NC-3000" (manufactured by Nippon Kayaku Co., Ltd., epoxy equivalent: 275 g / eq).

[0042] (Preparation of Prepreg) The thermosetting resin composition obtained by the above method was impregnated into glass cloth "T2118" (trade name, manufactured by Nitto Boseki Co., Ltd.), and then heated and dried at 120°C for 5 minutes to obtain a prepreg. Using the prepreg, test specimens and semiconductor chip mounting boards were prepared according to the above methods, and various evaluations were performed. The results are shown in Table 3.

[0043] Comparative Example 2 (Preparation of Thermosetting Resin Composition) A thermosetting resin composition containing an epoxy resin, a silicone resin, spherical silica, and an organic solvent was prepared.

[0044] (Preparation of Prepreg) The thermosetting resin composition obtained by the above method was applied to a 0.1 mm thick glass cloth (manufactured by Nitto Boseki Co., Ltd.) and then heated and dried at 130°C for 5 minutes to prepare a prepreg containing approximately 50 mass% of the thermosetting resin composition. Test specimens and semiconductor chip mounting boards were prepared using the prepreg according to the above methods and evaluated. The results are shown in Table 3.

[0045]

[0046] As can be seen from Table 3, in the semiconductor packages (Examples 1 to 3) having a printed wiring board and a semiconductor element including a resin layer in which the ratio (Z / X) of the thermal expansion coefficient Z in the thickness direction to the thermal expansion coefficient X in the surface direction is 1.6 or less, the crack occurrence rate was significantly reduced.

[0047] REFERENCE SIGNS LIST 1 resin layer 2 printed wiring board substrate 10 observation area

Claims

1. A semiconductor package comprising a printed wiring board including a resin layer in which the ratio (Z / X) of the thermal expansion coefficient Z in the thickness direction to the thermal expansion coefficient X in the surface direction is 1.6 or less, and a semiconductor element.

2. The semiconductor package according to claim 1, wherein said Z / X is 1.4 or less.

3. The semiconductor package according to claim 1, wherein said Z / X is 1.2 or less.

4. The semiconductor package according to claim 1, wherein the printed wiring board has a core layer containing a fiber base material inside the resin layer.

5. The semiconductor package of claim 4, wherein said printed wiring board further comprises a build-up layer.

6. The semiconductor package according to claim 5, wherein the total thickness of said core layer is 500 to 3,600 μm, and the total thickness of said build-up layer is 20 to 350 μm.

7. The semiconductor package according to claim 1, wherein the thermal expansion coefficient X in the plane direction is 1 to 100 ppm / °C.

8. The semiconductor package according to claim 1, wherein the thermal expansion coefficient X in the plane direction is 10 to 30 ppm / °C.

9. The semiconductor package according to claim 1, wherein the thermal expansion coefficient Z in the thickness direction is 100 ppm / °C or less.

10. The semiconductor package according to claim 1, wherein the thermal expansion coefficient Z in the thickness direction is 40 ppm / °C or less.

11. The semiconductor package according to claim 1, having a size of 20 to 270 mm in length and 20 to 270 mm in width.

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