Crystal film, semiconductor device, and method for manufacturing laminated structure

Abstract

The present invention addresses the problem of providing a crystal film and a semiconductor device excellent in reliability. This crystal film contains a crystalline oxide semiconductor containing gallium. When the crystal film is observed using an optical microscope, the crystal film does not contain a black spot or a bright spot within a region of at least 1.0 mm2.

Description

Crystalline film, semiconductor device, and method for manufacturing laminated structure

[0001] The present disclosure relates to a method for manufacturing a crystalline film, a semiconductor device, and a laminated structure.

[0002] Patent Document 1 discloses a crystalline oxide semiconductor film containing a crystalline oxide semiconductor having a corundum structure as a main component, the crystalline oxide semiconductor film substantially not containing cracks within a 300 μm square area of ​​the film surface.

[0003] JP 2018-002544 A

[0004] An object of the present disclosure is to provide a semiconductor device with excellent reliability, and a crystal film and a layered structure useful for such a semiconductor device.

[0005] In order to solve the above problems, a crystalline film according to one embodiment of the present disclosure is a crystalline film including a crystalline oxide semiconductor containing gallium, and when the crystalline film is observed with an optical microscope, the crystalline film has a thickness of at least 1.0 mm. ２ The area does not contain any dark or bright spots.

[0006] In order to solve the above problems, a crystalline film according to one embodiment of the present disclosure is a crystalline film including a crystalline oxide semiconductor containing gallium, and the crystalline film does not include particulate matter containing amorphous solids and / or crystals at least in a cross section cut in the thickness direction.

[0007] In order to solve the above problems, a semiconductor device according to one embodiment of the present disclosure includes a semiconductor layer including a crystalline oxide semiconductor containing gallium and an electrode, and the semiconductor layer has a thickness of at least 1.0 mm when observed with an optical microscope. ２ The area does not contain any dark or bright spots.

[0008] In order to solve the above problem, a method for manufacturing a stacked structure according to one embodiment of the present disclosure includes heating a substrate, cleaning the heated substrate, and forming a crystalline film containing a crystalline oxide semiconductor containing gallium on the cleaned substrate via an intermediate layer or directly.

[0009] According to the present disclosure, it is possible to provide a semiconductor device with excellent reliability, or a crystalline film or a layered structure useful for such a semiconductor device.

[0010] FIG. 1 is a perspective view schematically showing a crystal film according to an embodiment. FIG. 2 is a plan view schematically showing a crystal film according to a reference example. FIG. 3 is a side view schematically showing a crystal film according to a reference example. FIG. 4 is a flowchart showing a method for manufacturing a crystal film. FIG. 5 is a cross-sectional view schematically showing a substrate. FIG. 6 is a cross-sectional view schematically showing a substrate having a groove formed thereon. FIG. 7 is a cross-sectional view schematically showing a stacked structure including a substrate and an intermediate layer formed on the substrate. FIG. 8 is a cross-sectional view schematically showing a stacked structure including a substrate, an intermediate layer, and a crystal film. FIG. 9 is a schematic view showing an example of a film formation apparatus. FIG. 10 is a schematic view showing another example of a film formation apparatus. FIG. 11 is a schematic view showing yet another example of a film formation apparatus. FIG. 12 is a flowchart showing a method for forming an intermediate layer. FIG. 13 is a cross-sectional view schematically showing an example of a semiconductor device. FIG. 14 is a plan view schematically showing a semiconductor device. FIG. 15 is a cross-sectional view schematically showing another example of a semiconductor device. FIG. 16 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 17 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 18 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 19 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 20 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 21 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 22 is a block diagram of an example power supply system. FIG. 23 is a block diagram of an example system device. FIG. 24 is a circuit diagram showing a power supply circuit of an example power supply device. FIG. 25 is a photograph of a cross-section of a crystalline film of an example taken using an SEM. FIG. 26 is a photograph of a cross-section of a crystalline film of a comparative example taken using an SEM. FIG. 27 is a photograph of a crystalline film taken using an optical microscope. FIG. 28 is a photograph of a crystalline film including black spots taken using an optical microscope. FIG. 29 is a photograph of a crystalline film including bright spots taken using an optical microscope. Figure 30 is a photograph of a crystalline film containing bright spots taken using a polarizing microscope. Figure 31 is a photograph of a cross section of a crystalline film containing grains taken using an SEM.

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the invention according to the claims is not limited to these embodiments. Furthermore, not all of the combinations of configurations described in the embodiments are necessarily required to solve the problems. Furthermore, each configuration of the present disclosure is described to the extent that it does not interfere with the solution of the problems of the present disclosure. Note that the same components are designated by the same reference numerals to avoid redundant description.

[0012] Additionally, as will be apparent to those skilled in the art, features shown in the drawings are not necessarily drawn to scale, even if not otherwise stated herein. It should also be noted that one feature of one embodiment may be used in another embodiment. Descriptions of well-known elements and processing techniques may be omitted so as not to unnecessarily obscure the embodiments of the present disclosure. The examples used herein are merely intended to aid in the understanding of the present disclosure and further enable those skilled in the art to practice the embodiments of the present disclosure. Therefore, the embodiments and examples herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the claims and applicable law.

[0013] Terms such as "first," "second," and the like are used to describe various elements used herein, but the elements are not limited by these terms. Terms such as first, second, and the like are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and a second element could be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any or all combinations of one or more of the listed items.

[0014] In this disclosure, the direction toward one side in the thickness direction of the crystal film will be described as "upper" and the direction toward the other side as "lower." Of the two main surfaces of a layer, substrate, or other member, the upper surface will be described as the upper surface, and the lower surface will be described as the lower surface. These "upper" and "lower" directions are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device. In this disclosure, viewing from above is referred to as a "planar view."

[0015] The terms used herein are intended to describe particular embodiments only and are not intended to limit the disclosure. As used herein, the terms "comprise" and "include" refer to the presence of stated elements but do not exclude the presence of one or more other elements.

[0016] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning that is consistent with the meaning in the context of this specification and the related art. Furthermore, unless defined herein, it should be understood that terms used herein should not be interpreted in an idealized or overly formal sense.

[0017] FIG. 1 is a perspective view schematically illustrating a crystal film 10 of this embodiment. The crystal film 10 includes a wide bandgap semiconductor. Therefore, the crystal film 10 is particularly useful for power devices. The crystal film 10 does not necessarily include a wide bandgap semiconductor. The crystal film 10 is included, for example, as a semiconductor film in a stacked structure or a semiconductor device. The stacked structure includes other layers in addition to the crystal film 10. The stacked structure may include multiple other layers in addition to the crystal film 10. Examples of the other layers include a substrate, a semiconductor layer, or a buffer layer. The semiconductor device is, for example, a diode or a transistor. The semiconductor device may include part or all of the stacked structure.

[0018] The crystalline film 10 is, for example, an epitaxially grown film. The crystalline film 10 may be a heteroepitaxially grown film or a homoepitaxially grown film. The crystalline film 10 may be, for example, circular or rectangular in plan view. The shape of the crystalline film 10 is not limited.

[0019] The crystalline film 10 includes a crystalline oxide semiconductor. The crystalline film 10 preferably includes a crystalline oxide semiconductor as a main component. In the present disclosure, "main component" means that the crystalline film 10 contains 50% or more of the crystalline oxide semiconductor in terms of atomic ratio relative to the whole. The crystalline film 10 may contain 70% or more, or 90% or more of the crystalline oxide semiconductor in terms of atomic ratio. The crystalline film 10 may be a crystalline oxide semiconductor. That is, the crystalline film 10 may contain 100% of the crystalline oxide semiconductor in terms of atomic ratio.

[0020] The crystalline oxide semiconductor contains gallium. Gallium may be a main component of all metal elements contained in the crystalline oxide semiconductor. That is, the atomic ratio of gallium to all metal elements contained in the crystalline oxide semiconductor may be 50% or more. The atomic ratio of gallium to all metal elements contained in the crystalline oxide semiconductor may be 70% or more, or 90% or more. Gallium may be the only metal element contained in the crystalline oxide semiconductor. The crystalline oxide semiconductor may contain, in addition to gallium, one or more metals selected from iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). The crystalline oxide semiconductor preferably contains, in addition to gallium, at least one metal selected from aluminum and indium. The crystalline oxide semiconductor is preferably a mixed crystal containing two or more metal oxides. The crystalline oxide semiconductor may contain, in addition to gallium, Ga ２ O ３ Or a mixed crystal thereof is preferred.

[0021] The crystalline oxide semiconductor may be single crystal or polycrystalline. The crystalline oxide semiconductor is preferably single crystal. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallium structure, a hexagonal crystal structure (e.g., an ε-type structure), an orthorhombic crystal structure (e.g., a κ-type structure), a cubic crystal structure, and a tetragonal crystal structure. The crystalline oxide semiconductor preferably has a corundum structure. The crystalline oxide semiconductor is preferably an α-Ga ２ O ３ Or, more preferably, it is a mixed crystal thereof.

[0022] The crystal film 10 may be either an n-type semiconductor layer or a p-type semiconductor layer. In this disclosure, the term "n-type semiconductor layer" includes a semiconductor layer used as an n-type semiconductor layer and a semiconductor layer used as an n+ type semiconductor layer. In this disclosure, the term "p-type semiconductor layer" includes a semiconductor layer used as a p-type semiconductor layer and a semiconductor layer used as a p+ type semiconductor layer.

[0023] The crystal film 10 may contain a dopant. The dopant may be a known one. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The content of the dopant in the composition of the crystal film 10 is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic % or less, and even more preferably 0.00001 atomic % to 10 atomic % or less. For example, the carrier concentration may be 1×10 １６ / cm ３ 1x10 or more ２２ / cm ３ The carrier concentration is 1×10 １６ / cm ３ It may be less than 1×10 ２２ / cm ３ The carrier concentration of the crystal film 10 may exceed 1×10 １７ / cm ３ The crystal film 10 may not contain a dopant.

[0024] 2 is a plan view schematically showing a crystal film 10A of a reference example, which is different from the crystal film 10 of the present embodiment. FIG. 3 is a side view schematically showing the crystal film 10A. The crystal film 10A of the reference example includes point defects 11 that are observed as black spots or bright spots when observed with an optical microscope. In contrast, the crystal film 10 of the present embodiment includes point defects 11 that are observed as black spots or bright spots with a size of at least 1.0 mm when observed with an optical microscope. ２The film does not contain point defects 11 in the region. Black spots are, for example, point defects observed with an optical microscope in bright field. Bright spots are, for example, point defects observed with an optical microscope in dark field or oblique illumination. Note that black spots or bright spots do not include extremely minute defects that cannot be observed with an optical microscope or cracks formed in the crystalline film 10. Black spots or bright spots are, for example, depressions or convex granular objects that appear on the main surface of the crystalline film 10, or granular objects contained within the crystalline film 10.

[0025] In the present disclosure, "at least 1.0 mm ２ "Does not contain black or bright spots in the region of 1.0 mm" means that when the crystal film 10 is observed from any direction using an optical microscope, the crystal film 10 does not contain at least one of black spots and bright spots. ２ For example, the crystal film 10 has a 1.0 mm area where at least one of black spots and bright spots is not included. ２ The crystal film 10 may have black or bright spots in other areas as long as it has the above-mentioned areas. ２ It is preferable that the crystalline film 10 is a film that does not include point defects 11 in the region. It is more preferable that the crystalline film 10 is a film that does not include any black spots or bright spots throughout the entire crystalline film 10.

[0026] The direction in which the crystal film 10 is observed with an optical microscope is, for example, the same direction as the thickness direction of the crystal film 10. The direction in which the crystal film 10 is observed with an optical microscope is not limited and may be a direction inclined relative to the thickness direction of the crystal film 10. The same applies to the observation of a semiconductor device with an optical microscope, as described below. When observing the crystal film 10 included in a stacked structure or a semiconductor device, if a portion of the crystal film 10 is hidden by an opaque member such as a substrate or an electrode, the crystal film 10 may be observed from a direction facing the surface with a large exposed area, or the opaque member may be removed to increase the exposed area of ​​the crystal film 10. For example, if a portion of the top surface of the crystal film 10 is hidden by an electrode, the crystal film 10 may be observed from below. It is preferable that the crystal film 10 included in a semiconductor device is a film that does not contain any black or bright spots throughout the entire crystal film 10 when observed with all opaque members removed.

[0027] In the present disclosure, a "region that does not contain black or bright spots" is a closed region. This region must not be one that has been intentionally selected so as not to contain black or bright spots. The shape of the region is not limited, and examples include a circle, an ellipse, a square, a rectangle other than a square, or a polygon other than a rectangle. The optical microscope may be a normal optical microscope that uses natural light to illuminate the sample, or a polarizing microscope that uses polarized light to illuminate the sample. In this case, the illumination method used may be, for example, incident illumination, oblique illumination, or ring illumination.

[0028] The crystal film 10 has a thickness of at least 1.0 mm when observed with an optical microscope. ２Preferably, the region does not contain any black or bright spots with a diameter of 1.0 μm or more, and more preferably does not contain any black or bright spots with a diameter of 0.5 μm or more. Here, "does not contain any black or bright spots with a diameter of 0.5 μm or more" means that the region does not contain any black or bright spots observable with an optical microscope, or that even if the region contains black or bright spots, the diameter of the black or bright spots is less than 0.5 μm. The same applies to a diameter of 1.0 μm. The "diameter" does not limit the shape of the point defect 11 to a strictly defined circle. Point defect 11 only needs to have a macroscopic point-like shape, and the microscopic shape of point defect 11 is not limited. The microscopic shape of the black or bright spot may be, for example, a circle, a polygon, or other complex shape. Furthermore, "diameter" may include, for example, the major axis, minor axis, unidirectional diameter, unidirectional equidistant diameter, unidirectional maximum width, biaxial mean diameter, or equivalent circle diameter of point defect 11. The same applies to the "diameter of the granules" described later. The crystalline film 10 is preferably a film that does not contain any black dots or bright dots with a diameter of 1.0 μm or more throughout the entire crystalline film 10, and more preferably a film that does not contain any black dots or bright dots with a diameter of 0.5 μm or more throughout the entire crystalline film 10.

[0029] The composition of the particulate matter appearing as black or bright spots may be the same as or different from the composition of the crystalline oxide semiconductor. For example, the particulate matter may contain gallium and / or aluminum. The particulate matter may be crystalline or amorphous. In the present disclosure, "the particulate matter is crystalline" includes both the particulate matter being single crystal and the particulate matter being polycrystalline. When the particulate matter is crystalline, the crystal structure of the particulate matter may be the same as or different from the crystal structure of the crystalline oxide semiconductor.

[0030] Preferably, the crystalline film 10 does not contain any particulate matter at least in a cross section cut in the thickness direction. Here, "a cross section cut in the thickness direction" can be rephrased as a cross section parallel to the thickness direction of the crystalline film 10. Particulate matter is a substance containing amorphous solids and / or crystals. In this disclosure, "not containing any particulate matter at least in a cross section cut in the thickness direction" means that any cross section cut in the thickness direction of the crystalline film 10 does not contain any particulate matter. Therefore, the crystalline film 10 may contain particulate matter in other cross sections as long as it has a cross section free of particulate matter. The cross section cut in the thickness direction of the crystalline film 10 is observed, for example, using an electron microscope. An example of the electron microscope is an SEM (scanning electron microscope). Particulate matter contained in the cross section of the crystalline film 10 includes, for example, particulate matter contained inside the crystalline film 10 as well as particulate matter appearing on the surface of the crystalline film 10. Particulate matter appearing on the surface of the crystalline film 10 may protrude from the surface of the crystalline film 10. The granular particles contained in the cross section of the crystal film 10 may be the same as or different from the granular particles that appear as black or bright spots when observed under an optical microscope. The crystal film 10 preferably does not contain granular particles with a diameter of 1.0 μm or more, and more preferably does not contain granular particles with a diameter of 0.5 μm or more, at least in a cross section cut in the thickness direction. If the crystal film 10 does not contain black or bright spots, it may or may not contain granular particles in any cross section cut in the thickness direction.

[0031] The stacked structure including the crystal film 10 or the semiconductor device including the crystal film 10 has a thickness of at least 1.0 mm when observed with an optical microscope. ２ In this case, it is preferable that the crystal film 10 does not contain any black or bright spots in the region of at least 1.0 mm. ２ and when there are no black or bright spots in the region of the semiconductor device or the laminated structure, and when there are at least 1.0 mm of elements (for example, electrodes, etc.) other than the crystal film 10 in the semiconductor device or the laminated structure. ２This includes both cases where there are no black dots or bright dots in the region. When the semiconductor device is observed with an optical microscope, it is preferable that there are no black dots or bright dots in the semiconductor device at positions that overlap with the electrodes. In this case, voltage is less likely to be applied to defective parts with black dots or bright dots, making it possible to make semiconductor device 100 less susceptible to malfunctions. It is also possible that there are no black dots or bright dots in positions that do not overlap with the electrodes in the semiconductor device. Of course, when the stacked structure or the semiconductor device is observed with an optical microscope, it is preferable that there are no black dots or bright dots in the entire stacked structure or the entire semiconductor device.

[0032] A semiconductor device including the crystalline film 10 preferably does not contain particulate matter containing amorphous solids and / or crystals at least in a cross section cut in the thickness direction of the crystalline film 10 .

[0033] (Method for manufacturing a crystalline film) Next, a method for manufacturing the crystalline film 10 and the laminated structure will be described. FIG. 4 is a flowchart showing an example of a method for manufacturing the crystalline film 10 and the laminated structure. FIGS. 5 to 8 are cross-sectional views sequentially illustrating the method for manufacturing the crystalline film 10 and the laminated structure. The crystalline film 10 is formed, for example, on an underlying substrate 20. The crystalline film 10 shown in FIG. 8 is a multi-layer film. Specifically, the crystalline film 10 is a two-layer film consisting of an n+ layer 12 and an n- layer 13. The crystalline film 10 may be a film of three or more layers, or may be a single-layer film.

[0034] The method for manufacturing the crystalline film 10 includes forming the crystalline film 10 on the substrate 20 (hereinafter, this step will be referred to as the "crystalline film forming step"). By forming the crystalline film 10 on the substrate 20 in this manner, a layered structure including the substrate 20 and the crystalline film 10 is formed. The method for manufacturing the crystalline film 10 may also be referred to as a method for manufacturing a layered structure. The layered structure may further include an intermediate layer 25 disposed between the substrate 20 and the crystalline film 10. In this disclosure, "forming the crystalline film 10 on the substrate 20" includes a case where the crystalline film 10 is formed directly on the substrate 20 and a case where the crystalline film 10 is formed on the substrate 20 via another layer such as the intermediate layer 25. The method for manufacturing the crystalline film 10 may further include preparing the substrate 20 (hereinafter, this step will be referred to as the "substrate preparation step"). The method for manufacturing the crystal film 10 may further include forming grooves 21 on the surface of the substrate 20 (hereinafter, this step will be referred to as the "groove forming step") and cleaning the surface of the substrate 20 on which the grooves 21 have been formed (hereinafter, this step will be referred to as the "first cleaning step"). The method for manufacturing the crystal film 10 may further include heating the substrate 20 before the crystal film forming step (hereinafter, this step will be referred to as the "preheating step") and cleaning the surface of the substrate 20 after the preheating step before the crystal film forming step (hereinafter, this step will be referred to as the "second cleaning step"). The method for manufacturing the crystal film 10 and the stacked structure may further include forming an intermediate layer on the substrate 20 before the crystal film forming step (hereinafter, this step will be referred to as the "intermediate layer forming step").

[0035] In the substrate preparation step, for example, a substrate 20 as shown in FIG. 5 is prepared. The substrate 20 is not particularly limited as long as it can support the crystal film 10. The substrate 20 may be an insulating substrate, a semiconductor substrate, or a conductive substrate. The substrate 20 may be a single crystal substrate or a polycrystalline substrate. The substrate 20 is, for example, a substrate containing a crystalline substance having a corundum structure as a main component. The substrate having a corundum structure is, for example, a sapphire substrate, an α-type gallium oxide substrate, or a Ga ２ O ３ and Al ２ O ３The α-type mixed crystal substrate is, for example, an α-type mixed crystal substrate containing Al ２ O ３ The sapphire substrate having a corundum structure may be, for example, a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, or an r-plane sapphire substrate. The substrate 20 may be a c-plane sapphire substrate or an α-Ga ２ O ３ Preferably it is a substrate.

[0036] The substrate 20 may or may not have an off-angle. The value of the off-angle is not particularly limited. For example, the off-angle is preferably 0.01° or more, and more preferably 0.2° or more. The off-angle is more preferably 0.2° or more and 12° or less. The substrate 20 is more preferably a c-plane sapphire substrate having an off-angle of 0.2° or more. The thickness of the substrate 20 is not particularly limited, but is preferably 10 μm or more and 20 mm or less, and more preferably 10 μm or more and 1000 μm or less.

[0037] The groove forming step is performed after the substrate preparation step. In the groove forming step, grooves 21 are formed in the surface of the substrate 20, for example, as shown in Fig. 6. The surface of the substrate 20 on which the grooves 21 are formed is the main surface of the substrate 20, and is the surface on which the intermediate layer 25 or the crystal film 10 will be formed later. The grooves 21 are formed, for example, by irradiating the surface of the substrate 20 with a laser.

[0038] The first cleaning step is performed after the groove formation step. In the first cleaning step, the surface of the substrate 20 on which the grooves 21 are formed is cleaned. The cleaning is performed, for example, by supplying a liquid to the grooves and the portions of the surface of the substrate 20 other than the grooves. The liquid is, for example, a cleaning liquid containing hydrofluoric acid or water. The cleaning liquid containing hydrofluoric acid is, for example, hydrofluoric acid, a hydrofluoric acid aqueous solution, or buffered hydrofluoric acid. Buffered hydrofluoric acid is preferable as the cleaning liquid containing hydrofluoric acid because it is easy to handle. The liquid is preferably sprayed onto the surface of the substrate 20. In this case, for example, a cleaning device is used that includes a nozzle that sprays the liquid onto the substrate 20 and a moving device that moves the nozzle, and that sprays the liquid from the nozzle onto the surface of the substrate 20 while moving the nozzle, thereby cleaning the entire surface of the substrate 20. The groove formation step and the first cleaning step may be omitted.

[0039] The preheating step is performed after the first cleaning step. In the preheating step, the substrate 20 is heated by a heating means (for example, the hot plate 39, the heater 43, or the heater 52b described later) to be maintained at a predetermined temperature for a certain period of time, and then cooled.

[0040] The second cleaning step is performed after the preheating step. In the second cleaning step, the substrate 20 after the preheating step, i.e., the substrate 20 that has been heated in the preheating step and then cooled, is cleaned. The cleaning is performed, for example, by supplying a liquid to the surface of the substrate 20. The liquid is, for example, water. The liquid is preferably sprayed onto the surface of the substrate 20. In this case, for example, a cleaning device is used that includes a nozzle that sprays the liquid onto the substrate 20 and a moving device that moves the nozzle, and that sprays the liquid from the nozzle onto the surface of the substrate 20 while moving the nozzle, thereby cleaning the entire surface of the substrate 20. Note that the preheating step and the second cleaning step may be omitted.

[0041] The intermediate layer forming process is performed after the second cleaning process. In the intermediate layer forming process, an intermediate layer 25 is formed on the substrate 20 as shown in FIG. 7 . While the intermediate layer 25 is shown flat in FIG. 7 for ease of understanding, the intermediate layer 25 may have a shape that conforms to both the portions of the upper surface of the substrate 20 where the grooves 21 are not formed and the portions where the grooves 21 are formed. In this case, a portion of the intermediate layer 25 extends into the grooves 21. The same applies to FIG. 8 . The intermediate layer 25 is, for example, a buffer layer or a stress relaxation layer. The buffer layer is not particularly limited, but preferably contains a metal oxide, and more preferably contains a metal oxide as a main component. Examples of metal oxides include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium. The metal oxide preferably contains one or more elements selected from indium, aluminum, and gallium, more preferably contains at least indium and / or gallium, and most preferably contains at least gallium. The buffer layer preferably has the same crystalline structure as the crystalline film. Specifically, the crystalline structure of the buffer layer is preferably a corundum structure or a β-gallium structure, and more preferably a corundum structure. The stress relaxation layer is, for example, an ELO mask layer. If the preheating step and the second cleaning step are omitted, the intermediate layer formation step is performed after the first cleaning step. Details of the intermediate layer formation step will be described later.

[0042] The crystalline film forming step is performed after the intermediate layer forming step. In the crystalline film forming step, the crystalline film 10 is formed on the intermediate layer 25. The means for forming the crystalline film 10 is not particularly limited and may be a known means. The crystalline film 10 is formed, for example, by epitaxial crystal growth. Examples of methods for forming the crystalline film 10 include CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MOVPE (Metalorganic Vapor-phase Epitaxy), Mist CVD, Mist Epitaxy, MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), and pulse growth. The method for forming the crystalline film is preferably Mist CVD, Mist Epitaxy, or HVPE. The crystal film formation process using the mist CVD method or the mist epitaxy method, and the crystal film formation process using the HVPE method will be described below in order.

[0043] When the crystalline film 10 is formed by the mist CVD method or the mist epitaxy method, the crystalline film formation process includes, for example, atomizing a raw material solution containing a metal to generate mist or atomized droplets consisting of droplets (hereinafter, this process will be referred to as the "atomization process"), and transporting the obtained atomized droplets to the vicinity of the substrate 20 by a carrier gas and reacting the atomized droplets to form the crystalline film 10 (film formation process).

[0044] The raw material solution used in the atomization step contains the metal contained in the crystal film 10. The raw material solution may contain an inorganic material or an organic material.

[0045] The source solution can be preferably a solution in which the metal contained in the crystal film 10 is dissolved or dispersed in an organic solvent or water in the form of a complex or salt. Examples of the complex include an acetylacetonate complex, a carbonyl complex, an ammine complex, and a hydride complex. Examples of the salt include an organic metal salt (e.g., a metal acetate, a metal oxalate, a metal citrate, etc.), a metal sulfide salt, a metal nitrate salt, a metal phosphate salt, or a metal halide salt (e.g., a metal chloride salt, a metal bromide salt, a metal iodide salt, etc.).

[0046] The solvent for the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. The solvent preferably contains water.

[0047] The raw material solution may contain additives such as hydrohalic acid or an oxidizing agent. The hydrohalic acid may be, for example, hydrobromic acid, hydrochloric acid, or hydroiodic acid. The oxidizing agent may be, for example, hydrogen peroxide (H ２ O ２ ), sodium peroxide (Na ２ O ２ ), barium peroxide (BaO ２ ) or benzoyl peroxide (C ６ H ５ CO) ２ O ２ The raw material solution may contain the above-mentioned dopant.

[0048] In the atomization process, a raw material solution containing the metal contained in the crystal film 10 is prepared, and the prepared raw material solution is atomized. As a result, atomized droplets are suspended. The atomization means for atomizing the raw material solution is not particularly limited and may be a known atomization means. The atomization means is preferably a means for atomizing the raw material solution using ultrasonic vibrations. The atomized droplets generated in the atomization process are suspended in the air, and are preferably droplets that float in space with an initial velocity of zero and can be transported as a gas, rather than being sprayed like a spray, for example. The size of the atomized droplets is not particularly limited and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 1 μm to 10 μm.

[0049] In the film formation process, the atomized droplets are transported to the substrate 20 by a carrier gas. The type of carrier gas is not particularly limited. Examples of the carrier gas include oxygen, ozone, an inert gas (e.g., nitrogen or argon), or a reducing gas (e.g., hydrogen gas or forming gas). The type of carrier gas may be one or more. A dilution gas (e.g., a 10-fold dilution gas) with a different carrier gas concentration may also be used as a second carrier gas. The number of carrier gas supply points may be two or more, rather than just one. The flow rates of the carrier gas and the dilution gas are not particularly limited, but are preferably 1.0 LPM or less, and more preferably 0.1 LPM or more and 1.0 LPM or less.

[0050] In the film formation process, atomized droplets supplied by a carrier gas react on a substrate 20 placed in a film formation chamber, forming a crystal film 10 on the substrate 20. The reaction is not particularly limited as long as it forms a film from the atomized droplets, but a thermal reaction is preferred. The thermal reaction is not particularly limited as long as the atomized droplets react due to heat, and the reaction conditions are not particularly limited. The thermal reaction is carried out while the temperature in the film formation chamber is maintained at a predetermined temperature by a heating means, such as a hot plate 39, heater 43, or heater 52b, which will be described later. Hereinafter, this predetermined temperature is referred to as the film formation temperature. The film formation temperature may also be referred to as the temperature of the substrate 20 during the thermal reaction. The film formation temperature is typically a temperature above the evaporation temperature of the solvent in the raw material solution, but is preferably relatively low, specifically, a temperature of 650°C or less. The thermal reaction may be carried out under any of the following conditions: vacuum, non-oxygen atmosphere, reducing gas atmosphere, and oxygen atmosphere. The thermal reaction may also be carried out under atmospheric pressure, pressurized pressure, or reduced pressure. The thermal reaction is preferably carried out under atmospheric pressure, since this makes it easier to calculate the evaporation temperature and simplifies the equipment, etc. The thickness of the crystal film 10 formed in the film formation process can be set by adjusting the film formation time.

[0051] An example of a film forming apparatus used in the crystal film formation process will be described below. Figure 9 is a schematic diagram showing an example of a film forming apparatus 30. The film forming apparatus 30 includes a carrier gas source 32a for supplying a carrier gas, a flow rate control valve 33a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 32a, a carrier gas source 32b for supplying a carrier gas (diluted), i.e., a diluted carrier gas, a flow rate control valve 33b for adjusting the flow rate of the carrier gas (diluted) delivered from the carrier gas source 32b, an atomized droplet generating source 34 containing a raw material solution 34a, a container 35 containing water 35a, an ultrasonic vibrator 36 attached to the bottom of the container 35, a film forming chamber 37, a supply pipe 38 connecting the atomized droplet generating source 34 and the film forming chamber 37, and a hot plate (heater) 39 installed in the film forming chamber 37. The film forming chamber 37 is provided with an exhaust port 37a for discharging the atomized droplets and exhaust gas after the reaction.

[0052] The substrate 20 is placed on the hot plate 39. The raw material solution 34a is contained in the atomized droplet generating source 34. In this state, the hot plate 39 is activated, and the temperature inside the film formation chamber 37 is increased by the hot plate 39. At the same time, the flow control valves 33a, 33b are opened to supply the carrier gas and the carrier gas (diluted) from the carrier gas sources 32a, 32b into the film formation chamber 37. After the atmosphere in the film formation chamber 37 is sufficiently replaced with the carrier gas, the flow rates of the carrier gas and the carrier gas (diluted) are adjusted, respectively. Next, the ultrasonic vibrator 36 begins to vibrate. The vibration of the ultrasonic vibrator 36 propagates to the raw material solution 34a through the water 35a. This causes the raw material solution 34a to atomize, generating atomized droplets 34b. The atomized droplets 34b are introduced into the film formation chamber 37 by the carrier gas and the carrier gas (diluted), and then transported to the vicinity of the substrate 20. Then, the atomized droplets 34 b undergo a thermal reaction in the film-forming chamber 37 under atmospheric pressure, and a crystalline film 10 (semiconductor layer) is formed on the substrate 20 .

[0053] FIG. 10 is a schematic diagram showing another example of a film formation apparatus 40. Similar to the film formation apparatus 30, the film formation apparatus 40 includes a carrier gas source 32a, a flow rate control valve 33a, a carrier gas source 32b, a flow rate control valve 33b, an atomized droplet generating source 34, a container 35, and an ultrasonic vibrator 36. Additionally, the film formation apparatus 40 includes a supply pipe 42 through which atomized droplets are supplied from the atomized droplet generating source 34, a susceptor 41 provided within the supply pipe 42, and a heater 43 installed around the supply pipe 42. The supply pipe 42 essentially forms a film formation chamber. The supply pipe 42 is provided with an exhaust port 42a for discharging atomized droplets and exhaust gas after reaction. The susceptor 41 has a mounting surface on which a substrate 20 is placed. The mounting surface is inclined relative to a horizontal plane. The film formation apparatus 40 can be used to form a film in the same manner as the film formation apparatus 30 described above.

[0054] On the other hand, when the crystalline film 10 is formed by the HVPE method, the crystalline film formation process includes, for example, gasifying a metal source containing a metal to generate a metal-containing source gas (hereinafter, this process is referred to as the "gasification process"), and supplying the metal-containing source gas and the oxygen-containing source gas to a crystalline substrate 20 placed in a reaction chamber and epitaxially growing a crystal to form the crystalline film 10 on the substrate 20 (hereinafter, this process is referred to as the "film formation process"). In the film formation process, a reactive gas may be supplied to the substrate 20 in addition to the metal-containing source gas and the oxygen-containing source gas.

[0055] An example of a film formation apparatus (HVPE apparatus) used when forming the crystalline film 10 by the HVPE method will be described below. Fig. 11 is a schematic diagram showing a film formation apparatus 50. The film formation apparatus 50 includes a reaction chamber 51, heaters 52a and 52b, a metal-containing source gas supply pipe 53b, and an oxygen-containing source gas supply pipe 55b. The film formation apparatus 50 may further include a reactive gas supply pipe 54b.

[0056] A metal source 57 and a substrate 20 are placed in the reaction chamber 51. The region of the reaction chamber 51 where the substrate 20 is placed essentially forms a film formation chamber. The substrate 20 is held by, for example, a holder 56 provided in the reaction chamber 51. Note that the substrate 20 is not shown in FIG. 11 . A protective sheet 58 that prevents the precipitation of reactants may be provided on the inner wall of the reaction chamber 51. The heater 52 a heats the metal source 57. The heater 52 b heats the substrate 20.

[0057] The metal-containing source gas supply pipe 53b and the oxygen-containing source gas supply pipe 55b are provided in the reaction chamber 51. The metal-containing source gas supply pipe 53b is provided in the reactive gas supply pipe 54b. The reactive gas supply pipe 54b and the metal-containing source gas supply pipe 53b form a double-pipe structure. The metal-containing source gas supply pipe 53b is connected to a halogen-containing source gas supply source 53a. A metal source 57 is provided in the metal-containing source gas supply pipe 53b. The halogen-containing source gas from the halogen-containing source gas supply source 53a is supplied to the metal-containing source gas supply pipe 53b. The halogen-containing source gas is supplied to the metal source 57 and becomes a metal-containing source gas. The metal-containing source gas is supplied to the substrate 20 via the metal-containing source gas supply pipe 53b. The oxygen-containing source gas supply pipe 55b is connected to the oxygen-containing source gas supply source 55a. The oxygen-containing source gas from the oxygen-containing source gas supply source 55a is supplied to the substrate 20 via an oxygen-containing source gas supply pipe 55b.

[0058] The metal source 57 is not particularly limited as long as it can be gasified, and may be a metal element or a metal compound. The metal source 57 includes the metal contained in the crystal film 10. The metal source 57 may be gallium element. The metal source 57 may be a gas, a liquid, or a solid. The metal source 57 is preferably a liquid.

[0059] The means for gasifying the metal source 57 is not particularly limited and may be a known means. The gasification of the metal source 57 is preferably carried out, for example, by halogenating the metal source 57. The halogenating agent used for the halogenation is, for example, contained in the halogen-containing source gas supplied from the halogen-containing source gas supply source 53a to the metal-containing source gas supply pipe 53b. The halogenating agent is not particularly limited as long as it can halogenate the metal source 57 and may be a known halogenating agent. The halogenating agent is, for example, a halogen or a hydrogen halide. Examples of halogens include fluorine, chlorine, bromine, or iodine. Examples of hydrogen halides include hydrogen fluoride, hydrogen chloride, hydrogen bromide, and hydrogen iodide. For halogenation, a hydrogen halide is preferably used, and hydrogen chloride is more preferably used. The gasification of the metal source 57 is preferably carried out by supplying a halogen or a hydrogen halide as a halogenating agent to the metal source 57 and reacting the metal source 57 with the halogen or the hydrogen halide at a temperature equal to or higher than the vaporization temperature of the metal halide to form a metal halide. The halogenation reaction temperature is not particularly limited. For example, when the metal source 57 is gallium and the halogenating agent is HCl, the halogenation reaction temperature is preferably 900°C or less. The halogenation reaction temperature is more preferably 700°C or less, and even more preferably 400°C or more and 700°C or less. The metal-containing source gas is not particularly limited as long as it is a gas containing the metal of the metal source 57. The metal-containing source gas is, for example, a metal halide (fluoride, chloride, bromide, iodide, etc.).

[0060] The oxygen-containing source gas is, for example, O ２ Gas, CO ２ Gas, NO Gas, NO ２ Gas, N ２ O gas, H ２ O gas or O ３ The oxygen-containing source gas is O ２ , H ２ O and N ２ Preferably, the gas is one or more gases selected from the group consisting of O ２ It is more preferable that the oxygen-containing source gas contains CO ２may include:

[0061] The reactive gas supply pipe 54b is provided in the reaction chamber 51. The reactive gas supply pipe 54b is connected to the reactive gas supply source 54a. The reactive gas from the reactive gas supply source 54a is supplied to the substrate 20 via the reactive gas supply pipe 54b. The reaction chamber 51 is provided with a gas exhaust unit 59 that exhausts used gas.

[0062] The reactive gas is typically a gas with a different reactivity from the metal-containing source gas and the oxygen-containing source gas, and does not include an inert gas. Examples of reactive gases include, but are not limited to, etching gases. The etching gas is also not limited to, and may be a known etching gas. The reactive gas is preferably a halogen gas (e.g., fluorine gas, chlorine gas, bromine gas, or iodine gas), a hydrogen halide gas (e.g., hydrofluoric acid gas, hydrochloric acid gas, hydrogen bromide gas, hydrogen iodide gas), hydrogen gas, or a mixed gas of two or more of these. It is more preferable that the reactive gas contains a hydrogen halide gas, and even more preferable that the reactive gas contains hydrogen chloride. The metal-containing source gas, oxygen-containing source gas, or reactive gas may contain a carrier gas. Examples of the carrier gas include inert gases such as nitrogen and argon. The partial pressure of the metal-containing source gas is not particularly limited, but is preferably 0.5 Pa or more and 1 kPa or less, and more preferably 5 Pa or more and 0.5 kPa or less. The partial pressure of the oxygen-containing source gas is not particularly limited, but is preferably 0.5 to 100 times the partial pressure of the metal-containing source gas, and more preferably 1 to 20. The partial pressure of the reactive gas is also not particularly limited, but is preferably 0.1 to 5 times the partial pressure of the metal-containing source gas, and more preferably 0.2 to 3 times.

[0063] A dopant-containing gas may further be supplied to the substrate 20. The dopant-containing gas is not particularly limited as long as it contains the dopant contained in the crystal film 10. By using the dopant-containing gas, the conductivity of the resulting crystal film 10 can be easily controlled. The dopant-containing gas preferably contains the dopant in the form of a compound (e.g., halide, oxide, etc.), more preferably in the form of a halide. The partial pressure of the dopant-containing source gas is not particularly limited, but is preferably 1×10 of the partial pressure of the metal-containing source gas. －７ It is preferable that the ratio is 2.5×10 to 0.1 times. －６ More than twice 7.5×10 －２ Preferably, the dopant-containing gas is supplied onto the substrate 20 together with the reactive gas.

[0064] By using the above-described film formation apparatuses 30, 40, and 50, the crystalline film 10 can be easily formed on the crystal growth surface of the substrate 20. In this case, the crystalline film 10 is usually formed by epitaxial crystal growth.

[0065] The intermediate layer 25 may be formed by a method similar to that for forming the crystalline film 10. The intermediate layer 25 can be formed, for example, by using the film-forming apparatus 30 shown in FIG. 9 and performing a process similar to the crystalline film formation process. In this case, as shown in FIG. 12 , the supply of carrier gas to the film-forming chamber 37 may be started before the temperature rise in the film-forming chamber 37 is completed, i.e., before the temperature in the film-forming chamber 37 reaches or exceeds the film-forming temperature. Furthermore, in this case, the supply of carrier gas (dilution) to the film-forming chamber 37 may be started before the temperature in the film-forming chamber 37 reaches or exceeds the film-forming temperature. This supply of carrier gas and carrier gas (dilution) to the film-forming chamber 37 is achieved, for example, by opening the flow rate control valves 33 a and 33 b simultaneously with, before, or immediately after the operation of the hot plate 39. The temperature in the film-forming chamber 37 then reaches the film-forming temperature, and the temperature in the film-forming chamber 37 is maintained thereafter until the intermediate layer 25 is formed. The supply of the carrier gas and the carrier gas (diluted) to the film formation chamber 37 is also maintained until the intermediate layer 25 is formed. One of the carrier gas and the carrier gas (diluted) may be supplied to the film formation chamber 37 after the temperature inside the film formation chamber 37 has reached or exceeded the film formation temperature. Alternatively, both the carrier gas and the carrier gas (diluted) may be supplied to the film formation chamber 37 after the temperature inside the film formation chamber 37 has reached or exceeded the film formation temperature.

[0066] In the preheating step described above, the substrate 20 is preferably heated under the same conditions as when the substrate 20 is heated in the intermediate layer forming step or the film forming step. That is, in the preheating step, the substrate 20 is preferably placed in a film forming chamber, and the temperature in the film forming chamber is preferably heated to the film forming temperature in the intermediate layer forming step or the film forming temperature in the film forming step. Note that in the preheating step, the substrate 20 may be heated under conditions different from when the substrate 20 is heated in the intermediate layer forming step or the film forming step.

[0067] The crystalline film 10 is useful for semiconductor devices, particularly power devices. A semiconductor device including the crystalline film 10 may be a vertical or horizontal device. A vertical device is a semiconductor device in which electrodes are disposed on both sides of the crystalline film 10 in the thickness direction. A horizontal device is a semiconductor device in which electrodes are disposed on only one side of the crystalline film 10 in the thickness direction. Semiconductor devices formed using the crystalline film 10 include, for example, transistors such as MESFETs (metal semiconductor field effect transistors), MOSFETs (metal oxide semiconductor field effect transistors), MISFETs (metal insulator semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), HEMTs (high electron mobility transistors), JFETs (junction field effect transistors), and SITs (static induction transistors), TFTs, SBDs (Schottky barrier diodes), JBSs (junction barrier Schottky diodes), PN or PIN diodes, LEDs (light emitting diodes), or light emitting / receiving elements using semiconductor-metal junctions. The crystalline film 10 can be used as a semiconductor layer in a semiconductor device after being peeled off from the substrate 20. The crystal film 10 can also be used by being disposed on another substrate having a higher thermal conductivity than the substrate 20, for example.

[0068] A preferred example of a semiconductor device incorporating the crystalline film 10 as a semiconductor layer will be described below. In the semiconductor devices described below, the crystalline film 10 may be incorporated as an n-type semiconductor layer or a p-type semiconductor layer. When a semiconductor device includes multiple semiconductor layers, all of the multiple semiconductor layers may be crystalline films 10, or only some of the multiple semiconductor layers may be crystalline films 10. When a semiconductor device includes an n-type semiconductor layer and a p-type semiconductor layer, each of the n-type semiconductor layer and the p-type semiconductor layer may be crystalline films 10, or only the n-type semiconductor layer or only the p-type semiconductor layer may be crystalline films 10. When a semiconductor device includes multiple semiconductor layers, the entire semiconductor layer may be crystalline films 10, or only some of the semiconductor layers may be crystalline films 10.

[0069] FIG. 13 is a cross-sectional view schematically illustrating an example semiconductor device 100. The semiconductor device 100 is an SBD. The semiconductor device 100 includes a semiconductor layer 101, a first electrode 104, and a second electrode 105. The semiconductor layer 101 includes an n+ type semiconductor layer 102 and an n- type semiconductor layer 103. The n+ type semiconductor layer 102 and the n- type semiconductor layer 103 are aligned in the thickness direction of the semiconductor layer 101. The surface of the n- type semiconductor layer 103 opposite to the n+ type semiconductor layer 102 forms a first surface 101a, which is one surface of the semiconductor layer 101 in the thickness direction. The surface of the n+ type semiconductor layer 102 opposite to the n- type semiconductor layer 103 forms a second surface 101b, which is the surface of the semiconductor layer 101 opposite to the first surface 101a. The first electrode 104 is disposed on the first surface 101a. The first electrode 104 is a Schottky electrode. The second electrode 105 is disposed on the second surface 101b. The second electrode 105 is an ohmic electrode.

[0070] The material of each of the first electrode 104 and the second electrode 105 may be a known electrode material, such as a metal such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or an alloy thereof; a conductive metal oxide film such as tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), or indium zinc oxide (IZO); an organic conductive compound such as polyaniline, polythiophene, or polypyrrole; or a mixture or laminate thereof.

[0071] The method for forming the first electrode 104 and the second electrode 105 is not particularly limited. The method for forming the first electrode 104 and the second electrode 105 can be appropriately selected from, for example, wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into account their suitability for the materials. The first electrode 104 and the second electrode 105 may each be formed using two types of metal, a first metal and a second metal. In this case, the first electrode 104 or the second electrode 105 may be formed by stacking a layer made of the first metal and a layer made of the second metal, and then patterning the layer made of the first metal and the layer made of the second metal using a photolithography technique.

[0072] When a forward bias is applied to the semiconductor device 100, electrons flow from the second electrode 105 to the first electrode 104. When a reverse bias is applied to the semiconductor device 100, a depletion layer spreads into the n-type semiconductor layer 103, resulting in a high-voltage SBD.

[0073] FIG. 15 is a cross-sectional view schematically illustrating another example of a semiconductor device 200. The semiconductor device 200 is a JBS. The semiconductor device 200 includes a semiconductor layer 201, a barrier height adjusting region 202, a first electrode 203, and a second electrode 204. The semiconductor layer 201 may be a single layer or may include multiple semiconductor layers. The semiconductor layer 201 has a first surface 201a, which is one surface of the semiconductor layer 201 in the thickness direction, and a second surface 201b, which is the surface opposite to the first surface 201a. The barrier height adjusting region 202 is formed on the first surface 201a. The first electrode 203 is formed on the first surface 201a so as to be in contact with both the semiconductor layer 201 and the barrier height adjusting region 202. The first electrode 203 is a barrier electrode that forms a Schottky barrier between the first electrode 203 and the semiconductor layer 201. The second electrode 204 is formed on the second surface 201b. The second electrode 204 is an ohmic electrode.

[0074] The barrier height adjusting region 202 is formed between the semiconductor layer 201 and the first electrode 203. The barrier height adjusting region 202 forms a Schottky barrier between the semiconductor layer 201 and the first electrode 203, the barrier height adjusting region 202 having a barrier height greater than that of the Schottky barrier of the first electrode 203. In this example, a plurality of trenches 201c are formed in the first surface 201a of the semiconductor layer 201. The barrier height adjusting region 202 is embedded in each trench 201c. The barrier height adjusting region 202 is preferably provided at least between both ends of the first electrode 203 and the semiconductor layer 201. The barrier height adjusting region 202 is preferably provided at regular intervals.

[0075] The material of each of the first electrode 203 and the second electrode 204 may be a known electrode material. The electrode material may be the same as the material of each of the first electrode 104 and the second electrode 105 of the semiconductor device 100. The first electrode 203 and the second electrode 204 may be formed by known means, such as a vacuum deposition method or a sputtering method. The first electrode 203 and the second electrode 204 may be formed in the same manner as the first electrode 104 and the second electrode 105 of the semiconductor device 100. The same applies to the material and formation of each electrode of the semiconductor devices 300, 400, 500, 600, 700, and 800 described below.

[0076] FIG. 16 is a cross-sectional view schematically illustrating a semiconductor device 300 according to another example. The semiconductor device 300 is a JBS. Like the semiconductor device 200, the semiconductor device 300 includes a semiconductor layer 201, a barrier height adjusting region 202, a first electrode 203, and a second electrode 204. In addition, the semiconductor device 300 further includes a guard ring 305 formed on the semiconductor layer 201. In this example, the semiconductor device 300 includes a plurality of guard rings 305. The guard rings 305 are positioned around the first electrode 203. At least a portion of the guard rings 305 is embedded in the semiconductor layer 201. By providing the guard rings 305, the breakdown voltage and other properties of the semiconductor device 300 can be improved, thereby improving the semiconductor characteristics of the semiconductor device 300.

[0077] The guard ring 305 is typically made of a material with a high barrier height. Examples of materials used for the guard ring 305 include conductive materials with a barrier height of 1 eV or more. The material for the guard ring 305 may be the same material as the electrode material. The material for the guard ring 305 may be the metal exemplified as the material for the first electrode 104 and the second electrode 105 of the semiconductor device 100. In this case, the design freedom for the voltage-resistant structure is high, and a large number of guard rings 305 can be provided, thereby flexibly improving the voltage resistance. The shape of the guard ring 305 is not particularly limited. The shape of the guard ring 305 may be, for example, a square shape, a circular shape, a U-shape, an L-shape, or a strip shape. The number of guard rings 305 included in the semiconductor device 300 is also not particularly limited. The semiconductor device 300 preferably includes three or more guard rings 305, and more preferably includes six or more guard rings 305.

[0078] FIG. 17 is a cross-sectional view schematically illustrating another example of a semiconductor device 400. The semiconductor device 400 is an LED. The semiconductor device 400 includes an n-type semiconductor layer 401, a light-emitting layer 402, a p-type semiconductor layer 403, a transparent electrode 404, a first electrode 405, and a second electrode 406. The light-emitting layer 402 is formed on the n-type semiconductor layer 401. The light-emitting layer 402 emits light. The p-type semiconductor layer 403 is formed on the light-emitting layer 402. The transparent electrode 404 is formed on the p-type semiconductor layer 403. The transparent electrode 404 is transparent. Therefore, light generated in the light-emitting layer 402 passes through the transparent electrode 404. The first electrode 405 is formed on the transparent electrode 404. The first electrode 405 is an anode electrode. The second electrode 406 is formed on the surface of the n-type semiconductor layer 401 opposite to the light emitting layer 402. The second electrode 406 is a cathode electrode. The semiconductor device 400 may be covered with a protective layer except for the electrode portion.

[0079] 18 is a cross-sectional view schematically illustrating another example of a semiconductor device 500. The semiconductor device 500 is a MOSFET, specifically a trench MOSFET. The semiconductor device 500 includes a first n+ type semiconductor layer 501, an n- type semiconductor layer 502, a p-type semiconductor layer 503, a second n+ type semiconductor layer 504, an insulating film 505, a first electrode 506, a second electrode 507, and a third electrode 508.

[0080] The n-type semiconductor layer 502 is formed on the first n+ type semiconductor layer 501. The p-type semiconductor layer 503 is formed on the n- type semiconductor layer 502. The second n+ type semiconductor layer 504 is formed on the p-type semiconductor layer 503. The first electrode 506 is formed on the second n+ type semiconductor layer 504. The first electrode 506 is a source electrode. The second electrode 507 is formed on the surface of the first n+ type semiconductor layer 501 opposite to the n- type semiconductor layer 502. The second electrode 507 is a drain electrode. A plurality of trenches 509 are formed on the surface of the semiconductor layer formed from the n- type semiconductor layer 502, the p-type semiconductor layer 503, and the second n+ type semiconductor layer 504, on the first electrode 506 side. Each of the plurality of trenches 509 penetrates the second n+ type semiconductor layer 504 and the p-type semiconductor layer 503 to reach the n- type semiconductor layer 502. A third electrode 508 is buried in each trench 509 via an insulating film 505. The third electrode 508 is a gate electrode.

[0081] 19 is a cross-sectional view schematically showing yet another example of a semiconductor device 600. The semiconductor device 600 is an IGBT. The semiconductor device 600 includes a p-type semiconductor layer 601, an n-type semiconductor layer 602, an n-type semiconductor layer 603, a p-type semiconductor region 604, an n+ type semiconductor region 605, an insulating film 606, and a plurality of first electrodes 607, second electrodes 608, and third electrodes 609.

[0082] The n-type semiconductor layer 602 is formed on the p-type semiconductor layer 601. The n-type semiconductor layer 603 is formed on the n-type semiconductor layer 602. A plurality of trenches 603a are formed on the surface of the n-type semiconductor layer 603 opposite to the n-type semiconductor layer 602. A p-type semiconductor region 604 is formed inside each of the plurality of trenches 603a. An n+ type semiconductor region 605 is formed inside each of the p-type semiconductor regions 604. An insulating film 606 is formed on the n-type semiconductor layer 603 so as to be in contact with the n- type semiconductor layer 603, the p-type semiconductor region 604, and the n+ type semiconductor region 605. Each of the plurality of first electrodes 607 is formed on the p-type semiconductor region 604 and in contact with the p-type semiconductor region 604 and the n+ type semiconductor region 605. The first electrodes 607 are emitter electrodes. The second electrode 608 is formed on the surface of the p-type semiconductor layer 601 opposite to the n-type semiconductor layer 602. The second electrode 608 is a collector electrode. The third electrode 609 is formed on the insulating film 606. The third electrode 609 is a gate electrode.

[0083] FIG. 20 is a cross-sectional view schematically illustrating a semiconductor device 700 according to another example. The semiconductor device 700 is a HEMT. The semiconductor device 700 includes a semi-insulating layer 701, a buffer layer 702, a first n-type semiconductor layer 703, a second n-type semiconductor layer 704, multiple n+ type semiconductor layers 705, a first electrode 706, a second electrode 707, and a third electrode 708. The buffer layer 702 is formed on the semi-insulating layer 701. The first n-type semiconductor layer 703 is formed on the buffer layer 702. The second n-type semiconductor layer 704 is formed on the first n-type semiconductor layer 703. The band gap of the second n-type semiconductor layer 704 is wider than the band gap of the first n-type semiconductor layer 703. The multiple n+ type semiconductor layers 705 are embedded in the first n-type semiconductor layer 703 and the second n-type semiconductor layer 704. The n+ type semiconductor layer 705 is in contact with the first n-type semiconductor layer 703 and the second n-type semiconductor layer 704. A first electrode 706 and a second electrode 707 are formed on each of the n+ type semiconductor layers 705. The first electrode 706 is a source electrode. The second electrode 707 is a drain electrode. A third electrode 708 is formed on the second n-type semiconductor layer 704. The third electrode 708 is a gate electrode.

[0084] FIG. 21 is a cross-sectional view schematically showing yet another example of a semiconductor device 800. The semiconductor device 800 is a JFET. The semiconductor device 800 includes a first n+ type semiconductor layer 801, an n- type semiconductor layer 802, a second n+ type semiconductor layer 803, a first electrode 804, a second electrode 805, and a third electrode 806. The n- type semiconductor layer 802 is formed on the first n+ type semiconductor layer 801. The second n+ type semiconductor layer 803 is formed on the n- type semiconductor layer 802. The first electrode 804 is formed on the second n+ type semiconductor layer 803. The first electrode 804 is a source electrode. A plurality of trenches 807 are formed in the layer formed by the n- type semiconductor layer 802, the second n+ type semiconductor layer 803, and the first electrode 804. Each of the plurality of trenches 807 extends from the surface of the first electrode 804 opposite to the n+ type semiconductor layer 803, through the first electrode 804 and the second n+ type semiconductor layer 803, and reaches the n- type semiconductor layer 802. The second electrode 805 is formed on the surface of the first n+ type semiconductor layer 801 opposite to the n- type semiconductor layer 802. The third electrode 806 is formed at the bottom of each trench 807. The third electrode 806 is in contact with the n- type semiconductor layer 802. The third electrode 806 is a gate electrode.

[0085] In addition to the above, semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800 can be suitably used as power modules, inverters, or converters using known methods, and can also be suitably used in, for example, semiconductor systems using power supply devices. A power supply device can be fabricated using known methods by connecting semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800 to a wiring pattern, etc.

[0086] Fig. 22 is a block diagram of an example power supply system 900. The power supply system 900 includes a plurality of power supply devices 901 and 902 and a control circuit 903. Fig. 23 is a block diagram of an example system device 910. The system device 910 includes the power supply system 900 and an electronic circuit 911.

[0087] Figure 24 is a circuit diagram showing the power supply circuit of an example power supply device. This power supply circuit includes a power circuit and a control circuit. This power supply circuit converts DC voltage into AC by high-frequency switching using an inverter 921 (comprising MOSFETs A to D), then performs isolation and transformation using a transformer 922, rectifies the voltage using a rectifier MOSFET 923, and smooths it using a DCL 924 (smoothing coils L1 and L2) and a capacitor to output a DC voltage. At this time, a voltage comparator 925 compares the output voltage with a reference voltage, and a PWM control circuit 926 controls the inverter 921 and rectifier MOSFET 923 to achieve the desired output voltage.

[0088] Conventionally, crystal films containing gallium-containing crystalline oxide semiconductors have been investigated for their excellent yield and semiconductor properties. However, even such crystal films have difficulty in obtaining good results in high-temperature, high-humidity reverse bias tests, and reliability has been an issue. In contrast, the crystal film 10 and semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800 of the present disclosure have a thickness of at least 1.0 mm. ２ No black or bright spots are included in the region. Alternatively, a cross section cut in the thickness direction of the crystal film 10 does not contain particles containing amorphous solids and / or crystals. Here, the black or bright spots are considered to be abnormal crystal growth areas, crystalline deposits, or amorphous deposits. Alternatively, the black or bright spots are considered to be depressions formed by the abnormal growth areas or deposits peeling off of foreign matter from the crystal film 10. Therefore, the reliability of the electrical characteristics, etc. of the crystal film 10 and the semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800 can be improved.

[0089] Furthermore, the manufacturing method of the crystal film 10 includes a groove forming step, and recesses are likely to be formed in the portions of the upper surface of the crystal film 10 corresponding to the grooves 21. Therefore, even if a crack occurs in a portion of the crystal film 10, once this crack reaches the recess, it is difficult for the crack to propagate to other portions of the crystal film 10. This can further improve the reliability of the crystal film 10 and the semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800.

[0090] Furthermore, since the manufacturing method of the crystal film 10 includes a first cleaning step of cleaning the surface of the substrate 20 on which the grooves 21 are formed, it is possible to remove particulate matter that could become black spots or bright spots, such as cutting debris generated when the grooves 21 are formed in the groove forming step. As a result, black spots or bright spots are less likely to occur in the crystal film 10 and the semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800. This further improves the reliability of the crystal film 10 and the semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800.

[0091] Furthermore, if the preheating step of heating the substrate 20 before the crystal film formation step were omitted, damage such as cracks caused by thermal stress could occur in the substrate 20 during the intermediate layer formation step and the crystal film formation step, potentially resulting in the generation of particles that could become black or bright spots. However, in the manufacturing method of the crystal film 10 of this example, the preheating step is performed before the intermediate layer formation step. Therefore, damage caused by thermal stress is less likely to occur during the intermediate layer formation step and the crystal film formation step. Furthermore, even if damage caused by thermal stress occurs during the preheating step and particles that could become black or bright spots are generated, these particles can be removed in the second cleaning step after the preheating step. Therefore, the reliability of the crystal film 10 and the semiconductor devices 100, 200, 300, 400, 500, 600, 700, and 800 can be further improved.

[0092] Furthermore, in the intermediate layer formation process, by starting the supply of carrier gas to the substrate 20 before the temperature in the film formation chamber 37 reaches or exceeds the film formation temperature, particulate matter that could become black or bright spots is less likely to adhere to the substrate 20. For example, if the supply of carrier gas is started after the temperature in the film formation chamber 37 reaches or exceeds the film formation temperature, particulate matter generated due to thermal stress associated with heating the substrate 20 may adhere to the surface of the substrate 20. However, as in the present disclosure, by starting the supply of carrier gas before the temperature in the film formation chamber 37 reaches or exceeds the film formation temperature, particulate matter generated on the substrate 20 is blown away by the carrier gas, preventing the particulate matter from adhering to the surface of the substrate 20. This also prevents the particulate matter from adhering to the subsequently formed intermediate layer 25. Incidentally, when the crystalline film 10 is formed, similar to when the intermediate layer 25 is formed, the supply of carrier gas to the film formation chamber 37 may be started before the temperature in the film formation chamber 37 reaches or exceeds a predetermined temperature lower than the film formation temperature, and this supply may be maintained until the crystalline film 10 is formed. In this case, too, adhesion of particulate matter to the intermediate layer 25 and the crystal film 10 can be suppressed.

[0093] (Example 1) Examples of the present disclosure will be described below, but the present disclosure is not limited to these.

[0094] 1. Preparation of Substrate A sapphire substrate was prepared as the substrate.

[0095] 2. Groove formation Grooves were formed on the upper surface of the substrate 20 obtained in 1 by irradiating a part of the upper surface of the substrate 20 with a long wavelength laser (SHG laser, laser wavelength 655 nm, processing speed 200 mm / s, number of repetitions 4).

[0096] 3. First Cleaning The upper surface of the substrate 20 on which the grooves had been formed in step 2 was cleaned with a cleaning solution containing hydrofluoric acid.

[0097] 4. Film Forming Apparatus A film forming apparatus 40 shown in FIG. 10 was prepared for producing a crystal film. A quartz tube with an inner diameter of 40 mm was used as the supply pipe 42. A susceptor 41 made of quartz was used. The reason for using quartz for both the supply pipe 42 and the susceptor 41 was to prevent impurities from the apparatus from being mixed into the crystal film.

[0098] 5. Preparation of Crystalline Film Raw Material Solution Gallium bromide was mixed with ultrapure water to a concentration of 0.1 mol / L, and hydrobromic acid was added at a volume ratio of 10%. This was used as a crystal film raw material solution.

[0099] 6. Film Formation Preparation The raw material solution 34a for the crystal film obtained in step 5 above was placed in the atomized droplet generating source 34. Next, the substrate 20 cleaned in step 3 was placed on the susceptor 41, and the temperature of the heater 43 was raised to 600°C. Next, the flow rate control valves 33a and 33b were opened, and carrier gas was supplied from the carrier gas sources 32a and 32b into the supply pipe 42. Thereafter, the flow rate of the carrier gas from the carrier gas source 32a was adjusted to 0.5 L / min, and the flow rate of the carrier gas (diluted) from the carrier gas source 32b was adjusted to 0.5 L / min, respectively, and the temperature of the heater 43 was maintained at 600°C. Note that oxygen was used as the carrier gas.

[0100] 7. Crystalline Film Formation Next, the ultrasonic vibrator 36 was vibrated, and the vibrations were propagated through the water 35a to the raw material solution 34a, thereby atomizing the raw material solution 34a and generating atomized droplets. These atomized droplets were transported by the carrier gas to the supply pipe 42, and under atmospheric pressure, the atomized droplets thermally reacted near the surface of the substrate 20, forming a crystalline film on the substrate 20.

[0101] Example 2 In Example 2, a crystal film was formed on a substrate 20 cleaned in the same manner as in 3 of Example 1, via a buffer layer. Specifically, the buffer layer was formed by the following method. 1. Film Forming Apparatus To produce the buffer layer, a film forming apparatus 40 shown in FIG. 10 was prepared. A quartz tube with an inner diameter of 40 mm was used as the supply pipe 42. A susceptor 41 made of quartz was used.

[0102] 2. Preparation of raw material solution for buffer layer Gallium bromide and tin bromide were mixed with ultrapure water to prepare an aqueous solution such that the atomic ratio of tin to gallium was 1:0.08 and the concentration of gallium was 0.1 mol / L. At this time, hydrobromic acid was further added to the aqueous solution so that the volume ratio was 20%, and this was used as raw material solution 34a for the buffer layer.

[0103] 3. Film Formation Preparation The buffer layer raw material solution 34a obtained in step 2 above was placed in the atomized droplet generating source 34. Next, the substrate 20, cleaned in the same manner as in step 3 of Example 1, was placed on the susceptor 41. Next, the flow rate control valve 33b was opened to supply carrier gas (diluted) from the carrier gas source 32b into the supply pipe 42. Next, the heater 43 was started to heat up, and the temperature of the heater 43 was raised to 600°C. Next, the flow rate control valve 33a was opened to supply carrier gas from the carrier gas source 32a into the supply pipe 42. After the heater 43 was heated, the flow rates of the carrier gas from the carrier gas source 32a and the carrier gas (diluted) from the carrier gas source 32b were adjusted to 1.0 L / min and 1.0 L / min, respectively, and the temperature of the heater 43 was maintained at 600°C. Oxygen was used as the carrier gas.

[0104] 4. Formation of Buffer Layer After the temperature increase of the heater 43 in step 3 was completed, the ultrasonic vibrator 36 was vibrated, and the vibration was propagated to the raw material solution 34a through the water 35a, thereby atomizing the raw material solution 34a and generating atomized droplets. The atomized droplets were transported by the carrier gas to the supply pipe 42, and under atmospheric pressure, the atomized droplets thermally reacted near the surface of the substrate 20, forming a buffer layer on the substrate 20.

[0105] 5. Formation of Crystalline Film Similar to step 7 of Example 1, a crystalline film was formed on the buffer layer using the film-forming device 40 .

[0106] (Example 3) In step 4 of Example 2, the flow control valves 33a and 33b were opened simultaneously with the start of temperature increase by the heater 43, and the carrier gas and the carrier gas (diluted) were supplied from the carrier gas sources 32a and 32b into the supply pipe 42. A buffer layer and a crystal film were formed on the substrate 20 by the same method as in Example 2 except for the above.

[0107] Example 4 In the first cleaning of Example 2, instead of cleaning the upper surface of the substrate 20 with a cleaning solution containing hydrofluoric acid, water was sprayed onto the upper surface of the substrate 20 to clean the substrate 20. Thereafter, the substrate 20 was preheated in the same manner as in Example 2, step 3. However, no buffer layer was formed on the substrate 20 this time. Specifically, a film formation apparatus 40 shown in FIG. 10 was prepared, and the substrate 20 was placed on a susceptor 41. Next, the flow rate control valve 33b was opened to supply a carrier gas (diluted) from the carrier gas source 32b into the supply pipe 42. Next, heating by the heater 43 was started, and the temperature of the heater 43 was raised to 600°C. Next, the flow rate control valve 33a was opened, and a carrier gas was supplied from the carrier gas source 32a into the supply pipe 42. After the heater 43 was heated, the flow rates of the carrier gas from the carrier gas source 32a and the carrier gas (diluted) from the carrier gas source 32b were adjusted to 1.0 L / min and 1.0 L / min, respectively, and the temperature of the heater 43 was maintained at 600°C. Oxygen was used as the carrier gas. Heating by the heater 43 was then stopped, and the substrate 20 was cooled to room temperature. Thereafter, a buffer layer and a crystalline film were formed in the same manner as in Example 2. However, in preparation for forming the buffer layer corresponding to step 3 of Example 2, the flow control valves 33a and 33b were opened simultaneously with the start of heating by the heater 43, and the carrier gas and the carrier gas (diluted) were supplied into the supply pipe 42 from the carrier gas sources 32a and 32b, as in Example 3.

[0108] Comparative Example 1 The only difference from Example 1 is that a groove was formed on the top surface of the substrate 20 by irradiating it with a short wavelength laser (SHG laser, laser wavelength 532 nm, processing speed 8 mm / s, repetition rate 1 time), and otherwise a crystal film was formed in the same manner as in Example 1.

[0109] Comparative Example 2 The only difference from Example 2 is that a groove was formed on the top surface of the substrate 20 by irradiating a short-wavelength laser (SHG laser, laser wavelength 532 nm, processing speed 8 mm / s, repetition rate 1 time). In other respects, a crystal film was formed on the substrate 20 via a buffer layer in the same manner as in Example 2.

[0110] (Evaluation) The layers of the crystal films formed in Examples 1 to 4 and Comparative Examples 1 and 2 were identified using an X-ray diffraction apparatus. ２ O ３ It was a membrane.

[0111] Fig. 25 is a photograph, taken using an SEM, of a cross section of a crystal film formed under the same conditions as in Example 1. Fig. 26 is a photograph, taken using an SEM, of a cross section of a crystal film formed under the same conditions as in Comparative Example 1.

[0112] The surfaces of the buffer layers and the crystal films formed in Examples 1 to 4 and Comparative Examples 1 and 2 were observed by an optical microscope. The observations were carried out using a VHX-6000 optical microscope manufactured by Keyence Corporation at a magnification of 50x.

[0113] 27 is a photograph taken with an optical microscope of a 1 mm square surface of the crystalline film of Example 1. As shown in this figure, neither black spots nor bright spots were observed in the multiple crystalline films formed by Example 1. Similarly, neither black spots nor bright spots were observed in the multiple buffer layers and multiple crystalline films formed by Example 2, the multiple buffer layers and multiple crystalline films formed by Example 3, and the multiple buffer layers and multiple crystalline films formed by Example 4.

[0114] Fig. 28 is a photograph of a 1 mm square surface of a crystal film containing black spots taken using an optical microscope. Fig. 29 is a photograph of a 1 mm square surface of a crystal film containing bright spots taken using an optical microscope. Fig. 30 is a photograph of a crystal film containing bright spots taken using a polarizing microscope. As shown in Figs. 28 to 30, black spots and bright spots were observed in the multiple crystal films formed according to Comparative Example 1 and the multiple buffer layers and multiple crystal films formed according to Comparative Example 2.

[0115] The crystalline films formed in Examples 1 to 4 and Comparative Examples 1 and 2 were observed using an electron microscope. The electron microscope observations were performed using a Regulus 8230 field-emission scanning electron microscope manufactured by Hitachi High-Technologies Corporation at a magnification of 200x to 10,000x. Figure 31 is a photograph of the cross section of a crystalline film containing granular particles taken using an electron microscope. In Figure 31, dashed lines are drawn on the surface of the crystalline film to clearly show the granular particles. No granular particles were observed in the multiple crystalline films formed in Examples 1 to 4. On the other hand, granular particles, as shown in Figure 31, were observed in the multiple crystalline films formed in Comparative Example 1 and the multiple buffer layers and multiple crystalline films formed in Comparative Example 2. Furthermore, when the cross sections of the buffer layers and crystalline films formed in Comparative Example 1 and Comparative Example 2 were observed using an electron microscope, the black and bright spots were confirmed to be granular particles.

[0116] Furthermore, energy dispersive X-ray analysis (EDX) confirmed that the crystalline film formed by Comparative Example 1 and the buffer layer and granules contained in the crystalline film formed by Comparative Example 2 contained gallium and aluminum, and that the atomic ratio of aluminum contained in these granules was greater than the atomic ratio of gallium.

[0117] Using the crystalline films obtained in each of Examples 1 to 4 and Comparative Examples 1 and 2, multiple semiconductor devices were fabricated with a one-to-one relationship between the crystalline film and the semiconductor device. Each of the multiple semiconductor devices was the semiconductor device shown in FIG. 13 , and included either a crystalline film containing black or bright spots, or a crystalline film containing no black or bright spots. A high-temperature, high-humidity reverse bias test was performed on each semiconductor device under conditions of a temperature of 85°C, humidity of 85%, and voltage of 220V to check for defects. The yield rates of semiconductor devices containing crystalline films in which black or bright spots were observed were compared with those of semiconductor devices containing crystalline films in which no black or bright spots were observed. The yield rates of crystalline films in which no black or bright spots were observed were higher than those of semiconductor devices containing crystalline films in which black or bright spots were observed.

[0118] The following additional notes are provided regarding this disclosure.

[0119] (Note 1) A crystalline film containing a crystalline oxide semiconductor containing gallium, wherein the crystalline film has a thickness of at least 1.0 mm when observed with an optical microscope. ２ A crystalline film that does not contain any dark or bright spots in the area.

[0120] (Appendix 1A) A crystalline film containing a crystalline oxide semiconductor containing gallium, wherein when the crystalline film is observed with an optical microscope, the thickness of the crystalline film is at least 1.0 mm. ２ A crystalline film that does not contain black or bright spots with a diameter of 0.5 μm or more in the area.

[0121] (Appendix 1B) The crystalline film according to Appendix 1 or Appendix 1A, wherein the black dots or the bright dots are granular.

[0122] (Appendix 2) A crystalline film including a crystalline oxide semiconductor containing gallium, wherein the crystalline film does not include particulate matter containing amorphous solids and / or crystals at least in a cross section cut in the thickness direction.

[0123] (Appendix 2A) The crystalline film according to appendix 1B or 2, wherein the particulate matter has crystallinity, and the crystalline structure of the particulate matter and the crystalline oxide semiconductor have different crystal structures.

[0124] (Appendix 2B) The crystalline film according to appendix 1B, 2 or 2A, wherein the composition of the particulate matter and the composition of the crystalline oxide semiconductor are different from each other.

[0125] (Appendix 2C) The crystalline film according to Appendix 1B, 2, 2A or 2B, wherein the particles contain gallium and / or aluminum.

[0126] (Supplementary Note 3) The crystalline film according to Supplementary Note 1, 1A, 1B, 2, 2A, 2B, or 2C, wherein the crystalline oxide semiconductor has a corundum structure.

[0127] (Note 4) A semiconductor layer including a crystalline oxide semiconductor containing gallium and an electrode are provided, and when observed with an optical microscope, the thickness of the semiconductor layer is at least 1.0 mm. ２ A semiconductor device that does not contain any dark or bright spots in the area.

[0128] (Appendix 4A) The semiconductor device according to appendix 4, wherein the semiconductor layer is the crystalline film according to appendix 1, 1A, 1B, 2, 2A, 2B, 2C, or 3.

[0129] (Supplementary Note 5) The semiconductor device according to Supplementary Note 4 or 4A, wherein the black dot or the bright dot is not included in a position of the semiconductor device that overlaps with the electrode.

[0130] (Supplementary Note 6) The semiconductor device according to Supplementary Note 4, 4A or 5, wherein the black dots or the bright dots are not included in positions of the semiconductor device that do not overlap with the electrodes.

[0131] (Appendix 7) A method for manufacturing a stacked structure, comprising: heating a substrate; cleaning the heated substrate; and forming a crystalline film containing a crystalline oxide semiconductor containing gallium on the cleaned substrate via an intermediate layer or directly.

[0132] (Appendix 7A) The method for manufacturing a laminated structure according to Appendix 7, wherein the cleaning comprises spraying a liquid onto the surface of the substrate.

[0133] (Appendix 7B) The method includes heating a substrate to a predetermined temperature or higher, atomizing a raw material solution to generate atomized droplets, and transporting the atomized droplets to the substrate heated to the predetermined temperature or higher by a carrier gas to form an intermediate layer or a crystal film on the substrate, and includes supplying the carrier gas to the substrate before the substrate reaches the predetermined temperature or higher during heating of the substrate.

[0134] (Appendix 7C) A method for manufacturing a crystalline film, comprising: forming grooves on a surface of a substrate; cleaning the surface of the substrate on which the grooves have been formed; and forming a crystalline film containing a crystalline oxide semiconductor containing gallium on the cleaned surface of the substrate.

[0135] (Appendix 7D) The method for producing a crystal film according to Appendix 7C, wherein in the cleaning, the surface of the substrate is cleaned with a cleaning liquid containing hydrofluoric acid.

[0136] The crystalline film of the present disclosure can be used in a variety of fields, such as semiconductor devices (e.g., compound semiconductor electronic devices, etc.), electronic and electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful for semiconductor devices, etc. The semiconductor device of the present disclosure can be used in a variety of fields, such as semiconductors (e.g., compound semiconductor electronic devices, etc.), electronic and electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful for power devices.

[0137] L1 Smoothing coil L2 Smoothing coil 10 Crystal film 10A Crystal film of reference example 11 Point defect 12 n+ layer 13 n- layer 20 Substrate 21 Groove 30 Film formation apparatus 32a Carrier gas source 32b Carrier gas (dilution) source 33a Flow rate adjustment valve 33b Flow rate adjustment valve 34 Atomized droplet generation source 34a Raw material solution 34b Atomized droplets 35 Container 35a Water 36 Ultrasonic vibrator 37 Film formation chamber 38 Supply pipe 39 Hot plate 40 Film formation apparatus 41 Susceptor 42 Supply pipe 42a Exhaust port 43 Heater 44 Exhaust port 50 Film formation apparatus 51 Reaction chamber 52a Heater 52b Heater 53a Halogen-containing raw material gas supply source 53b Metal-containing source gas supply pipe 54a Reactive gas supply source 54b Reactive gas supply pipe 55a Oxygen-containing source gas supply source 55b Oxygen-containing source gas supply pipe 56 Holder 57 Metal source 59 Gas exhaust unit 100 Semiconductor device 101 n-type semiconductor layer 101a First surface 101b Second surface 102 n+ type semiconductor layer 103 n- type semiconductor layer 104 First electrode 105 Second electrode 200 Semiconductor device 201 Semiconductor layer 201a First surface 201b Second surface 201c Trench 202 Barrier height adjusting region 203 First electrode 204 Second electrode 300 Semiconductor device 305 Guard ring 400 Semiconductor device 401 n-type semiconductor layer 402 Light-emitting layer 403 p-type semiconductor layer 404 Translucent electrode 405 First electrode 406 Second electrode 500 Semiconductor device 501 First n+ type semiconductor layer 502 n- type semiconductor layer 503 p-type semiconductor layer 504 Second n+ type semiconductor layer 505 Insulating film 506 First electrode 507 Second electrode 508 Third electrode 509 Trench 600 Semiconductor device 601 P-type semiconductor layer 602 N- type semiconductor layer 603 N- type semiconductor layer 603a Trench 604 P-type semiconductor region 605 N- type semiconductor region 606 Insulating film 607 First electrode 608 Second electrode 609 Third electrode 700 Semiconductor device 701 Semi-insulating layer 702 Buffer layer 703 First n-type semiconductor layer 704 Second n-type semiconductor layer 705 n+ type semiconductor layer 706 First electrode 707 Second electrode 708 Third electrode 800 Semiconductor device 801 First n+ type semiconductor layer802 n-type semiconductor layer 803 second n+ type semiconductor layer 804 first electrode 805 second electrode 806 third electrode 807 trench 900 power supply system 901 power supply device 902 power supply device 903 control circuit 910 system device 911 electronic circuit 921 inverter 922 transformer 923 rectifying MOSFET 924 DCL 925 voltage comparator 926 PWM control circuit

Claims

1. A crystalline film containing a crystalline oxide semiconductor containing gallium, wherein when the crystalline film is observed with an optical microscope, the thickness of the film is at least 1.0 mm. ２ A crystalline film that does not contain any dark or bright spots in the area.

2. A crystalline film containing a crystalline oxide semiconductor containing gallium, wherein the crystalline film does not contain particulate matter containing amorphous solids and / or crystals at least in a cross section cut in the thickness direction.

3. The crystalline film according to claim 1 or 2, wherein the crystalline oxide semiconductor has a corundum structure.

4. A semiconductor layer containing a crystalline oxide semiconductor containing gallium and an electrode, and when observed with an optical microscope, the thickness is at least 1.0 mm ２ A semiconductor device that does not contain any dark or bright spots in the area.

5. The semiconductor device according to claim 4, wherein the dark spots or the bright spots are not included in positions of the semiconductor device that overlap with the electrodes.

6. The semiconductor device according to claim 4 or 5, wherein the dark spots or the bright spots are not included in positions of the semiconductor device that do not overlap with the electrodes.

7. A method for producing a stacked structure, comprising: heating a substrate; cleaning the heated substrate; and forming a crystalline film containing a crystalline oxide semiconductor containing gallium on the cleaned substrate via an intermediate layer or directly.

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