Crystal film, laminated structure, semiconductor device, and method for manufacturing laminated structure

Abstract

The present invention addresses the problem of providing a crystal film having excellent reliability, a laminated structure, and a semiconductor device. This crystal film comprises a gallium-containing crystalline oxide semiconductor, wherein no stain is observed when said crystal film is observed with an optical microscope or a scanning electron microscope.

Description

Crystalline film, laminated structure, semiconductor device, and method for manufacturing laminated structure

[0001] The present disclosure relates to a crystalline film, a laminated structure, a semiconductor device, and a method for manufacturing the laminated structure.

[0002] Patent Document 1 discloses a crystalline oxide semiconductor film containing a crystalline oxide semiconductor having a corundum structure as a main component, the crystalline oxide semiconductor film substantially not containing cracks within a 300 μm square area of ​​the film surface.

[0003] JP 2018-002544 A

[0004] An object of the present disclosure is to provide a highly reliable crystal film, a layered structure, and a semiconductor device.

[0005] In order to solve the above problem, a crystalline film according to one embodiment of the present disclosure is a crystalline film including a crystalline oxide semiconductor containing gallium, and when the crystalline film is observed with an optical microscope or a scanning electron microscope, no stains are observed.

[0006] In order to solve the above problems, a crystalline film according to one aspect of the present disclosure is a crystalline film including a crystalline oxide semiconductor containing gallium, and the reflectance of the surface of the crystalline film is uniform.

[0007] In order to solve the above problem, a layered structure according to one aspect of the present disclosure includes the above-described crystal film.

[0008] In order to solve the above problems, a semiconductor device according to one aspect of the present disclosure includes the above-described crystal film.

[0009] In order to solve the above problem, a method for manufacturing a stacked structure according to one aspect of the present disclosure includes supplying an etching agent to a stacked structure including a crystalline oxide semiconductor containing gallium, and placing the stacked structure in a reduced pressure space and reducing the pressure of the reduced pressure space.

[0010] According to the present disclosure, it is possible to provide a crystal film, a stacked structure, or a semiconductor device with excellent reliability.

[0011] FIG. 1 is a perspective view schematically showing a crystal film according to an embodiment. FIG. 2 is a cross-sectional view schematically showing an example of a semiconductor device including a crystal film. FIG. 3 is a plan view schematically showing the semiconductor device. FIG. 4 is a flowchart showing a first example of a method for manufacturing a semiconductor device. FIG. 5 is a cross-sectional view schematically showing a substrate prepared in a manufacturing process of a semiconductor device. FIG. 6 is a cross-sectional view schematically showing a stacked structure formed in the first example of a method for manufacturing a semiconductor device. FIG. 7 is a cross-sectional view schematically showing a stacked structure formed in the first example of a method for manufacturing a semiconductor device. FIG. 8 is a cross-sectional view schematically showing a stacked structure formed in the first example of a method for manufacturing a semiconductor device. FIG. 9 is a cross-sectional view schematically showing a stacked structure formed in the first example of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view schematically showing a stacked structure formed in the first example of a method for manufacturing a semiconductor device. FIG. 11 is a schematic diagram showing an example of a film formation apparatus. FIG. 12 is a schematic diagram showing another example of a film formation apparatus. FIG. 13 is a schematic diagram showing yet another example of a film formation apparatus. FIG. 14 is a flowchart showing a second example of a method for manufacturing a semiconductor device. FIG. 15 is a cross-sectional view schematically showing a stacked structure formed in a second example manufacturing method of a semiconductor device. FIG. 16 is a cross-sectional view schematically showing a stacked structure formed in a second example manufacturing method of a semiconductor device. FIG. 17 is a cross-sectional view schematically showing a stacked structure formed in a second example manufacturing method of a semiconductor device. FIG. 18 is a cross-sectional view schematically showing a stacked structure formed in a second example manufacturing method of a semiconductor device. FIG. 19 is a front view schematically showing a pressure reducing apparatus. FIG. 20 is a flowchart showing a third example manufacturing method of a semiconductor device. FIG. 21 is a cross-sectional view schematically showing a stacked structure formed in a third example manufacturing method of a semiconductor device. FIG. 22 is a cross-sectional view schematically showing a stacked structure formed in a third example manufacturing method of a semiconductor device. FIG. 23 is a cross-sectional view schematically showing a stacked structure formed in a third example manufacturing method of a semiconductor device. FIG. 24 is a cross-sectional view schematically showing a semiconductor device of another example. FIG. 25 is a cross-sectional view schematically showing a substrate on which an intermediate layer is formed. FIG. 26 is a cross-sectional view schematically showing a stacked structure formed in a manufacturing method of a semiconductor device.FIG. 27 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 28 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 29 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 30 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 31 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 32 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 33 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 34 is a cross-sectional view schematically showing a semiconductor device of yet another example. FIG. 35 is a block diagram of an example power supply system. FIG. 36 is a block diagram of an example system device. FIG. 37 is a circuit diagram showing a power supply circuit of an example power supply device. FIG. 38 is a photograph of an example crystal film including blemishes taken using an optical microscope. FIG. 39 is a photograph of another example crystal film including blemishes taken using an optical microscope.

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The invention according to the claims is not limited to the embodiments shown below. Furthermore, not all of the combinations of the configurations described in the embodiments shown below are necessarily required to solve the problems. Furthermore, each configuration of the present disclosure is described to the extent that it does not interfere with solving the problems of the present disclosure. Note that the same components are designated by the same reference numerals to avoid redundant description.

[0013] Additionally, as will be apparent to those skilled in the art, features shown in the drawings are not necessarily drawn to scale, even if not otherwise stated herein. It should also be noted that one feature of one embodiment may be used in another embodiment. Descriptions of well-known elements and processing techniques may be omitted so as not to unnecessarily obscure the embodiments of the present disclosure. The examples used herein are merely intended to aid in the understanding of the present disclosure and further enable those skilled in the art to practice the embodiments of the present disclosure. Therefore, the embodiments and examples herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the claims and applicable law.

[0014] Terms such as "first," "second," and the like are used to describe various elements used herein, but the elements are not limited by these terms. Terms such as first, second, and the like are used only to distinguish one element from another. For example, a first element could be referred to as a second element, and a second element could be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any or all combinations of one or more of the listed items.

[0015] In this disclosure, the direction toward one side in the thickness direction of the crystal film will be described as "upper" and the direction toward the other side as "lower." Of the two main surfaces of a layer, substrate, or other member, the upper surface will be described as the upper surface, and the lower surface will be described as the lower surface. These "upper" and "lower" directions are not limited to the direction of gravity or the direction of attachment to a substrate or the like when mounting a semiconductor device. In this disclosure, viewing from above is referred to as a "planar view."

[0016] The terminology used herein is intended to describe particular embodiments only and is not intended to limit the disclosure. As used herein, the terms "comprise" and "include" each refer to the presence of the stated elements, but do not exclude the presence of one or more other elements.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs. Terms used herein should be interpreted to have a meaning that is consistent with the meaning in the context of this specification and the related art. Furthermore, unless defined herein, it should be understood that terms used herein should not be interpreted in an idealized or overly formal sense.

[0018] FIG. 1 is a perspective view schematically showing a crystal film 10 of this embodiment. The crystal film 10 is included in a semiconductor device, for example, as a semiconductor layer. The crystal film 10 has a wide bandgap semiconductor. Therefore, the crystal film 10 is particularly useful for power devices. Note that the crystal film 10 does not have to have a wide bandgap semiconductor. A semiconductor device including the crystal film 10 may be a vertical device or a horizontal device. A vertical device is a semiconductor device in which electrodes are arranged on both sides of the crystal film 10 in the thickness direction. A horizontal device is a semiconductor device in which electrodes are arranged on only one side of the crystal film 10 in the thickness direction. The semiconductor device is, for example, a diode or a transistor. More specifically, semiconductor devices formed using the crystalline film 10 include, for example, transistors such as MESFETs (metal semiconductor field effect transistors), MOSFETs (metal oxide semiconductor field effect transistors), MISFETs (metal insulating film semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), HEMTs (high electron mobility transistors), JFETs (junction field effect transistors), and SITs (static induction transistors), TFTs, SBDs (Schottky barrier diodes) and JBSs (junction barrier Schottky diodes) that utilize semiconductor-metal junctions, PN or PIN diodes combined with other P layers, LEDs (light emitting diodes), and light emitting and receiving elements.

[0019] FIG. 2 is a cross-sectional view schematically showing an example of a semiconductor device 100 including a crystal film 10. FIG. 3 is a plan view schematically showing the semiconductor device 100. The semiconductor device 100 is an SBD. The semiconductor device 100 is a power semiconductor. Note that the semiconductor device 100 may be a device other than a power semiconductor. The semiconductor device 100 includes a substrate 101, a porous layer 102, an ohmic electrode 103, a semiconductor layer 104, and a Schottky electrode 106. The semiconductor layer 104 includes the crystal film 10.

[0020] The substrate 101 is not particularly limited as long as it can support the semiconductor layer 104. In this example, the substrate 101 is conductive. Materials included in the substrate 101 include, for example, metals (e.g., aluminum, nickel, chromium, nichrome, copper, gold, silver, platinum, rhodium, indium, molybdenum, and tungsten), conductive metal oxides (e.g., ITO (InSnO compound), FTO (tin oxide doped with fluorine or the like), zinc oxide, and the like), silicon (Si), and conductive carbon.

[0021] The substrate 101 preferably contains a transition metal, and more preferably contains at least one metal selected from Group 6 metals and Group 11 metals in the periodic table. Here, "periodic table" refers to the periodic table established by the International Union of Pure and Applied Chemistry (IUPAC). The Group 6 metal is, for example, at least one metal selected from chromium (Cr), molybdenum (Mo), and tungsten (W). The Group 11 metal is, for example, at least one metal selected from copper (Cu), silver (Au), and gold (Au). The substrate 101 may contain two or more metals selected from the metals of Group 6, may contain two or more metals selected from the metals of Group 11, or may contain at least one metal selected from the metals of Group 6 and at least one metal selected from the metals of Group 11. The substrate 101 preferably contains two or more metals, and examples of such combinations of two or more metals include copper (Cu)-silver (Ag), copper (Cu)-tin (Sn), copper (Cu)-iron (Fe), copper (Cu)-tungsten (W), copper (Cu)-molybdenum (Mo), copper (Cu)-titanium (Ti), molybdenum (Mo)-lanthanum (La), molybdenum (Mo)-yttrium (Y), molybdenum (Mo)-rhenium (Re), molybdenum (Mo)-tungsten (W), molybdenum (Mo)-niobium (Nb), and molybdenum (Mo)-tantalum (Ta). The substrate 109 preferably contains molybdenum as a major component, and more preferably contains molybdenum and copper. In this disclosure, the term "major component" means that the component accounts for 50% or more of the total atomic ratio. The substrate 101 preferably contains 70% or more, and more preferably 90% or more, of Mo in terms of atomic ratio relative to the total components of the substrate. The substrate 101 may contain 100% Mo in terms of atomic ratio. That is, the substrate 101 may be formed solely from Mo. The substrate 109 may be a multi-layer substrate in which Cu layers and Mo layers are alternately stacked. In this case, the outermost layer of the substrate 109 may be either a Cu layer or a Mo layer. Furthermore, the thickness of the Mo layer may be smaller or larger than the thickness of the Cu layer. The number of layers of the substrate 109 is not limited.The substrate 101 may also contain nickel or gold on at least a portion of the surface of the substrate 109. The material of the substrate 101 is not limited.

[0022] The porous layer 102 is, for example, a porous film or a porous aggregate that is a continuous film-like structure. The porous layer 102 is disposed above the substrate 101. The porous layer 102 may be formed on the substrate 101 so as to be in contact with the substrate 101, or may be adhered to the substrate 109 via one or more other layers, such as an adhesive layer (for example, an adhesive layer made of a conductive adhesive or a metal).

[0023] The porous layer 102 may be a single layer or multiple layers. The porous layer 102 is, for example, a layer containing a metal. The porous layer 102 is preferably a metal porous layer. The porous layer 102 contains, for example, at least one precious metal selected from gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), and ruthenium (Ru). The porous layer 102 preferably contains silver (Ag), and more preferably is a silver (Ag) porous layer. The metal contained in the porous layer 102 is not limited to a precious metal and may be a metal other than the aforementioned precious metals. The porous layer 102 does not need to contain a metal, and the material of the porous layer 102 is not limited. The porous layer 102 may be a layer in which a metal film is coated on a porous substrate. The metal film is formed of, for example, the aforementioned precious metals.

[0024] The thickness of the porous layer 102 is preferably 10 nm to 1 mm, more preferably 10 nm to 200 μm, and even more preferably 30 nm to 50 μm. The thickness of the porous layer 102 is not limited.

[0025] The porosity of the porous layer 102 is preferably 10% or less. Here, "porosity" refers to the ratio of the volume of the space created by the voids to the volume of the porous layer 102 (volume including the voids). The porosity of the porous layer 102 can be determined, for example, based on a cross-sectional photograph taken using a scanning electron microscope (SEM). For example, cross-sectional photographs (SEM images) of the porous layer 102 are taken at multiple positions. Next, commercially available image analysis software is used to binarize the SEM images, and the proportion of the areas corresponding to holes (voids) in the SEM images (e.g., black areas) is determined. The proportions of the black areas determined from the SEM images taken at multiple positions are averaged to determine the porosity of the porous layer 102. The porosity of the porous layer 102 is not limited and may exceed 10%. The porous layer 102 can be suitably obtained, for example, by sintering a metal.

[0026] The ohmic electrode 103 is formed on the porous layer 102. The ohmic electrode 103 may be made of an inorganic material or an organic material. The ohmic electrode 103 may be made of a known material. The ohmic electrode 103 includes, for example, a metal. The metal included in the ohmic electrode 103 is, for example, at least one metal selected from Groups 4 to 11 and Group 13 of the periodic table. The Group 4 metal is, for example, at least one metal selected from titanium (Ti), zirconium (Zr), and hafnium (Hf). The Group 5 metal is, for example, at least one metal selected from vanadium (V), niobium (Nb), and tantalum (Ta). The Group 6 metal is, for example, at least one metal selected from chromium (Cr), molybdenum (Mo), and tungsten (W). The Group 7 metal is, for example, at least one metal selected from manganese (Mn), technetium (Tc), and rhenium (Re). The metal of Group 8 is, for example, at least one metal selected from iron (Fe), ruthenium (Ru), and osmium (Os). The metal of Group 9 is, for example, at least one metal selected from cobalt (Co), rhodium (Rh), and iridium (Ir). The metal of Group 10 is, for example, at least one metal selected from nickel (Ni), palladium (Pd), and platinum (Pt). The metal of Group 11 is, for example, at least one metal selected from copper (Cu), silver (Ag), and gold (Au). The metal of Group 13 is, for example, indium (In). The ohmic electrode 103 may be a single layer or may be formed from multiple layers. The material of the ohmic electrode 103 is not limited. The thickness of the ohmic electrode 103 is preferably 0.1 nm or more and 10 μm or less, more preferably 5 nm or more and 500 nm or less, and even more preferably 10 nm or more and 200 nm or less.

[0027] The ohmic electrode 103 is formed by, for example, a dry method or a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD (Chemical Vapor Deposition). Wet methods include, for example, screen printing, die coating, electrolytic plating, and electroless plating. The ohmic electrode 103 may be formed by forming a film by vacuum deposition, CVD, sputtering, or various coating techniques, and then patterning the film by photolithography, or by directly patterning the film using a printing technique or the like. Note that the method for forming the ohmic electrode 103 is not limited and may be any other known forming method.

[0028] The semiconductor layer 104 is formed on the ohmic electrode 103. The semiconductor layer 104 may be either an n-type semiconductor or a p-type semiconductor. In the present disclosure, an "n-type semiconductor layer" includes both a semiconductor layer used as an n-type semiconductor layer and a semiconductor layer used as an n+-type semiconductor layer. In the present disclosure, a "p-type semiconductor layer" includes both a semiconductor layer used as a p-type semiconductor layer and a semiconductor layer used as a p+-type semiconductor layer. Therefore, each of the n-type semiconductor layer and the n+-type semiconductor layer in the present disclosure can also be referred to as an n-type semiconductor layer. Furthermore, each of the p-type semiconductor layer and the p+-type semiconductor layer can also be referred to as a p-type semiconductor layer.

[0029] The semiconductor layer 104 may be a single layer or multiple layers. In this example, the semiconductor layer 104 includes a first semiconductor layer 104a and a second semiconductor layer 104b. The first semiconductor layer 104a and the second semiconductor layer 104b are each a crystal film 10. The first semiconductor layer 104a and the second semiconductor layer 104b have a common configuration. In the following description, matters common to the first semiconductor layer 104a and the second semiconductor layer 104b will be described by referring to both the first semiconductor layer 104a and the second semiconductor layer 104b as the "crystal film 10."

[0030] In this example, the first semiconductor layer 104a is an n+ type semiconductor layer. The second semiconductor layer 104b is an n- type semiconductor layer whose carrier concentration is lower than that of the first semiconductor layer 104a. In this disclosure, "carrier concentration" may be rephrased as "dopant concentration." The first semiconductor layer 104a is formed on the ohmic electrode 103. The second semiconductor layer 104b is formed on the first semiconductor layer 104a.

[0031] The crystalline film 10 includes a crystalline oxide semiconductor. The crystalline film 10 is, for example, an epitaxially grown film. The crystalline film 10 may be a homoepitaxially grown film or a heteroepitaxially grown film.

[0032] The crystalline film 10 preferably contains a crystalline oxide semiconductor as a main component. That is, the crystalline film 10 preferably contains 50% or more of the crystalline oxide semiconductor in terms of atomic ratio relative to the entire crystalline film 10. The crystalline film 10 may contain 70% or more, or 90% or more of the crystalline oxide semiconductor in terms of atomic ratio. The crystalline film 10 may also be a crystalline oxide semiconductor. That is, the crystalline film 10 may contain 100% of the crystalline oxide semiconductor in terms of atomic ratio.

[0033] The crystalline oxide semiconductor of the crystal film 10 contains gallium. The atomic ratio of gallium to all metal elements contained in the crystalline oxide semiconductor may be 50% or more, 70% or more, or 90% or more. In addition to gallium, the crystalline oxide semiconductor may contain one or more metals selected from Group 9 of the periodic table (e.g., cobalt, rhodium, iridium, etc.) and Group 13 other than gallium (e.g., aluminum, indium, etc.). The crystalline oxide semiconductor may contain, in addition to gallium, one or more metals selected from iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). The crystalline oxide semiconductor may contain, in addition to gallium, at least one metal selected from aluminum and indium. The crystalline oxide semiconductor is preferably a mixed crystal containing two or more metal oxides. The crystalline oxide semiconductor may contain, in addition to gallium, at least one metal selected from Ga ２ O ３ Or a mixed crystal thereof is preferred.

[0034] The crystalline oxide semiconductor of the crystal film 10 may be single crystal or polycrystalline. The crystalline oxide semiconductor is preferably single crystal. The crystalline structure of the crystalline oxide semiconductor is, for example, a corundum structure, a β-gallium structure, a hexagonal structure (for example, an ε-type structure), an orthorhombic structure (for example, a κ-type structure), a cubic structure, or a tetragonal structure. The crystalline oxide semiconductor preferably has a corundum structure. It is more preferable that the crystalline oxide semiconductor has a corundum structure and that the principal surface is an m-plane or a c-plane. The crystalline oxide semiconductor may or may not have an off-axis angle. The crystalline oxide semiconductor is an α-Ga ２ O ３ Or, more preferably, it is a mixed crystal thereof.

[0035] The crystal film 10 may contain a dopant. The dopant may be a known dopant. The dopant may be, for example, an n-type dopant such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or a p-type dopant such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The content of the dopant in the composition of the crystal film 10 is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic % or less, and even more preferably 0.00001 atomic % to 10 atomic % or less. The carrier concentration of the crystal film 10 may be, for example, 1×10 １６ / cm ３ 1x10 or more ２２ / cm ３ The carrier concentration of the crystal film 10 is 1×10 １６ / cm ３ It may be less than 1×10 ２２ / cm ３ The carrier concentration of the crystal film 10 may exceed 1×10 １７ / cm ３ The crystal film 10 may not contain a dopant.

[0036] The thickness of the crystal film 10 is, for example, 1 μm or more. The thickness of the crystal film 10 is preferably 10 μm or more. The surface area of ​​the crystal film 10 is, for example, 1 mm ２ The surface area of ​​the crystal film 10 is 10 mm ２ More than 300cm ２ It is preferable that the thickness is less than 100 mm. ２ More than 300cm ２ The thickness of the crystal film 10 is not limited, and may be less than 1 μm. The surface area of ​​the crystal film 10 is preferably less than 1 mm. ２ It may be less than.

[0037] The second semiconductor layer 104b may include, for example, multiple regions having different carrier concentrations. In this example, the second semiconductor layer 104b includes a first region 105a and a second region 105b having different carrier concentrations. The carrier concentration of the second region 105b is lower than the carrier concentration of the first region 105a. The second semiconductor layer 104b may also be formed from only one region having a substantially uniform carrier concentration.

[0038] The upper surface of the first region 105a forms a part of the upper surface of the second semiconductor layer 104b, and the lower surface of the first region 105a forms the entire lower surface of the second semiconductor layer 104b.

[0039] The second region 105b is the remaining region of the second semiconductor layer 104b excluding the first region 105a. The second region 105b functions, for example, as a guard ring that increases the breakdown voltage of the semiconductor device 100. The top surface of the second region 105b forms part of the top surface of the second semiconductor layer 104b. The second region 105b extends downward from the top end of the second semiconductor layer 104b.

[0040] The depth of the second region 105b is, for example, 1.0 μm or more. The depth of the second region 105b is preferably 1.2 μm or more, and more preferably 1.5 μm or more. The depth of the second region 105b may be less than 1.0 μm. The second region 105b is formed, for example, in a ring shape in a planar view. The shape of the second region 105b in a planar view may be a circular ring or a rectangular ring. The shape of the second region 105b is not limited. The second region 105b may be formed as a continuous, continuous region in a planar view, or may be formed from multiple discontinuous regions. When the second region 105b is formed from multiple discontinuous regions, the second region 105b may be striped in a planar view, or each of the multiple regions may be L-shaped, dot-shaped, or bar-shaped. Furthermore, the second region 105b may be a region that contacts the first region 105a, or may be a region that is adjacent to the first region 105a via another region. When the second region 105b contacts the first region 105a, there may or may not be a clear boundary between the first region 105a and the second region 105b.

[0041] The second region 105b is a region containing, for example, an oxide as a main component. The oxide preferably contains gallium, and Ga ２ O ３ or Ga ２ O ３ and other metal oxides or Ga ２ O ３ The oxide may be a crystalline oxide semiconductor, but is preferably a microcrystalline oxide, and more preferably contains an amorphous material or is amorphous. Note that the second region 105b may contain both a crystalline semiconductor and an amorphous material.

[0042] When the oxide contained as a main component in the second region 105b includes a crystalline oxide semiconductor, the crystal structure of the crystalline oxide is, for example, a corundum structure, a β-gallia structure, a hexagonal structure (e.g., an ε-type structure), an orthorhombic structure (e.g., a κ-type structure), a cubic structure, or a tetragonal structure. The crystalline oxide semiconductor preferably has a corundum structure, a β-gallia structure, or a hexagonal structure (e.g., an ε-type structure), and more preferably has a corundum structure. The crystal structure of the crystalline oxide semiconductor in the second region 105b may be the same as or different from the crystal structure of the crystalline oxide semiconductor in the first region 105a.

[0043] At least one of the first region 105a and the second region 105b may contain a dopant. The dopant contained in each of the first region 105a and the second region 105b may be, for example, the dopant contained in the crystal film 10 described above. The first region 105a and the second region 105b may contain the same dopant. The dopant contained in each of the first region 105a and the second region 105b is preferably tin. The carrier concentration of the second semiconductor layer 104b may be approximately uniform. In this case, the carrier concentration in the first region 105a and the carrier concentration in the second region 105b are each approximately uniform. The first region 105a and the second region 105b are preferably included in the same semiconductor layer. Note that the same semiconductor layer refers to a semiconductor layer having approximately the same carrier concentration, and may be expressed as a single layer.

[0044] The second region 105b may contain an impurity other than a dopant. The second region 105b may contain only a dopant, or only an impurity, or both a dopant and an impurity. The impurity is introduced into the second region 105b by, for example, ion implantation. The impurity includes an element different from the element constituting the main component of the second region 105b. The maximum concentration of the impurity contained in the second region 105b is preferably greater than the maximum concentration of the impurity contained in the first region 105a. The concentration of the impurity contained in the second region 105b is, for example, 1.0×10 １５ / cm３ Above 1.0 x 10 ２２ / cm ｓ The elements contained in the impurities are described below. In this disclosure, the elements contained in the impurities may be referred to as "impurity elements." The elements contained in the second region 105b excluding the impurity elements may be the same as the elements contained in the first region 105a.

[0045] The impurity element is contained in the second region 105b as a single element, for example. The impurity element may be contained in the second region 105b as part of a compound. Only one element or multiple elements may be selected as the impurity element. The impurity element is preferably selected from elements that do not function as donors or acceptors to gallium oxide. The impurity element is preferably one that can relatively easily adjust the amount of damage to a crystalline oxide semiconductor containing gallium when ion-implanted. Factors that affect the amount of damage include the mass number of the impurity element and the value of implantation energy. If the mass number of the impurity element is too small, the region through which the ion-implanted impurity passes within the crystal mainly composed of gallium oxide is hardly damaged. Therefore, the region that can be damaged is far from the lower surface of the Schottky electrode 106, making it difficult to improve the breakdown voltage of the semiconductor device 100. If the mass number of the impurity element is too large, the increased amount of damage may result in excessive crystal defects, potentially deteriorating the breakdown voltage of the semiconductor device 100. Furthermore, the larger the mass number of the impurity element, the greater the required implantation energy, which places constraints on the load and configuration of the ion implantation device, making it industrially disadvantageous. Considering these factors, the impurity element is preferably a metal element with a mass number greater than Mg, and more preferably aluminum (Al). The ion implantation may be a box profile or a single profile. According to the present disclosure, even a single profile can improve the breakdown voltage of a semiconductor device. The impurity element is not limited.

[0046] The second region 105b may be a high-resistance layer. The high-resistance layer may be, for example, SiO ２The high-resistance layer is formed, for example, by forming a trench on the upper surface of the second semiconductor layer 104b and depositing the high-resistance layer in the trench by a method such as sputtering, vacuum deposition, coating, CVD, atmospheric pressure CVD, plasma CVD, or mist CVD. The second region 105b may be a p-type semiconductor.

[0047] The Schottky electrode 106 is formed on the semiconductor layer 104. The Schottky electrode 106 may be a single layer or may be formed of multiple layers. The Schottky electrode 106 preferably contacts the first region 105a and the second region 105b. The Schottky electrode 106 may be made of an inorganic material or an organic material. The Schottky electrode 106 includes, for example, a metal. The metal included in the Schottky electrode 106 is, for example, at least one metal selected from Groups 4 to 11 of the periodic table. The Group 4 metal is, for example, at least one metal selected from titanium (Ti), zirconium (Zr), and hafnium (Hf). The Group 5 metal is, for example, at least one metal selected from vanadium (V), niobium (Nb), and tantalum (Ta). The Group 6 metal is, for example, at least one metal selected from chromium (Cr), molybdenum (Mo), and tungsten (W). The Group 7 metal is, for example, at least one metal selected from manganese (Mn), technetium (Tc), and rhenium (Re). The Group 8 metal is, for example, at least one metal selected from iron (Fe), ruthenium (Ru), and osmium (Os). The Group 9 metal is, for example, at least one metal selected from cobalt (Co), rhodium (Rh), and iridium (Ir). The Group 10 metal is, for example, at least one metal selected from nickel (Ni), palladium (Pd), and platinum (Pt). The Group 11 metal is, for example, at least one metal selected from copper (Cu), silver (Ag), and gold (Au). The Schottky electrode 106 preferably contains molybdenum and / or cobalt. Note that the material of the Schottky electrode 106 is not limited to the metals described above.

[0048] The thickness of the Schottky electrode 106 is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and even more preferably 10 nm to 200 nm.

[0049] By providing the Schottky electrode 106 with such a preferable configuration, it is possible to obtain a semiconductor device having excellent Schottky characteristics and also to more effectively suppress leakage current. Note that the thickness of the Schottky electrode 106 is not limited to the thickness described above.

[0050] The Schottky electrode 106 is formed by, for example, the dry method or the wet method described above. Note that the method for forming the Schottky electrode 106 is not limited thereto, and other known forming methods may also be used.

[0051] When a forward voltage is applied to the semiconductor device 100, electrons flow from the ohmic electrode 103 to the Schottky electrode 106. When a reverse voltage is applied to the semiconductor device 100, a depletion layer spreads into the first semiconductor layer 104a. As a result, the semiconductor device 100 becomes a high-voltage SBD.

[0052] Next, the crystalline film 10 will be described in detail. The crystalline film 10 is a film that does not contain stains when observed with an optical microscope or an electron microscope. A "stain" is a stain that has the appearance of, for example, a liquid or the like partially seeping in.

[0053] When checking for stains on the crystal film 10, the crystal film 10 may be observed while it is included in the semiconductor device 100 or the stacked structure, or after it has been removed from other components of the semiconductor device 100. The crystal film 10 may be observed as a whole from any direction, for example, using an optical microscope or an electron microscope. The observation direction of the crystal film 10 using an optical microscope or an electron microscope is, for example, the same direction as the thickness direction of the crystal film 10. The observation direction of the crystal film 10 is not limited. The observation direction of the crystal film 10 may be a direction oblique to the thickness direction of the semiconductor layer 104. For example, when a portion of the crystal film 10 is externally hidden by an opaque member such as the substrate 101 or an electrode, as in the case of the crystal film 10 included in the semiconductor device 100, the crystal film 10 may be observed from a direction facing the surface with a large exposed area of ​​the crystal film 10, or the crystal film 10 may be observed after the opaque member is removed to increase the exposed area of ​​the crystal film 10. For example, when a portion of the top surface of the crystal film 10 is hidden by an electrode, the crystal film 10 may be observed from below.

[0054] The optical microscope may be a normal optical microscope that uses natural light to illuminate a sample, or a polarizing microscope that uses polarized light to illuminate a sample for observation. In this case, the illumination method used may be, for example, incident illumination, oblique illumination, or ring illumination. The electron microscope may be, for example, a SEM.

[0055] The stains appear, for example, on the surface of the crystalline film 10 or in the crystalline film 10. When the stains are present in the crystalline film 10, they may or may not be exposed on the surface of the crystalline film 10. The stains may contain elements not contained in crystalline oxide semiconductors, or may contain elements contained in crystalline oxide semiconductors. The elements not contained in crystalline oxide semiconductors are, for example, elements contained in etching solutions, cleaning solutions, gases, manufacturing equipment, etc. used in the manufacture of the semiconductor device 100. The stains may be regions of the crystalline film 10 that contain one or more elements selected from phosphorus (P), aluminum (Al), carbon (C), silicon (Si), fluorine (F), and silver (Ag).

[0056] For example, when observing the crystal film 10 with an optical microscope, the light reflectance of the stains is different from the light reflectance of the portions of the crystal film 10 other than the stains. The light reflectance of the stains is, for example, smaller than the light reflectance of the portions of the crystal film 10 other than the stains. The light reflectance of the surface of the crystal film 10 may be uniform across the entire surface. "The light reflectance of the surface of the crystal film 10 is uniform" can also be rephrased as meaning that the surface of the crystal film 10 does not contain any stains when observed with an optical microscope. In the present disclosure, "uniform" includes not only strictly uniform but also substantially uniform. "The light reflectance of the surface of the crystal film 10 is uniform" includes the difference between the minimum and maximum light reflectance of the surface of the crystal film 10 being within ±10% of the average light reflectance of the entire surface of the crystal film 10. It is preferable that the difference between the minimum and maximum light reflectance of the surface of the crystal film 10 be within ±5% of the average light reflectance of the entire surface of the crystal film 10.

[0057] The darkness of the blemish may be the same throughout the blemish or may vary depending on the part of the blemish, i.e., the light reflectance of the blemish may be uniform throughout the blemish or may vary depending on the part of the blemish.

[0058] The outline of a blemish may be blurred or clear. In other words, the reflectance of the blemish may gradually decrease toward the surrounding area other than the blemish, or may be significantly different from the reflectance of the area other than the blemish. Furthermore, the reflectance of the outline of a blemish may be uniform across the entire outline, or may vary depending on the part of the outline.

[0059] The blemishes preferably have a diameter of 0.1 μm or more. That is, the crystal film 10 preferably does not contain blemishes with a diameter of 0.1 μm or more. The blemishes may be 0.3 μm or more, or may be 0.5 μm or more. Here, "not containing blemishes with a diameter of 0.1 μm or more" means that the crystal film 10 does not contain blemishes that can be observed with an optical microscope or an electron microscope, and that even if the crystal film 10 contains blemishes, the diameter of the blemishes is less than 0.1 μm. Furthermore, "diameter" does not limit the shape of the blemish to a circular shape. That is, a blemish with a diameter of 0.1 μm or more means a blemish having an area equal to or greater than the area of ​​a circle with a diameter of 0.1 μm. The same applies to blemishes with a diameter of 0.3 μm or more and blemishes with a diameter of 0.5 μm or more.

[0060] When the semiconductor device 100 incorporating the crystalline film 10 is observed with an optical microscope or a scanning electron microscope, it is preferable that the semiconductor device 100 does not contain any stains at positions that overlap with the electrodes. In this case, voltage is less likely to be applied to defective portions with stains, making it possible to reduce the likelihood of malfunctions in the semiconductor device 100. When the semiconductor device 100 is observed with an optical microscope or a scanning electron microscope, it is not necessary that the stains be contained at positions that do not overlap with the electrodes. It is even more preferable that the stacked structure or semiconductor device 100 incorporating the crystalline film 10 does not contain any stains.

[0061] (Method for Manufacturing Semiconductor Device) Next, a method for manufacturing the semiconductor device 100 will be described.

[0062] (First Example) FIG. 4 is a flowchart showing a first example of a method for manufacturing the semiconductor device 100. FIG. 5 is a cross-sectional view schematically showing a base 107 used in manufacturing the semiconductor device 100. FIGS. 6 to 10 are cross-sectional views schematically showing a stacked structure 1 formed during the manufacturing process of the semiconductor device 100. The manufacturing method for the semiconductor device 100 of the first example includes a first step of preparing the base 107, a second step of forming a semiconductor layer 104 (crystal film 10) on the base 107, a third step of forming a second region 105b in the semiconductor layer 104, a fourth step of forming a Schottky electrode 106 on the semiconductor layer 104, a fifth step of removing the base 107 from the stacked structure 1 including the base 107 and the semiconductor layer 104, a sixth step of forming an ohmic electrode 103 on the semiconductor layer 104, and a seventh step of attaching a substrate 101 to the ohmic electrode 103 via a porous layer 102.

[0063] In the first step, for example, a base 107 as shown in FIG. 5 is prepared. The base 107 is not particularly limited as long as it can support the semiconductor layer 104. Examples of the shape of the base 107 include a plate-like shape such as a flat plate or a disk, a fiber-like shape, a rod-like shape, a column-like shape, a prism-like shape, a tube-like shape, a spiral-like shape, a sphere-like shape, and a ring-like shape. In this example, the base 107 is a substrate. The shape of the base 107 is not particularly limited. Furthermore, the thickness of the base 107 is not particularly limited.

[0064] The base 107 is preferably, for example, a crystal growth substrate suitable for crystal growth of a film that will become the semiconductor layer 104. Although the base 107 is an insulating substrate, it may be a semiconductor substrate or a conductive substrate.

[0065] The substrate 107 may be a single crystal substrate or a polycrystalline substrate. The material of the substrate 107 may be an organic compound or an inorganic compound. The substrate 107 may be, for example, a sapphire substrate, a gallium oxide substrate, or a Ga ２ O ３ and Al ２ O ３ and a mixed crystal substrate containing the above.

[0066] The substrate 107 is preferably a substrate containing a material having a corundum structure, a substrate containing a material having a β-gallia structure, or a substrate containing a material having a hexagonal crystal structure. The substrate 107 preferably contains a substrate material having a corundum structure, a β-gallia structure, or a hexagonal crystal structure as its main component, and particularly preferably contains a material having a corundum structure as its main component. The substrate 107 may contain 70% or more, or 90% or more, of a material having a corundum structure, a β-gallia structure, or a hexagonal crystal structure. The substrate 107 may be formed solely from a material having a corundum structure, a β-gallia structure, or a hexagonal crystal structure.

[0067] Examples of materials having a corundum structure include α-Al ２ O ３ (sapphire substrate) or α-Ga ２ O ３ The substrate 107 having a corundum structure is, for example, an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, or an α-type gallium oxide substrate (a-plane, m-plane, or r-plane). The substrate 107 having a β-gallium oxide structure is, for example, a β-Ga ２ O ３ Substrate, or Ga ２ O ３ and Al ２ O ３ and Al ２ O ３ % or more and 60 wt % or less. The substrate 107 having a hexagonal crystal structure is, for example, a SiC substrate, a ZnO substrate, or a GaN substrate.

[0068] 6, for example, a semiconductor layer 104 is formed on a substrate 107. The semiconductor layer 104 includes a first semiconductor layer 104a and a second semiconductor layer 104b. The semiconductor layer 104 can be formed by, for example, a CVD method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, a MOVPE (Metalorganic Vapor-phase Epitaxy) method, a mist CVD method, a mist epitaxy method, a MBE (Molecular Beam Epitaxy) method, a HVPE (Hydride Vapor Phase Epitaxy) method, a pulse growth method, an ALD method, or any other known method. By carrying out the second step, a stacked structure 1 including the base 107 and the semiconductor layer 104 is formed. The semiconductor layer 104 may be formed directly on the base 107, or may be formed on the base 107 via another layer. The other layer may be, for example, a stress relaxation layer (e.g., a buffer layer, an ELO layer, etc.) and / or a peeling sacrificial layer.

[0069] In the third step, for example, as shown in FIG. 7, a second region 105b is formed in the semiconductor layer 104. In the third step, for example, the second region 105b is formed by ion-implanting an impurity element into the semiconductor layer 104. Specifically, a mask is formed on a portion of the upper surface of the semiconductor layer 104, and then the impurity element is ion-implanted into the portion of the semiconductor layer 104 that is not covered by the mask. The mask is, for example, an oxide film such as a p-teos film. The mask is formed, for example, by forming a mask layer on the semiconductor layer 104 and removing a portion of the mask layer. In other words, the mask is the remaining portion of the mask layer excluding the removed portion. When removing the portion of the mask layer, for example, an etchant is used. The etchant is preferably a wet etchant containing hydrofluoric acid such as buffered hydrofluoric acid. In this case, α-Ga ２ O ３It is also expected that the etching agent will not easily damage the semiconductor layer 104 containing the impurity. The material of the etching agent is not limited, and may be, for example, sulfuric acid. The impurity is implanted into the second semiconductor layer 104b to a depth of 1.0 μm or more from the upper surface of the second semiconductor layer 104b. The element to be ion-implanted is, for example, Al. The implantation energy when the element is ion-implanted into the second semiconductor layer 104b is, for example, 1500 keV or more and 3000 keV or less. The dose of Al is, for example, 1.0×10 １３ atoms / cm ２ Above 4.0 x 10 １４ atoms / cm ２ or less. The implantation beam current is, for example, 140 nA or more and 260 nA or less. The implantation time is, for example, 83.0 sec or more and 253.0 sec or less. The apparatus used is, for example, an apparatus with a maximum implantation energy of 8 MeV. Note that the element to be ion-implanted does not have to be Al, and an element having a mass number greater than that of Mg may also be used.

[0070] The region of the second semiconductor layer 104b into which ions have been implanted and the region through which the implanted elements have passed become the second region 105b. For example, the maximum concentration of the impurity element contained in the second region 105b is greater than the maximum concentration of the impurity element contained in the first region 105a. In this case, the carrier concentration of the second region 105b is lower than the carrier concentration of the first region 105a.

[0071] In the third step, after the second region 105b is formed in the semiconductor layer 104, the mask on the semiconductor layer 104 is removed. For example, an etching agent is used to remove the mask. The etching agent is preferably a wet etching agent containing hydrofluoric acid such as buffered hydrofluoric acid. In this case, α-Ga ２ O ３ It is also expected that the etching agent will not easily damage the semiconductor layer 104 containing the etchant. The material of the etching agent is not limited, and may be, for example, sulfuric acid.

[0072] 8, for example, a Schottky electrode 106 is formed on the semiconductor layer 104 in which the second region 105b is formed. The Schottky electrode 106 is formed by, for example, the dry method or wet method described above. The fourth step may include a pre-cleaning step, an electrode layer forming step, a resist forming step, an etching step, and a resist removing step, which will be described later.

[0073] The pre-cleaning step is a step of cleaning the stacked structure 1. In the pre-cleaning step, the top surface of the semiconductor layer 104 shown in FIG. 7 is cleaned using a wet etching agent containing hydrofluoric acid, such as buffered hydrofluoric acid. That is, the pre-cleaning step is an example of supplying an etching agent to the stacked structure 1. The material of the etching agent used for cleaning is not limited. Furthermore, the agent used for cleaning is not limited to an etching agent. Furthermore, the pre-cleaning step may also serve as a step of removing the mask in the third step.

[0074] The electrode layer forming step is performed after the pre-cleaning step. In the electrode layer forming step, an electrode layer is formed on the semiconductor layer 104. A part of the electrode layer thus formed forms the Schottky electrode 106. In the electrode layer forming step, the electrode layer is formed by, for example, vapor deposition.

[0075] The resist forming step is performed after the electrode layer forming step. In the resist forming step, a resist is formed on a portion of the upper surface of the electrode layer that will become the Schottky electrode 106. The resist is formed, for example, through the steps of applying the resist onto the electrode layer, exposing it to light, and developing it.

[0076] The etching process is performed after the resist formation process. In the etching process, the portions of the electrode layer that are not covered by the resist are etched. The Schottky electrode 106 is formed by the electrode layer etched in this manner. That is, the remaining unetched portions of the electrode layer become the Schottky electrode 106. The electrode layer is etched using, for example, an etching agent. The etching agent is, for example, a wet etching agent containing phosphoric acid, such as a phosphoric acid solution. That is, the etching process is an example of supplying an etching agent to the stacked structure 1. Note that an etching agent containing phosphoric acid is particularly suitable for etching an electrode layer containing aluminum. The resist removal process is performed after the etching process. In the resist removal process, the resist on the Schottky electrode 106 is removed.

[0077] In a fifth step, the semiconductor layer 104 and the Schottky electrode 106 in the stacked structure 1 are peeled off from the base 107. The semiconductor layer 104 and the Schottky electrode 106 are peeled off from the base 107 using, for example, a known peeling means. By peeling off the semiconductor layer 104 and the Schottky electrode 106 from the base 107, the surface of the semiconductor layer 104 opposite to the Schottky electrode 106 is exposed as shown in FIG.

[0078] 10 , for example, the ohmic electrode 103 is formed on the surface of the semiconductor layer 104 opposite to the Schottky electrode 106, i.e., on the surface exposed by peeling off the base 107. The ohmic electrode 103 is formed on the semiconductor layer 104 by, for example, the dry method or wet method described above.

[0079] In the seventh step, for example, the substrate 101 is laminated on the surface of the ohmic electrode 103 opposite to the semiconductor layer 104 via the porous layer 102. In this way, the semiconductor device 100 as shown in FIG.

[0080] In the first example manufacturing method, the third step of forming the second region 105b in the semiconductor layer 104 is performed before the seventh step of joining the porous layer 102 to the ohmic electrode 103. This prevents the chemical solution, such as the etching agent, used in the third step from penetrating into the pores of the porous layer 102. This prevents stains from being formed on the semiconductor layer 104 due to the chemical solution, such as the etching agent, that has entered the porous layer 102.

[0081] Furthermore, in the manufacturing method of the first example, the fourth step of forming the Schottky electrode 106 on the semiconductor layer 104 is performed before the seventh step of joining the porous layer 102 to the ohmic electrode 103. This prevents the chemical solution, such as the etching agent, used in the fourth step from penetrating into the pores of the porous layer 102. This further prevents stains from being formed due to the chemical solution, such as the etching agent, penetrating into the porous layer 102.

[0082] In the second step, the semiconductor layer 104 is preferably formed by mist CVD, mist epitaxy, or HVPE. The film formation step using mist CVD or mist epitaxy, and the film formation step using HVPE will be described below in order.

[0083] The film formation process using the mist CVD method or the mist epitaxy method includes, for example, atomizing a raw material solution containing a metal to generate mist or atomized droplets (hereinafter, this process will be referred to as the "atomization process"), and transporting the obtained atomized droplets to the vicinity of the substrate 107 by a carrier gas, and reacting the atomized droplets to form the semiconductor layer 104 on the substrate 107 (hereinafter, this process will be referred to as the "film formation process").

[0084] The raw material solution used in the atomization step contains the metal contained in the semiconductor layer 104. The raw material solution may contain an inorganic material or an organic material.

[0085] The source solution can be preferably a solution in which the metal contained in the semiconductor layer 104 is dissolved or dispersed in an organic solvent or water in the form of a complex or salt. Examples of the complex include an acetylacetonate complex, a carbonyl complex, an ammine complex, and a hydride complex. Examples of the salt include an organic metal salt (e.g., a metal acetate, a metal oxalate, a metal citrate), a metal sulfide, a metal nitrate, a metal phosphate, or a metal halide (e.g., a metal chloride, a metal bromide, a metal iodide).

[0086] The raw material solution may contain additives such as hydrohalic acid or an oxidizing agent. The hydrohalic acid may be, for example, hydrobromic acid, hydrochloric acid, or hydroiodic acid. The oxidizing agent may be, for example, hydrogen peroxide (H ２ O ２ ), sodium peroxide (Na ２ O ２ ), barium peroxide (BaO ２ ) or benzoyl peroxide (C ６ H ５ CO) ２ O ２ or organic peroxides such as hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid, or nitrobenzene. The raw material solution may contain the above-mentioned dopant.

[0087] The solvent for the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. The solvent preferably contains water, and more preferably is water or a mixed solvent of water and alcohol.

[0088] In the atomization process, a raw material solution containing a metal is prepared, and the prepared raw material solution is atomized. As a result, atomized droplets are suspended. The atomization means for atomizing the raw material solution is not particularly limited and may be a known means. The atomization means is preferably a means for atomizing the raw material solution using ultrasonic vibrations. The atomized droplets generated in the atomization process are suspended in the air, and are preferably droplets that are not sprayed like a spray, for example, but have an initial velocity of zero and float in space and can be transported as a gas. The size of the atomized droplets is not particularly limited and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 1 μm or more and 10 μm or less.

[0089] In the film forming process, the atomized droplets are carried to the substrate 107 by a carrier gas. Examples of the carrier gas include oxygen, ozone, an inert gas (such as nitrogen or argon), or a reducing gas (such as hydrogen gas or forming gas). The type of carrier gas may be one type, or two or more types. The type of carrier gas is not particularly limited.

[0090] As the carrier gas, a dilution gas with a changed carrier gas concentration (e.g., a 10-fold diluted gas) may be further used as a second carrier gas. The number of carrier gas supply points may be one or more, and may be two or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 L / min to 20 L / min, and more preferably 1 L / min to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 L / min to 2 L / min, and more preferably 0.1 L / min to 1 L / min.

[0091] In the film formation process, the atomized droplets react on the substrate 107 to form a semiconductor layer 104 on the substrate 107. The reaction is not particularly limited as long as it forms a film from the atomized droplets, but a thermal reaction is preferred. The thermal reaction is not particularly limited as long as the atomized droplets react due to heat, and the reaction conditions are not particularly limited. The thermal reaction is typically carried out at a temperature equal to or higher than the evaporation temperature of the solvent in the raw material solution, but a relatively low temperature is preferred. Specifically, it is preferably carried out at a temperature of 650°C or lower, and more preferably at a temperature of 300°C to 650°C. The thermal reaction may be carried out under vacuum, in a non-oxygen atmosphere, in a reducing gas atmosphere, or in an oxygen atmosphere, and may be carried out under atmospheric pressure, pressurized pressure, or reduced pressure. The thermal reaction is preferably carried out under atmospheric pressure, as this simplifies the calculation of the evaporation temperature and simplifies the equipment. The film thickness of the semiconductor layer 104 formed in the film formation process can be set by adjusting the film formation time.

[0092] After the film formation process, an annealing treatment may be performed. The annealing temperature is, for example, 300°C or higher and 650°C or lower. The annealing temperature is preferably 350°C or higher and 550°C or lower. The annealing temperature is not limited to the above-mentioned temperature. The annealing time is, for example, 1 minute or higher and 48 hours or lower. The annealing time is preferably 10 minutes or higher and 24 hours or lower, and more preferably 30 minutes or higher and 12 hours or lower. The annealing time is not limited to the above-mentioned time. The annealing treatment may be performed in any atmosphere as long as it does not impede the objectives of the present disclosure. The annealing may be performed in a non-oxygen atmosphere or an oxygen atmosphere. Examples of the non-oxygen atmosphere include an inert gas atmosphere (e.g., a nitrogen atmosphere) or a reducing gas atmosphere. The annealing treatment is preferably performed in an inert gas atmosphere or a nitrogen atmosphere.

[0093] 11 is a schematic diagram showing a film formation apparatus 30 used in the mist CVD method or the mist epitaxy method. The film formation apparatus 30 includes a carrier gas source 32a for supplying a carrier gas, a flow rate control valve 33a for adjusting the flow rate of the carrier gas delivered from the carrier gas source 32a, a carrier gas source 32b for supplying a carrier gas (diluted), i.e., a diluted carrier gas, a flow rate control valve 33b for adjusting the flow rate of the carrier gas (diluted) delivered from the carrier gas source 32b, an atomized droplet generating source 34 containing a raw material solution 34a, a container 35 for containing water 35a, an ultrasonic vibrator 36 attached to the bottom of the container 35, a film formation chamber 37, a supply pipe 38 connecting the atomized droplet generating source 34 and the film formation chamber 37, and a hot plate (heater) 39 installed in the film formation chamber 37. The film formation chamber 37 is provided with an exhaust port 37a for discharging the atomized droplets and exhaust gas after reaction.

[0094] A substrate 107 is placed on the hot plate 39. The raw material solution 34a is contained in the atomized droplet generating source 34. In this state, the hot plate 39 is operated, and the temperature inside the film formation chamber 37 is increased by the hot plate 39. Next, the flow rate control valves 33a, 33b are opened, and a carrier gas and a carrier gas (diluted) are supplied from the carrier gas sources 32a, 32b into the film formation chamber 37. After the atmosphere in the film formation chamber 37 is sufficiently replaced with the carrier gas and the carrier gas (diluted), the flow rates of the carrier gas and the carrier gas (diluted) are adjusted, respectively. Next, the ultrasonic vibrator 36 is driven, causing the ultrasonic vibrator 36 to vibrate. The vibration of the ultrasonic vibrator 36 is propagated to the raw material solution 34a through the water 35a. As a result, the raw material solution 34a is atomized, generating atomized droplets 34b. The atomized droplets 34b are introduced into the film-forming chamber 37 by the carrier gas and the carrier gas (diluted), and then transported to the vicinity of the substrate 107. Then, the atomized droplets 34b undergo a thermal reaction in the film-forming chamber 37 under atmospheric pressure, and a semiconductor layer 104 (crystal film 10) is formed on the substrate 107.

[0095] FIG. 12 is a schematic diagram showing another example of a film formation apparatus 40 used in a mist CVD method or a mist epitaxy method. Similar to the film formation apparatus 30, the film formation apparatus 40 includes a carrier gas source 32a, a flow rate control valve 33a, a carrier gas source 32b, a flow rate control valve 33b, an atomized droplet generating source 34, a container 35, and an ultrasonic vibrator 36. Additionally, the film formation apparatus 40 includes a supply pipe 42 through which atomized droplets are supplied from the atomized droplet generating source 34, a susceptor 41 provided within the supply pipe 42, and a heater 43 installed around the supply pipe 42. The supply pipe 42 essentially forms a film formation chamber. The supply pipe 42 is provided with an exhaust port 42a for discharging atomized droplets and exhaust gas after reaction. The susceptor 41 has a mounting surface on which a substrate 107 is placed. The mounting surface is inclined relative to a horizontal plane. The film forming apparatus 40 can be handled in the same manner as the film forming apparatus 30 described above.

[0096] On the other hand, a film formation process using the HVPE method includes, for example, gasifying a metal source containing a metal to generate a metal-containing source gas (hereinafter, this process is referred to as the "gasification process"), and supplying the metal-containing source gas and the oxygen-containing source gas to a crystalline substrate 107 placed in a reaction chamber, and forming a semiconductor layer 104 on the substrate 107 by epitaxial growth of crystals (hereinafter, this process is referred to as the "film formation process"). In the film formation process, a reactive gas may be supplied to the substrate 107 in addition to the metal-containing source gas and the oxygen-containing source gas.

[0097] 13 is a schematic diagram showing an example of a film formation apparatus (HVPE apparatus) 50 used in the HVPE method. The film formation apparatus 50 includes a reaction chamber 51, heaters 52a and 52b, a metal-containing source gas supply pipe 53b, and an oxygen-containing source gas supply pipe 55b. The film formation apparatus 50 may further include a reactive gas supply pipe 54b.

[0098] A metal source 57 and a substrate 107 are placed in the reaction chamber 51. The substrate 107 is held by, for example, a holder 56 provided in the reaction chamber 51. Note that the substrate 107 is not shown in FIG. 13 . A protective sheet 58 for preventing the precipitation of reactants may be provided on the inner wall of the reaction chamber 51. The heater 52 a heats the metal source 57. The heater 52 b heats the substrate 107.

[0099] The metal-containing source gas supply pipe 53b and the oxygen-containing source gas supply pipe 55b are provided in the reaction chamber 51. The metal-containing source gas supply pipe 53b is provided in the reactive gas supply pipe 54b. The reactive gas supply pipe 54b and the metal-containing source gas supply pipe 53b form a double-pipe structure. The metal-containing source gas supply pipe 53b is connected to a halogen-containing source gas supply source 53a. A metal source 57 is provided in the metal-containing source gas supply pipe 53b. The halogen-containing source gas from the halogen-containing source gas supply source 53a is supplied to the metal-containing source gas supply pipe 53b. The halogen-containing source gas is supplied to the metal source 57 and becomes a metal-containing source gas. The metal-containing source gas is supplied to the substrate 107 via the metal-containing source gas supply pipe 53b. The oxygen-containing source gas supply pipe 55b is connected to the oxygen-containing source gas supply source 55a. The oxygen-containing source gas from the oxygen-containing source gas supply source 55a is supplied to the substrate 107 via an oxygen-containing source gas supply pipe 55b.

[0100] The metal source 57 is not particularly limited as long as it can be gasified, and may be a metal element or a metal compound. The metal source 57 includes the metal contained in the semiconductor layer 104. The metal source 57 may be gallium element. The metal source 57 may be a gas, a liquid, or a solid. The metal source 57 is preferably a liquid.

[0101] The means for gasifying the metal source 57 is not particularly limited and may be a known means. The gasification of the metal source 57 is preferably carried out, for example, by halogenating the metal source 57. The halogenating agent used for the halogenation is, for example, contained in the halogen-containing source gas supplied from the halogen-containing source gas supply source 53a to the metal-containing source gas supply pipe 53b. The halogenating agent is not particularly limited as long as it can halogenate the metal source 57, and may be a known halogenating agent. Examples of the halogenating agent include halogen and hydrogen halide. Examples of halogen include fluorine, chlorine, bromine, and iodine. Examples of hydrogen halide include hydrogen fluoride, hydrogen chloride, hydrogen bromide, and hydrogen iodide. For halogenation, it is preferable to use hydrogen halide, and it is more preferable to use hydrogen chloride. The gasification of the metal source 57 is preferably carried out by supplying a halogen or hydrogen halide as a halogenating agent to the metal source 57 and reacting the metal source 57 with the halogen or hydrogen halide at a temperature equal to or higher than the vaporization temperature of the metal halide to form a metal halide. The halogenation reaction temperature is not particularly limited. For example, when the metal source 57 is gallium and the halogenating agent is HCl, the halogenation reaction temperature is preferably 900°C or lower. The halogenation reaction temperature is more preferably 700°C or lower, and even more preferably 400°C or higher and 700°C or lower. The metal-containing source gas is not particularly limited as long as it is a gas containing the metal of the metal source 57. The metal-containing source gas is, for example, a metal halide (such as a fluoride, chloride, bromide, or iodide).

[0102] The oxygen-containing source gas is, for example, O ２ Gas, CO ２ Gas, NO Gas, NO ２ Gas, N ２ O gas, H ２ O gas or O ３ The oxygen-containing source gas is O ２ , H ２ O and N ２ Preferably, the gas is one or more gases selected from the group consisting of O ２ It is more preferable that the oxygen-containing source gas contains CO２ may include:

[0103] The reactive gas supply pipe 54b is provided in the reaction chamber 51. The reactive gas supply pipe 54b is connected to the reactive gas supply source 54a. The reactive gas from the reactive gas supply source 54a is supplied to the substrate 107 via the reactive gas supply pipe 54b. The reaction chamber 51 is provided with a gas exhaust unit 59 that exhausts used gas.

[0104] The reactive gas is typically a gas with a different reactivity from the metal-containing source gas and the oxygen-containing source gas, and does not include an inert gas. Examples of reactive gases include, but are not limited to, etching gases. The etching gas is also not limited to, and may be a known etching gas. The reactive gas is preferably a halogen gas (e.g., fluorine gas, chlorine gas, bromine gas, or iodine gas), a hydrogen halide gas (e.g., hydrofluoric acid gas, hydrochloric acid gas, hydrogen bromide gas, hydrogen iodide gas), hydrogen gas, or a mixed gas of two or more of these. It is more preferable that the reactive gas contains a hydrogen halide gas, and even more preferable that the reactive gas contains hydrogen chloride. The metal-containing source gas, oxygen-containing source gas, or reactive gas may contain a carrier gas. The carrier gas is, for example, an inert gas such as nitrogen or argon. The partial pressure of the metal-containing source gas is not particularly limited, but is preferably 0.5 Pa or more and 1 kPa or less, and more preferably 5 Pa or more and 0.5 kPa or less. The partial pressure of the oxygen-containing source gas is not particularly limited, but is preferably 0.5 to 100 times the partial pressure of the metal-containing source gas, and more preferably 1 to 20. The partial pressure of the reactive gas is also not particularly limited, but is preferably 0.1 to 5 times the partial pressure of the metal-containing source gas, and more preferably 0.2 to 3 times.

[0105] A dopant-containing gas may further be supplied to the substrate 107. The dopant-containing gas is not particularly limited as long as it contains the dopant contained in the semiconductor layer 104. By using the dopant-containing gas, the conductivity of the resulting semiconductor layer 104 can be easily controlled. The dopant-containing gas preferably contains the dopant in the form of a compound (e.g., halide, oxide, etc.), more preferably in the form of a halide. The partial pressure of the dopant-containing source gas is not particularly limited, but is preferably 1×10 of the partial pressure of the metal-containing source gas. －７ It is preferable that the ratio is 2.5×10 to 0.1 times. －６ More than twice 7.5×10 －２ Preferably, the dopant-containing gas is supplied onto the substrate 107 together with the reactive gas.

[0106] By using the above-described film formation apparatuses 30, 40, and 50, the semiconductor layer 104 can be easily formed on the crystal growth surface of the substrate 107. In this case, the semiconductor layer 104 is usually formed by epitaxial crystal growth.

[0107] Second Example Next, a second example of the method for manufacturing the semiconductor device 100 will be described. Fig. 14 is a flowchart showing the second example of the method for manufacturing the semiconductor device 100. The manufacturing method of the second example differs from the first example in that the order of the third, fourth, fifth, sixth, and seventh steps, which are performed after the second step, is changed, but the remaining steps are performed under the same conditions as in the first example to manufacture the semiconductor device 100. Specifically, in the second example manufacturing method, after the second step of forming the semiconductor layer 104 on the base 107, a fifth step of removing the base 107 from the stacked structure 1 including the base 107 and the semiconductor layer 104 is performed (see FIG. 15 ), followed by a sixth step of forming an ohmic electrode 103 on the semiconductor layer 104 (see FIG. 16 ), followed by a seventh step of attaching the substrate 101 to the ohmic electrode 103 via the porous layer 102 (see FIG. 17 ), followed by a third step of forming a second region 105 b in the semiconductor layer 104 (see FIG. 18 ), followed by a fourth step of forming a Schottky electrode 106 on the semiconductor layer 104, thereby manufacturing the semiconductor device 100 shown in FIG. 2 . That is, in the first example, the step of forming the second region 105b in the semiconductor layer 104 and the step of forming the Schottky electrode 106 are performed in a state where the porous layer 102 is not attached to the semiconductor layer 104, whereas in the second example, the step of forming the second region 105b in the semiconductor layer 104 and the step of forming the Schottky electrode 106 are performed in a state where the porous layer 102 is attached to the semiconductor layer 104. The manufacturing method of the second example further includes a depressurization step of placing the stacked structure 1 in a depressurized space and depressurizing the depressurized space. Specifically, the manufacturing method of the second example includes a first depressurization step, a second depressurization step, and a third depressurization step as the depressurization steps.

[0108] 19 is a front view schematically showing a decompression device 60. In each of the first decompression step, the second decompression step, and the third decompression step, for example, a decompression device 60 that decompresses the laminated structure 1 is used. The decompression device 60 is, for example, a vacuum desiccator, and includes a decompression chamber 61 in which the laminated structure 1 is placed, and a pump 62 that decompresses the interior of the decompression chamber 61. The decompression device 60 may further include a tank 63 that contains a liquid 64 in which the laminated structure 1 is immersed. The decompression chamber 61 is, for example, formed inside a container 65, and forms a sealable space. The pump 62 is, for example, a vacuum pump that suctions the decompression chamber 61. The tank 63 is placed inside the decompression chamber 61. The liquid stored in the tank 63 is, for example, water such as pure water.

[0109] The first depressurization step is performed before the pre-cleaning step of the fourth step. In the first depressurization step, the laminated structure 1 after the third step shown in FIG. 18 is depressurized. Specifically, for example, as shown in FIG. 19 , a tank 63 in which the laminated structure 1 is immersed in a liquid 64 is placed in a sealed state within a depressurization chamber 61, and then a pump 62 is driven to depressurize the depressurization chamber 6. This depressurization is performed, for example, until the pressure within the depressurization chamber 6 reaches 0.9 MPa or less. By depressurizing the depressurization chamber 6 in this manner, degassing occurs, in which gas contained in the laminated structure 1, such as air contained in the porous layer 102 and the semiconductor layer 104, is extracted. At this time, the gas contained in the porous layer 102 and the semiconductor layer 104 is replaced with the liquid placed in the tank 63. Thereafter, the depressurization chamber 6 is opened to the atmosphere. Note that in the first depressurization step, a series of steps in which the depressurization chamber 6 is depressurized and then opened to the atmosphere may be repeated multiple times. Furthermore, in the first depressurization step, the depressurization chamber 6 may be depressurized with the laminated structure 1 placed in the air in the depressurization chamber 6 rather than immersed in a liquid. That is, during degassing in the first depressurization step, the gas contained in the laminated structure 1 does not have to be replaced with a liquid. The laminated structure 1 after the first depressurization step is cleaned in a pre-cleaning step in the fourth step. The first depressurization step is preferably performed immediately before the pre-cleaning step in the fourth step, but may also be performed before the fourth step. For example, the first depressurization step may be performed after a portion of the mask layer is removed by an etching agent in the third step and before the mask is removed by the etching agent (for example, immediately before impurity ion implantation).

[0110] The second depressurization step is performed after the pre-cleaning step of the fourth step. That is, in the second depressurization step, the laminated structure 1 is depressurized after the pre-cleaning step. In the second depressurization step, for example, a step similar to the first depressurization step is performed. That is, in this case, in the second depressurization step, a tank 63 in which the laminated structure 1 is immersed in a liquid 64 is placed in a sealed state within the depressurization chamber 61, and then the pump 62 is driven to depressurize the depressurization chamber 6 until the pressure therein reaches 0.9 MPa or less. As a result, the liquid, such as the etching agent, contained in the porous layer 102 and the semiconductor layer 104 is extracted from the laminated structure 1. At this time, the liquid contained in the porous layer 102 and the semiconductor layer 104 is replaced with the liquid contained in the tank 63. Thereafter, the depressurization chamber 6 is opened to the atmosphere. Note that in the second depressurization step, a series of steps in which the depressurization chamber 6 is depressurized and then opened to the atmosphere may also be repeated multiple times. Furthermore, in the second depressurization step, the depressurization chamber 6 may be depressurized while the laminated structure 1 is placed in the air within the depressurization chamber 6. After the second decompression step, an electrode layer is formed on the laminated structure 1 in the fourth step, the electrode layer forming step.

[0111] The third depressurization step is performed after the etching step of the fourth step. That is, in the third depressurization step, the laminated structure 1 is depressurized after the etching step. In the third depressurization step, for example, a step similar to the first or second depressurization step is performed. That is, in this case, a tank 63 in which the laminated structure 1 is immersed in a liquid 64 is placed in a sealed state within the depressurization chamber 61, and then the pump 62 is driven to depressurize the depressurization chamber 6 to 0.9 MPa or less. As a result, the liquid, such as the etching agent, contained in the porous layer 102 and the semiconductor layer 104 is extracted from the laminated structure 1. At this time, the liquid contained in the porous layer 102 and the semiconductor layer 104 is replaced with the liquid placed in the tank 63. Thereafter, the depressurization chamber 6 is opened to the atmosphere. Note that in the third depressurization step, a series of steps in which the depressurization chamber 6 is depressurized and then opened to the atmosphere may be repeated multiple times. Furthermore, in the third depressurization step, the depressurization chamber 6 may be depressurized while the laminated structure 1 is placed in the air within the depressurization chamber 6. After the third depressurization step, the resist is removed from the stacked structure 1 in the fourth step, the resist removal step. The third depressurization step is preferably performed before the resist removal step, but may be performed after the resist removal step. The method for manufacturing the semiconductor device 100 may include only one or two of the first depressurization step, the second depressurization step, and the third depressurization step as the depressurization step. The method for manufacturing the semiconductor device 100 is not limited to the first and second examples described above.

[0112] A portion of the semiconductor device 100 including at least the crystalline film 10 and a portion of the stacked structure 1 formed during the manufacturing process of the semiconductor device 100 including at least the crystalline film 10 may be detached from the semiconductor device 100 or other elements of the stacked structure 1 and used as an element of another semiconductor device. For example, only the crystalline film 10 may be detached from the semiconductor device 100 or other elements of the stacked structure 1 and used as a semiconductor layer of the semiconductor device. Alternatively, the ohmic electrode 103, the semiconductor layer 104, the guard ring 105, and the Schottky electrode 106 of the semiconductor device 100 may be detached from the substrate 101 and the porous layer 102 and used as elements of another semiconductor device. That is, the crystalline film 10 may be used as a semiconductor layer of the semiconductor device 100, or may be used as a semiconductor layer of a semiconductor device other than the semiconductor device 100. In addition to the first and second examples, the order in which the steps are performed in the manufacturing method of the semiconductor device 100 can be changed as appropriate.

[0113] In the manufacturing method of the second example, after the third step of forming the second region 105b in the semiconductor layer 104, decompression steps (specifically, a first decompression step, a second decompression step, and a third decompression step) are performed in which the stacked structure 1 is placed in a decompression space and the decompression space is decompressed. Therefore, the chemical solution such as the etching agent used in the third step can be removed from the stacked structure 1. Therefore, the formation of stains on the semiconductor layer 104 due to the chemical solution such as the etching agent is suppressed.

[0114] Furthermore, after the fourth step of forming the Schottky electrode 106 on the semiconductor layer 104, a decompression step (specifically, a third decompression step) is performed in which the stacked structure 1 is placed in a decompression space and the decompression space is decompressed. This allows the chemical solution, such as the etching agent, used in the fourth step to be removed from the stacked structure 1. This further prevents stains from being formed on the semiconductor layer 104 due to the chemical solution, such as the etching agent.

[0115] Furthermore, for example, when bonding the porous layer 102 to the ohmic electrode 103, the stacked structure including the ohmic electrode 103 and / or the porous layer 102 may be heated. Here, in the second example manufacturing method, the third step of forming the second region 105b in the semiconductor layer 104 is performed after the seventh step of bonding the porous layer 102 to the ohmic electrode 103. This prevents the heat generated when bonding the porous layer 102 from being applied to the second region 105b. This makes it difficult for thermal stress caused by the difference in thermal expansion coefficient between the first region 105a and the second region 105b to be applied to the semiconductor layer 104, thereby preventing cracks from occurring in the semiconductor layer 104.

[0116] Furthermore, the third step of forming the second region 105b in the semiconductor layer 104 and the fourth step of forming the Schottky electrode 106 in the semiconductor layer 104 are performed after the seventh step of joining the porous layer 102 to the ohmic electrode 103. Therefore, compared to the case where the third step and the fourth step are performed before the seventh step, the pattern design of the second region 105b and the pattern design of the Schottky electrode 106 can be determined in a later step in the manufacturing method of the semiconductor device 100, thereby increasing the degree of freedom in design.

[0117] (Third Example) Next, a third example of the method for manufacturing the semiconductor device 100 will be described. Fig. 20 is a flowchart showing the third example of the method for manufacturing the semiconductor device 100. The manufacturing method of the third example differs from the second example in that the order of the third, fourth, fifth, sixth, and seventh steps, which are performed after the second step, is changed, but the remaining steps are performed under the same conditions as in the second example to manufacture the semiconductor device 100. Specifically, similar to the first example, the semiconductor device 100 shown in FIG. 2 is manufactured by sequentially performing the first step of preparing a base 107 (see FIG. 5 ), the second step of forming a semiconductor layer 104 on the base 107 (see FIG. 6 ), and the third step of forming a second region 105b in the semiconductor layer 104 (see FIG. 7 ). This is followed by the fifth step of removing the base 107 from the stacked structure 1 including the base 107 and the semiconductor layer 104 (see FIG. 21 ). This is followed by the sixth step of forming an ohmic electrode 103 on the semiconductor layer 104 (see FIG. 22 ). This is followed by the seventh step of attaching the substrate 101 to the ohmic electrode 103 via the porous layer 102 (see FIG. 23 ). This is followed by the fourth step of forming a Schottky electrode 106 on the semiconductor layer 104. The manufacturing method of the third example also includes a depressurization step similar to that of the second example. The manufacturing method of the third example includes, for example, a first depressurization step, a second depressurization step, and a third depressurization step as depressurization steps, similar to the second example. In this case, the first depressurization step is also performed before the pre-cleaning step of step 4. The first depressurization step may be performed between steps 3 and 5, between steps 5 and 6, between steps 6 and 7, or between steps 7 and 4.

[0118] Next, another example of a semiconductor device 130 will be described. Fig. 24 is a cross-sectional view schematically showing another example of the semiconductor device 130. The semiconductor device 130 has a configuration in common with the semiconductor device 100. Therefore, with regard to the semiconductor device 130, a description of the matters in common with the semiconductor device 100 will be omitted, and only matters different from the semiconductor device 100 will be described.

[0119] The semiconductor device 130 includes an intermediate layer 131 instead of the porous layer 102. The intermediate layer 131 is formed on the surface of the substrate 101. The ohmic electrode 103 is formed on the substrate 101 with the intermediate layer 131 interposed therebetween.

[0120] The substrate 101 may be a five-layer substrate in which Cu layers and Mo layers are alternately stacked, with the Cu layer being the outermost layer of the substrate 101. In this case, an intermediate layer 131 is formed on the surface of the Cu layer of the substrate.

[0121] The intermediate layer 131 preferably contains the same metal as the metal contained in the ohmic electrode 103. For example, if the ohmic electrode 103 contains Ti, the intermediate layer 131 also contains Ti. Note that the intermediate layer 131 does not necessarily need to contain the same metal as the metal contained in the ohmic electrode 103.

[0122] Each of the intermediate layer 131 and the ohmic electrode 103 may be a single layer or multiple layers. The intermediate layer 131 may include a contact layer 131a in contact with the substrate 101 and a bonding layer 131b bonded to the ohmic electrode 103. The ohmic electrode 103 may include a contact layer 103a in contact with the semiconductor layer 104 and a bonding layer 103b bonded to the intermediate layer 131. In this example, the intermediate layer 131 may be formed of two layers, the contact layer 131a and the bonding layer 131b, and the ohmic electrode 103 may be formed of two layers, the contact layer 103a and the bonding layer 103b. For example, when the first semiconductor layer 104a is Ga ２ O ３In the case where the ohmic electrode 103 includes a crystalline oxide semiconductor or a mixed crystal thereof, the ohmic electrode 103 may be formed of two layers: a contact layer 103a made of Ti and a bonding layer 103b made of Au, and the intermediate layer 131 may be formed of two layers: a contact layer 131a made of Ti and a bonding layer 131b made of Au. The intermediate layer 131 may include another layer disposed between the contact layer 131a and the bonding layer 131b. The ohmic electrode 103 may also include another layer disposed between the contact layer 103a and the bonding layer 103b. A clearly defined boundary may or may not be present between the intermediate layer 131 and the ohmic electrode 103, or between the contact layer 131a and the contact layer 103a. The metals contained in the intermediate layer 131 and the ohmic electrode 103 are not limited.

[0123] Next, a description will be given of a method for manufacturing the semiconductor device 130. The method for manufacturing the semiconductor device 130 is generally the same as the method for manufacturing the second example of the semiconductor device 100. Therefore, with regard to the method for manufacturing the semiconductor device 130, a description of the points in common with the second example of the manufacturing method of the semiconductor device 100 will be omitted, and only the points that are different will be described.

[0124] In the method for manufacturing the semiconductor device 130, the first, second, fifth, sixth, seventh, third, and fourth steps are performed in order, as in the second example, or the first, second, third, fifth, sixth, seventh, and fourth steps are performed in order, as in the third example. However, in the seventh step, the substrate 101 is attached to the ohmic electrode 103 via an intermediate layer 131. In the method for manufacturing the semiconductor device 130, the decompression step may or may not be performed, as in the second example. In addition, in the method for manufacturing the semiconductor device 130, the first, second, third, fifth, sixth, seventh, and fourth steps may be performed in order, as in the third example.

[0125] Specifically, as shown in FIG. 25 , an intermediate layer 131 is formed on the surface of the substrate 101 before the ohmic electrode 103 is attached. For example, the intermediate layer 131 is formed on the surface of the Cu layer, which is the outermost layer of the substrate 101. The intermediate layer 131 is formed on the surface of the substrate 101 using, for example, the dry method or wet method described above. After the intermediate layer 131 is formed on the substrate 101 in this manner, the ohmic electrode 103 of the stacked structure shown in FIG. 26 , which includes the semiconductor layer 104 including the second region 105b and the ohmic electrode 103, is bonded to the surface of the intermediate layer 131 opposite the substrate 101. For example, if the ohmic electrode 103 includes the contact layer 103a and the bonding layer 103b and the intermediate layer 131 includes the contact layer 131a and the bonding layer 131b, the bonding layer 103b and the bonding layer 131b are bonded to each other, thereby bonding the substrate 101 and the semiconductor layer 104 via the intermediate layer 131.

[0126] The intermediate layer 131 and the ohmic electrode 103 may be bonded together in an unheated state, i.e., at room temperature. In this case, the electrical connection between the ohmic electrode 103 and the substrate 101 can be improved, thereby improving the reliability of the semiconductor device 130. The intermediate layer 131 and the ohmic electrode 103 can be bonded together by, for example, bringing the intermediate layer 131 and the ohmic electrode 103 into close contact with each other while the intermediate layer 131 and the ohmic electrode 103 are both activated. The activation process for the intermediate layer 131 and the ohmic electrode 103 is performed, for example, by irradiating them with an atomic beam or an ion beam. One or more other layers may be formed on the surface of the substrate 101 opposite the intermediate layer 131. The other layer may be formed before the substrate 101 is attached to the ohmic electrode 103, or may be formed after the substrate 101 is attached to the ohmic electrode 103. The other layer may be, for example, a layer containing a metal, and may be formed using the dry method or wet method described above. The substrate 101 is connected to a lead frame or the like via another layer, for example. In the method for manufacturing the semiconductor device 130, the decompression step described above can be omitted.

[0127] Next, another example of a semiconductor device incorporating the crystalline film 10 as a semiconductor layer will be described. The crystalline film 10 may be incorporated into the semiconductor device as an n-type semiconductor layer or as a p-type semiconductor layer. Furthermore, when the semiconductor device includes multiple semiconductor layers, only some of the multiple semiconductor layers may be crystalline films 10, or all of the multiple semiconductor layers may be crystalline films 10. For example, when the semiconductor device includes an n-type semiconductor layer and a p-type semiconductor layer, each of the n-type semiconductor layer and the p-type semiconductor layer may be crystalline films 10.

[0128] FIG. 27 is a cross-sectional view schematically illustrating yet another example of a semiconductor device 150. The semiconductor device 150 is an SBD. The semiconductor device 150 includes a semiconductor layer 151, a first electrode 154, and a second electrode 155. The semiconductor layer 151 includes an n+ type semiconductor layer 152 and an n- type semiconductor layer 153. The n+ type semiconductor layer 152 and the n- type semiconductor layer 153 are aligned in the thickness direction of the semiconductor layer 151. The surface of the n- type semiconductor layer 153 opposite to the n+ type semiconductor layer 152 forms a first surface 151a, which is one surface of the semiconductor layer 151 in the thickness direction. The surface of the n+ type semiconductor layer 152 opposite to the n- type semiconductor layer 153 forms a second surface 151b, which is the surface of the semiconductor layer 151 opposite to the first surface 151a. The first electrode 154 is formed on the first surface 151a. The first electrode 154 is a Schottky electrode. The second electrode 155 is formed on the second surface 151b. The second electrode 155 is an ohmic electrode.

[0129] Examples of materials for the first electrode 154 and the second electrode 155 include the same materials as the materials for the ohmic electrode 103 and the Schottky electrode 106 of the semiconductor device 100. The same applies to the materials and formation of the electrodes of the semiconductor devices 200, 300, 400, 500, 600, 700, and 800 described below.

[0130] Each of the first electrode 154 and the second electrode 155 is formed by, for example, the same method as the ohmic electrode 103 or the Schottky electrode 106 of the semiconductor device 100 described above. The method for forming each of the first electrode 154 and the second electrode 155 is not limited, and they may be formed by other known methods. The same applies to the method for forming each electrode of the semiconductor devices 200, 300, 400, 500, 600, 700, and 800 described below.

[0131] FIG. 28 is a cross-sectional view schematically illustrating another example of a semiconductor device 200. The semiconductor device 200 is a JBS. The semiconductor device 200 includes a semiconductor layer 201, a barrier height adjusting region 202, a first electrode 203, and a second electrode 204. The semiconductor layer 201 may be a single layer or may include multiple semiconductor layers. The semiconductor layer 201 has a first surface 201a, which is one surface of the semiconductor layer 201 in the thickness direction, and a second surface 201b, which is the surface opposite to the first surface 201a. The barrier height adjusting region 202 is formed on the first surface 201a. The first electrode 203 is formed on the first surface 201a so as to be in contact with both the semiconductor layer 201 and the barrier height adjusting region 202. The first electrode 203 is a barrier electrode that forms a Schottky barrier between the first electrode 203 and the semiconductor layer 201. The second electrode 204 is formed on the second surface 201b. The second electrode 204 is an ohmic electrode.

[0132] The barrier height adjusting region 202 is formed between the semiconductor layer 201 and the first electrode 203. The barrier height adjusting region 202 forms a Schottky barrier between the semiconductor layer 201 and the first electrode 203, the barrier height adjusting region 202 having a barrier height greater than that of the Schottky barrier of the first electrode 203. In this example, a plurality of trenches 201c are formed in the first surface 201a of the semiconductor layer 201. The barrier height adjusting region 202 is embedded in each trench 201c. The barrier height adjusting region 202 is preferably provided at least between both ends of the first electrode 203 and the semiconductor layer 201. The barrier height adjusting region 202 is preferably provided at regular intervals.

[0133] FIG. 29 is a cross-sectional view schematically illustrating a semiconductor device 300 according to another embodiment. The semiconductor device 300 is a JBS. Like the semiconductor device 200, the semiconductor device 300 includes a semiconductor layer 201, a barrier height adjusting region 202, a first electrode 203, and a second electrode 204. In addition, the semiconductor device 300 further includes a guard ring 305 formed on the semiconductor layer 201. In this embodiment, the semiconductor device 300 includes a plurality of guard rings 305. The guard rings 305 are positioned around the first electrode 203. At least a portion of the guard rings 305 is embedded in the semiconductor layer 201. By providing the guard rings 305, it is possible to improve the breakdown voltage and the like, thereby obtaining a semiconductor device with better semiconductor characteristics.

[0134] The guard ring 305 is typically made of a material with a high barrier height. Examples of materials used for the guard ring 305 include conductive materials with a barrier height of 1 eV or greater. The material for the guard ring 305 may be the same material as the electrode material. Examples of materials used for the guard ring 305 include metals exemplified as the materials for the first electrode 154 and the second electrode 155 of the semiconductor device 150. In this case, the design freedom for the voltage-resistant structure is high, and multiple guard rings 305 can be provided, resulting in a more flexible and improved voltage resistance. The shape of the guard ring 305 is not particularly limited. Examples of shapes for the guard ring 305 include a square shape, a circular shape, a U-shape, an L-shape, and a strip shape. The number of guard rings 305 included in the semiconductor device 300 is also not particularly limited. The semiconductor device 300 preferably includes three or more guard rings 305, and more preferably six or more guard rings 305.

[0135] FIG. 30 is a cross-sectional view schematically illustrating a semiconductor device 400 according to another example. The semiconductor device 400 is an LED. The semiconductor device 400 includes an n-type semiconductor layer 401, a light-emitting layer 402, a p-type semiconductor layer 403, a transparent electrode 404, a first electrode 405, and a second electrode 406. The light-emitting layer 402 is formed on the n-type semiconductor layer 401. The light-emitting layer 402 emits light. The p-type semiconductor layer 403 is formed on the light-emitting layer 402. The transparent electrode 404 is formed on the p-type semiconductor layer 403. The transparent electrode 404 is transparent. Therefore, light generated in the light-emitting layer 402 passes through the transparent electrode 404. The first electrode 405 is formed on the transparent electrode 404. The first electrode 405 is an anode electrode. The second electrode 406 is formed on the surface of the n-type semiconductor layer 401 opposite to the light emitting layer 402. The second electrode 406 is a cathode electrode. The semiconductor device 400 may be covered with a protective layer except for the electrode portion.

[0136] 31 is a cross-sectional view schematically showing yet another example of a semiconductor device 500. The semiconductor device 500 is a MOSFET, and more specifically, a trench MOSFET. The semiconductor device 500 includes a first n+ type semiconductor layer 501, an n- type semiconductor layer 502, a p-type semiconductor layer 503, a second n+ type semiconductor layer 504, an insulating film 505, a first electrode 506, a second electrode 507, and a third electrode 508.

[0137] The n-type semiconductor layer 502 is formed on the first n+ type semiconductor layer 501. The p-type semiconductor layer 503 is formed on the n- type semiconductor layer 502. The second n+ type semiconductor layer 504 is formed on the p-type semiconductor layer 503. The first electrode 506 is formed on the second n+ type semiconductor layer 504. The first electrode 506 is a source electrode. The second electrode 507 is formed on the surface of the first n+ type semiconductor layer 501 opposite to the n- type semiconductor layer 502. The second electrode 507 is a drain electrode. A plurality of trenches 509 are formed on the surface of the semiconductor layer formed from the n- type semiconductor layer 502, the p-type semiconductor layer 503, and the second n+ type semiconductor layer 504, on the first electrode 506 side. Each of the plurality of trenches 509 penetrates the second n+ type semiconductor layer 504 and the p-type semiconductor layer 503 to reach the n- type semiconductor layer 502. A third electrode 508 is buried in each trench 509 via an insulating film 505. The third electrode 508 is a gate electrode.

[0138] 32 is a cross-sectional view schematically showing yet another example of a semiconductor device 600. The semiconductor device 600 is an IGBT. The semiconductor device 600 includes a p-type semiconductor layer 601, an n-type semiconductor layer 602, an n-type semiconductor layer 603, a p-type semiconductor region 604, an n+ type semiconductor region 605, an insulating film 606, and a plurality of first electrodes 607, second electrodes 608, and third electrodes 609.

[0139] The n-type semiconductor layer 602 is formed on the p-type semiconductor layer 601. The n-type semiconductor layer 603 is formed on the n-type semiconductor layer 602. A plurality of trenches 603a are formed on the surface of the n-type semiconductor layer 603 opposite to the n-type semiconductor layer 602. A p-type semiconductor region 604 is formed inside each of the plurality of trenches 603a. An n+ type semiconductor region 605 is formed inside each of the p-type semiconductor regions 604. An insulating film 606 is formed on the n-type semiconductor layer 603 so as to be in contact with the n- type semiconductor layer 603, the p-type semiconductor region 604, and the n+ type semiconductor region 605. Each of the plurality of first electrodes 607 is formed on the p-type semiconductor region 604 so as to be in contact with the p-type semiconductor region 604 and the n+ type semiconductor region 605. The first electrodes 607 are emitter electrodes. The second electrode 608 is formed on the surface of the p-type semiconductor layer 601 opposite to the n-type semiconductor layer 602. The second electrode 608 is a collector electrode. The third electrode 609 is formed on the insulating film 606. The third electrode 609 is a gate electrode.

[0140] FIG. 33 is a cross-sectional view schematically illustrating a semiconductor device 700 according to another example. The semiconductor device 700 is a HEMT. The semiconductor device 700 includes a semi-insulating layer 701, a buffer layer 702, a first n-type semiconductor layer 703, a second n-type semiconductor layer 704, multiple n+ type semiconductor layers 705, a first electrode 706, a second electrode 707, and a third electrode 708. The buffer layer 702 is formed on the semi-insulating layer 701. The first n-type semiconductor layer 703 is formed on the buffer layer 702. The second n-type semiconductor layer 704 is formed on the first n-type semiconductor layer 703. The band gap of the second n-type semiconductor layer 704 is wider than the band gap of the first n-type semiconductor layer 703. The multiple n+ type semiconductor layers 705 are embedded in the first n-type semiconductor layer 703 and the second n-type semiconductor layer 704. The n+ type semiconductor layer 705 is in contact with the first n-type semiconductor layer 703 and the second n-type semiconductor layer 704. A first electrode 706 and a second electrode 707 are formed on each of the n+ type semiconductor layers 705. The first electrode 706 is a source electrode. The second electrode 707 is a drain electrode. A third electrode 708 is formed on the second n-type semiconductor layer 704. The third electrode 708 is a gate electrode.

[0141] 34 is a cross-sectional view schematically showing yet another example of a semiconductor device 800. The semiconductor device 800 is a JFET. The semiconductor device 800 includes a first n+ type semiconductor layer 801, an n- type semiconductor layer 802, a second n+ type semiconductor layer 803, a first electrode 804, a second electrode 805, and a third electrode 806. The n- type semiconductor layer 802 is formed on the first n+ type semiconductor layer 801. The second n+ type semiconductor layer 803 is formed on the n- type semiconductor layer 802. The first electrode 804 is formed on the second n+ type semiconductor layer 803. The first electrode 804 is a source electrode. A layer formed by the n-type semiconductor layer 802, the second n+ type semiconductor layer 803, and the first electrode 804 has a plurality of trenches 807 formed therein, the trenches 807 extending from the surface of the first electrode 804 opposite the n+ type semiconductor layer 803, through the first electrode 804 and the second n+ type semiconductor layer 803, and reaching the n- type semiconductor layer 802. The second electrode 805 is formed on the surface of the first n+ type semiconductor layer 801 opposite the n- type semiconductor layer 802. The third electrode 806 is formed at the bottom of each trench 807. The third electrode 806 is in contact with the n- type semiconductor layer 802. The third electrode 806 is a gate electrode.

[0142] In addition to the above, semiconductor devices 100, 130, 150, 200, 300, 400, 500, 600, 700, and 800 can be suitably used as power modules, inverters, or converters using known methods, and can also be suitably used in, for example, semiconductor systems using power supply devices. A power supply device can be fabricated using known methods by connecting semiconductor devices 100, 130, 150, 200, 300, 400, 500, 600, 700, and 800 to a wiring pattern, etc.

[0143] Fig. 35 is a block diagram of an example power supply system 900. The power supply system 900 includes a plurality of power supply devices 901 and 902 and a control circuit 903. Fig. 36 is a block diagram of an example system device 910. The system device 910 includes the power supply system 900 and an electronic circuit 911.

[0144] Figure 37 is a circuit diagram showing the power supply circuit of an example power supply device. The power supply circuit includes a power circuit and a control circuit. In the power supply circuit, DC voltage is switched at high frequency by an inverter 921 (comprising MOSFETs A to D) to convert it to AC, followed by insulation and transformation by a transformer 922, rectification by a rectifying MOSFET 923, smoothing by a DCL 924 (smoothing coils L1 and L2) and a capacitor, and outputting a DC voltage. At this time, a voltage comparator 925 compares the output voltage with a reference voltage, and a PWM control circuit 926 controls the inverter 921 and rectifying MOSFET 923 to achieve the desired output voltage.

[0145] Previously, studies have been conducted on crystalline films containing gallium-containing crystalline oxide semiconductors to develop crystalline films with excellent yield and semiconductor properties. However, even such crystalline films have difficulty obtaining good results in high-temperature, high-humidity reverse bias tests, posing reliability issues. In contrast, the crystalline film 10 and semiconductor devices 100, 130, 150, 200, 300, 400, 500, 600, 700, and 800 disclosed herein do not contain stains when observed with an optical microscope or a scanning electron microscope. Here, stains are considered to be, for example, chemical solutions adhering to the crystalline film 10. Therefore, the reliability of the electrical properties of the crystalline film 10 and semiconductor devices 100, 130, 150, 200, 300, 400, 500, 600, 700, and 800 can be improved. Furthermore, for example, when packaging the semiconductor devices 100, 130, 150, 200, 300, 400, 500, 600, 700, and 800, the adhesion between the crystal film 10 and the molding resin can be improved, making it less likely that problems such as interface peeling will occur.

[0146] (Example 1) Hereinafter, an example of the present disclosure will be described.

[0147] The semiconductor device 100 was manufactured by the above-described first example manufacturing method, that is, the first, second, third, fourth, fifth, sixth, and seventh steps were carried out in this order.

[0148] In the second step, a crystalline film was produced using a film-forming apparatus 40 shown in Fig. 12. A quartz tube with an inner diameter of 40 mm was used as the supply pipe 42. A susceptor 41 made of quartz was used. The reason for using quartz for both the supply pipe 42 and the susceptor 41 was to prevent impurities from the apparatus from being mixed into the crystalline film.

[0149] Gallium bromide was mixed with ultrapure water to a concentration of 0.1 mol / L, and hydrobromic acid was added at a volume ratio of 10%. This was used as a raw material solution 34a.

[0150] The raw material solution 34a was contained in the atomized droplet generating source 34. Next, a c-plane sapphire substrate was placed on the susceptor 41 as the substrate 107, and the temperature of the heater 43 was raised to 500°C. Next, the flow rate control valves 33a and 33b were opened, and carrier gas was supplied from the carrier gas sources 32a and 32b into the supply pipe 42, and the atmosphere in the supply pipe 42 was thoroughly replaced with the carrier gas. Thereafter, the flow rate of the carrier gas from the carrier gas source 32a was adjusted to 5.0 L / min, and the flow rate of the carrier gas (diluted) from the carrier gas source 32b was adjusted to 0.5 L / min. Note that oxygen was used as the carrier gas.

[0151] Next, the ultrasonic vibrator 36 was vibrated, and the vibrations were propagated to the raw material solution 34a through the water 35a, thereby atomizing the raw material solution 34a and generating atomized droplets. The atomized droplets were transported by the carrier gas to the supply pipe 42, and the atomized droplets were thermally reacted near the surface of the substrate 107 at 500°C under atmospheric pressure, forming a crystal film on the substrate 107.

[0152] After forming the crystalline film in this manner, the third, fourth, fifth, sixth, and seventh steps described above were carried out in order to fabricate the semiconductor device 100. In the fourth pre-cleaning step, the stacked structure 1 was cleaned using a wet etching agent containing buffered hydrofluoric acid, and in the fourth etching step, the electrode layer was etched using a phosphoric acid solution.

[0153] Example 2 In Example 2, a semiconductor device 100 was manufactured by the manufacturing method of the second example described above. That is, in Example 2, the first, second, fifth, sixth, seventh, third, and fourth steps were performed in this order. Note that the first, second, fifth, sixth, seventh, third, and fourth steps of Example 2 were each performed in the same manner as in Example 1. Furthermore, in the fourth step, the first depressurization step, pre-cleaning step, second depressurization step, electrode layer formation step, resist formation step, etching step, third depressurization step, and resist removal step were performed in this order.

[0154] Comparative Example In the comparative example, the only difference from Example 1 was that the order of the third, fourth, fifth, sixth, and seventh steps, which are performed after the second step, was changed, and the remaining steps were performed in the same manner as in Example 1 to manufacture the semiconductor device 100. Specifically, in the comparative example, the first, second, fifth, sixth, seventh, third, and fourth steps were performed in the same order as in Example 2. However, in the comparative example, the decompression step of Example 2 was not performed.

[0155] (Evaluation) The crystal films obtained in Examples 1, 2, and Comparative Example were each subjected to layer identification using an X-ray diffraction apparatus. ２ O ３ It was a membrane.

[0156] The surfaces of the crystal films obtained in each of Examples 1, 2, and the Comparative Example were observed using an optical microscope and a scanning electron microscope. Optical microscope observations were performed using a VHX-6000 optical microscope manufactured by Keyence Corporation at a magnification of 50x. Electron microscope observations of the semiconductor layer 104 were performed using a Regulus 8230 field emission scanning electron microscope manufactured by Hitachi High-Technologies Corporation at a magnification of 200x to 10,000x.

[0157] No stains were observed in the multiple crystal films obtained in Example 1 and the multiple crystal films obtained in Example 2. Stains were observed in the multiple crystal films obtained in the comparative example. FIG. 38 is a photograph of a crystal film containing stains taken using an optical microscope. FIG. 39 is a photograph of another crystal film containing stains taken using an optical microscope. Furthermore, phosphorus, silver, and fluorine were detected in the portion of the crystal film where stains were observed.

[0158] Furthermore, a high-temperature, high-humidity reverse bias test was performed on each of the semiconductor devices 100 in which no stains were observed and the semiconductor devices 100 in which stains were observed, under conditions of a temperature of 85°C, a humidity of 85%, and a voltage of 220V, to check for the presence or absence of defects. The yield rate of the semiconductor devices 100 in which no stains were observed was higher than the yield rate of the semiconductor devices 100 in which stains were observed. Furthermore, when the defective semiconductor devices 100 were observed with an optical microscope, some were found to have damage in the areas corresponding to the stains.

[0159] The following additional notes are provided regarding this disclosure.

[0160] (Note 1) A crystalline film containing a crystalline oxide semiconductor containing gallium, which does not contain stains when observed with an optical microscope or a scanning electron microscope.

[0161] (Supplementary Note 2) A crystalline film including a crystalline oxide semiconductor containing gallium, wherein the reflectance of the surface of the crystalline film is uniform.

[0162] (Supplementary Note 3) The crystalline film according to Supplementary Note 1 or 2, wherein the crystalline oxide semiconductor has a corundum structure.

[0163] (Appendix 3A) The crystal film according to any one of Appendices 1 to 3, wherein the stains have a diameter of 0.1 μm or more.

[0164] (Appendix 3B) The crystalline film according to any one of Appendices 1 to 3 or 3A, wherein the stain is a region containing phosphorus on the surface of the crystalline film.

[0165] (Appendix 3C) The crystalline film according to any one of Appendices 1 to 3, 3A, and 3B, wherein the stain is a region containing one or more elements selected from aluminum, carbon, silicon, fluorine, and silver.

[0166] (Appendix 4) A laminated structure comprising the crystal film according to any one of appendices 1 to 3, 3A, 3B, and 3C.

[0167] (Appendix 5) A semiconductor device comprising the crystalline film according to any one of appendices 1 to 3, 3A, 3B, and 3C.

[0168] (Appendix 6) A method for manufacturing a stacked structure, comprising: supplying an etching agent to a stacked structure including a crystalline oxide semiconductor containing gallium; and placing the stacked structure in a reduced pressure space and reducing the pressure of the reduced pressure space.

[0169] (Appendix 6A) The method for producing a laminated structure according to Appendix 6, wherein the laminated structure further includes a porous layer.

[0170] (Appendix 6B) A method for manufacturing a stacked structure, comprising: removing a mask on a semiconductor layer including a crystalline oxide semiconductor containing gallium by using an etching agent; and attaching a substrate to the semiconductor layer from which the mask has been removed via a porous layer.

[0171] (Appendix 6C) A method for manufacturing a laminated structure, comprising: bonding a substrate and an electrode via an intermediate layer in a room temperature environment.

[0172] The crystalline film of the present disclosure can be used in a variety of fields, such as semiconductor devices (e.g., compound semiconductor electronic devices, etc.), electronic and electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful for semiconductor devices, etc. The semiconductor device of the present disclosure can be used in a variety of fields, such as semiconductors (e.g., compound semiconductor electronic devices, etc.), electronic and electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful for power devices.

[0173] L1 Smoothing coil L2 Smoothing coil 1 Laminated structure 6 Decompression chamber 10 Crystal film 30 Film forming apparatus 32a Carrier gas source 32b Carrier gas (dilution) source 33a Flow rate control valve 33b Flow rate control valve 34 Atomized droplet generating source 34a Raw material solution 34b Atomized droplets 35 Container 35a Water 36 Ultrasonic vibrator 37 Film forming chamber 37a Exhaust port 38 Supply pipe 39 Hot plate 40 Film forming apparatus 41 Susceptor 42 Supply pipe 42a Exhaust port 43 Heater 50 Film forming apparatus 51 Reaction chamber 52a Heater 52b Heater 54b Reactive gas supply pipe 55b Oxygen-containing raw material gas supply pipe 56 Holder 57 Metal source 58 Protective sheet 59 Gas exhaust section 60 Pressure reducing device 61 Pressure reducing chamber 62 Pump 63 Tank 64 Liquid 65 Container 100 Semiconductor device 101 Substrate 102 Porous film 103 Ohmic electrode 103a Contact layer 103b Bonding layer 104 Semiconductor layer 104a First semiconductor layer 104b Second semiconductor layer 105 Guard ring 105a First region 105b Second region 106 Schottky electrode 107 Base 130 Semiconductor device 131 Intermediate layer 131a Contact layer 131b Bonding layer 150 Semiconductor device 151 Semiconductor layer 151a First surface 151b Second surface 152 n+ type semiconductor layer 153 n- type semiconductor layer 154 First electrode 155 Second electrode 200 Semiconductor device 201 Semiconductor layer 201a First surface 201b Second surface 201c Trench 202 Barrier height adjusting region 203 First electrode 204 Second electrode 300 Semiconductor device 305 Guard ring 400 Semiconductor device 401 N-type semiconductor layer 402 Light-emitting layer 403 P-type semiconductor layer 404 Light-transmitting electrode 405 First electrode 406 Second electrode 500 Semiconductor device 501 First n+ type semiconductor layer 502 N- type semiconductor layer 503 P-type semiconductor layer 504 Second n+ type semiconductor layer 505 Insulating film 506 First electrode 507 Second electrode 508 Third electrode 509 Trench 600 Semiconductor device 601 P-type semiconductor layer 602 N- type semiconductor layer 603 N- type semiconductor layer 603a Trench 604 p-type semiconductor region 605 n-type semiconductor region 606 insulating film 607 first electrode608 Second electrode 609 Third electrode 700 Semiconductor device 701 Semi-insulating layer 702 Buffer layer 703 First n-type semiconductor layer 704 Second n-type semiconductor layer 705 n+ type semiconductor layer 706 First electrode 707 Second electrode 708 Third electrode 800 Semiconductor device 801 First n+ type semiconductor layer 802 n- type semiconductor layer 803 Second n+ type semiconductor layer 804 First electrode 805 Second electrode 806 Third electrode 807 Trench 900 Power supply system 901 Power supply device 902 Power supply device 903 Control circuit 910 System device 911 Electronic circuit 921 Inverter 922 Transformer 923 Rectifying MOSFET 924 DCL 925 Voltage comparator 926 Control circuit

Claims

1. A crystalline film containing a crystalline oxide semiconductor containing gallium, which does not contain any stains when observed with an optical microscope or a scanning electron microscope.

2. A crystalline film comprising a crystalline oxide semiconductor containing gallium, wherein the reflectance of the surface of the crystalline film is uniform.

3. The crystalline film according to claim 1, wherein the crystalline oxide semiconductor has a corundum structure.

4. A laminated structure comprising the crystal film according to any one of claims 1 to 3.

5. A semiconductor device comprising the crystalline film according to any one of claims 1 to 3.

6. A method for manufacturing a stacked structure, comprising: supplying an etching agent to a stacked structure including a crystalline oxide semiconductor containing gallium; and placing the stacked structure in a reduced pressure space and reducing the pressure of the reduced pressure space.

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