Systems and methods for frequency stabilization firmware in transceivers

Abstract

A communication system is provided. The communication system includes at least one processor in communication with at least one memory device configured to store computer-executable instructions. The instructions cause the processor to a) determine whether a Phase-Locked Loop (PLL) is in a LOCK state; and b) if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to: i) set a PLL frequency to a first frequency; ii) change a polarity of a phase frequency detector to positive; iii) change the polarity of the phase frequency detector to negative; iv) set the PLL frequency to a second frequency; v) change the polarity of the phase frequency detector; and / or vi) monitor for a PLL transition to the LOCK state.

Description

SYSTEMS AND METHODS FOR FREQUENCYSTABILIZATION FIRMWARE IN TRANSCEIVERSFIELD OF THE DISCLOSURE

[0001] The field of the invention relates generally to frequency stabilization firmware in transceivers, and more specifically, to systems and methods for frequency stabilization using transceiver firmware in fixed wireless access networks.BACKGROUND

[0002] In fixed wireless access (FWA) networks with Point-to- Multipoint architecture, where a central base station communicates with multiple customer premises equipment (CPE) devices, frequency synchronization is crucial. Allowing synchronized operation across the network reduces interference and enhances overall performance. Remote frequency stabilization helps to resolve several issues, such as, regulatory' compliance and frequency drift compensation, for example. Regulatory bodies allocate specific frequency bands for FWA services to prevent interference and ensure efficient use of the radio spectrum. Electronic components and environmental conditions can cause the frequency of a wireless signal to drift over time and temperature compensation. Additionally, temperature changes can impact the stability of electronic components, further affecting performance.

[0003] Data Over Cable Service Interface Specification (DOCSIS) 3. 1 international standard is used as transport standard in FWA situations. The DOCSIS 3.1 standard enhances the capabilities of cable networks, allowing for higher data throughput and more efficient use of existing cable infrastructure. The DOCSIS 3.1 standards requires low phase noise to achieve high throughputs. The implications of phase noise in the realm of DOCSIS 3.1 are multi-faceted. First, excessive phase noise can introduce distortions to the signal, posing challenges to its quality and making accurate demodulation more difficult. Additionally, higher levels of phase noise maycontribute to elevated bit error rates, thereby diminishing the overall reliability of data transmission.

[0004] DOCSIS 3.1's support for advanced modulation schemes, such as Quadrature Amplitude Modulation (QAM), may be hindered by phase noise, affecting the capability to achieve higher-order modulations and limiting potential data rates. This impact extends to spectral efficiency, where phase noise can influence the system's ability to utilize the available spectrum efficiently, potentially posing limitations on overall network performance.

[0005] Accordingly, there is a need for consistent frequency stabilization in FWA networks.BRIEF SUMMARY

[0006] In one aspect, a communication system is provided. The communication system includes at least one transceiver. The at least one transceiver includes at least one processor in communication with at least one memory device configured to store computer-executable instructions. When executed by the processor, the instructions cause the determine whether a Phase-Locked Loop (PLL) is in a LOCK state. If the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to set a PLL frequency to a first frequency. If the determination is that the PLL is not in a LOCK state, the instructions also cause the transceiver to change a polarity of a phase frequency detector to positive. If the determination is that the PLL is not in a LOCK state, the instructions further cause the transceiver to change the polarity of the phase frequency detector to negative. Additionally, if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to set the PLL frequency to a second frequency. Moreover, if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to change the polarity of the phase frequency detector. Furthermore, if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to monitor for a PLL transition to the LOCK state. The communication system may include additional, less, or alternate functionality, including that discussed elsewhere herein.

[0007] Advantages will become more apparent to those skilled in the art from the following description of the preferred embodiments which have been shown and described by way of illustration. As will be realized, the present embodiments may be capable of other and different embodiments, and their details are capable of modification in various respects. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The Figures described below depict various aspects of the systems and methods disclosed therein. It should be understood that each Figure depicts an embodiment of a particular aspect of the disclosed systems and methods, and that each of the Figures is intended to accord with a possible embodiment thereof. Further, wherever possible, the following description refers to the reference numerals included in the following Figures, in which features depicted in multiple Figures are designated with consistent reference numerals.

[0009] There are shown in the drawings arrangements which are presently discussed, it being understood, however, that the present embodiments are not limited to the precise arrangements and are instrumentalities shown, wherein:

[0010] Figure 1 illustrates an exemplary process for achieving frequency stabilization with the support of firmware on transceiver hardware, in accordance with at least one embodiment.

[0011] Figure 2 illustrates an exemplary transceiver for frequency stabilization using the process shown in Figure 1.

[0012] The Figures depict preferred embodiments for purposes of illustration only. One skilled in the art will readily recognize from the following discussion that alternative embodiments of the systems and methods illustrated herein may be employed without departing from the principles of the invention described herein.DETAILED DESCRIPTION

[0013] As used herein, a base station may refer to a relay located at the center of any of the cells in a cellular telephone system. A base station may also refer to a short-range transceiver which connects a cordless phone, computer, or other wireless device, such as customer premises equipment (CPE) devices, to a central hub and allows connection to a network, such as a cellular network. CPE includes telecommunications and information technology equipment kept at the customer's physical location rather than on the service provider's premises. Telephone handsets, cable TV set-top boxes and Digital Subscriber Line (DSL) routers are examples of CPEs. In some embodiments, a base station may also be connected to a sector antenna, wherein the sector antenna is a type of directional microwave antenna with a sectorshaped radiation pattern.

[0014] As used herein, a transceiver is a device that can both transmit and receive communications, such as a combined radio transmitter and receiver. It can both transmit and receive radio waves using an antenna, for communication purposes.

[0015] The present embodiments may relate to, inter alia, networkbased system and method for frequency stabilization using transceiver firmware in fixed wireless access (FWA) networks. In one exemplary embodiment, the process may be performed by a frequency stabilization (FS) system. In the exemplary embodiment, the FS system may include a midbox or interface between two or more transmission and / or receiving devices.

[0016] In the exemplary embodiment, frequency stabilization is performed by using a received radio frequency continuous wave signal utilizing the known characteristics of the incoming signal to correct or adjust for the signal of a local oscillator. The transceiver must get into a “lock” state to ensure that it operates at the correct frequency. The lock state is mandatory to enable transmission on the transceiver.

[0017] At the start of process, the variables “freq” (frequency) and “pol” (polarity) are declared and set to zero. Then the system checks the LOCK state of the PLL. In at least one embodiment, the system includes a transceiver that performs one or more of the described steps. If the PLL is in the LOCK state, the system delays and checks 104 the LOCK state again. The process remains in this loop as long as the PLL stays in the LOCK state.

[0018] If the LOCK state is not present, the system sets the PLL frequency to 7 MHz and changes the polarity of the phase frequency detector (PFD) once to positive (0) and once to negative (1). This shifts the VCO to an extreme frequency point.

[0019] Next, the system sets the desired "Target" frequency to 10.8 MHz and changes the polarity of the PFD. This causes a shift in the VCO from the extreme frequency point. If, during the PLL transition, it locks onto the correct frequency (10.8 MHz), it sets the LOCK state, and the routine only checks for the presence of PLL LOCK.

[0020] In the case where the shift from 7 MHz to 10.8 MHz is unsuccessful, the routine sets another edge frequency of 18 MHz and begins testing the LOCK state again.

[0021] Figure 1 illustrates an exemplary process 100 for achieving frequency stabilization with the support of firmware on transceiver hardware, in accordance with at least one embodiment. In at least one embodiment, the system includes a transceiver 200 (shown in Figure 2) that performs one or more of the described steps.

[0022] The goal of process 100 is to modulate the “charge the pump voltage of the Phase-Locked Loop (PLL) from zero volts to 3.3 volts. This shifts the output frequency of the 50 MHz Voltage-Controlled Oscillator (VCO) reference.

[0023] At the start of process 100, the variables “freq” (frequency) and “pol” (polarity) are declared and set 102 to zero. Then the system checks 104 the LOCKstate of the PLL. If the PLL is in the LOCK state, the system delays 106 and checks 104 the LOCK state again. The process 100 remains in this loop as long as the PLL stays in the LOCK state.

[0024] If the LOCK state is not present, the system checks 108 the frequency, to determine which state that the frequency is in.

[0025] If the frequency is in the first state where the frequency is 0, then the system determines 110 the polarity. If the polarity is 0 (positive), then the system sets 112 the PIL-PLL (pilot phase-locked loop) PLL frequency to 7 MHz and changes the polarity of the phase frequency detector (PFD) to positive (0). Then the system sets 114 the polarity of the phase frequency detector (PFD) to negative (1). This shifts the VCO to an extreme frequency point. Then the system returns 116 to the return point 118 of the PLL loop in process 100.

[0026] If instead when the system determines 110 that the polarity is 1 (negative), then the system sets 120 the PIL-PLL (pilot phase-locked loop) PLL frequency to 7 MHz and changes the polarity of the phase frequency detector (PFD) to negative (1). Then the system sets 122 the frequency to the second state, indicated by a 1 in Figure 1, and the polarity of the phase frequency detector (PFD) to positive (0). Then the system returns 116 to the return point 118 of the PLL loop in process 100.

[0027] If the LOCK state is not present and the system determines 108 that the frequency is in the in the second state, indicated with 1 in Figure 1, then the system determines 124 the polarity. If the polarity is 0 (positive), then the system sets 126 the PIL-PLL (pilot phase-locked loop) PLL frequency to 10.8 MHz and changes the polarity of the phase frequency detector (PFD) to positive (0). Then the system sets 128 the polarity of the phase frequency detector (PFD) to negative (1). This shifts the VCO to an extreme frequency point. Then the system returns 130 to the return point 118 of the PLL loop in process 100.

[0028] If instead when the system determines 110 that the polarity is 1 (negative), then the system sets 132 the PIL-PLL (pilot phase-locked loop) PLLfrequency to 10.8 MHz and changes the polarity of the phase frequency detector (PFD) to negative (1). Then the system sets 122 the frequency to the third state, indicated by a 2 in Figure 1, and the polarity of the phase frequency detector (PFD) to positive (0). Then the system returns 134 to the return point 118 of the PLL loop in process 100.

[0029] If the LOCK state is not present and the system determines 108 that the frequency is in the in the third state, indicated with 2 in Figure 1, then the system determines 136 the polarity. If the polarity is 0 (positive), then the system sets 138 the PIL-PLL (pilot phase-locked loop) PLL frequency to 18 MHz and changes the polarity of the phase frequency detector (PFD) to positive (0). Then the system sets 140 the polarity of the phase frequency detector (PFD) to negative (1). This shifts the VCO to an extreme frequency point. Then the system returns 142 to the return point 118 of the PLL loop in process 100.

[0030] If instead when the system determines 110 that the polarity is 1 (negative), then the system sets 144 the PIL-PLL (pilot phase-locked loop) PLL frequency to 18 MHz and changes the polarity of the phase frequency detector (PFD) to negative (1). Then the system sets 146 the frequency to the second state, indicated by a 1 in Figure 1, and the polarity of the phase frequency detector (PFD) to positive (0). Then the system returns 142 to the return point 118 of the PLL loop in process 100.

[0031] In the exemplary embodiment, the desired "Target" frequency is 10.8 MHz. Setting 126 the desired frequency and changing the polarity causes a shift in the VCO from the extreme frequency point. If, during the PLL transition, it locks onto the correct frequency (10.8 MHz), it sets the LOCK state, and the process 100 only checks for the presence of PLL LOCK.

[0032] In the case where the shift from 7 MHz to 10.8 MHz is unsuccessful, the routine sets another edge frequency of 18 MHz and begins testing the LOCK state again.

[0033] Figure 2 illustrates an exemplary transceiver 200 for frequency stabilization using the process 100 (shown in Figure 1).

[0034] At least one of the technical problems addressed by this system may include: (i) improved frequency stabilization; (ii) improved transmission accuracy; (iii) enhanced network performance; (iv) higher data throughput over the available frequency bands; and / or (v) improved bandwidth.

[0035] A technical effect of the systems and processes described herein may be achieved by performing at least one of the following steps: a) determine whether a Phase-Locked Loop (PLL) is in a LOCK state; b) if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to: i) set a PLL frequency to a first frequency; ii) change a polarity of a phase frequency detector to positive; iii) change the polarity of the phase frequency detector to negative; iv) set the PLL frequency to a second frequency; v) change the polarity of the phase frequency detector; and vi) monitor for a PLL transition to the LOCK state; c) determine whether a Phase-Locked Loop (PLL) is in a LOCK state; d) if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to: i) set a PLL frequency to a third frequency; ii) change a polarity of a phase frequency detector to positive; iii) change the polarity of the phase frequency detector to negative; and iv) monitor for a PLL transition to the LOCK state; and / or e) wherein the first frequency is 7 MHz, wherein the second frequency is 10.8 MHz, and where the third frequency is 18 MHz.ADDITIONAL CONSIDERATIONS

[0036] As will be appreciated based upon the foregoing specification, the above-described embodiments of the disclosure may be implemented using computer programming or engineering techniques including computer software, firmware, hardware or any combination or subset thereof Any such resulting program, having computer-readable code means, may be embodied or provided within one or more computer-readable media, thereby making a computer program product, i.e., an article of manufacture, according to the discussed embodiments of the disclosure. The computer-readable media may be, for example, but is not limited to, a fixed (hard) drive,diskette, optical disk, magnetic tape, semiconductor memory such as read-only memory (ROM), and / or any transmitting / receiving medium such as the Internet or other communication network or link. The article of manufacture containing the computer code may be made and / or used by executing the code directly from one medium, by copying the code from one medium to another medium, or by transmitting the code over a network.

[0037] These computer programs (also known as programs, software, software applications, “apps,” or code) include machine instructions for a programmable processor and can be implemented in a high-level procedural and / or object-oriented programming language, and / or in assembly / machine language. As used herein, the terms “machine-readable medium” “computer-readable medium” refers to any computer program product, apparatus and / or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The “machine-readable medium” and “computer-readable medium,” however, do not include transitory signals. The term “machine-readable signal” refers to any signal used to provide machine instructions and / or data to a programmable processor.

[0038] As used herein, the term “database” can refer to either a body of data, a relational database management system (RDBMS), or to both. As used herein, a database can include any collection of data including hierarchical databases, relational databases, flat file databases, object-relational databases, object-oriented databases, and any other structured collection of records or data that is stored in a computer system. The above examples are example only, and thus are not intended to limit in any way the definition and / or meaning of the term database. Examples of RDBMS’ include, but are not limited to including, Oracle® Database, MySQL, IBM® DB2, Microsoft® SQL Server, and PostgreSQL. However, any database can be used that enables the systems and methods described herein. (Oracle is a registered trademark of Oracle Corporation, Redwood Shores, California; IBM is a registeredtrademark of International Business Machines Corporation, Armonk, New York; and Microsoft is a registered trademark of Microsoft Corporation, Redmond, Washington.)

[0039] As used herein, a processor may include any programmable system including systems using micro-controllers, reduced instruction set circuits (RISC), application specific integrated circuits (ASICs), logic circuits, and any other circuit or processor capable of executing the functions described herein. The above examples are example only and are thus not intended to limit in any way the definition and / or meaning of the term “processor.”

[0040] As used herein, the terms “software” and “firmware” are interchangeable and include any computer program stored in memory for execution by a processor, including RAM memory, ROM memory, EPROM memory, EEPROM memory, and non-volatile RAM (NVRAM) memory. The above memory types are example only and are thus not limiting as to the types of memory usable for storage of a computer program.

[0041] In another example, a computer program is provided, and the program is embodied on a computer-readable medium. In an example, the system is executed on a single computer system, without requiring a connection to a server computer. In a further example, the system is being run in a Windows® environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another example, the system is run on a mainframe environment and a UNIX® server environment (UNIX is a registered trademark of X / Open Company Limited located in Reading, Berkshire, United Kingdom). In a further example, the system is run on an iOS® environment (iOS is a registered trademark of Cisco Systems, Inc. located in San Jose, CA). In yet a further example, the system is run on a Mac OS® environment (Mac OS is a registered trademark of Apple Inc. located in Cupertino, CA). In still yet a further example, the system is run on Android® OS (Android is a registered trademark of Google, Inc. of Mountain View, CA). In another example, the system is run on Linux® OS (Linux is a registered trademark of Linus Torvalds ofBoston, MA). The application is flexible and designed to run in various different environments without compromising any major functionality.

[0042] In some embodiments, the system includes multiple components distributed among a plurality of computing devices. One or more components may be in the form of computer-executable instructions embodied in a computer-readable medium. The systems and processes are not limited to the specific embodiments described herein. In addition, components of each system and each process can be practiced independent and separate from other components and processes described herein. Each component and process can also be used in combination with other assembly packages and processes.

[0043] As used herein, an element or step recited in the singular and proceeded with the word “a” or “an” should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to “example” or “one example” of the present disclosure are not intended to be interpreted as excluding the existence of additional examples that also incorporate the recited features. Further, to the extent that terms “includes,” “including,” “has,” “contains,” and variants thereof are used herein, such terms are intended to be inclusive in a manner similar to the term “compnses” as an open transition word without precluding any additional or other elements.

[0044] Furthermore, as used herein, the term “real-time” refers to at least one of the time of occurrence of the associated events, the time of measurement and collection of predetermined data, the time to process the data, and the time of a system response to the events and the environment. In the examples described herein, these activities and events occur substantially instantaneously.

[0045] The patent claims at the end of this document are not intended to be construed under 35 U.S.C. § 112(f) unless traditional means-plus-function language is expressly recited, such as “means for” or “step for” language being expressly recited in the claim(s).

[0046] This writen description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.

Claims

WHAT IS CLAIMED IS:

1. A communication system comprising at least one transceiver comprising at least one processor in communication with at least one memory device configured to store computer-executable instructions, which, when executed by the processor, cause the transceiver to: determine whether a Phase-Locked Loop (PLL) is in a LOCK state; if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to: set a PLL frequency to a first frequency; change a polarity of a phase frequency detector to positive; change the polarity of the phase frequency detector to negative; set the PLL frequency to a second frequency; change the polarity of the phase frequency detector; and monitor for a PLL transition to the LOCK state.

2. The system in accordance with Claim 1, wherein the instructions further cause the transceiver to: determine whether a Phase-Locked Loop (PLL) is in a LOCK state; if the determination is that the PLL is not in a LOCK state, the instructions cause the transceiver to: set a PLL frequency to a third frequency; change a polarity of a phase frequency detector to positive;change the polarity of the phase frequency detector to negative; and monitor for a PLL transition to the LOCK state.3 The system of Claim 2, wherein the first frequency is 7 MHz, wherein the second frequency is 10.8 MHz, and where the third frequency is 18 MHz.

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