N-way doherty power amplifier supporting ghz modulation bandwidth and its integration in transceiver front-end modules

Abstract

An electronic device includes an N-way Doherty power amplifier with an amplifier input and an amplifier output, wherein N is an integer larger than or equal to two, a number of transformers for the Doherty output network, wherein the number of transformers is N-l; and a high-speed adaptive biasing circuit. A transmit / receive front-end module that integrates the N-way Doherty amplifier with a low-noise amplifier and a transmit / receive switch, occupying a compact area.

Description

N-WAY DOHERTY POWER AMPLIFIER SUPPORTING GHz MODULATION BANDWIDTH AND ITS INTEGRATION IN TRANSCEIVER FRONT-END MODULESCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This PCT application claims priority to and the benefit of the filing date of U.S. Provisional Patent Application 63 / 554,598, filed on February 16, 2024.BACKGROUND

[0002] In the rapidly evolving landscape of wireless communication technologies, the demand for enhanced efficiency and performance in power amplifiers (PAs) has become increasingly imperative. For example, PAs play a pivotal role in transmitting high-output power signals to antennas, making them critical components in mobile devices, base stations, and various wireless transceivers. As the advent of 5G and subsequent generations of cellular communications, alongside Wi-Fi advancements, introduces new challenges such as high peak-to-average-power-ratios (PAPR) and broader channel bandwidth requirements, conventional PA architectures, particularly Doherty PAs, face limitations.

[0003] Current 2-way Doherty PAs, while effective, fall short in providing sufficient efficiency enhancement at deep back-offs, proving inadequate for the demands of 5G New Radio (NR) signals. The proposed N-way Doherty architecture presented in this invention addresses these challenges by introducing a novel approach, utilizing N-l transformers to achieve lower losses, smaller chip areas, and higher efficiency, while also integrating a high-speed adaptive biasing circuit that surpasses existing modulation bandwidth limitations.SUMMARY

[0004] This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identifykey or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

[0005] One or more embodiments of the invention are directed to an N-way Doherty amplifier with an amplifier input and an amplifier output, N sub-power amplifiers, wherein N is an integer larger than or equal to two; and N-l transformers, wherein one of the N sub-power amplifiers is a main amplifier and a remaining N-l amplifiers are peaking amplifiers, and wherein an N* amplifier and an N-lthamplifier share a single transformer footprint.

[0006] One or more embodiments of the invention are directed to a method for realizing the output network of an N-way Doherty power amplifier using N-l transformers. The method includes inserting a number of ideal transformers into a quarter-wave transmission line-based Doherty architecture; replacing all transmission lines with equivalent networks; rearranging shunt inductors and capacitors; consolidating series inductors, the shunt inductors, and the ideal transformers into the number of physical transformers; and converting the networks to a differential configuration to interface with differential power cells. The number N is an integer larger than or equal to two and the number of transformers is less than N.

[0007] One or more embodiments of the invention are directed toward an N-way Doherty output network with an amplifier input and an amplifier output, N sub-power amplifiers, wherein N is an integer larger than or equal to two; N-l transformers; a power divider; and a high-speed adaptive biasing circuit; wherein an input signal is divided by the power divider into N paths, wherein each of the N paths includes a chain of driver stages and an output stage, wherein a main path of the N paths has a fixed biasing, and wherein a remaining N-l paths of the N paths are peaking paths and adopt high-speed adaptive biasing.

[0008] One or more embodiments of the invention are directed toward a front-end module with an N-way Doherty power amplifier; a high-speed adaptive biasing circuit; a low-noise amplifier (LNA); a set of switches; and an inductor, wherein the inductor is shared between the N-way Doherty power amplifier and the low-noise amplifier.

[0009] Other aspects and advantages of one or more embodiments disclosed herein will be apparent from the following description and the appended claims.BRIEF DESCRIPTION OF DRAWINGS

[0010] The following is a description of the figures in the accompanying drawings. In the drawings, identical reference numbers identify similar elements or acts. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. For example, the shapes of various elements and angles are not necessarily drawn to scale, and some of these elements may be arbitrarily enlarged and positioned to improve drawing legibility. Further, the particular shapes of the elements as drawn are not necessarily intended to convey any information regarding the actual shape of the particular elements and have been solely selected for ease of recognition in the drawing.

[0011] FIG. 1 shows a circuit diagram in accordance with one or more embodiments of the invention.

[0012] FIGs. 2A, 2B, 2C, 2D and 2E show circuit diagrams in accordance with additional embodiments of the invention.

[0013] FIGs. 3A, 3B, 3C, 3D and 3E show circuit diagrams in accordance with additional embodiments of the invention.

[0014] FIGs. 4A-4F show circuit diagrams in accordance with additional embodiments of the invention.

[0015] FIGs. 5A, 5B, 5C and 5D show circuit diagrams in accordance with additional embodiments of the invention.

[0016] FIG. 6 shows a diagram in accordance with one or more embodiments of the invention.

[0017] FIG. 7 shows a circuit diagram of components incorporated in the one or more embodiments of the invention shown in FIG. 6.

[0018] FIG. 8 shows a diagram in accordance with one or more embodiments of the invention.

[0019] FIG. 9 depicts a flowchart of a method in accordance with one or more embodiments of the invention.

[0020] FIG. 10 shows a circuit diagram in accordance with one or more embodiments of the invention.

[0021] FIGs. 11A and 11B show circuit diagrams in accordance with one or more embodiments of the invention.

[0022] FIG. 12 depicts a flowchart of a method for operating one or more embodiments of the invention.DETAILED DESCRIPTION

[0023] Specific embodiments of the invention will now be described in detail with reference to the accompanying figures.

[0024] In the following detailed description of embodiments of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0025] Throughout the application, ordinal numbers (e.g., first, second, third, etc.) may be used as an adjective for an element (i.e., any noun in the application). The use of ordinal numbers is not to imply or create any particular ordering of the elements nor to limit any element to being only a single element unless expressly disclosed, such as using the terms "before", "after", "single", and other such terminology. Rather, the use of ordinal numbers is to distinguish between the elements. By way of an example, a first element is distinct from a second element, and the first element may encompass more than one element and succeed (or precede) the second element in an ordering of elements.

[0026] It is to be understood that the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to an “on-demand electrode” includes reference to one or more of such on-demand electrodes.

[0027] Terms such as “approximately,” “substantially,” etc., mean that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide.

[0028] It is to be understood that one or more of the steps shown in the method may be omitted, repeated, and / or performed in a different order than the order shown. Accordingly, the scope disclosed herein should not be considered limited to the specific arrangement of steps shown in the method.

[0029] Although multiple dependent claims are not introduced, it would be apparent to one of ordinary skill that the subject matter of the dependent claims of one or more embodiments may be combined with other dependent claims.

[0030] In the following description of FIGs. 1-12, any component described with regard to a figure, in various embodiments disclosed herein, may be equivalent to one or more like-named components described with regard to any other figure. For brevity, descriptions of these components will not be repeated with regard to each figure. Thus, each and every embodiment of the components of each figure is incorporated by reference and assumed to be optionally present within every other figure having one or more like-named components. Additionally, in accordance with various embodiments disclosed herein, any description of the components of a figure is to be interpreted as an optional embodiment which may be implemented in addition to, in conjunction with, or in place of the embodiments described with regard to a corresponding like-named component in any other figure.

[0031] As 5G communication continues to advance in the FR2 frequency band (24.25 to 71 GHz), along with future beyond-5G communication planned for the FR3 frequency band (7.125 to 24.25 GHz), achieving high energy efficiency in poweramplifiers (PAs) and front-end modules (FEMs) remains a critical design challenge. Modem wireless communication systems, including cellular and Wi-Fi, commonly employ a series of advanced modulation techniques, such as high-order quadrature amplitude modulation (QAM), orthogonal frequency-division multiplexing (OFDM), and carrier aggregation (CA), to enhance spectral efficiency and data rates and enable resilience to multi-path effects. However, these advanced modulation schemes lead to large peak-to-average power ratios (PAPR), which in turn, leads to compromised energy efficiency of PAs and FEMs. For example, a typical 5G NR 1-CC 64-QAM OFDM signal has a PAPR of 10-12dB. If a conventional Class-B PA is used to amplify this signal, although its peak efficiency can be high, the average efficiency is only 1 / 4 to 1 / 3 of its peak efficiency. Such low efficiency must be addressed by advanced PA architectures and circuit techniques to enhance the back-off efficiency.

[0032] This motivates the development of PA with back-off efficiency enhancement, i.e., to enhance the average efficiency of the PA when amplifying high-PAPR signals. Doherty PA is a classic architecture for realizing back-off efficiency enhancement. It has been extensively used in sub-6GHz base stations. However, existing Doherty PAs face three challenges in the context of millimeter wave (mmWave) 5G. First, classic Doherty can only provide efficiency enhancement up to 6-dB back-off, which is insufficient for 5G NR signals that usually have a PAPR of 10-12 dB. Second, Doherty PAs usually have a narrow modulation bandwidth, making it challenging to meet the 2000-MHz channel bandwidth requirement in the latest 3GPP 5G standard (3GPP V17.6.0). Third, the PA needs to be integrated with a low-noise amplifier (LNA) and a Transmit / Receive (T / R) Switch as a FEM in practical use. However, existing Doherty PAs are only demonstrated at the individual component level but have not yet been demonstrated in a functional FEM.

[0033] In one or more embodiments, this invention addresses the aforementioned challenges and introduces three circuit innovations to advance Doherty PA for wireless transceivers in mobile devices and base stations, particularly for 5G and future generations of cellular communications and Wi-Fi. More specifically, first, this invention proposes a new N-way Doherty network using N-l transformers, i.e., one fewer transformer, and thus lower loss and chip area than conventional designs. Forexample, when choosing N = 4, the resulting 4-way Doherty network occupies a footprint similar to a typical 3 -way Doherty PA, while still achieving the desired 4- way Doherty load modulation. Additionally, compared to existing linear PAs, the 4- way Doherty can achieve at least 1.5x total efficiency enhancement.

[0034] Second, this invention proposes a high-speed adaptive biasing circuit, which addresses the modulation bandwidth bottleneck of existing Doherty implementations. By utilizing compact inductors and optimizing circuit topology, this invention supports modulation bandwidths of at least 400 MHz and up to approximately 2 GHz, thereby meeting the bandwidth requirement of the latest 3GPP 5G standard.

[0035] Third, this invention introduces a FEM solution and a TX-RX co-design approach that integrates the proposed compact Doherty PA with the LNA and T / R switch. This enables a similar FEM footprint compared to existing FEMs that utilize linear Class-AB PAs, while significantly enhancing the TX-mode energy efficiency over prior art.

[0036] This invention has wide applications that include but are not limited to the development of radio transceivers for 5G and future generations of cellular communications and Wi-Fi. Potential uses for the invention include but are not limited to wireless communication, radar, and sensing systems, which need to deliver a high output power to the antenna for radiation.

[0037] In one or more embodiments, FIG. 1 shows an N-way Doherty power amplifier with N-l transformers. It is based on a key insight that the N111and the N-lthpeaking amplifiers form a 2-way sub-Doherty and can be implemented in a single transformer footprint. The choice of N highly depends on the signal PAPR, the operating frequency, and the transistor technology. For example, a two-way Doherty PA (i.e., N = 2) is well suited for amplifying single-carrier modulated signals with a PAPR of ~6 dB, while a multi-way Doherty PA offers higher efficiency for high-PAPR signals such as OFDM-based 5GNR signals with multiple component carriers.

[0038] The N-way Doherty power amplifier (1000) of FIG. 1 comprises N power amplifiers (101, 102, 103, 104 and 106) and N-l transformers (105, 107, 109 and 111). The power amplifier has a main amplifier (101) and the N* amplifier (103) andthe N-lthamplifier (106) share a single transformer (107). Additional capacitors (115, 117, 119, 121, 123, 125, 127, 129, 131, 133, and 135) are included in the circuit and all paths are combined into one output (113).

[0039] The N-way Doherty power amplifier of FIG. 1 requires N to be greater than or equal to 2. Additional embodiments of an N-way Doherty output network where N = 2 are depicted in FIGs. 2A-2E. FIGs. 2A and 2B depict the two foundational Doherty PA architectures, the two-way parallel Doherty (2001) and the two-way series Doherty (2002), respectively. The two-way parallel Doherty PA depicted in FIG. 2A utilizes current sources for the main amplifier (201) and peaking amplifier (203). A quarter-wave transmission line (205), functioning as an impedance inverter, is attached to the main amplifier’s output (213). This configuration has become the most common Doherty PA topology as current sources can be readily implemented using transistors. Using a “hypothetical” voltage source for the peaking amplifier (203), which is then combined with the main amplifier (201), leading to the two-way series Doherty PA depicted in FIG. 2B (2002). The two transformers (207, 209) enable the series-combining of the main and peaking amplifiers into one output (213).

[0040] There are several variations of the two-way series Doherty architecture. First, the ideal-transformers (207, 209) in the series combiner (shown in FIG. 2B) can be replaced by two parallel-connected transmission lines (211, 215), leading to the Doherty PA (2003) shown in FIG. 2C. In addition, at higher frequencies where the voltage source becomes challenging to implement, it can be replaced by a current source in series with a quarter- wave transmission line (221 in FIG. 2D and 227 in FIG. 2E), yielding another two series Doherty PA embodiments (2004 and 2005) shown in FIG. 2D and FIG. 2E. The two transformers (217, 219) in FIG. 2D and the two transmission lines (223, 225) in FIG. 2E enable the series-combining of the main and peaking amplifiers into one output (213). A person of ordinary skill in the art will recognize that additional 2-way Doherty architectures may be realized, and the embodiments shown in FIGs. 2A-2E are shown for illustrative purposes.

[0041] Embodiments disclosed herein propose a systematic approach to scaling an N- 1 way Doherty PA to N ways. The key idea is to treat an existing N-l way DohertyPA as a “sub-Doherty,” which represents the aggregation of N-l peaking amplifiers within a larger N-way Doherty PA. This N-l way sub-Doherty is then combined with a new main amplifier using an appropriate combiner circuit, as illustrated in FIGs 3 A- 3E. In other words, in one or more embodiments, an N-way Doherty PA can be created by adding a main amplifier (301) to an existing N-l way sub-Doherty (303).

[0042] The selection of the combiner circuit depends on the output impedance (AOUT) of the A-l way sub-Doherty (303). If AOUT presents an open circuit (OC), which implies that the A-l way sub-Doherty behaves as a current source, the combiner should mirror the connections used for the current-source peaking amplifier in two- way Doherty PAs (for example, FIGs. 2A, 2D, 2E). For an N-way Doherty PA these combiner circuits are depicted in FIGs. 3A, 3D and 3E (3001, 3004, 3005). The N- way Doherty PA in FIG. 3A (3001) includes the main amplifier (301) and a corresponding transmission line (305) attached to the main amplifier’s output (313). In another embodiment, the N-way Doherty PA shown in FIG. 3D (3004) includes two transformers (317, 319) and an additional transmission line (321) attached to the output of the N-l way sub-Doherty (303). In yet another embodiment, the N-way Doherty PA in FIG. 3E (3005) includes two transmission lines (323 and 325) and an additional transmission line (327) attached to the output of the N-l way sub-Doherty (303).

[0043] If AOUT presents a short circuit (SC), which implies that the A-l way sub-Doherty behaves as a voltage source, the combiner should mirror the connections used for the voltage- source peaking amplifier in two-way Doherty PAs (for example, FIGs. 2B and 2C). This can be expanded to an N-way Doherty PA using the combiner circuits depicted in FIGs. 3B and 3C (3002, 3003). The N-way Doherty PA depicted in FIG. 3B includes two transformers (307, 309) included as part of the passive network to combine all amplifiers into one output (313). In another embodiment, the N-way Doherty PA shown in FIG. 3C includes two transmission lines (311, 315) included as part of the passive network to combine all amplifiers into one output (313).

[0044] Following the approach described above, FIGs. 4A-4F present several possible three-way Doherty PAs, extended from two-way parallel Doherty PAs or two-way series Doherty PAs. For the two-way parallel Doherty PA in FIG. 2A, its output impedance exhibits an SC. Consequently, when extending it to a three-way Doherty PA, the addition of the new main amplifier needs to follow FIG. 3B or 3C, using either an ideal -transformer-based series combiner (4001; see FIG. 4A) or a two-transmission line-based series combiner (4002; see FIG. 4B). The 3-way Doherty PA depicted in FIG. 4 A (4001) includes a main amplifier (401), a 2-way sub-Doherty PA (2001) and two transformers (405, 407) which serve as a series combiner to combine all amplifiers into one output (413). In another embodiment, the 3-way Doherty PA depicted in FIG. 4B (4002) includes a main amplifier (401), a 2-way sub-Doherty PA (2001) and two transmission lines (409, 411) which serve as a series combiner to combine all amplifiers into one output (413).

[0045] For the two-way series Doherty PAs in FIG. 2B-2E, its output impedance exhibits either an SC (as in FIG. 2C and 2E) or an OC (as in FIG. 2B and 2D). As such, additional embodiments can be realized, as shown in FIGs. 4C to 4F. The 3-way Doherty PA depicted in FIG. 4C (4003) includes a main amplifier (401), a 2- way sub-Doherty PA (2003) and two transformers (414, 415) which serve as a series combiner to combine all amplifiers into one output (413). In another embodiment, the 3 -way Doherty PA depicted in FIG. 4D (4004) includes a main amplifier (401), a 2- way sub-Doherty PA (2003) and two transmission lines (417, 419) which serve as a series combiner to combine all amplifiers into one output (413). In yet another embodiment, the 3 -way Doherty PA depicted in FIG. 4E (4005) includes a main amplifier (401), a 2-way sub-Doherty PA (2005), and two transformers (421, 423) which serve as a series combiner to combine all amplifiers into one output (413). In yet another embodiment, the 3 -way Doherty PA depicted in FIG. 4F (4006) includes a main amplifier (401), an additional transmission line (429) attached to the output of the 2-way sub-Doherty PA (2004) and two transformers (425, 427) which serve as a series combiner to combine all amplifiers into one output (413). A person of ordinary skill in the art will recognize that further embodiments of a 3 -way Doherty PA maybe realized, and the embodiments shown in FIGs. 4A-4F are not intended to limit the scope of the present invention.

[0046] It is worth noting that the three-way Doherty PA embodiments in FIG. 4 are derived systematically using the proposed extension technique. Hence, they all follow the desired three-way Doherty load modulation behavior, which can be further verified by analyzing the current and voltage profiles at each amplifier output.

[0047] Extending three-way Doherty PAs to four-way Doherty PAs can be achieved using the same proposed extension technique. The combiner circuit selection depends on the output impedance of the three-way sub-Doherty. A number of four-way Doherty PA examples are depicted in FIGs. 5A-5D. A person of ordinary skill in the art will recognize that further embodiments of a four-way Doherty PA may be realized, and the embodiments shown in FIGs. 5A-5D are not intended to limit the scope of the present invention. In one exemplary embodiment shown in FIG. 5A, a main amplifier (501) and a corresponding transmission line (505) is attached to the main amplifier’s output (513). An additional transmission line (507) is attached to the output of a 3-way sub-Doherty PA (4002). In another embodiment, the 4-way Doherty PA depicted in FIG. 5B, comprises a main amplifier (501), a 3-way sub-Doherty PA (4001) and a transmission line (509) attached to the main amplifier’s output (513). In yet another embodiment, depicted in FIG. 5C, the 4-way Doherty PA includes a main amplifier (501), an additional transmission line (515) attached to the output of the 3- way sub-Doherty PA (4001) and two transformers (511, 512) which serve as a series combiner to combine all amplifiers into one output (513). In yet another embodiment, the 4-way Doherty PA depicted in FIG. 5D includes a main amplifier (501), an additional transmission line (521) attached to the output of the 3 -way sub-Doherty PA (4006) and two transformers (517, 519) which serve as a series combiner to combine all amplifiers into one output (513).

[0048] This proposed framework provides a person of ordinary skill in the art with a comprehensive library of customizable templates, which in turn allows for circuit design tailored to specific application needs. Importantly, all embodiments presentedin FIGs. 2-5 can achieve the desired Doherty load modulation without early compression of the main amplifier, addressing a common concern in previous multiway Doherty PA designs. A person of ordinary skill in the art will recognize that all embodiments presented in FIGs. 2-5 are for illustrative purposes and are not intended to depict all possible realizations of multi-way Doherty PAs.

[0049] An efficiency comparison of N-way Doherty PAs with N = 2 to 4, assuming their output networks are designed using quarter-wave transmission lines with a practical transmission line loss, shows that a 4-way Doherty PA achieves 1.44* power saving over a 2-way Doherty when amplifying an OFDM signal with 12dB PAPR. The 4-way Doherty exhibits 3 additional efficiency peaks at 4.1dB, 9.5dB, and 12dB PBO.

[0050] As proof of concept, this invention also presents a 4-way Doherty PA for the 47GHz 5G band (n262). It achieves 24.0dBm PSAT, 23.7dBm PMB, 26.8% peak PAE (PAEPEAK), 21.7% PAE at 6dB PBO (PAE6dB), and 13.1% PAE at 12dB PBO (PAEi2dB), advancing state of the art. For the first time, it has been demonstrated a 2000MHz channel bandwidth for 5G NR 64-QAM OFDM with 14.1dBm Pavgand 13.7% PAEavg. The 2000 MHz bandwidth is achieved with high-speed adaptive biasing.

[0051] FIG. 6 shows the proposed high-speed adaptive biasing circuit featuring compact inductors Lsi (609) and Ls2 (613) to enhance bandwidth while achieving fundamental rejection with negligible area overhead. The adaptive biasing circuit (617) consists of two stages: the first stage is an envelope detector (ED; 607) that extracts the signal envelope, and the second stage is a buffer (611) to drive the large parasitic capacitance of the power cell. The ED can be realized in either a single-ended or a differential fashion.

[0052] Specifically, as shown in FIG. 6, in one or more embodiments, adaptive biasing is a key component for mmWave Doherty PAs to ensure the desired cooperation between the Main and Peaking paths. Typically, a differential envelope detector (ED; 607) may be used at the driver (DRV; 603) input to extract the signal envelope. The ED extracts envelope or magnitude information from a signal. However, thecombined parasitic capacitance of the ED (74fF) and DRV (123fF) may be too large for the proposed design, causing ~ldB extra loss for the balun (605) compared to the case without the ED. Alternatively, a single-ended ED is attached to the balun input, where the capacitor budget is large enough to fully absorb the ED parasitic capacitance. However, single-ended EDs cannot provide sufficient fundamental rejection, especially under large modulation BW. To address this issue, an LC notch filter (615; FIG. 7) may be introduced and disposed between the ED and the following buffer (611; FIG. 7). Note that Lsi (609) is designed to fit into the existing routing space between the ED (607) and buffer (611) as shown in FIG. 6, resulting in negligible area overhead.

[0053] The adaptive biasing bandwidth is usually limited by the second-stage buffer, as it is loaded by the large input capacitance of the power cell (~lpF in the proposed design). An insufficient bandwidth prevents the buffer output VAB from being fully charged or discharged to the desired voltage level when the PA output envelope is sampled, leading to EVM degradation. To increase the buffer bandwidth, a shuntpeaking inductor Ls2 (613) is introduced (FIG. 7). The buffer response can then be modeled as an RLC second-order network. Based on this model, the buffer bandwidth under different Ls2 values can be examined. With Ls2 = 700pH, which has a damping factor S, = 0.7, the bandwidth can be extended by 87% without overshoot. It is worth noting that the quality factor of Ls2 is not a concern, as an additional series Rs is naturally needed to provide sufficient buffer gain. Therefore, Ls2 is implemented in a compact footprint (23*23pm2), adding negligible area.

[0054] FIG. 8 illustrates a top-level schematic, EM model of the output network, nonoverlapped transistor layout scheme. More specifically, in one or more embodiments, the PA top-level schematic and the EM model of the output network are shown in FIG. 8. The input signal (625) is distributed into 4 paths using a power divider (619) followed by 2 EQ hybrids (621), achieving the desired phase relationship. Each path contains a common-source driver (DRV; 603) and a cascade output stage (PA; 601) which forms the main amplifier (501) and the peaking amplifiers (401, 201 and 203). The main path has fixed biasing for its DRV and output stage, while the 3 peaking paths adopt high-speed adaptive biasing to ensure the desired current relationshipamong the four paths. The interconnect parasitic between the three transformers (505, 405, 205) and the output GSG pads (623) are fully absorbed in the design (FIG. 8). Specifically, the parasitic inductances between the peaking 1 (405) and peaking 2 (205) transformers are compensated by decreasing Cs2 (627), and the parasitic capacitances looking into the GSG pads (623) are absorbed by CM (629). Furthermore, in one or more embodiments, a non-overlapped transistor layout scheme may be implemented for the drain and source when routing them to higher metal layers. This reduces the parasitic Cds by 23%, which in turn, reduces the loss of the Doherty network.

[0055] The EM-simulated load modulation performance and passive efficiency of the output network shows that at peak power, the main and 3 peaking paths all see a well- balanced ROPT of 22Q. At 12dB PBO, the main path sees 70Q (3.2XROPT), and the 3 peaking paths see high impedance, demonstrating close-to-ideal 4-way Doherty load modulation behavior. The passive efficiency is 66.7%-72.4% across different PBO levels, which is equivalent to 1.76-1.4dB loss. Such a low loss is mainly due to the reduced number of transformers in the design.

[0056] In one or more embodiments according to FIG. 8, the proposed PA prototype is implemented in a 45nm complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) process. In one or more embodiments, this technology can be applied to other CMOS process nodes too, and other semiconductor processes such as SiGe, GaAs, InP, and GaN.

[0057] The network synthesis flow is depicted in the flowchart in FIG. 9. Initially, the first step (701) is inserting N-l ideal transformers into a transmission line-based Doherty. These ideal transformers enable the desired impedance scaling from / G i to AOPT. They will be merged with series and shunt inductors around them to form on- chip physical transformers in a later step. In step (702), all quarter-wave transmission lines are replaced with equivalent C-L-C or L-C-L TI networks, which includes shunt components on both sides allowing for direct re-positioning of these components around the ideal transformers. At this stage, in step (703), the shunt inductors and capacitors are rearranged so that the series inductors, shunt inductors, and idealtransformers are consolidated into N-l physical transformers in step (704). The N- way Doherty now includes N-l physical transformers along with additional capacitors. Finally, in step (705), the network is converted to differential to interface with differential power cells. It is important to note that the proposed network not only realizes N-way Doherty load modulation but also achieves the desired impedance transformation from the 50Q RANT to the optimal impedance ROPT and effectively absorbs the device parasitic capacitance CDEV. All transformer design parameters and capacitance values have been theoretically derived to guide the proposed design.

[0058] Small signal S-parameter measurement results of the exemplary embodiment of the four- way Doherty PA presented in FIG. 8 shows a 17.1-dB gain at the center frequency of 47 GHz. The measured 21 3-dB bandwidth is 7.4 GHz with a wide -10-dB 5n bandwidth. The measured S12 is below -45 dB across the S21 3-dB bandwidth. The large-signal power sweep at 47 GHz demonstrates 23.7-dBm Pi dB, 24.0-dBm PSAT, and 26.8% PAEPEAK. PAEe dB and PAEndB are 21.7% and 13.1%, respectively, achieving 1.6* and 2. Ox efficiency enhancement over an ideal Class-B PA. To verify the cooperation among the four paths, the DC currents of the four output stages were measured. The three peaking paths turn on sequentially with a rapid ramp- up. This desired current relationship is achieved by adjusting the control voltages of the adaptive biasing circuit within each peaking path. The large-signal frequency sweep demonstrates a PSAT 1-dB bandwidth of 42.5-50 GHz. A large-signal power sweep at 47 GHz for three samples showed gain and PSAT variations less than 0.1 dB, demonstrating the robustness of the design. Additionally, the large-signal power sweep was performed with the adaptive biasing circuit enabled and disabled. Adaptive biasing can be effectively disabled by setting both the ED supply and gate bias to 0. Due to the DC coupling between the ED output and the buffer gate, this action ensures that the buffer transistor is turned off. In this state, the output voltage of the adaptive biasing is solely determined by the buffer supply voltage, allowing for constant biasing control. When the adaptive biasing is disabled, i.e., turning off the ED and biasing the peaking paths in the Class-C region, Pi dB drops by 2.5 dB from 23.7 to 21.2 dBm, and PAE12 dB drops by 1.7x from 13.1% to 7.7%. These results highlightthe advantages of the adaptive biasing circuit in terms of efficiency and linearity enhancement for Doherty PAs.

[0059] Modulation measurements were performed with 800MHz and 2000MHz 5G NR FR2 1-CC 64-QAM OFDM signals. Specifically, the PA using an 800MHz 5G NR FR2 1-CC 64-QAM OFDM signal with 9.8dB PAPR achieves 14.1dBm Pavgand 13.8% PAEavg at -25dB EVM without DPD. The measured Pavgand PAEavgat -25dB EVM remain similar for 2000MHz channel bandwidth, demonstrating the high-speed envelope tracking capability of the proposed adaptive biasing circuit. This is likely the first silicon PA demonstration of 2000MHz channel bandwidth for 5G NR OFDM, along with back-off efficiency enhancement up to 12dB PBO.

[0060] In comparison with recently reported multi-way Doherty PAs at 28 and 38GHz, this PA achieves the highest PAEPEAK, PAEedB, and PAEndB with a competitive PSAT and PidB, despite operating at a higher frequency of 47GHz. To make a fair comparison across frequencies, according to one or more embodiments, the “normalized efficiency” is defined as the measured PAE divided by the highest PAEPEAK reported at each PA’s operating frequency. As a non-limiting example, the measured PAEPEAK of the PA is 26.8%, and the highest reported PAEPEAK in the 47- GHz band is 34.3%. Therefore, the normalized PAEPEAK of this four-way Doherty network design is 26.8% / 34.3% = 77.5%.

[0061] Compared with previous 3-way and 4-way Doherty, this PA achieves superior normalized PAEPEAK, PAEedB, and PAEndB. Additionally, compared with a 2-way Doherty, this PA achieves >1.25* higher normalized PAEedB with a comparable normalized PAEPEAK. These results demonstrate the unique advantage of the proposed N-way Doherty network.

[0062] PAs are typically integrated with a low-noise amplifier (LNA), and a transmit / receive (T / R) switch to form a front-end module (FEM) in mmWave beamformers and transceivers. As such, the performance of mmWave beamformers is largely determined by the FEM. Additionally, as mmWave beamformers and transceivers utilize multiple channels to form a phased array, and each channel incorporates a FEM, the FEM must be compact. To date, Doherty PAs have primarilybeen demonstrated as standalone building blocks, with only a few Doherty -PA-based FEMs reported. However, these demonstrations and their underlying design methodologies suffer from substantial size overhead and compromised efficiency.

[0063] Turning to FIG. 10, FIG. 10 depicts the front-end module (FEM) top-level schematic and a TX-RX co-design methodology for the PA output (801, 803) matching and LNA input (819) matching, along with embedded T / R switches (815), which enables optimal TX / RX performance within a compact size. As proof of concept, in one or more embodiments, this invention also presents a highly efficient 24-to-29GHz FEM with a compact core area of 0.22mm2, achieving a significant PAEavg enhancement of 1.5 * in 5G NR OFDM tests.

[0064] In the exemplary embodiment in FIG. 10, the PA employs a two-way asymmetric Doherty architecture, in which the peaking amplifier (803) is twice the size of the main amplifier (801) (i.e., the size of the peaking amplifier is larger than that of the main amplifier). Compared to conventional two-way symmetric Doherty PAs, the asymmetric Doherty architecture extends efficiency enhancement to deeper back-off levels (e.g., 9.5dB in this work), while maintaining a similar area. Simulated using an OFDM signal with a lOdB PAPR, the two-way asymmetric Doherty architecture achieves 1.22x PAEavg of the symmetric counterpart.

[0065] The antenna interface of the front-end module (FEM; 8000) consists of two transformers TXFi (805) and TXF2 (807), a compact inductor (Lp; 817), two series capacitors for matching (Csi; 811), two AC-coupling capacitors (Cs2; 812), and two sets of switches (SWi and SW2; 815). It is worth noting that the inductor Lp is shared between the TX and RX modes for area saving. As a result, the overall area of the PA output network and the LNA input network (819) is only 460x210pm2. With such a compact antenna interface, the overall FEM area is only 460x480 pm2= 0.22 mm2.

[0066] The switches in the device depicted in FIG. 10 allow for switching between a receive mode (depicted in FIG. 11 A) and a transmit mode (depicted in FIG. 1 IB).

[0067] In the RX mode (8001), switches SWi and SW2 (815) are both turned off (FIG. 11 A). The offstate SWi enables a high impedance looking into the PA, effectively minimizing leakage to the TX. The series inductor Lp and the transformer TXF2(which couples the gate and source of the input transistor) enable simultaneous LNA input matching and noise matching. Lp and TXF2 are co-designed to bring both ZOPT (the optimum source impedance for minimum NF) and ZIN (the LNA input impedance) to ~50Q. Additionally, a pair of gm-boosting capacitors (Cc) for the cascode transistors are included. As the noise contribution of cascode transistors becomes more significant at mm-wave frequencies, this gm-boosting technique effectively reduces their noise by 0.7dB in simulations.

[0068] In the TX mode (8002), switches SWi and SW2 are both turned on (FIG. 1 IB). The transformer TXFi and the shunt inductor Lp form the output matching network of the asymmetric Doherty PA. This network is synthesized following the synthesis flow described above and depicted in FIG. 9. Starting with a transmission-line-based asymmetric parallel Doherty PA and an LCL-based TI network between the PA and the 50Q RANT (813). This TI network down-scales RANT to Ro to achieve the desired output power level. It is worth noting that in an asymmetric Doherty PA, the optimum load impedance of the peaking amplifier (ROPT.P) is lower than that of the main amplifier ROPT,M). AS described above, in step 701, an ideal transformer is introduced between the quarter-wave transmission and the TI network. This ideal transformer is later merged with the surrounding inductors to form an on-chip physical transformer. In step 702 the quarter-wave transmission line is replaced with an equivalent CLC- based TI network. Next, in step 703, the shunt inductor and capacitor, are swapped between the primary and secondary sides. In step 704, the components are consolidated into a physical transformer. Note that the transistors’ parasitic capacitances (CDEV; 809) are absorbed by shunt capacitors (Cpi and Cp2). Finally, in step 705, the single-ended schematic is converted into differential to interface with capacitively neutralized power cells.

[0069] The PA input is split into two ways using an unequal 1 :2 I / Q hybrid. Both main and peaking amplifiers employ a differential cascode topology with capacitive neutralization. The size of the peaking amplifier is twice that of the main, enabling asymmetric Doherty operation with efficiency enhancement up to 9.5dB back-off. A series inductor is implemented between the cascode transistor and bottom transistor to improve gain and stability. The main amplifier (801) is biased in Class-AB, whilethe peaking amplifier (803) adopts an adaptive biasing circuit. At peak power, the main and peaking amplifiers see optimum impedances of 40Q and 24Q, respectively. At 9.5dB back-off, the main amplifier sees 11 I (2.8 *ROPT,M, as opposed to 2* in a two-way symmetric Doherty PA), while the peaking amplifier sees high impedance, demonstrating the desired asymmetric Doherty load modulation. The passive efficiency is 64.6% to 78.7% from small signal to peak power, equivalent to 1.9 to l.OdB loss.

[0070] The proposed PA matching network offers three key advantages. First, it enables asymmetric Doherty operation with an arbitrary impedance transformation ratio from RANT to ROPT.M and ROPT.P. AS a result, the component values of the network can be scaled to meet different power levels for different applications. Secondly, it employs only a single transformer (TXFi) along with a small inductor (Lp, shared with RX), leading to a compact area (0.1mm2). Finally, with both switches SWi and SW2 turned on, the voltage swing across switches is minimal, ensuring high linearity. Additionally, the parasitic capacitances of the switches can be absorbed by slightly adjusting Lp, allowing for a large switch size (128pm / 20nm) to reduce on-resistance.

[0071] The flowchart of FIG 12. depicts a method to operate the front-end module of FIG. 10 and switch between the TX and RX modes. To enter TX mode, the switches are turned on (901). To enter the RX mode, the switches are turned off (902).

[0072] The TX mode achieves 14.0dB peak gain with a 3dB BW of 24.1 to 31 ,4GHz. The continuous-wave (CW) power sweep at 25GHz demonstrates 20.8dBm PSAT, 20.3dBm OPidB, 27.3% PAE at OPidB (PAEpidB), and 19.8% PAE at 9.5dB back-off (PAE9.5dB.B0). The measured DC currents of Main and Peaking amplifiers demonstrate the desired asymmetric Doherty operation. The CW frequency sweep shows 19.6-to- 20.6dBm OPidB, 25.0-to-27.7% PAEpidB, and 14.2-to-19.8% PAE9.5dB.B0 between 24 and 29GHz. Next, the FEM was measured using a 100MHz 5G NR FR2 64-QAM OFDM signal. At -25dB EVM, it achieves 12.6dBm average output power (Pavg) and 18.6% average PAE (PAEavg) without using DPD. Tested under the 100MHz 5GNR FR2 256-QAM OFDM, the FEM achieves 10.3 dBm Pavgand 15.4% PAEavg at - 29.1dB EVM.

[0073] The RX mode achieves 15.0dB peak gain with a 3dB BW of 23.4 to 33.9GHz, under 19.6mW DC power. The NF is 3.1 to 4.0dB between 24 and 29GHz. The measured IPidB is -17.3dBm and the IIP3 is -8.3dBm at 28GHz.

[0074] Compared with previous 28GHz FEMs this design achieves the highest PSAT, OPidB, PAEpidB, and PAE9.5dB.B0 in the TX mode, a significant PAEavg enhancement of 1.5x in 5G NR OFDM tests (18.6% vs. 11.9% previously), a competitive NF, and a comparable area to FEMs adopting linear Class-AB PAs. The state-of-the-art performance is attributed to the proposed asymmetric Doherty PA in the TX mode and its co-design with the LNA input matching and T / R switch. Given its high performance and compact area, the present invention is well-suited for size- constrained 5GNR FR2 and SATCOM phased-array applications.

[0075] Although the disclosure has been described with respect to only a limited number of embodiments, those skilled in the art, having benefit of this disclosure will appreciate that various other embodiments may be devised without departing from the scope of the present invention. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims

CLAIMSWhat is claimed is:

1. An N-way Doherty power amplifier, comprising: an amplifier input; an amplifier output;N sub-power amplifiers, wherein N is an integer larger than or equal to two; andN-l transformers, wherein one of the N sub-power amplifiers is a main amplifier and a remaining N-l amplifiers are peaking amplifiers, and wherein an N* amplifier and an N-lthamplifier share a single transformer footprint.

2. An N-way Doherty output network, comprising: an amplifier input; an amplifier output;N sub-power amplifiers, wherein N is an integer larger than or equal to two; andN-l transformers, wherein one of the N sub-power amplifiers is a main amplifier and a remaining N-l amplifiers are peaking amplifiers, and wherein an N* amplifier and an N-lthamplifier share a single transformer footprint; a power divider; and a high-speed adaptive biasing circuit, wherein an input signal is divided by the power divider into N paths, wherein each of the N paths includes a chain of driver stages and an output stage, wherein a main path of the N paths has a fixed biasing, and wherein a remaining N-l paths of the N paths are peaking paths and adopt high-speed adaptive biasing.

3. The N-way Doherty output network according to claim 2, wherein each of the N paths includes a common-source driver and a cascode output stage amplifier.

4. The N-way Doherty output network according to claim 2, wherein the high-speed adaptive biasing circuit comprises: an envelope detector; a notch filter; and a buffer.

5. The N-way Doherty output network according to claim 4, wherein the notch filter is an LC notch filter that comprises inductors and capacitors.

6. The N-way Doherty output network according to claim 5, wherein the LC notch filter is disposed between the envelope detector and the buffer.

7. The N-way Doherty output network according to claim 6, wherein the buffer further comprises a shunt-peaking inductor that increases a modulation bandwidth.

8. The N-way Doherty output network according to claim 2, wherein the N-way Doherty output network is implemented in a complementary metal-oxide-semiconductor process.

9. The N-way Doherty output network according to claim 2, wherein the N-l transformers are implemented based on a synthesis flow, the synthesis flow comprising: inserting N-l ideal transformers into a quarter-wave transmission line-based Doherty architecture; replacing all transmission lines with equivalent C-L-C or L-C-L TI networks; rearranging shunt inductors and capacitors; consolidating series inductors, the shunt inductors, and the ideal transformers into the N-l transformers; and converting the networks to a differential configuration to interface with differential power cells.

10. A front-end module comprising: an N-way Doherty power amplifier comprising: an amplifier input, an amplifier output,N sub-power amplifiers, wherein N is an integer larger than or equal to two, anda number of transformers, wherein the number of transformers is N-l, wherein one of the N sub-power amplifiers is a main amplifier and a remaining N-l amplifiers are peaking amplifiers, and wherein an N111amplifier and an N-lthamplifier share a single transformer footprint, a high-speed adaptive biasing circuit; a low-noise amplifier (LNA); a set of switches; and an inductor, wherein the inductor is shared between the N-way Doherty power amplifier and the low-noise amplifier.

11. The front-end module of claim 10, wherein N=2 and the main amplifier and the peaking amplifier are asymmetric.

12. A method for operating the front-end module of claim 10, the method comprising: switching the set of switches on to enter a transmit mode; switching the set of switches off to enter a receive mode.

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