Irregularly-shaped display panel and display apparatus

Abstract

An irregularly-shaped display panel (100). A display area (AA) of the irregularly-shaped display panel (100) comprises a first sub-boundary (S11), and the first sub-boundary (S11) extends along a non-straight line, or the first sub-boundary (S11) is not perpendicular to a boundary of the display area (AA) adjacent to the first sub-boundary. At a position corresponding to the first sub-boundary (S11) of the display area (AA), extension directions of a plurality of clock signal lines (31) are consistent with the extension direction of the first sub-boundary (S11); and each clock signal line (31) is connected to a shift register (20) by means of a corresponding adapter line (40). In the extension direction of the adapter line (40), the adapter line (40) comprises a first line segment (41) and a second line segment (42); the first line segment (41) and the second line segment (42) are connected to form a corner; the first line segment (41) is connected to a shift register (20), and the second line segment (42) is connected to a clock signal line (31); the orthographic projection of the second line segment (42) on a substrate overlaps the orthographic projection of a first part (311) of the clock signal line (31), which is connected to the second line segment (42), on the substrate; and the extension direction of the second line segment (42) is parallel to the line-width extension direction of the first part (311) of the clock signal line (31).

Description

Special-shaped display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a special-shaped display panel and a display device. Background Art

[0002] At present, liquid crystal display devices (English full name: Liquid Crystal Display, English abbreviation: LCD) have been widely used in electronic products such as mobile phones and computers.

[0003] Summary of the Invention

[0004] On the one hand, a special-shaped display panel is provided. The special-shaped display panel has a display area and a peripheral area surrounding the display area. The display area includes a first sub-boundary, and at least two sections within the first sub-boundary extend in different directions, or the first sub-boundary is not perpendicular to the boundary of the adjacent display area. The special-shaped display panel includes: a substrate, a plurality of pixel units, at least one gate drive circuit and a plurality of clock signal lines. The plurality of pixel units are located on one side of the substrate, and the plurality of pixel units are arranged in multiple rows and columns in the display area, and the pixel units include multiple sub-pixels. At least one gate drive circuit is located in the peripheral area, and the gate drive circuit includes a plurality of cascaded shift registers, and one shift register is connected to a plurality of sub-pixels arranged in a row. At a position corresponding to the first sub-boundary of the display area, the extension direction of the centerline connecting the plurality of shift registers is consistent with the extension direction of the first sub-boundary. The plurality of clock signal lines are located in the peripheral area and on a side of the gate drive circuit away from the display area. At a position corresponding to a first sub-boundary of the display area, the extension direction of the plurality of clock signal lines is consistent with the extension direction of the first sub-boundary. Each of the clock signal lines is connected to the shift register via a corresponding adapter line. Along the extension direction of the adapter line, the adapter line includes a first line segment and a second line segment. The first line segment and the second line segment are connected to form a corner. The first line segment is connected to the shift register, and the second line segment is connected to the clock signal line. The orthographic projection of the second line segment on the substrate overlaps with the orthographic projection of the first portion of the clock signal line connected to it on the substrate. Furthermore, the extension direction of the second line segment is parallel to the line width extension direction of the first portion of the clock signal line.

[0005] In some embodiments, an extension direction of the first edge of the shift register is parallel to or consistent with an outer tangent line of the first sub-boundary, and the first edge is an inner edge of the shift register close to the first sub-boundary.

[0006] In some embodiments, an extension direction of the first edge of the shift register is perpendicular to a row direction.

[0007] In some embodiments, any two adjacent clock signal lines have equal line widths. Among the multiple clock signal lines, the clock signal line farthest from the display area is defined as a first target clock signal line, and the remaining clock signal lines are defined as second target clock signal lines. The orthographic projection of the second line segment of each adapter line on the substrate passes through all of the second target clock signal lines and overlaps with the orthographic projection of the first target clock signal line on the substrate.

[0008] In some embodiments, the peripheral area further includes a sealing frame area, at least one of the clock signal lines is located within the sealing frame area, and each of the clock signal lines includes a plurality of openings. The orthographic projection of the patch line on the substrate and the orthographic projection of the openings of at least two of the clock signal lines on the substrate have an overlapping area equal to that of the orthographic projection.

[0009] In some embodiments, the special-shaped display panel further includes: a gate metal layer and a source-drain metal layer, the gate metal layer is located between the substrate and the source-drain metal layer, a plurality of the clock signal lines are located in the gate metal layer, and a plurality of the transfer lines are located in the source-drain metal layer. The special-shaped display panel further includes a plurality of first connection parts, and the plurality of first connection parts are located on the side of the source-drain metal layer facing away from the gate metal layer. The first connection part includes a first connection sub-part and a second connection sub-part, the orthographic projection of the first connection sub-part of the first connection part on the substrate overlaps with the orthographic projection of the transfer line on the substrate, and the first connection sub-part of the first connection part is connected to the transfer line, the orthographic projection of the second connection sub-part of the first connection part on the substrate overlaps with the clock signal line, and the second connection sub-part of the first connection part is connected to the clock signal line.

[0010] In some embodiments, the special-shaped display panel further includes a transparent electrode layer, the transparent electrode layer being located on a side of the source / drain metal layer facing away from the gate metal layer. The sub-pixel includes a pixel electrode, the pixel electrode being located on the transparent electrode layer; wherein the first connecting portion is located on the same layer as the pixel electrode.

[0011] In some embodiments, the special-shaped display panel further comprises a plurality of data signal lines and a plurality of scan signal lines. The plurality of data signal lines are located in the display area, extending in the column direction and arranged in the row direction, and are located in the source / drain metal layer. The plurality of scan signal lines are located in the display area, extending in the row direction and arranged in the column direction, and are located in the gate metal layer. The gate metal layer is located between the substrate and the source / drain metal layer. The peripheral area is divided into two sub-peripheral areas, and the display area is divided into two sub-display areas, along a first reference line, which is an extension of a line connecting the centers of the plurality of scan signal lines. Along the column direction, the sub-peripheral areas include a first border area and a second border area. The special-shaped display panel further comprises a binding area. Along the column direction, the first border area, the plurality of data signal lines, and the binding area are arranged sequentially. The first border area includes a first region and a second region, the first region overlapping with the gate driver circuit, and the second region not overlapping with the gate driver circuit. Two first short-circuit rings, one of which is located in one of the sub-peripheral areas. The first short-circuit ring includes: a first sub-segment, a second sub-segment, and a third sub-segment. In one short-circuit ring: the second sub-segment is located in the first border area, and the second sub-segment is located between the gate drive circuit and the display area, and the second sub-segment is connected to the end of all the data signal lines in the corresponding sub-display area away from the binding area. The third sub-segment is located in the second area of ​​the first border area. The first sub-segment is located on the side of the clock signal line away from the gate drive circuit, and the first sub-segment extends from the binding area to the second area of ​​the first border area, and is connected to the second sub-segment through the third sub-segment.

[0012] In some embodiments, the special-shaped display panel further comprises a plurality of output signal lines, one shift register is connected to one scan signal line via one output signal line, and the output signal line, the second sub-segment and the data signal line are on the same layer.

[0013] In some embodiments, the special-shaped display panel further includes: a gate metal layer and a source-drain metal layer, the gate metal layer is located between the substrate and the source-drain metal layer, a plurality of the clock signal lines are located in the gate metal layer, and a plurality of the adapter lines are located in the source-drain metal layer. The special-shaped display panel further includes a plurality of scan signal line extensions and a plurality of second connection portions. The plurality of scan signal line extensions are located in the peripheral area, the plurality of scan signal line extensions are in the same layer as the scan signal lines, and the scan signal line extensions are consistent with the extension direction of the scan signal lines. Along the row direction, one scan signal line extension is located on one side of a scan signal line and is connected to the scan signal line. A plurality of second connection portions are located in the peripheral area, and a plurality of second connection portions are located on the side of the source-drain metal layer facing away from the gate metal layer. The second connecting portion includes a third connecting sub-portion and a fourth connecting sub-portion, the orthographic projection of the third connecting sub-portion of the second connecting portion on the substrate overlaps with the orthographic projection of the output signal line on the substrate, and the third connecting sub-portion of the second connecting portion is connected to the output signal line, the orthographic projection of the fourth connecting sub-portion of the second connecting portion on the substrate overlaps with the orthographic projection of the scan signal line extension portion on the substrate, and the fourth connecting sub-portion of the second connecting portion is connected to the scan signal line extension portion.

[0014] In some embodiments, the special-shaped display panel further includes a transparent electrode layer, the transparent electrode layer being located on a side of the source / drain metal layer facing away from the gate metal layer. The sub-pixel includes a pixel electrode, the pixel electrode being located on the transparent electrode layer. The second connecting portion is located on the same layer as the pixel electrode.

[0015] In some embodiments, the special-shaped display panel further includes a plurality of switch units and two second short-circuit rings. The plurality of switch units are located between the second sub-segment and the display area, the first end of the switch unit is connected to the first short-circuit ring, the second end of the switch unit is connected to the data signal line, and the control end of the switch unit is connected to the second short-circuit ring. The second short-circuit ring includes: a fourth sub-segment, a fifth sub-segment, and a sixth sub-segment. The fifth sub-segment is located in the first border area, and the fifth sub-segment is located between the gate drive circuit and the second sub-segment. The fifth sub-segment is connected to the control ends of all the switch units in the same sub-peripheral area. The sixth sub-segment is located in the second area of ​​the first border area. The fourth sub-segment is located between the first sub-segment and the clock signal line, and the fourth sub-segment extends from the binding area to the second area of ​​the first border area and is connected to the fifth sub-segment via the sixth sub-segment.

[0016] In some embodiments, the second shorting ring and the scan signal line are in the same layer, and the second connecting portion is projected onto the substrate between the orthographic projections of the first shorting ring and the second shorting ring onto the substrate.

[0017] In some embodiments, the pixel unit includes three sub-pixels. Among the multiple rows of pixel units corresponding to the first sub-border of the display area, two adjacent rows of pixel units are included in the direction from the first border area to the second border area. The two adjacent rows of pixel units are respectively the nth pixel unit row and the n+1th pixel unit row. The number of pixel units in the nth pixel unit row is less than the number of pixel units in the n+1th pixel unit row. n is a positive integer. The n+1th pixel unit row includes at least one n+1th target pixel unit. Along the column direction, the n+1th target pixel unit does not overlap with the nth pixel unit row, and the n+1th target pixel unit forms an nth step region with the nth pixel unit row. A switch unit connected to the same data signal line as a sub-pixel in the n+1th target pixel unit is defined as the n+1th target switch unit. Multiple n+1th target switch units are located in the nth step region and are in the same row as the nth pixel unit row. Multiple n+1th target switch units are arranged along the row direction.

[0018] In some embodiments, the n+1th target switch unit is away from a side edge of the n+1th pixel unit row and overlaps with the nth pixel unit row in the row direction, and the n+1th target switch unit is away from a side edge of the nth pixel unit row and overlaps with the n+1th pixel unit row in the column direction.

[0019] In some embodiments, the pixel unit includes three sub-pixels. In the multiple rows of pixel units corresponding to the first sub-border of the display area, three rows of pixel units are arranged sequentially along the direction from the first border area to the second border area, and the three rows of pixel units are respectively: the nth pixel unit row, the n+1th pixel unit row, and the n+2th pixel unit row. The number of pixel units in the nth pixel unit row, the n+1th pixel unit row, and the n+2th pixel unit row gradually increases. The n+2th pixel unit row includes at least one n+2th target pixel unit, and along the column direction, the n+2th target pixel unit does not overlap with the n+1th pixel unit row, and the n+2th target pixel unit and the n+1th pixel unit row form an n+1th step region. The n+1th pixel unit row includes at least one n+1th target pixel unit, and along the column direction, the n+1th target pixel unit does not overlap with the nth pixel unit row, and the n+1th target pixel unit and the nth pixel unit row form an nth step region. A switch unit connected to the same data signal line as a sub-pixel within the n+2th target pixel unit is defined as an n+2th target switch unit, and the sub-pixels within the n+2th target switch unit are arranged in two rows and multiple columns. The n+2th target switch units in a first row are located within the n+1th step region, in the same row as the n+1th pixel unit row, and the n+2th target switch units in a second row are located in the same row as the nth pixel unit row and on a side of the nth step region away from the nth pixel unit row.

[0020] In some embodiments, a switch unit connected to the same data signal line as a sub-pixel in the n+1th target pixel unit is defined as an n+1th target switch unit, and the sub-pixels in the n+1th target switch unit are arranged in two rows and multiple columns. The n+1th target switch unit in the first row is located in the nth step region, in the same row as the n+2th target switch unit and the nth pixel unit in the second row.

[0021] In some embodiments, the ratio of the number of the (n+2)th target switch units in the first row to the number of the (n+2)th target switch units in the second row is 1:2.

[0022] In some embodiments, the special-shaped display panel further includes a third connecting portion and a fourth connecting portion. The third connecting portion is on the same layer as the second subsegment of the first shorting ring, one end of the third connecting portion is connected to the second subsegment of the first shorting ring in one sub-display area, and the other end of the third connecting portion is connected to the second subsegment of the first shorting ring in another sub-display area. The fourth connecting portion is on the same layer as the fifth subsegment of the second shorting ring, one end of the fourth connecting portion is connected to the fifth subsegment of the second shorting ring in one sub-display area, and the other end of the fourth connecting portion is connected to the fifth subsegment of the second shorting ring in another sub-display area.

[0023] In some embodiments, the third subsegment of the first shorting ring includes a first portion and a second portion. The first portion of the third subsegment is located on the same layer as the first subsegment of the first shorting ring and is connected to the first subsegment of the first shorting ring. The second portion of the third subsegment is located on the same layer as the second subsegment of the first shorting ring and is connected to the second subsegment of the first shorting ring. An orthographic projection of the second portion of the third subsegment on the substrate overlaps with an orthographic projection of the fourth connecting portion on the substrate.

[0024] In another aspect, a display device is provided, comprising: a cover plate and the special-shaped display panel according to any one of the above embodiments, wherein the cover plate is located on a light-emitting side of the special-shaped display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0026] FIG1 is a cross-sectional view of a display device according to some embodiments;

[0027] FIG2 is a cross-sectional view of a display panel according to some embodiments;

[0028] FIG3 is a structural diagram of a display panel according to some embodiments;

[0029] FIG4 is a structural diagram of a display panel according to some other embodiments;

[0030] FIG5 is a structural diagram of a display panel according to yet other embodiments;

[0031] FIG6 is a partially enlarged view of a target subspace of a special-shaped display panel according to some embodiments;

[0032] FIG7 is a partial enlarged view of C1 in FIG6 ;

[0033] FIG8 is a structural diagram of a display panel according to yet other embodiments;

[0034] FIG9 is a cross-sectional view of a special-shaped display panel according to some embodiments;

[0035] FIG10 is a structural diagram of a special-shaped display panel according to some other embodiments;

[0036] FIG11 is a partial enlarged view of C2 in FIG10 ;

[0037] FIG12 is a layout diagram of C2 in FIG10 ;

[0038] FIG13 is an equivalent circuit diagram of FIG12;

[0039] FIG14 is a structural diagram of a special-shaped display panel according to yet other embodiments;

[0040] FIG15 is a partial enlarged view of C3 in FIG14;

[0041] FIG16 is a structural diagram of a special-shaped display panel according to yet other embodiments;

[0042] FIG17 is another layout diagram of C2 in FIG10;

[0043] FIG18 is an equivalent circuit diagram of FIG17 ;

[0044] FIG19 is another layout diagram of C2 in FIG10 . DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0050] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0051] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0052] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0055] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0056] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0057] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0058] FIG1 is a cross-sectional view of a display device according to some embodiments. As shown in FIG1 , some embodiments of the present disclosure provide a display device 200 , which includes a cover plate 210 and a display panel 100 . The cover plate 210 is located on the light-emitting side of the display panel 100 .

[0059] The cover plate 210 may be used for the display panel 100 to prevent the display panel 100 from being scratched, thereby increasing the service life of the display device 200 .

[0060] In some examples, the material of the cover plate 210 includes at least one of inorganic glass, thermoplastic polyester, transparent polyimide, or organic glass. The inorganic glass may include non-bendable ordinary glass and bendable ultra-thin glass (English full name: Ultra Thin Glass, abbreviated: UTG).

[0061] The present disclosure provides a display device 200. The display device may be a liquid crystal display (LCD); the display device may also be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0062] When the display device 200 is a liquid crystal display device, in some embodiments, the display panel 100 in the display device 200 is a liquid crystal display panel. The display device 200 may further include a backlight assembly, which is located on a side of the liquid crystal display panel 100 facing away from the cover plate 210 and is used to provide light for the liquid crystal display panel 100.

[0063] When the display device 200 is an electroluminescent display device or a photoluminescent display device, in some embodiments, the display panel 100 in the display device 200 may be an electroluminescent display panel or a photoluminescent display panel.

[0064] The electroluminescent display panel 100 or the photoluminescent display panel 100 includes a display substrate and an encapsulation layer for encapsulating the display substrate. Here, the encapsulation layer can be an encapsulation film or an encapsulation substrate.

[0065] Exemplarily, the display device 200 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0066] With the development of display panel technology, display panels with diverse shapes are becoming more and more common. Based on this, the display panel 100 in the display device 200 can be a special-shaped display panel 100.

[0067] FIG. 2 is a cross-sectional view of a display panel according to some embodiments.

[0068] In some embodiments, as shown in FIG2 , the special-shaped display panel 100 is a special-shaped liquid crystal display panel. The main structure of the special-shaped liquid crystal display panel 100 includes an array substrate 110, a cell substrate 120, and a liquid crystal layer 130 disposed between the array substrate 110 and the cell substrate 120. In some examples, the cell substrate 120 may be a color filter substrate (CF).

[0069] As can be understood, light can be emitted through the backlight assembly and illuminate the liquid crystal layer 130. By adjusting the arrangement of the liquid crystal molecules in the liquid crystal layer 130, the intensity of light passing through the liquid crystal layer 130 can be adjusted, thereby adjusting the intensity of light irradiating the cell substrate 120. Since the cell substrate 120 is a color filter substrate, by adjusting the intensity of light irradiating the different color photoresist units, the special-shaped display panel 100 can display color images.

[0070] In some examples, as shown in FIG2 , the peripheral area SA further includes a sealing frame area F, which is disposed around the display area AA. The irregular display panel 100 may further include a sealing adhesive F1, which is located within the sealing frame area F and between the array substrate 110 and the alignment substrate 120, surrounding the liquid crystal layer 130 to prevent leakage of liquid crystal in the liquid crystal layer 130 and maintain the peripheral thickness of the irregular display panel 100.

[0071] FIG. 3 is a structural diagram of a display panel according to some embodiments, and FIG. 4 is a structural diagram of a display panel according to other embodiments.

[0072] As shown in FIG3 and FIG4, some embodiments of the present disclosure provide a special-shaped display panel 100, which includes a display area (full name: Active Area, referred to as AA area; also called effective display area) AA and a peripheral area SA surrounding the display area AA.

[0073] In some examples, as shown in FIG3 , the first boundary S1 of the display area AA includes a first sub-boundary S11 and a second sub-boundary S12. The first sub-boundary S11 and the second sub-boundary S12 are adjacent and connected, and the first sub-boundary S11 and the second sub-boundary S12 are not perpendicular. In other words, the display area AA of the irregular display panel 100 includes at least two adjacent non-perpendicular boundaries. The second sub-boundary S12 is located away from the first sub-boundary S11 and may be perpendicular or non-perpendicular to the other adjacent boundary.

[0074] In other examples, as shown in FIG4 , the first boundary S1 of the display area AA includes a first sub-boundary S11, and at least two segments within the first sub-boundary S11 extend in different directions. That is, the first sub-boundary S11 does not extend in a straight line. For example, the first sub-boundary S11 may be an arc, a broken line, a wavy line, or the like.

[0075] In some other examples, the first boundary S1 of the display area AA may be a first sub-boundary S11. In this case, the shape of the first boundary S1 of the display area AA may be circular, elliptical, or the like.

[0076] Any of the above-mentioned special-shaped display panels 100 may include a substrate 10 and a plurality of pixel units P located on the substrate 10 .

[0077] In some examples, the substrate 10 may be a flexible substrate. For example, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0078] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a polymethyl methacrylate (PMMA) substrate.

[0079] Multiple pixel cells P are located in the display area AA, and the pixel cells P are arranged in multiple rows and columns. A row of pixel cells P is defined as a pixel cell row, and a column of pixel cells P is defined as a pixel cell column. Because the boundary of the display area AA of the special-shaped display panel 100 has a first sub-boundary S11, the shape of the display area AA is not a regular shape. Therefore, the number of pixel cells P in at least two pixel cell rows arranged in the display area AA is different, and the number of pixel cells P in at least two pixel cell columns is different.

[0080] It should be noted that the first boundary S1 of the display area AA may coincide with the second boundary S2 of the peripheral area SA on the side closer to the display area AA. That is, the first boundary S1 of the display area AA or the second boundary S2 of the peripheral area SA can be understood as the boundary between the display area AA and the peripheral area SA. The third boundary S3 of the peripheral area SA on the side farther from the display area AA may be disposed opposite the second boundary S2 of the peripheral area SA or the first boundary S1 of the display area AA. That is, the trajectory of the third boundary S3 of the peripheral area SA may be consistent with the trajectory of the second boundary S2 of the peripheral area SA or the trajectory of the first boundary of the display area AA.

[0081] Among them, the third boundary S3 of the peripheral area SA includes a third sub-boundary S31, and the third sub-boundary S31 of the peripheral area SA is arranged opposite to the first sub-boundary S11 of the display area AA. The space sandwiched between the third sub-boundary S31 of the peripheral area SA and the first sub-boundary S11 of the display area AA is the target subspace SA0 of the peripheral area.

[0082] In some examples, as shown in FIG4 , a pixel unit P includes multiple sub-pixels P0. Through the light emitted by the multiple sub-pixels P0, the special-shaped display panel 100 can display a predetermined image in the display area AA. Specifically, the multiple sub-pixels P0 can include multiple sub-pixels with different luminous colors. Exemplarily, the multiple sub-pixels P0 include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. The first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 respectively emit three primary colors of light. For example, the first sub-pixel P1 can emit red light, the second sub-pixel P2 can emit green light, and the third sub-pixel P3 can emit blue light.

[0083] In some other examples, the special-shaped display panel 100 may further include white sub-pixels.

[0084] The plurality of sub-pixels P0 in all pixel units P are arranged in multiple rows and columns in the display area AA, wherein a row of sub-pixels P0 is defined as a sub-pixel row, and a column of sub-pixels P0 is defined as a sub-pixel column.

[0085] Fig. 5 is a structural diagram of a display panel according to some further embodiments, wherein Fig. 5 takes the non-linear extension of the first sub-boundary S11 as an example.

[0086] In some embodiments, as shown in conjunction with FIG4 and FIG5 , the special-shaped display panel 100 may further include multiple scan signal lines G1 and multiple data signal lines Data. The multiple data signal lines Data and the multiple scan signal lines G1 may be intersected to define multiple sub-pixels P0. One data signal line Data may be connected to one sub-pixel column, and one scan signal line G1 may be connected to one sub-pixel row.

[0087] The special-shaped display panel 100 may further include at least one gate driver circuit G, which is located in the peripheral area SA. The gate driver circuit G is configured to output scan signals to the pixel driver circuits in the plurality of sub-pixels P. Since the gate driver circuit G is provided on the special-shaped display panel 100, the gate driver circuit G may also be referred to as a GOA (Gate Driver on Array).

[0088] A gate drive circuit G includes a plurality of cascaded shift registers 20. Each shift register 20 is connected to a sub-pixel row (a plurality of sub-pixels P0 arranged in a row) so that the shift register 20 outputs a scan signal to each sub-pixel row. Specifically, each shift register 20 can be connected to a scan signal line G1 to connect to each sub-pixel row through the scan signal line G1.

[0089] In some examples, the gate drive circuit G includes multiple transistors. In some embodiments, the structure of the gate drive circuit G in the present disclosure includes multiple structures, which can be selected according to actual needs. For example, the structure of the gate drive circuit G may include "3T1C", "8T2C" or "12T1C", etc. Here, "T" represents a thin film transistor, and the number before "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number before "C" represents the number of storage capacitors C.

[0090] Along the column direction Y (the direction in which the data signal lines Data extend), the peripheral area SA includes a first border area SA1 (upper border) and a second border area SA2 (lower border). Along the row direction X (the direction in which the scan signal lines G1 extend), the peripheral area SA includes a third border area SA3 (left border) and a fourth border area SA4 (right border).

[0091] In some examples, the special-shaped display panel 100 includes a gate driving circuit G, and the gate driving circuit G is located in the third frame area SA3 or the fourth frame area SA4 of the peripheral area SA.

[0092] In other examples, the special-shaped display panel 100 includes two gate driving circuits G, one gate driving circuit G is located in the third border area SA3 of the peripheral area SA, and the other gate driving circuit G is located in the second border area SA2 of the peripheral area SA.

[0093] The special-shaped display panel 100 also includes a plurality of input signal lines 30 for providing drive signals to the gate drive circuit G. The input signal lines 30 may include a plurality of clock signal lines 31, and the input signal lines 30 may also include other signal lines. The types of other signal lines will be described in detail below.

[0094] The plurality of input signal lines 30 may be located in the peripheral area SA, and the plurality of input signal lines 30 may be located on a side of the gate drive circuit G away from the display area AA. Specifically, the plurality of clock signal lines 31 may be located on a side of the other signal lines away from the display area AA. Specifically, the plurality of input signal lines 30 and the gate drive circuit G to which they are connected are located within the same border area, the extension direction of the plurality of input signal lines 30 is consistent with the extension direction of the border area, and the plurality of input signal lines 30 are arranged in a direction from the border area to the display area AA.

[0095] That is, multiple clock signal lines 31 and the gate drive circuit G connected to them are located in the same border area, the extension direction of the multiple clock signal lines 31 is consistent with the extension direction of the border area, and the multiple clock signal lines 31 are arranged along the direction of the border area pointing to the display area AA.

[0096] The special-shaped display panel 100 may further include a plurality of adapter lines 40 , where one adapter line 40 is used to connect one clock signal line 31 to its corresponding one shift register 20 .

[0097] In some feasible embodiments, the adapter line 40 extends along the row direction X to connect the clock signal line 31 to its corresponding shift register 20. However, due to the existence of the first boundary S1 of the display area AA, some border areas in the peripheral area SA may overlap. For example, the first boundary S1 of the display area AA1 is the boundary of the first border area SA1 of the peripheral area SA close to the side of the display area AA. That is, the first border area SA1 includes the target subspace SA0. This will cause the first border area SA1 to extend into the third border area SA3 and the fourth border area SA4. Therefore, the first border area SA1 will have an overlapping area with the third border area SA3, and / or the first border area SA1 will have an overlapping area with the fourth border area SA4. As a result, multiple shift registers 20 located in the third border area SA3 or the fourth border area SA4 will be located in the target subspace SA0. Therefore, multiple clock signal lines 31 also need to extend into the target subspace SA0 to facilitate the connection of the clock signal lines 31 to the shift registers 20.

[0098] Among them, at the position corresponding to the first sub-boundary S11 of the display area AA (target sub-space SA0), the extension direction of the centerline connection U of multiple shift registers 20 is consistent with the extension direction of the first sub-boundary S11, and the extension direction of multiple clock signal lines 31 is consistent with the extension direction of the first sub-boundary S11, so that the clock signal line 31 is connected to the shift register 20, and there is no need to design a fan-shaped wiring for the adapter line 40, which is beneficial to reducing the occupation of the adapter line 40 in the peripheral area SA space and is beneficial to achieving a narrow frame.

[0099] However, the above arrangement will cause the orthographic projection of the adapter line 40 extending along the row direction X on the substrate 10 to intersect with the orthographic projection of the clock signal line 31 to which it is connected on the substrate 10, and the angle formed by the intersection is an obtuse angle. On the one hand, since the area of ​​the overlapping region formed by the orthographic projection of the adapter line 40 on the substrate 10 and the orthographic projection of the clock signal line 31 to which it is connected on the substrate 10 is large, an overlapping capacitance will be formed between the two, increasing the load of the clock signal line 31. In addition, when the first sub-boundary S11 extends non-linearly, the orthographic projection of at least two adapter lines 40 on the substrate 10 and the orthographic projection of the clock signal line 31 to which it is connected on the substrate 10 will be different in size, which will cause the area of ​​the overlapping region formed between different adapter lines 40 and the clock signal line 31 to which they are connected to be different, thereby causing the overlapping capacitance formed between the two to be different, resulting in different loads on at least two clock signal lines 31, affecting the display effect of the special-shaped display panel 100.

[0100] It should be noted that the orthographic projection of a shift register 20 on the substrate 10 can be a rectangle. That is, the orthographic projections of all transistors in a register 20 on the substrate 10 can be combined into a rectangle. The centerline connection U of multiple shift registers 20 can be understood as a line connecting the center points of multiple rectangles corresponding to the multiple shift registers 20. The extension direction of the centerline connection of the shift registers 20 is set to be consistent with the extension direction of the first sub-boundary S11. That is, at the position corresponding to the first sub-boundary S11 of the display area AA (target subspace SA0), multiple shift registers 20 are arranged along the extension direction of the first sub-boundary S11.

[0101] FIG. 6 is a partial enlarged view of a target subspace of a special-shaped display panel according to some embodiments, and FIG. 7 is a partial enlarged view of C1 in FIG. 6 .

[0102] Based on this, in some embodiments, as shown in conjunction with Figures 5 to 7 , along the extension direction of the patch cable 40, the patch cable 40 includes a first line segment 41 and a second line segment 42. The first line segment 41 and the second line segment 42 are connected to form a corner J. The first line segment 41 is connected to the shift register 20, and the second line segment 42 is connected to the clock signal line 31. The orthographic projection of the second line segment 42 on the substrate 10 overlaps with the orthographic projection of the first portion 311 of the clock signal line 31 connected to it. The extension direction of the second line segment 42 is parallel to the line width extension direction of the first portion 311 of the clock signal line 31.

[0103] That is to say, each adapter line 40 can be divided into two parts, and the extension direction of the second line segment 42 connecting the adapter line 40 and the clock signal line 31 can be adjusted so that the positive projection of the second line segment 42 of each adapter line 40 on the substrate 10 is approximately perpendicular to the first part 311 of the clock signal line 31 connected to it.

[0104] In other words, the overlapping area formed by the orthographic projection of the second line segment 42 of each adapter line 40 on the substrate 10 and the orthographic projection of the first portion 311 of the clock signal line 31 connected thereto on the substrate 10 can be approximately rectangular, and the area of ​​this rectangle is approximately the product of the line width of the second line segment 42 of the adapter line 40 and the line width of the clock signal line 31. Therefore, not only can the area of ​​the overlapping area formed by the orthographic projection of the adapter line 40 on the substrate 10 and the orthographic projection of the clock signal line 31 connected thereto on the substrate 10 be made smaller, the overlapping capacitance formed between the two can be made smaller, thereby reducing the load on the clock signal line 31; the areas of the overlapping areas formed between different adapter lines 40 and the clock signal lines 31 connected thereto can also be made approximately equal, so that the load on each adapter line 40 and the load on each clock signal line 31 are approximately the same, which is beneficial to improving the display effect of the special-shaped display panel 100.

[0105] In some embodiments, the plurality of input signal lines 30 may include other lines in addition to the clock signal line 31, such as a first power signal line VDD1, a second power signal line VDD2, a start trigger signal line STV, a first gate control signal line Vgl, and a second gate control signal line Lvgl. The voltage of the signal transmitted by the second gate control signal line Lvgl is less than or equal to the voltage of the signal transmitted by the first gate control signal line Vgl.

[0106] Among the plurality of input signal lines 30 , except for the clock signal line 31 , the other lines may be located between the clock signal line 31 and the gate drive circuit G. That is, the first power signal line VDD1 (not shown in the figure), the second power signal line VDD2 , the start trigger signal line STV (not shown in the figure), the first gate control signal line Vgl (not shown in the figure), and the second gate control signal line Lvgl (not shown in the figure) are all located between the clock signal line 31 and the gate drive circuit G.

[0107] Specifically, along the direction of the clock signal line 31 pointing to the gate driving circuit G, the first power signal line VDD1, the second power signal line VDD2, the second gate control signal line Lvgl, the start trigger signal line STV and the first gate control signal line Vgl are arranged in sequence.

[0108] In addition, the trends of the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl are consistent with the trend of the clock signal line 31, so as to improve the regularity of the routing of the peripheral area SA and make full use of the space of the peripheral area SA.

[0109] When the trends of the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl are consistent with the trends of the clock signal line 31, the shape of the overlapping area formed by the orthographic projection of the second line segment 42 of each adapter line 40 on the substrate 10 and the orthographic projection of the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl on the substrate 10 through which it passes can be approximately rectangular. In this way, the parasitic capacitance between the adapter line 40 and any of the first power signal line VDD1, the second power signal line VDD2, the start trigger signal line STV, the first gate control signal line Vgl, and the second gate control signal line Lvgl can be reduced, which is conducive to reducing the load.

[0110] In some embodiments, as shown in FIG. 5 to FIG. 7 , along the row direction X, any shift register 20 in the gate driving circuit G at least partially overlaps with a sub-pixel row connected thereto.

[0111] Based on this, the length of the gate drive circuit G in the column direction Y is set to be approximately equal to the length of the sub-pixel column with the largest number of sub-pixels P0. Furthermore, when connecting the shift register to the scan signal line G1, there is no need to design the wiring connecting the two in a fan-out pattern, which helps reduce the space occupied by such wiring in the peripheral area SA and facilitates the realization of a narrow frame.

[0112] In the row direction X, any shift register 20 in the gate driving circuit G at least partially overlaps with a sub-pixel row connected thereto, which may include the following two configurations.

[0113] The first type: along the row direction X, the shift register 20 partially overlaps with the sub-pixel row it is connected to.

[0114] The second type: the shift register 20 completely overlaps the sub-pixel row connected to it along the row direction X. That is, in this case, along the Y direction, the width of the shift register 20 is substantially equal to the width of a sub-pixel row.

[0115] Such an arrangement is equivalent to arranging a plurality of shift registers 20 corresponding to the sub-pixel rows connected thereto, so that the shift registers 20 are connected to the scanning signal lines G1 connected to the sub-pixel rows, thereby realizing a narrow frame.

[0116] In some examples, as shown in Figures 5 to 7 , the first line segment 41 of each patch cord 40 can be substantially perpendicular to the direction in which the first edge 21 of the shift register 20 extends. The first edge 21 is the inner edge of the shift register 20 near the first sub-boundary. This facilitates connection between the first line segment 41 of each patch cord 40 and the transistor within the shift register 20 to which it is connected, thereby alleviating the problem of winding of the first line segment 41.

[0117] In the same patch cord 40 , the relative positional relationship between the first line segment 41 and the second line segment 42 may include the following two situations.

[0118] The first type: as shown in FIG7 , the extension direction of the first line segment 41 intersects with the extension direction of the second line segment 42 , and the angle (corner J) formed by the intersection of the two can be an obtuse angle.

[0119] The second type: in the same adapter line 40 , the first line segment 41 and the second line segment 42 can be connected by an arc.

[0120] Regardless of any of the above-mentioned relative positional relationships between the first line segment 41 and the second line segment 42, the structure of the adapter line 40 can be changed to ensure that the extension direction of the second line segment 42 of the adapter line 40 is parallel to the line width extension direction of the first part 311 of the clock signal line 31, and the extension direction of the first line segment 41 of the adapter line 40 is approximately perpendicular to the first edge 21 of the shift register 20.

[0121] Based on this, the overlapping capacitance formed between the adapter line 40 and the clock signal line 31 can be reduced, reducing the load on both while facilitating the connection between the first line segment 41 of the adapter line 40 and the transistor in the shift register 20 to which it is to be connected.

[0122] In addition, except for the different extension directions, the first line segment 41 and the second line segment 42 in the adapter line 40 have the same data parameters. For example, the line width of the first line segment 41 and the second line segment 42 are the same, and the line thickness of the first line segment 41 and the second line segment 42 are the same. This can reduce the difference between the two and reduce the difference at different positions on the same adapter line 40, which is conducive to improving the display effect of the special-shaped display panel 100.

[0123] It should be noted that the orthographic projection of a shift register 20 on the substrate 10 can be a rectangle. That is, the orthographic projections of all transistors in a shift register 20 on the substrate 10 can be combined to form a rectangle. The first edge 21 of the shift register 20 can be understood as the side of the rectangle corresponding to the shift register 20 that is close to the display area AA. Alternatively, the first edge 21 of the shift register 20 can be understood as the connecting line of the multiple transistors in the shift register 20 that are adjacent to the display area AA that are close to the display area AA. The "first edge 21 of the shift register 20" mentioned herein is the same as explained above.

[0124] FIG8 is a structural diagram of a display panel according to some further embodiments, wherein FIG8 takes the non-linear extension of the first sub-boundary S11 as an example.

[0125] In some embodiments, as shown in Figures 4 and 8, any two adjacent shift registers 20 are rotated relative to each other, and the extension direction of the first edge 21 of the shift register 20 is parallel to the tangent line of the first sub-boundary S11 or consistent with the extension direction of the first sub-boundary S11, and the first edge 21 is the inner edge of the shift register 20 close to the first sub-boundary.

[0126] This arrangement is equivalent to adjusting the position of each shift register 20 within the target subspace SA0 so that the shift register 20 is positioned adjacent to the first edge 21 of the display area AA and opposite its corresponding first sub-boundary S11. In other words, the width of the gap between the first edge 21 of the shift register 20 and the first sub-boundary S11 of the display area AA is substantially equal at any two locations within the gap formed between the first edge 21 of the shift register 20 and the first sub-boundary S11 of the display area AA.

[0127] Based on this, the multiple shift registers 20 set in the target subspace SA0 are rotated and arranged around the first sub-boundary S11 of the display area AA, so as to reduce the occupation of the gate driving circuit G in the peripheral area SA, which is conducive to achieving a narrow frame.

[0128] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the difference in gap width at any two positions in the gap formed between the first edge 21 of the shift register 20 and the first sub-boundary S11 of the display area AA fluctuates within 10% of any gap, it can also be considered that the gap width at any two positions in the gap formed between the first edge 21 of the shift register 20 and the first sub-boundary S11 of the display area AA are equal.

[0129] In some embodiments, as shown in FIG. 5 to FIG. 7 , any two adjacent shift registers 20 are arranged in parallel, and the extending direction of the first edge 21 of the shift register 20 is perpendicular to the row direction X.

[0130] This arrangement is equivalent to adjusting the position of each shift register 20 within the target subspace SA0, with the first edge 21 of each shift register 20 extending perpendicular to the row direction X, so that each shift register 20 is arranged approximately parallel. In other words, the multiple shift registers 20 within the target subspace SA0 are arranged in a staircase-like pattern. This ensures that the multiple transistors within the shift register 20 are arranged in a consistent direction, which helps improve the uniformity of the transistor channel etching process.

[0131] It should be noted that the extension direction of the first edge 21 of the shift register 20 is approximately perpendicular to the row direction X. In this case, the angle between the extension direction of the first edge 21 of the shift register 20 and the row direction X is approximately 90°. For example, the angle between the extension direction of the first edge 21 of the shift register 20 and the row direction X can be 85°, 90°, or 95°.

[0132] In some embodiments, as shown in Figures 5 to 7 , among the multiple clock signal lines 31, the clock signal line 31 farthest from the display area AA is defined as a first target clock signal line 31A, and the remaining clock signal lines 31 are second target clock signal lines 31B. The orthographic projection of the second line segment 42 of each patch cable 40 on the substrate 10 passes through all of the second target clock signal lines 31B and overlaps with the orthographic projection of the first target clock signal line 31A on the substrate 10.

[0133] This configuration allows the orthographic projection of any patch line 40 on the substrate 10 to overlap with the orthographic projections of all clock signal lines 31 (one first target clock signal line 31A and all second target clock signal lines 31B) on the substrate 10. Consequently, the orthographic projection of each patch line 40 on the substrate 10 can overlap with the orthographic projections of the same number of clock signal lines 31 on the substrate 10. Furthermore, the overlapping capacitance formed between each patch line 40 and all clock signal lines 31 is approximately equal, which indirectly also allows the overlapping capacitance formed between each clock signal line 31 and all patch lines 40 to be approximately equal.

[0134] Based on this, the load of each adapter line 40 and the load of each clock signal line 31 can be made substantially the same, which is beneficial to improving the display effect of the special-shaped display panel 100 .

[0135] In some examples, the special-shaped display panel 100 may include eight clock signal lines 31. In the direction from the display area AA toward the peripheral area SA, the eight clock signal lines 31 are respectively a first clock signal line 311, a second clock signal line 312, a third clock signal line 313, a fourth clock signal line 314, a fifth clock signal line 315, a sixth clock signal line 316, a seventh clock signal line 317, and an eighth clock signal line 318. In this case, the eighth clock signal line 318 is the first target clock signal line 31A, and the first clock signal line 311, the second clock signal line 312, the third clock signal line 313, the fourth clock signal line 314, the fifth clock signal line 315, the sixth clock signal line 316, and the seventh clock signal line 317 are all second target clock signal lines 31B.

[0136] The number of clock signal lines 31 can be set according to the needs of actual application scenarios. For example, the number of clock signal lines 31 can be 4, 6, or 8, etc. The embodiments of the present disclosure are not limited thereto.

[0137] The positive projection of the adapter line 40 connected to the first clock signal line 311 (second target clock signal line 31B) closest to the display area AA on the substrate 10 must pass through the remaining second target clock signal lines 31B (second clock signal line 312, third clock signal line 313, fourth clock signal line 314, fifth clock signal line 315, sixth clock signal line 316 and seventh clock signal line 317), and overlap with the positive projection of the eighth clock signal line 318 (first target clock signal line 31A) on the substrate 10.

[0138] That is, the orthographic projection of the patch cord 40 on the substrate 10 overlaps with the orthographic projections of the first clock signal line 311, the second clock signal line 312, the third clock signal line 313, the fourth clock signal line 314, the fifth clock signal line 315, the sixth clock signal line 316, the seventh clock signal line 317, and the eighth clock signal line 318 on the substrate 10. The same applies to the other patch cords 40. Furthermore, the overlapping capacitance formed between each patch cord 40 and all the clock signal lines 31 can be made substantially equal, which indirectly also makes the overlapping capacitance formed between each clock signal line 31 and all the patch cords 40 substantially equal.

[0139] Based on this, the load of each adapter line 40 and the load of each clock signal line 31 can be made substantially the same, which is beneficial to improving the display effect of the special-shaped display panel 100 .

[0140] Furthermore, the line widths of any two adjacent clock signal lines 31 can be set to be approximately equal, and the widths of any two positions within the gap formed between any two adjacent clock signal lines 31 can be approximately equal. In other words, multiple clock signal lines 31 can be arranged with equal widths and equal spacing. This can reduce the differences between the clock signal lines 31, thereby improving the display quality of the special-shaped display panel 100.

[0141] Because the orthographic projection of the second line segment 42 of each patch line 40 on the substrate 10 is substantially perpendicular to the first portion 311 of the clock signal line 31 connected thereto, when multiple clock signal lines 31 are laid out as described above, the orthographic projection of the second line segment 42 of any patch line 40 on the substrate 10 can be substantially perpendicular to the first portions 311 of all the clock signal lines 31 (one first target clock signal line 31A and all second target clock signal lines 31B) on the substrate 10.

[0142] Based on this, the shape of the overlapping area formed by the orthographic projection of the second line segment 42 of each adapter line 40 on the substrate 10 and the orthographic projection of the first portion 311 of all the clock signal lines 31 on the substrate 10 can be a rectangle, and the area of ​​this rectangle is approximately the product of the line width of the second line segment 42 of the adapter line 40 and the line width of the clock signal line 31. Therefore, not only can the area of ​​the overlapping area formed by the orthographic projection of the adapter line 40 on the substrate 10 and the orthographic projection of all the clock signal lines 31 on the substrate 10 be made smaller, the overlapping capacitance formed between the two can be made smaller, thereby reducing the load of all the clock signal lines 31; the area of ​​the overlapping area formed between different adapter lines 40 and all the clock signal lines 31 can also be made roughly equal, so that the load of each adapter line 40 and the load of each clock signal line 31 are roughly the same, which is beneficial to improving the display effect of the special-shaped display panel 100.

[0143] In some embodiments, as shown in FIG7 , the orthographic projection of the edge of the second line segment 42 of each transfer line 40 away from the first line segment 41 on the substrate 10 roughly coincides with the orthographic projection of the edge of the first target clock signal line 31A away from the second target clock signal line 31B on the substrate 10 .

[0144] With such an arrangement, any adapter line 40 can be extended to roughly coincide with the side of the first target clock signal line 31A away from the second target clock signal line 31B, and thus the orthographic projection of each adapter line 40 on the substrate 10 can form an overlapping area with the orthographic projection of the first target clock signal line 31A on the substrate 10 in the shape of a rectangle, and the area of ​​this rectangle is approximately the product of the line width of the second line segment 42 of the adapter line 40 and the line width of the first target clock signal line 31A.

[0145] Based on this, the orthographic projection of each patch cord 40 on the substrate 10 can be made to extend exactly to the position of the orthographic projection of the side of the first target clock signal line 31A away from the second target clock signal line 31B on the substrate 10. As a result, the area of ​​the overlapping region formed by the orthographic projection of each patch cord 40 on the substrate 10 and the orthographic projection of the first target clock signal line 31A on the substrate 10 can be made substantially equal, so that the load of each patch cord 40 and each clock signal line 31 is substantially the same, which is beneficial to improving the display effect of the special-shaped display panel 100.

[0146] In some embodiments, as shown in Figure 7, when the orthographic projection of the second line segment 42 of each adapter line 40 on the substrate 10 overlaps with the orthographic projection of the first target clock signal line 31A on the substrate 10, the orthographic projection of the edge of the second line segment 42 of each adapter line 40 can be set away from the orthographic projection of the edge of the first line segment 41 on the substrate 10, and both are located outside the boundary of the orthographic projection of the first target clock signal line 31A on the substrate 10.

[0147] With such a setting, each adapter line 40 can pass through the first target clock signal line 31A, so that the area of ​​the overlapping area formed by the orthographic projection of each adapter line 40 on the substrate 10 and the orthographic projection of the first target clock signal line 31A on the substrate 10 are roughly equal, so that the load of each adapter line 40 is roughly the same and the load of each clock signal line 31 is roughly the same, which is beneficial to improving the display effect of the special-shaped display panel 100.

[0148] In some examples, a first spacing between the orthographic projection of the edge of the second line segment 42 of each adapter line 40 away from the first line segment 41 on the substrate 10 and the orthographic projection of the edge of the first target clock signal line 31 away from the second target clock signal line 31B on the substrate 10 is in the range of 1 μm to 3 μm.

[0149] When the first spacing is in the range of 1μm to 3μm, it can ensure that each adapter line 40 can pass through the first target clock signal line 31, so that the area of ​​the overlapping area formed by the orthographic projection of each adapter line 40 on the substrate 10 and the orthographic projection of the first target clock signal line 31A on the substrate 10 are roughly equal, so that the load of each adapter line 40 and the load of each clock signal line 31 are roughly the same; it can also reduce the size of the adapter line 40 protruding from the first target clock signal line 31, so as to reduce the length of the adapter line 40, reduce the resistance of the adapter line 40, and also reduce the occupation of the size of the peripheral area SA by the adapter line 40, which is convenient for the layout of other devices and lines in the peripheral area SA.

[0150] In other examples, the first spacing ranges from 1 μm to 2 μm.

[0151] When the first spacing is within the range of 1μm to 2μm, it can ensure that each adapter line 40 can pass through the first target clock signal line 31 to realize the positive projection of each adapter line 40 on the substrate 10, so that the load of each adapter line 40 and the load of each clock signal line 31 are roughly the same; it can also better reduce the length of the adapter line 40, reduce the resistance of the adapter line 40, and reduce the size of the peripheral area SA occupied by the adapter line 40.

[0152] For example, the first spacing is approximately 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm. However, the embodiments of the present disclosure are not limited thereto.

[0153] It should be noted that for the purpose of this introduction, the first pitch is assumed to be approximately 1.5 μm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the first pitch fluctuates within the range of ±10% × 1.5 μm, it can also be considered that the first pitch is equal to 1.5 μm.

[0154] The above embodiments primarily describe how to layout multiple adapter lines 40 and multiple clock signal lines 31 to achieve approximately uniform loads on each adapter line 40 and each clock signal line 31, thereby improving the display quality of the special-shaped display panel 100. The above embodiments can be applied to electroluminescent display panels 100 or photoluminescent display panels 100, as well as special-shaped liquid crystal display panels 100. The following describes the structure of the special-shaped liquid crystal display panel 100, specifically the layout of the components and traces in its peripheral area SA.

[0155] In some embodiments, as shown in Figures 2 and 7, at least one clock signal line 31 is located in the sealing frame area F. The clock signal line 31 located in the sealing frame area F may include multiple openings K, so that UV light can be irradiated through the multiple openings K to the frame sealing glue F1 to achieve curing of the frame sealing glue F1.

[0156] In addition, if any one or more of the multiple clock signal lines 31 are provided with multiple openings K, all the clock signal lines 31 can be synchronously provided with multiple openings K to reduce the differences between the clock signal lines 31, thereby reducing the differences in loads between the clock signal lines 31 and improving the display effect of the special-shaped display panel 100.

[0157] It should be noted that the shape, size and position of the opening K in each clock signal line 31 may be the same, so as to reduce the difference between the clock signal lines 31 .

[0158] When each clock signal line 31 includes multiple openings K, the orthographic projection of the patch cord 40 on the substrate 10 is equal to the area of ​​the overlapping region formed by the orthographic projections of the openings K of at least two clock signal lines 31 on the substrate 10. In other words, the orthographic projection of the patch cord 40 on the substrate 10 is equal to the area of ​​the overlapping region formed by the orthographic projections of the portions of at least two clock signal lines 31 not having the openings K on the substrate 10.

[0159] Specifically, the orthographic projection of the transfer line 40 on the substrate 10 may be set to be equal to the area of ​​the overlapping region formed by the orthographic projection of the opening K on each clock signal line 31 on the substrate 10 .

[0160] Such a setting can reduce the difference in the area of ​​the overlapping area formed by the orthographic projection of the adapter line 40 on the substrate 10 and the orthographic projection of each clock signal line 31 on the substrate 10, thereby reducing the difference in the coupling capacitance formed between the adapter line 40 and each clock signal line 31, thereby reducing the load difference between each clock signal line 31, and improving the display effect of the special-shaped display panel 100.

[0161] In addition, when each clock signal line 31 includes multiple openings K, the orthographic projections of at least two patch cords 40 on the substrate 10 may be set to have an area equal to the overlapping area formed by the orthographic projections of the openings K of all the clock signal lines 31 on the substrate 10. In other words, the orthographic projections of at least two patch cords 40 on the substrate 10 and the orthographic projections of the portions of all the clock signal lines 31 that are not provided with the openings K on the substrate 10 have an area equal to the overlapping area formed by the orthographic projections of the portions of the clock signal lines 31 that are not provided with the openings K on the substrate 10.

[0162] Specifically, the orthographic projection of each transfer line 40 on the substrate 10 may be set to be equal to the area of ​​the overlapping region formed by the orthographic projections of the openings K on all the clock signal lines 31 on the substrate 10 .

[0163] Such a setting can reduce the difference in the area of ​​the overlapping area formed by the orthographic projection of each adapter line 40 on the substrate 10 and the orthographic projection of each clock signal line 31 on the substrate 10, thereby reducing the difference in the coupling capacitance formed between each low adapter line 40 and each clock signal line 31, thereby reducing the load difference between each low adapter line 40 and improving the display effect of the special-shaped display panel 100.

[0164] In some embodiments, the adapter line 40 and the clock signal line 31 are on different layers to prevent the adapter line 40 from being short-circuited with the clock signal line 31 that does not need to be connected to it.

[0165] In some examples, because the patch line 40 and the clock signal line 31 are on different layers, the patch line 40 can be directly connected to the clock signal line 31 to which it is to be connected through a via.

[0166] In other examples, as shown in Figure 7, since the adapter line 40 and the clock signal line 31 are in different layers, the special-shaped display panel 100 also includes multiple first connection parts W1, and the multiple first connection parts W1 are located on the side of the multiple adapter lines 40 away from the multiple clock signal lines 31. One end of the first connection part W1 is connected to the clock signal line 31, and the other end of the first connection part W1 is connected to the adapter line 40 to realize the connection between the adapter line 40 and the clock signal line 31 to which it needs to be connected.

[0167] Specifically, the first connection portion W1 may include a first sub-connection portion W11 and a second sub-connection portion W12. The orthographic projection of the first sub-connection portion W11 of the first connection portion W1 on the substrate 10 overlaps with the orthographic projection of the adapter wire 40 to be connected thereto on the substrate 10, so as to facilitate the connection between the first sub-connection portion W11 of the first connection portion W1 and the adapter wire 40. For example, the first sub-connection portion W11 of the first connection portion W1 may be connected to the adapter wire 40 through a via.

[0168] The orthographic projection of the second sub-connection portion W12 of the first connection portion W1 on the substrate 10 overlaps with the orthographic projection of the clock signal line 31 to which it is to be connected on the substrate 10, so that the second sub-connection portion W12 of the first connection portion W1 is connected to the clock signal line 31. For example, the second sub-connection portion W12 of the first connection portion W1 can be connected to the clock signal line 31 through a via.

[0169] FIG9 is a cross-sectional view of a special-shaped display panel according to some embodiments, wherein FIG9 takes the special-shaped display panel 100 as a special-shaped liquid crystal display panel as an example, and FIG9 mainly introduces the structure of the array substrate in the special-shaped liquid crystal display panel.

[0170] In some embodiments, as shown in conjunction with Figures 4, 7, and 9, each sub-pixel P0 in the special-shaped liquid crystal display panel 100 is provided with a driving circuit Q and a pixel electrode 51 located on the substrate 10. The driving circuit Q may include a first transistor T1, which includes an active layer, a source, a drain, a gate, and a gate insulating layer. The source and the drain are respectively in contact with the active layer. The source of the first transistor T1 is electrically connected to the data signal line Data, and the drain of the first transistor T1 is electrically connected to the pixel electrode 51, for transmitting a data signal on the data signal line Data to the pixel electrode 51.

[0171] In some examples, the first transistor T1 can be a thin film transistor, a field effect transistor, or other devices with the same characteristics. Since the source and drain of the transistors used are interchangeable under certain conditions, there is no difference in the description of the connection relationship between the source and drain. In addition, transistors can be divided into N-type and P-type according to their characteristics. In this embodiment, the transistor is described as an N-type transistor. When an N-type transistor is used, when the gate input is high, the source and drain of the second transistor T2 are turned on, and the opposite is true for the P-type. This will not be repeated here.

[0172] In some examples, the pixel electrode 51 is a transparent electrode. For example, the material of the pixel electrode 51 can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin dioxide (F2O).

[0173] In addition, the array substrate 110 of the special-shaped liquid crystal display panel 100 also includes a common electrode 61 disposed on the substrate 10. The pixel electrode 51 and the common electrode 61 can be disposed on the same layer. In this case, the pixel electrode 51 and the common electrode 61 both have a comb-tooth structure including a plurality of strip-shaped sub-electrodes. The pixel electrode 51 and the common electrode 61 can also be disposed on different layers, and the common electrode 61 can be a surface electrode. In this case, a first insulating layer V1 is disposed between the pixel electrode 51 and the common electrode 61. When the common electrode 61 is disposed between the first transistor T1 and the pixel electrode 51, a second insulating layer V2 is further disposed between the common electrode 61 and the first transistor T1. In other embodiments, the cell substrate 120 includes the common electrode 61.

[0174] Based on this, the electric field formed between the pixel electrode 51 and the common electrode 61 can be used to deflect the liquid crystal in the liquid crystal layer of the display panel 100 to achieve picture display.

[0175] In some embodiments, as shown in conjunction with FIG5 and FIG9 , the array substrate 110 of the special-shaped liquid crystal display panel 100 further includes a gate metal layer Gate, a source / drain metal layer SD, and a transparent electrode layer 50 in a direction away from the substrate 10. Pixel electrodes 51 within the plurality of sub-pixels P0 are located in the pixel electrode layer 50.

[0176] The gate metal layer Gate is located between the substrate 10 and the source / drain metal layer SD. The gate metal layer Gate may include the gate of the first transistor T1 of the driving circuit and may also be used to form the scan signal line G1. In addition, the gate metal layer Gate may also include the gate of the transistor in the shift register.

[0177] In some examples, the multiple clock signal lines 31 are located in the gate metal layer Gate. That is, the multiple clock signal lines 31 are arranged on the same layer as the gates of the transistors in the shift register and the scan signal line G1. This eliminates the need to form an additional metal layer in the special-shaped display panel 100. This not only facilitates electrical connection between the clock signal lines 31 and the transistors in the shift register, but also helps simplify the manufacturing process of the special-shaped display panel 100.

[0178] In some examples, the material of the gate metal layer Gate includes a conductive metal, and the conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0179] The source / drain metal layer SD is located between the gate metal layer Gate and the transparent electrode layer 50. The source / drain metal layer SD may include the source and drain of the first transistor T1 and may also be used to form the data signal line Data. Furthermore, the gate metal layer Gate may also include the source and drain of the transistors in the shift register.

[0180] In some examples, the plurality of adapter lines 40 are located in the source / drain metal layer SD. That is, the plurality of adapter lines 40 can be arranged in the same layer as the data signal lines Data, eliminating the need to form an additional metal layer in the special-shaped display panel 100, thereby simplifying the manufacturing process of the special-shaped display panel 100.

[0181] In some examples, the material of the source / drain metal layer SD includes a conductive metal. The conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto. In other examples, the material of the source / drain metal layer SD may include a molybdenum (Mo)-aluminum (Al)-molybdenum (Mo) multilayer composite material.

[0182] In some examples, a planarization layer (PLN) is provided between the source / drain metal layer SD and the gate metal layer Gate. The planarization layer PLN can electrically insulate the source / drain metal layer SD from the gate metal layer Gate.

[0183] Exemplarily, the material of the planarization layer PLN is generally an organic material. For example, the material of the planarization layer PLN may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0184] Based on this, when the adapter line 40 and the clock signal line 31 are directly connected through a via, a via is provided on the planarization layer PLN, and the via exposes the clock signal line 31 located on the gate metal layer Gate, so as to facilitate the electrical connection between the adapter line 40 located on the source and drain metal layer SD and the clock signal line 31.

[0185] When the adapter line 40 and the clock signal line 31 are electrically connected via the first connection portion W1, the first connection portion W1 can be provided on the same layer as the pixel electrode 51. Furthermore, no additional conductive layer needs to be formed in the special-shaped display panel 100, which helps simplify the manufacturing process of the special-shaped display panel 100.

[0186] The term "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, followed by a single patterning process using the same mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching steps, and the specific patterns within the resulting layer structure may be continuous or discontinuous, at varying heights or thicknesses.

[0187] In some examples, as shown in Figure 7, the adapter wire 40 may also include a adapter wire connection portion 40a. Along the extension direction of the clock signal line 31, the adapter wire connection portion 40a of the adapter wire 40 is located on one side of the second line segment 42 of the adapter wire 40, and the extension direction of the adapter wire connection portion 40a can be consistent with the extension direction of the clock signal line 31.

[0188] At this time, the orthographic projection of the first sub-connection part W11 of the first connection part W1 on the substrate 10 may overlap with the orthographic projection of the adapter wire connection part 40a of the adapter wire 40 on the substrate 10, so as to facilitate the connection between the first sub-connection part W11 of the first connection part W1 and the adapter wire connection part 40a of the adapter wire 40.

[0189] In addition, since the adapter wire connection portion 40a of the adapter wire 40 is located on one side of the second line segment 42 of the adapter wire 40, and the extension direction of the adapter wire connection portion 40a can be consistent with the extension direction of the clock signal line 31, it is equivalent to using the adapter wire connection portion 40a to increase the contact area between the first connection portion W1 and the adapter wire 40, which is beneficial to reducing the contact resistance between the two.

[0190] In some examples, the orthographic projection of the patch cord connection portion 40a of the patch cord 40 on the substrate 10 can be located within the boundary of the orthographic projection of the first sub-connection portion W11 of the first connection portion W1 on the substrate 10. The large size of the first sub-connection portion W11 of the first connection portion W1 can further reduce the contact resistance between the first connection portion W1 and the patch cord 40. In addition, the large size of the first sub-connection portion W11 of the first connection portion W1 can also facilitate the connection between the first sub-connection portion W11 of the first connection portion W1 and the patch cord 40 through a via.

[0191] The above embodiments, combined with the relevant drawings, primarily describe the relative positional relationship between the clock signal lines 31 and the adapter lines 40 within the peripheral area SA, thereby reducing the load on both and improving the display quality of the special-shaped display panel 100. The following description, combined with the relevant drawings, describes how to perform an array test (AT) on all data signal lines in the anisotropic display panel 100 to improve the yield rate of the special-shaped display panel 100.

[0192] Specifically, the following mainly introduces a special-shaped display panel 100 whose bonding process adopts COG (Chip On Glass, chip fixed on glass substrate). When the special-shaped display panel 100 is tested, the driving chip (Integrated Circuit, IC) has not been bonded to the array substrate.

[0193] At this time, the substrate 10 (glass substrate) is provided with a first pad PAD1 for connecting to the driver chip IC. When the driver chip IC is bonded to the special-shaped display panel 100, the input end of the driver chip IC can be connected to the first pad PAD1, and the output end of the driver chip IC can be connected to multiple data signal lines Data to transmit the driving signal to the data signal lines Data.

[0194] Since the number of the first pads PAD1 is much smaller than the number of the data signal lines Data, a shorting ring design solution needs to be adopted so as to match the number of the first pads PAD1 with the number of the shorting rings.

[0195] FIG10 is a structural diagram of a special-shaped display panel according to some further embodiments, and FIG11 is a partial enlarged diagram of C2 in FIG10 .

[0196] In some embodiments, as shown in Figures 5, 10 and 11, the peripheral area SA is divided into two sub-peripheral areas SA0 along the first reference line O1, and the display area AA is divided into two sub-display areas AA0. The first reference line O1 is an extension line of the center connection line of multiple scan signal lines G1.

[0197] Along the column direction Y, the sub-peripheral area SA0 includes a first border area SA1 (upper border) and a second border area SA2 (lower border). The special-shaped display panel 100 also includes a binding area BB. In the column direction Y, the first border area, multiple data signal lines Data and the binding area BB are arranged in sequence.

[0198] The first border area SA1 includes a first area SA11 and a second area SA12. The first area SA11 overlaps with the gate drive circuit G, while the second area SA12 does not overlap with the gate drive circuit G. That is, part of the shift register 20 in the gate drive circuit G is located in the first area SA11 of the first border area SA1, but the gate drive circuit G does not extend into the second area SA12 of the first border area SA1.

[0199] Two first shorting rings H1 can be provided in the special-shaped display panel 100. One first shorting ring H1 is located in each sub-peripheral area SA0 and is used to electrically connect all data signal lines Data within its corresponding sub-display area AA0. This facilitates testing (Arraytest, AT) of all data signal lines Data in the special-shaped display panel 100 using the two first shorting rings H1. Upon detecting a data line disconnection (Data Open, DO), appropriate repairs can be performed, thereby improving the yield of the special-shaped display panel 100.

[0200] Specifically, the first shorting loop H1 includes a first subsegment H01, a second subsegment H02, and a third subsegment H03. Within a first shorting loop H1, the second subsegment H02 is located in the first border area SA1 and connects to all data signal lines Data within its corresponding sub-display area AA0 at their ends away from the binding area BB. The third subsegment H03 is located in the second area SA12 of the first border area SA1. The first subsegment H01 extends from the binding area BB through the second border area SA2, the third border area SA3 / the fourth border area SA4, and the first area SA11 of the first border area SA1 to the second area SA12 of the first border area SA1. The first subsegment H01 is connected to the second subsegment H02 via the third subsegment H03.

[0201] That is, the first short-circuit ring H1 led out from the first pad PAD1 of the binding area BB first extends to the second area SA12 of the first border area SA1, then bends toward the side of the display area AA, extends to the position of the first border area SA1 close to the edge of the display area AA, and then the first short-circuit ring H1 is folded back and connected to the end of all the data signal lines Data in the corresponding sub-display area AA0 away from the binding area BB.

[0202] Based on this, the first subsegment H01 of the first shorting ring H1 is located on the side of the gate driver circuit G away from the display area AA, and the second subsegment H02 is located on the side of the gate driver circuit G closer to the display area AA. The third subsegment H03 is formed using the space outside the gate driver circuit G to connect the first subsegment H01 and the second subsegment H02. Furthermore, the end of the second subsegment H02 away from the third subsegment H03 extends to the outermost data signal line Data (closest to the gate driver circuit G) and does not extend between the gate driver circuit G and the scan signal line G1.

[0203] Exemplarily, the first sub-segment H01 of the first short-circuit ring H1 is located on the side of the clock signal line 31 away from the gate drive circuit G, and the second sub-segment H02 of the first short-circuit ring H1 is located on the side of the gate drive circuit G away from the clock signal line 31, and is located between the gate drive circuit G and the display area AA.

[0204] With such a configuration, the space of the peripheral area SA can be fully utilized to achieve that the first short-circuit ring H1 can be connected to all the data signal lines Data in its corresponding sub-display area AA0 away from the end of the binding area BB, without affecting the electrical connection between the gate drive circuit G and the multiple scanning signal lines G1, so as to prevent the short circuit problem between the first short-circuit ring H1, the gate drive circuit G and the scanning signal line G1.

[0205] In some examples, after the special-shaped display panel 100 is manufactured and packaged, a cell test is required. At this point, although the driver chip IC is bonded to the first pads PAD1, the spacing between the pins on the lighting device corresponding to the cell test (larger) does not match the spacing between the multiple first pads PAD1.

[0206] Based on this, second pads can be provided in the binding area BB. These second pads can be located at the edge of the binding area BB along the row direction X. In this case, the spacing between the multiple second pads PAD2 can match the spacing between the pins on the lighting device corresponding to the cell test. Thus, the multiple second pads PAD2 can be used to connect the first shorting ring H1 and the second shorting ring H2 to the external lighting device for cell test.

[0207] FIG12 is a layout diagram of C2 in FIG10 , and FIG13 is an equivalent circuit diagram of FIG12 .

[0208] In some embodiments, as shown in Figures 10 to 13, the special-shaped display panel 100 further includes a plurality of output signal lines OUT, and the output signal lines OUT are located between the shift register 20 and the display area AA, so that one shift register 20 is connected to one scan signal line G1 in the display area AA through one output signal line OUT.

[0209] The second subsegment H02 of the first shorting ring H1 can also be provided on the same layer as the data signal line Data. This eliminates the need to form an additional metal layer in the special-shaped display panel 100 to fabricate the second subsegment H02 of the first shorting ring H1, simplifying the manufacturing process of the special-shaped display panel 100. Furthermore, since the second subsegment H02 of the first shorting ring H1 can also be provided on the same layer as the data signal line Data, the second subsegment H02 of the first shorting ring H1 can be integrated with the data signal line Data, eliminating the need for an additional connection between the two. This simplifies the structure of the special-shaped display panel 100.

[0210] In some examples, the first sub-segment H01 of the first shorting ring H1 can be provided on the same layer as the scan signal line G1. This eliminates the need to form an additional metal layer in the special-shaped display panel 100 to fabricate the first sub-segment H01 of the first shorting ring H1, thereby simplifying the manufacturing process of the special-shaped display panel 100.

[0211] In other examples, the first sub-segment H01 of the first shorting ring H1 can be provided on the same layer as the data signal line Data. In other words, there is no need to form an additional metal layer in the special-shaped display panel 100 to form the first sub-segment H01 of the first shorting ring H1, which helps simplify the manufacturing process of the special-shaped display panel 100.

[0212] Among them, the above introduces two ways to set the first sub-segment H01 of the first short-circuit ring H1. The setting method can be selected according to the resistivity of the gate metal layer Gate and the source-drain metal layer SD. Selecting a film layer with a smaller resistivity to form the first sub-segment H01 of the first short-circuit ring H1 is beneficial to reducing the resistance of the first short-circuit ring H1.

[0213] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0214] In some examples, the output signal line OUT may be provided on the same layer as the data signal line Data, that is, the second sub-segment H02 of the first shorting ring H1, the output signal line OUT, and the data signal line Data are provided on the same layer.

[0215] No additional metal layer is required in the special-shaped display panel 100 to fabricate the output signal line OUT, further simplifying the manufacturing process of the special-shaped display panel 100. In this case, the output signal line OUT is equivalent to being disposed in the source / drain metal layer SD, and can also conveniently cross over other traces located in the gate metal layer Gate to prevent short circuits between the two, or the output signal line OUT being unable to extend to connect with the scan signal line G1. The traces located in the gate metal layer Gate may include common electrode lines, etc.

[0216] As shown in the above structure, the output signal line OUT is located in the source / drain metal layer SD, and the scan signal line G1 is located in the gate metal layer Gate. That is, the output signal line OUT and the scan signal line G1 are arranged in different layers.

[0217] In some examples, as shown in conjunction with Figures 10 to 13 , a scan signal line extension portion G2 may be provided. The scan signal line extension portion G2 is located on the same layer as the scan signal line G1 and is located in the peripheral area SA. The extension direction of the scan signal line extension portion G2 is consistent with the extension direction of the scan signal line G1. Furthermore, along the row direction X (the extension direction of the scan signal line G1), the scan signal line extension portion G2 is located on one side of the scan signal line G1 and is connected to the scan signal line G1. In other words, the scan signal line extension portion G2 can extend the scan signal line G1 so that the scan signal line G1 can be connected to the output signal line OUT located in the peripheral area SA. The scan signal line extension portion G2 can be understood as the portion that extends the scan signal line G1 to the peripheral area SA.

[0218] In some examples, the scan signal line G1 and the output signal line OUT can be connected through a via. The scan signal line G1 can utilize a scan signal line extension G2 to achieve a via connection with the output signal line OUT. Specifically, the orthographic projection of the end of the scan signal line extension G2 away from the scan signal line G1 on the substrate 10 overlaps with the orthographic projection of the end of the output signal line OUT away from the shift register 20 on the substrate 10. A via is provided on the planarization layer PLN between the two, exposing the scan signal line extension G2 on the gate metal layer Gate through the via, so that the output signal line OUT on the source / drain metal layer SD is electrically connected to the scan signal line extension G2.

[0219] In other examples, as shown in FIG12 , the special-shaped display panel 100 further includes a plurality of second connection portions W2. The second connection portions W2 are located on a side of the source / drain metal layer SD facing away from the gate metal layer Gate. One end of the second connection portion W2 is connected to the output signal line OUT, and the other end of the second connection portion W2 is connected to the scan signal line G1. In other words, the output signal line OUT and the scan signal line G1 can be connected via the second connection portions W2.

[0220] Exemplarily, the second connection portion W2 includes a third sub-connection portion W21 and a fourth sub-connection portion W22. The orthographic projection of the third sub-connection portion W21 of the second connection portion W2 on the substrate 10 overlaps with the orthographic projection of the output signal line OUT on the substrate 10, facilitating connection between the third sub-connection portion W21 of the second connection portion W2 and the output signal line OUT. For example, the third sub-connection portion W21 of the second connection portion W2 can be connected to the output signal line OUT through a via.

[0221] The orthographic projection of the fourth sub-connection portion W22 of the second connection portion W2 on the substrate 10 overlaps with the orthographic projection of the end of the scan signal line extension portion G2 away from the scan signal line G1 to which it is connected, so as to facilitate the connection between the fourth sub-connection portion W22 of the second connection portion W2 and the scan signal line extension portion G2. For example, the fourth sub-connection portion W22 of the second connection portion W2 can be connected to the scan signal line extension portion G2 through a via.

[0222] Based on this, the fourth sub-connection portion W22 of the second connection portion W2 is connected to the scanning signal line G1 , and the output signal line OUT and the scanning signal line G1 are connected by the second connection portion W2 .

[0223] In some examples, the second connection portion W2 may be provided in the same layer as the pixel electrode 51. Therefore, there is no need to form an additional conductive layer in the special-shaped display panel 100, which helps to simplify the manufacturing process of the special-shaped display panel 100.

[0224] It should be noted that in order to clearly illustrate the structure of each pixel electrode 51 in FIG12 , no pattern is filled in the pixel electrode 51 structure. In other words, the pixel electrode 51 is not filled with the same pattern as that filled in the second connecting portion W2. However, this does not mean that the second connecting portion W2 is not provided on the same layer as the pixel electrode 51.

[0225] In some embodiments, as shown in Figures 10 to 13 , the special-shaped display panel 100 further includes a plurality of switch units R and two second shorting rings H2 , with one second shorting ring H2 corresponding to each first shorting ring H1 . The plurality of switch units R are located between the second subsegment H02 of the first shorting ring H1 and the display area AA. A first end of the switch unit R is connected to the second subsegment H02 of the first shorting ring H1 , a second end of the switch unit R is connected to the data signal line Data, and a control end of the switch unit R is connected to the second shorting ring H2 .

[0226] Based on this, the second short-circuit ring H2 can be used to control the switch unit R to open or close. When the second short-circuit ring H1 controls the switch unit R to be turned on, the detection signal transmitted by the first short-circuit ring H1 can be transmitted to the corresponding data signal line Data through the switch unit R to detect whether the data signal line Data is broken.

[0227] The second short-circuit ring H2 includes a fourth sub-segment H04, a fifth sub-segment H05, and a sixth sub-segment H06. The fifth sub-segment H05 is located in the first border area SA1 and between the first sub-segment H01 and the second sub-segment H02. The fifth sub-segment H05 is connected to the control terminals of all switch units R within the same sub-peripheral area SA0. The sixth sub-segment H06 is located in the second area SA12 of the first border area SA1. The fourth sub-segment H04 is located between the first sub-segment H01 and the fifth sub-segment H05 and extends from the binding area BB to the second area SA12 of the first border area SA1. The fourth sub-segment H04 is connected to the fifth sub-segment H05 via the sixth sub-segment H06.

[0228] That is, the second short-circuit ring H2 led out from the binding area BB first extends to the second area SA12 of the first border area SA1, then bends toward the side of the display area AA, extends to a position of the first border area SA1 close to the edge of the display area AA, and then the second short-circuit ring H2 is folded back and connected to the end of all the data signal lines Data in the corresponding sub-display area AA0 away from the binding area BB.

[0229] Based on this, the fourth subsegment H04 of the second shorting ring H2 is positioned between the first subsegment H01 of the first shorting ring H1 and the gate drive circuit G. The fifth subsegment H05 of the second shorting ring H2 is positioned between the gate drive circuit G and the second subsegment H02 of the first shorting ring H1. The space outside the gate drive circuit G is then used to form the sixth subsegment H06 of the second shorting ring H2, connecting the fourth subsegment H04 and the fifth subsegment H05. The sixth subsegment H06 of the second shorting ring H2 is positioned between the third subsegment H03 of the first shorting ring H1 and the gate drive circuit G, preventing overlap between the second and first shorting rings H2 and H1. Furthermore, the end of the fifth subsegment H05 away from the sixth subsegment H06 extends to the outermost data signal line (closest to the gate drive circuit G) and does not extend between the gate drive circuit G and the scan signal line G1.

[0230] Illustratively, the fourth sub-segment H04 of the second short-circuit ring H2 is located between the first sub-segment H01 of the first short-circuit ring H1 and the clock signal line 31, and the fifth sub-segment H05 of the second short-circuit ring H2 is located on the side of the gate drive circuit G away from the clock signal line 31, and is located between the gate drive circuit G and the second sub-segment H02 of the first short-circuit ring H1.

[0231] With such a setting, the space of the peripheral area SA can be fully utilized to ensure that the second short-circuit ring H2 can be electrically connected to the switch unit R without affecting the electrical connection between the gate drive circuit G and the multiple scanning signal lines G1, thereby preventing short circuit problems between the second short-circuit ring H2, the gate drive circuit G and the scanning signal lines G1.

[0232] In some examples, the switch unit R may include a second transistor T2, which includes an active layer, a source, a drain, a gate, and a gate insulating layer. The source and drain are respectively in contact with the active layer. The source of the second transistor T2 is the first end of the switch unit R and is electrically connected to the second subsegment H02 of the first short-circuit ring H1. The drain of the second transistor T2 is the second end of the switch unit R and is electrically connected to the data signal line Data. The gate of the second transistor T2 is the control end of the switch unit R and is electrically connected to the fifth subsegment H05 of the second short-circuit ring H2. The source and drain of the second transistor T2 in the switch unit R may be located in the source-drain metal layer SD, and the gate of the second transistor T2 in the switch unit R may be located in the gate metal layer Gate.

[0233] Based on this, the second short-circuit ring H2 can be used to transmit the scan signal to the gate of the second transistor T2, controlling the second transistor T2 to turn on. The detection signal transmitted by the first short-circuit ring H1 can be transmitted to the corresponding data signal line Data through the switch unit R to detect whether the data signal line Data has a break. That is, during the detection phase, the second short-circuit ring H2 can control the second transistor T2 to turn on, and the detection signal transmitted by the first short-circuit ring H1 can be transmitted to the corresponding data signal line Data through the switch unit R. Subsequently, when the special-shaped display panel 100 is in the display phase, the second short-circuit ring H2 can control the second transistor T2 to turn off.

[0234] In some examples, the second transistor T2 can be a thin film transistor, a field effect transistor, or other devices with the same characteristics. Since the source and drain of the transistors used are interchangeable under certain conditions, there is no difference in the description of the connection relationship between the source and drain. In addition, transistors can be divided into N-type and P-type according to their characteristics. In this embodiment, the transistor is described as an N-type transistor. When an N-type transistor is used, when the gate input is high, the source and drain of the second transistor T2 are turned on, and the P-type is the opposite. This will not be repeated here.

[0235] In some embodiments, as shown in Figures 10 to 13 , the second shorting ring H2 and the scan signal line G1 are on the same layer. Therefore, there is no need to form an additional conductive layer in the special-shaped display panel 100 for forming the second shorting ring H2 , which helps simplify the manufacturing process of the special-shaped display panel 100 .

[0236] This arrangement is equivalent to arranging the fifth sub-segment H05 of the second short-circuit ring H2 and the second sub-segment H02 of the first short-circuit ring H1 in different layers, thereby preventing the fifth sub-segment H05 of the second short-circuit ring H2 and the second sub-segment H02 of the first short-circuit ring H1 from intersecting and short-circuiting.

[0237] In addition, since the gate of the second transistor T2 in the switching unit R can be located in the gate metal layer Gate, setting the second short-circuit ring H2 and the scanning signal line G1 on the same layer is equivalent to setting the second short-circuit ring H2 and the gate of the second transistor T2 on the same layer, which facilitates the electrical connection between the second short-circuit ring H2 and the gate of the second transistor T2 and simplifies the structure of the peripheral area SA of the special-shaped display panel 100.

[0238] In some examples, the second short-circuit ring H2 may further include a plurality of connecting sub-segments H07, the connecting sub-segments H07 extending along the row direction X, and the connecting sub-segments H07 being located between the fifth sub-segment H05 of the second short-circuit ring H2 and the display area AA, so that the fifth sub-segment H05 of the second short-circuit ring H2 can be connected to the second transistor T2 of the switching unit R through the connecting sub-segment H07.

[0239] In some examples, the connecting sub-segment H07 may include multiple conductive portions, which may be reused as the gate of the second transistor T2. Therefore, there is no need to separately fabricate the gate of the second transistor T2, which can simplify the fabrication process of the special-shaped display panel 100.

[0240] In some embodiments, as shown in FIG10 to FIG13 , since the second sub-segment H02 of the first shorting ring H1 is located in the source-drain metal layer SD, the output signal line OUT is also located in the source-drain metal layer SD, and the scan signal line extension G2 is located in the gate metal layer Gate.

[0241] The scanning signal line extension portion G2 can be set to extend between the fifth sub-segment H05 of the second short-circuit ring H2 and the orthographic projection of the second sub-segment H02 of the first short-circuit ring H1 on the substrate 10, so as to prevent the output signal line OUT from intersecting with the second sub-segment H02 of the first short-circuit ring H1 and causing a short circuit.

[0242] Based on this, the orthographic projection of the second connecting portion W2 on the substrate 10 can be arranged between the fifth subsegment H05 of the second short-circuit ring H2 and the orthographic projection of the second subsegment H02 of the first short-circuit ring H1 on the substrate 10. This prevents the second connecting portion W2 from being short-circuited with the second subsegment H02 of the first short-circuit ring H1 on the source-drain metal layer SD when connected to the scan signal line extension G2 on the gate metal layer Gate through a via.

[0243] In some examples, a gap is formed between the orthographic projection of the second connecting portion W2 on the substrate 10 and the orthographic projection of the fifth subsegment H05 of the second short-circuit ring H2 on the substrate 10 to prevent short circuit between the two.

[0244] In some examples, an orthographic projection of the second connecting portion W2 on the substrate 10 and an orthographic projection of the second sub-segment H02 of the first short-circuit ring H1 on the substrate 10 have a gap to prevent short circuit between the two.

[0245] FIG14 is a structural diagram of a special-shaped display panel according to some further embodiments, and FIG15 is a partially enlarged layout diagram of C3 in FIG14 .

[0246] In some embodiments, as shown in conjunction with FIG. 14 and FIG. 15 , the irregular display panel 100 further includes a third connection portion W3. The third connection portion W3 is co-layered with the second sub-segment H02 of the first short-circuit ring H1. One end of the third connection portion W3 is connected to the second sub-segment H02 of the first short-circuit ring H1 in one sub-display area AA0, and the other end of the third connection portion W3 is connected to the second sub-segment H02 of the first short-circuit ring H1 in another sub-display area AA0. In other words, the second sub-segments H02 of the first short-circuit ring H1 in two sub-peripheral areas SA0 are connected by a single third connection portion W3, thereby facilitating joint control of the first short-circuit ring H1 in both sub-peripheral areas SA0.

[0247] In some embodiments, as shown in conjunction with FIG. 14 and FIG. 15 , the irregular display panel 100 further includes a fourth connection portion W4. The fourth connection portion W4 is co-layered with the fifth subsegment H05 of the second short-circuit ring H2. One end of the fourth connection portion W4 is connected to the fifth subsegment H05 of the second short-circuit ring H2 in one sub-display area AA0, and the other end of the fourth connection portion W4 is connected to the fifth subsegment H05 of the second short-circuit ring H2 in another sub-display area AA0. In other words, the fifth subsegment H05 of the second short-circuit ring H2 in two sub-peripheral areas SA0 is connected by a single fourth connection portion W4, thereby facilitating joint control of the second short-circuit rings H2 in the two sub-peripheral areas SA0.

[0248] In some embodiments, as shown in Figures 14 and 15, the third sub-segment H03 of the first short-circuit ring H1 includes a first part H031 and a second part H032. The first part H031 of the third sub-segment H03 is on the same layer as the first sub-segment H01 of the first short-circuit ring H1, and the second part H032 of the third sub-segment H03 is on the same layer as the second sub-segment H02 of the first short-circuit ring H1.

[0249] This arrangement facilitates connection between the first portion H031 of the third sub-segment H03 and the first sub-segment H01 of the first short-circuit ring H1, and facilitates connection between the second portion H032 of the third sub-segment H03 and the second sub-segment H02 of the first short-circuit ring H1. The third sub-segment H03 of the first short-circuit ring H1, including the first portion H031 and the second portion H032, can be connected via vias.

[0250] In some embodiments, as shown in FIG14 and FIG15 , the orthographic projection of the second portion H032 of the third subsegment H03 on the substrate 10 overlaps with the orthographic projection of the fourth connecting portion W4 on the substrate 10. In other words, the orthographic projection of the first portion H031 of the third subsegment H03 on the substrate 10 does not overlap with the orthographic projection of the third connecting portion W3 on the substrate 10, thereby preventing a short circuit between the first portion H031 of the third subsegment H03 and the fourth connecting portion W4 located on the same layer.

[0251] FIG. 16 is a structural diagram of a special-shaped display panel according to still other embodiments.

[0252] In some embodiments, as shown in FIG16 , the special-shaped display panel 100 can implement split-screen control. That is, the two sub-display areas AA0 in the special-shaped display panel 100 are independently controlled. For example, each scan signal line G1 in the special-shaped display panel 100 is disconnected at the first reference line O1, and if the common electrode is a surface electrode, the common electrode is also disconnected at the first reference line O1, thereby achieving independent control of the two sub-display areas AA0.

[0253] In this case, the third and fourth connecting portions may not be provided on the special-shaped display panel 100. That is, the two first short-circuit rings H1 located in the two sub-peripheral areas SA0 are independently provided, and the two second short-circuit rings H2 located in the two sub-peripheral areas SA0 are independently provided, so as to facilitate the detection of the data signal lines Data in the two sub-display areas AA0.

[0254] 10 and 12 , the pixel unit P includes three sub-pixels P0. In the pixel unit rows corresponding to the first boundary S1 of the display area AA, the number of pixel units P in at least two pixel unit rows is different.

[0255] Along the direction from the first border area SA1 to the second border area SA2 (from the top to the bottom in FIG12 ), there are two adjacent rows of pixel units P, the two adjacent rows of pixel units are the nth pixel unit row and the n+1th pixel unit row, the number of pixel units P in the nth pixel unit row is less than the number of pixel units P in the n+1th pixel unit row, and n is a positive integer. The n+1th pixel unit row includes at least one n+1th target pixel unit P n+1 , along the column direction Y, the n+1th target pixel unit P n+1 There is no overlap with the nth pixel unit row, and the n+1th target pixel unit P n+1 The nth step region E is formed with the nth pixel unit row n .

[0256] In other words, the number of pixel units P in the n+1 pixel unit row is greater than the number of pixel units P in the n pixel unit row, and the extra pixel units P in the n+1 pixel unit row relative to the n pixel unit row are defined as the n+1 target pixel unit P in the n+1 pixel unit row. n+1 The n+1th target pixel unit P in the n+1th pixel unit row n+1 Protruding from the nth pixel unit row, forming the nth step area E with the nth pixel unit row n .

[0257] The switch unit R connected to the same data signal line Data as a sub-pixel P0 in the n+1th target pixel unit P is defined as the n+1th target switch unit R n+1 , multiple n+1th target switch units R n+1 Located in the nth step area E n That is, multiple n+1th target switch units R n+1 The nth pixel unit row is in the same row, and a plurality of n+1th target switch units R are arranged along the row direction X.

[0258] In other words, the n+1th target switch unit R corresponding to the sub-pixel P0 in the n+1th target pixel unit P is n+1 Set in the nth step area E n The step area outside the first sub-boundary S11 of the display area AA is fully utilized to improve the space utilization of the peripheral area SA. Furthermore, the switch unit R is disposed on one side of the data signal line Data along the column direction Y, facilitating the connection between the data signal line Data and the switch unit R.

[0259] In some embodiments, as shown in FIG. 12 , the n+1th target pixel unit P n+1 Away from one side edge of the n+1 pixel unit row, overlapping with the n pixel unit row in the row direction X, the n+1 target pixel unit P n+1 The edge of one side away from the n-th pixel unit row overlaps with the (n+1)-th pixel unit row in the column direction Y.

[0260] In other words, along the column direction Y, a plurality of n+1th target pixel units P do not protrude from the nth step region E. n , and along the row direction X, a plurality of n+1th target pixel units P do not protrude from the nth step region E n That is, a plurality of n+1th target pixel units P are collectively arranged in the nth step area E. n The circuit is configured to prevent affecting the routing layout of the output signal line OUT connected to the scanning signal line G1 corresponding to the n-th pixel unit row, thereby reducing the problem of short circuit between the output signal line OUT and the switch unit R.

[0261] In some examples, the width of the sub-pixel P0 along the row direction X is approximately px, and the length of the sub-pixel along the column direction Y is approximately py. Based on this, when the number of the n+1th target pixel unit P is 2, that is, corresponding to 6 sub-pixels P0. At this time, the nth step area E n The length along the row direction X is approximately 6px.

[0262] The minimum distance between the second subsection H01 of the first shorting ring H1 and the pixel unit row in the row direction X is bx, and the minimum distance between the second subsection H01 of the first shorting ring H1 and the pixel unit row in the column direction Y is by, where bx<px, by<py.

[0263] Based on this, it can be ensured that along the column direction Y, a plurality of n+1th target pixel units P do not protrude from the nth step region E. n , and along the row direction X, a plurality of n+1th target pixel units P do not protrude from the nth step region E n That is, a plurality of n+1th target pixel units P are collectively arranged in the nth step area E. n The circuit is configured to prevent affecting the routing layout of the output signal line OUT connected to the scanning signal line G1 corresponding to the n-th pixel unit row, thereby reducing the problem of short circuit between the output signal line OUT and the switch unit R.

[0264] In some examples, along the row direction X, the width of the second connection portion W2 is approximately cx, and along the column direction Y, the length of the second connection portion W2 is approximately cy.

[0265] The minimum distance between the fifth sub-segment H05 of the second shorting ring H2 and the step area in the row direction X is ax, and the minimum distance between the fifth sub-segment H05 of the second shorting ring H2 and the step area in the column direction Y is ay, where ax≥bx+b, ay>by+b+cy.

[0266] Based on this, a gap may be provided between the second subsegment H02 of the first shorting ring H1 and the fifth subsegment H05 of the second shorting ring H2 in the direction from the peripheral area SA to the display area AA to prevent parasitic capacitance from forming therebetween and increasing their loads.

[0267] FIG17 is another layout diagram of C2 in FIG10 , and FIG18 is an equivalent circuit diagram of FIG17 .

[0268] In some embodiments, as shown in Figures 10, 17, and 18, the pixel unit P includes three sub-pixels P0. In the pixel unit row corresponding to the first boundary S1 of the display area AA, along the direction from the first border area SA1 to the second border area SA2 (from top to bottom in Figure 17), three rows of pixel units P are arranged in sequence, and the three rows of pixel units P are respectively: the nth pixel unit row, the n+1th pixel unit row, and the n+2th pixel unit row. The number of pixel units P in the n+1th pixel unit row is greater than the number of pixel units P in the nth pixel unit row, and the number of pixel units P in the n+1th pixel unit row is less than the number of pixel units P in the n+2th pixel unit row. Specifically, the number of pixel units P in the nth pixel unit row, the n+1th pixel unit row, and the n+2th pixel unit row gradually increases.

[0269] The n+1th pixel unit row includes at least one n+1th target pixel unit P n+1 , along the column direction Y, the n+1th target pixel unit P n+1 There is no overlap with the nth pixel unit row, and the n+1th target pixel unit P forms the nth step area E with the nth pixel unit row. n .

[0270] In other words, the number of pixel units P in the n+1 pixel unit row is greater than the number of pixel units P in the n pixel unit row, and the extra pixel units P in the n+1 pixel unit row relative to the n pixel unit row are defined as the n+1 target pixel unit P in the n+1 pixel unit row. n+1 The n+1th target pixel unit P in the n+1th pixel unit row n+1 Protruding from the nth pixel unit row, forming the nth step area E with the nth pixel unit row n .

[0271] and the n+1th target pixel unit P n+1 The switch unit R connected to the same data signal line Data in a sub-pixel P0 is defined as the n+1th target switch unit R n+1 .

[0272] The n+2th pixel unit row includes at least one n+2th target pixel unit P n+2 , along the column direction Y, the n+2th target pixel unit P n+2 There is no overlap with the n+1 pixel unit row, and the n+2 target pixel unit P forms the n+1 step area E with the n+1 pixel unit row. n+1 .

[0273] In other words, the number of pixel units P in the n+2 pixel unit row is greater than the number of pixel units P in the n+1 pixel unit row, and the extra pixel units P in the n+2 pixel unit row relative to the n+1 pixel unit row are defined as the n+2 target pixel unit P in the n+2 pixel unit row. n+2 The n+2th target pixel unit P in the n+2th pixel unit row n+2 Protruding from the n+1th pixel unit row, forming the n+1th step area E with the n+1th pixel unit row n+1 .

[0274] and the n+2th target pixel unit P n+2 The switch unit R connected to the same data signal line Data in a sub-pixel P0 is defined as the n+2th target switch unit R n+2 .

[0275] Among them, multiple n+2 target switch units R n+2 The sub-pixels P0 in the image are arranged in two rows and multiple columns, with the n+2th target switch unit R in the first row. n+2 Located in the n+1 step area E n+1 In the same row as the n+1 pixel unit, the second row n+2 target switch unit R n+2 In the same row as the nth pixel unit and located in the nth step area E n A side away from the nth pixel unit row.

[0276] Based on this, multiple n+2 target switch units R n+2 The sub-pixel P0 in the image is divided into two parts. The first part (the n+2th target switch unit R in the first row) n+2 ) is set in the n+1th step area E n+1 In the second part (the second row n+2 target switch unit R n+2 ) is set in the n+1th step area E n+1 Far away from the n+2th target switch unit R n+2 and the second part (the second row n+2 target switch unit R n+2 ) and the nth step area E n That is, the second part (the second row n+2 target switch unit R n+2 ) is not directly set in the nth step area E n The nth step area E needs to be reserved n The space is used to place the n+1th target switch unit R n+1 .

[0277] In this way, all the n+2 target switch units R n+2 Both are set in the n+1 step area E n+1The internal method can prevent the n+2 target switch unit R n+2 The number of steps is too large to be completely set in the n+1 step area E n+1 The n+2 target switch unit R can be more reasonably arranged. n+2 , in order to make full use of the space in the peripheral area SA and facilitate the arrangement of wiring in the peripheral area SA.

[0278] In some embodiments, as shown in FIG. 17 and FIG. 18 , a plurality of n+1 target switch units R n+1 The sub-pixel P0 in the image may correspond to multiple n+2 target switch units R n+2 That is, the plurality of n+1th target switching units R n+1 The sub-pixels P0 in the image are arranged in two rows and multiple columns, with the n+1th target switch unit R in the first row. n+1 Located in the nth step area E n Inside, and the second row n+2 target switch unit R n+2 The same row as the nth pixel unit.

[0279] That is, the n+1th target switch unit R in the first row n+1 The target switch unit R located in the second row (n+2) n+2 Between the nth pixel unit row and the n+2th target switch unit R in the second row n+2 It can be adjacent to the n+1th target switch unit R in the first row n+1 In order to make full use of the space of the surrounding area SA, the n+1th target switch unit R in the second row is configured. n+1 The setting mode is the same as the second row n+2 target switch unit R n+2 The setting method is similar, and it is also set to the n+1 target switch unit R in the first row. n+1 A side away from the (n+1)th pixel unit row and may be on the same row as the (n-1)th pixel unit row. In this case, n is a positive integer greater than 1.

[0280] In some examples, due to the second row (n+2) target switch unit R n+2 It can be adjacent to the n+1th target switch unit R in the first row n+1 Setting, you can use the same connecting sub-segment H07 and the second row n+2 target switch unit R n+2 and the first row n+1 target switch unit R n+1 That is, the n+2th target switch unit R is set in the branch n+2 There is no need to add a separate connection sub-section H07, and the first row (n+1) target switch unit R can be shared. n+1 The required connected sub-segments H07 can save space in the peripheral area SA.

[0281] In some embodiments, as shown in FIG17 and FIG18 , the n+2th target switch unit R in the first row n+2 The number of target switch units R in the second row (n+2) n+2 The ratio of the number is 1:2.

[0282] Based on this, set the first row (n+2) target switch unit R n+2 The number of target switch units R in the second row (n+2) is greater than n+2 The number of second target switch units R is equivalent to setting a larger number of second target switch units R n+2 Located on one side of the second subsection H02 close to the first short-circuit ring H1, so that the n+2 target switch unit R n+2 Connected to the second subsection H02 of the first short-circuit ring H1. In addition, since each pixel unit P includes three sub-pixels P0, the first row (n+2) target switch unit R n+2 The number of target switch units R in the second row (n+2) n+2 The ratio of the number of is set to 1:2, which can facilitate the n+2th target switch unit R n+2 The sub-pixel column is electrically connected to the data signal line Data corresponding to the sub-pixel column.

[0283] FIG19 is another layout diagram of C2 in FIG10 .

[0284] In some embodiments, other wiring is provided between the gate drive circuit and the fifth sub-segment H05 of the second short-circuit ring H2. For example, a common electrode line Cm is provided between the gate drive circuit and the fifth sub-segment H05 of the second short-circuit ring H2, and the common electrode line Cm can be electrically connected to the common electrode layer.

[0285] Based on this, the orthographic projection of the output signal line OUT on the substrate 10 overlaps with the orthographic projection of the common electrode line Cm on the substrate 10. Parasitic capacitance is easily formed in the overlapping area between the two, thereby increasing the load on both. Therefore, the common electrode line Cm can be configured to include multiple hollow areas. The orthographic projection of the output signal line OUT on the substrate 10 overlaps with the orthographic projection of at least one hollow area of ​​the common electrode line Cm on the substrate 10. This can reduce the overlapping area between the output signal line OUT and the common electrode line Cm, thereby reducing the parasitic capacitance formed between the two and reducing the load on both, thereby improving the display effect of the special-shaped display panel 100.

[0286] The above embodiments primarily describe the arrangement of target switch units corresponding to target pixel units into one or two rows. If the number of target pixel units is large, resulting in a large number of target switch units, multiple target switch units may be arranged into three rows. The principle behind arranging multiple target switch units into three rows is similar to the principle behind arranging multiple target switch units into two rows. For details, please refer to the description of the above embodiments and will not be elaborated upon here.

[0287] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A special-shaped display panel comprising a display area and a peripheral area surrounding the display area, wherein the display area includes a first sub-border, at least two segments within the first sub-border extending in different directions, or the first sub-border is not perpendicular to a border of the adjacent display area; The special-shaped display panel includes: substrate; A plurality of pixel units are located on one side of the substrate, the plurality of pixel units are arranged in a plurality of rows and columns in the display area, and the pixel units include a plurality of sub-pixels; At least one gate drive circuit is located in the peripheral area, the gate drive circuit includes a plurality of cascaded shift registers, each shift register is connected to a plurality of sub-pixels arranged in a row; at a position corresponding to a first sub-boundary of the display area, an extension direction of a line connecting midlines of the plurality of shift registers is consistent with an extension direction of the first sub-boundary; a plurality of clock signal lines located in the peripheral area and on a side of the gate drive circuit away from the display area, at a position corresponding to a first sub-boundary of the display area, wherein an extension direction of the plurality of clock signal lines is consistent with an extension direction of the first sub-boundary; Each of the clock signal lines is connected to the shift register via a corresponding adapter line; Along the extension direction of the transfer line, the transfer line includes a first line segment and a second line segment, the first line segment and the second line segment are connected to form a corner, the first line segment is connected to the shift register, the second line segment is connected to the clock signal line, the orthographic projection of the second line segment on the substrate overlaps with the orthographic projection of the first part of the clock signal line connected to it on the substrate, and the extension direction of the second line segment is parallel to the line width extension direction of the first part of the clock signal line.

2. The special-shaped display panel according to claim 1, wherein: An extension direction of the first edge of the shift register is parallel to an outer tangent line of the first sub-boundary or consistent with an extension direction of the first sub-boundary. The first edge is an inner edge of the shift register close to the first sub-boundary.

3. The special-shaped display panel according to claim 1, wherein: An extending direction of the first edge of the shift register is perpendicular to the row direction.

4. The irregular-shaped display panel according to any one of claims 1 to 3, wherein: The line widths of any two adjacent clock signal lines are equal, and among the multiple clock signal lines: the clock signal line farthest from the display area is defined as a first target clock signal line, and the remaining clock signal lines are second target clock signal lines; The orthographic projection of the second line segment of each of the transfer lines on the substrate passes through all of the second target clock signal lines and overlaps with the orthographic projection of the first target clock signal line on the substrate.

5. The irregular-shaped display panel according to any one of claims 1 to 4, wherein: The peripheral area further includes a sealing frame area, at least one clock signal line is located in the sealing frame area, and each clock signal line includes a plurality of openings; The orthographic projection of the transfer line on the substrate is parallel to the openings of at least two clock signal lines on the substrate. The areas of the overlapping regions formed by the orthographic projections on the substrate are equal.

6. The special-shaped display panel according to any one of claims 1 to 5, further comprising: a gate metal layer and a source / drain metal layer, wherein the gate metal layer is located between the substrate and the source / drain metal layer; A plurality of the clock signal lines are located in the gate metal layer, and a plurality of the adapter lines are located in the source / drain metal layer; The special-shaped display panel also includes a plurality of first connection parts, and the plurality of first connection parts are located on the side of the source-drain metal layer away from the gate metal layer; the first connection part includes a first connection sub-part and a second connection sub-part, the orthographic projection of the first connection sub-part of the first connection part on the substrate overlaps with the orthographic projection of the adapter line on the substrate, and the first connection sub-part of the first connection part is connected to the adapter line, the orthographic projection of the second connection sub-part of the first connection part on the substrate overlaps with the clock signal line, and the second connection sub-part of the first connection part is connected to the clock signal line.

7. The special-shaped display panel according to claim 6, wherein: The special-shaped display panel further includes a transparent electrode layer, wherein the transparent electrode layer is located on a side of the source and drain metal layer away from the gate metal layer; The sub-pixel includes a pixel electrode, and the pixel electrode is located in the transparent electrode layer; wherein the first connecting portion is in the same layer as the pixel electrode.

8. The irregular-shaped display panel according to any one of claims 1 to 7, wherein: Also includes: A plurality of data signal lines are located in the display area, the plurality of data signal lines extend in a column direction, are arranged in a row direction, and are located in a source / drain metal layer; a plurality of scan signal lines located in the display area, the plurality of scan signal lines extending in a row direction and arranged in a column direction, and the plurality of scan signal lines located in the gate metal layer; wherein the gate metal layer is located between the substrate and the source / drain metal layer; The peripheral area is divided into two sub-peripheral areas and the display area is divided into two sub-display areas along a first reference line, wherein the first reference line is an extension line of a center line connecting the plurality of scanning signal lines; Along the column direction, the sub-peripheral area includes a first border area and a second border area, and the special-shaped display panel further includes a binding area. Along the column direction, the first border area, the plurality of data signal lines, and the binding area are arranged in sequence. The first border area includes a first area and a second area. The first area overlaps with the gate drive circuit, and the second area does not overlap with the gate drive circuit. Two first short-circuit rings, one of which is located in each of the sub-peripheral areas; the first short-circuit ring comprises: a first sub-segment, a second sub-segment, and a third sub-segment; In a short-circuit loop: the second sub-segment is located in the first border area, and the second sub-segment is located between the gate drive circuit and the display area, and the second sub-segment is connected to the end of all the data signal lines in the corresponding sub-display area away from the binding area; the third sub-segment is located in the second area of ​​the first border area; the first sub-segment is located on the side of the clock signal line away from the gate drive circuit, and the first sub-segment extends from the binding area to the second area of ​​the first border area, and is connected to the second sub-segment through the third sub-segment.

9. The special-shaped display panel according to claim 8, further comprising a plurality of output signal lines, wherein one shift register is connected to one scan signal line via one output signal line; and the output signal line, the second sub-segment and the data signal line are on the same layer.

10. The special-shaped display panel according to claim 8 or 9, further comprising: a gate metal layer and a source / drain metal layer, wherein the gate metal layer is located between the substrate and the source / drain metal layer; A plurality of the clock signal lines are located in the gate metal layer, and a plurality of the adapter lines are located in the source / drain metal layer; The special-shaped display panel further includes: a plurality of scanning signal line extension portions located in the peripheral area, the plurality of scanning signal line extension portions being on the same layer as the scanning signal lines, and the scanning signal line extension portions being consistent with the extending direction of the scanning signal lines, and one scanning signal line extension portion being located on one side of a scanning signal line in the row direction and being connected to the scanning signal line; A plurality of second connection portions are located in the peripheral area, and a plurality of the second connection portions are located on the side of the source / drain metal layer away from the gate metal layer; the second connection portion includes a third connection sub-portion and a fourth connection sub-portion, the orthographic projection of the third connection sub-portion of the second connection portion on the substrate overlaps with the orthographic projection of the output signal line on the substrate, and the third connection sub-portion of the second connection portion is connected to the output signal line, the orthographic projection of the fourth connection sub-portion of the second connection portion on the substrate overlaps with the orthographic projection of the scan signal line extension portion on the substrate, and the fourth connection sub-portion of the second connection portion is connected to the scan signal line extension portion.

11. The special-shaped display panel according to claim 10, wherein: The special-shaped display panel further includes a transparent electrode layer, wherein the transparent electrode layer is located on a side of the source and drain metal layer away from the gate metal layer; The sub-pixel includes a pixel electrode, and the pixel electrode is located in the transparent electrode layer; wherein the second connecting portion is in the same layer as the pixel electrode.

12. The special-shaped display panel according to any one of claims 8 to 11, further comprising a plurality of switch units and two second short-circuit rings; The plurality of switch units are located between the second sub-segment and the display area, the first end of the switch unit is connected to the first short-circuit ring, the second end of the switch unit is connected to the data signal line, and the control end of the switch unit is connected to the second short-circuit ring; The second short-circuit ring includes: the fourth, fifth, and sixth subparagraphs; The fifth sub-segment is located in the first border area, and the fifth sub-segment is located between the gate driving circuit and the second sub-segment, and the fifth sub-segment is connected to the control terminals of all the switch units in the same sub-peripheral area; The sixth sub-segment is located in the second area of ​​the first border area; the fourth sub-segment is located between the first sub-segment and the clock signal line, and the fourth sub-segment extends from the binding area to the second area of ​​the first border area, and is connected to the fifth sub-segment through the sixth sub-segment.

13. The special-shaped display panel according to claim 12, wherein: The second short-circuit ring and the scanning signal line are in the same layer, and the second connecting portion is projected onto the substrate and is located between the orthographic projections of the first short-circuit ring and the second short-circuit ring onto the substrate.

14. The special-shaped display panel according to claim 12 or 13, wherein: The pixel unit includes three sub-pixels; Among the multiple rows of pixel units corresponding to the first sub-border of the display area, two adjacent rows of pixel units are included in a direction from the first border area to the second border area, and the two adjacent rows of pixel units are respectively an n-th pixel unit row and an n+1-th pixel unit row, and the number of pixel units in the n-th pixel unit row is less than the number of pixel units in the n+1-th pixel unit row; n is a positive integer; The n+1th pixel unit row includes at least one n+1th target pixel unit, and along the column direction, the n+1th target pixel unit has no overlap with the nth pixel unit row, and the n+1th target pixel unit and the nth pixel unit row form an nth step region; A switch unit connected to the same data signal line as one of the sub-pixels in the n+1 target pixel unit is defined as the n+1 target switch unit, and multiple n+1 target switch units are located in the n step area, in the same row as the n pixel unit, and multiple n+1 target switch units are arranged along the row direction.

15. The special-shaped display panel according to claim 14, wherein: The n+1th target switch unit is away from one side edge of the n+1th pixel unit row and overlaps with the nth pixel unit row in the row direction. The n+1th target switch unit is away from one side edge of the nth pixel unit row and overlaps with the n+1th pixel unit row in the column direction.

16. The special-shaped display panel according to claim 12 or 13, wherein: The pixel unit includes three sub-pixels; Among the multiple rows of pixel units corresponding to the first sub-border of the display area, three rows of pixel units are sequentially arranged in a direction from the first border area to the second border area, and the three rows of pixel units are respectively: an nth pixel unit row, an n+1th pixel unit row, and an n+2th pixel unit row; The number of pixel units in the nth pixel unit row, the n+1th pixel unit row and the n+2th pixel unit row gradually increases; The n+2th pixel unit row includes at least one n+2th target pixel unit, and along the column direction, the n+2th target pixel unit does not overlap with the n+1th pixel unit row, and the n+2th target pixel unit and the n+1th pixel unit row form an n+1th step area; The n+1th pixel unit row includes at least one n+1th target pixel unit, and along the column direction, the n+1th target pixel unit has no overlap with the nth pixel unit row, and the n+1th target pixel unit and the nth pixel unit row form an nth step region; A switch unit connected to the same data signal line as one of the sub-pixels in the n+2th target pixel unit is defined as an n+2th target switch unit, and the sub-pixels in the n+2th target switch unit are arranged in two rows and multiple columns; The n+2th target switch unit in the first row is located in the n+1th step area, and the n+1th pixel unit row is the same as the n+1th pixel unit row. The (n+2)th target switch unit in the second row is in the same row as the nth pixel unit row and is located on a side of the nth step region away from the nth pixel unit row.

17. The special-shaped display panel according to claim 16, wherein: A switch unit connected to the same data signal line as one of the sub-pixels in the n+1th target pixel unit is defined as an n+1th target switch unit, and the sub-pixels in multiple n+1th target switch units are arranged in two rows and multiple columns; the n+1th target switch unit in the first row is located in the nth step area, and is in the same row as the n+2th target switch unit and the nth pixel unit in the second row.

18. The special-shaped display panel according to claim 16 or 17, wherein: The ratio of the number of the (n+2)th target switch units in the first row to the number of the (n+2)th target switch units in the second row is 1:

2.

19. The special-shaped display panel according to any one of claims 10 to 16, further comprising: a third connecting portion, located in the same layer as the second subsegment of the first shorting ring, one end of the third connecting portion being connected to the second subsegment of the first shorting ring in one sub-display area, and the other end of the third connecting portion being connected to the second subsegment of the first shorting ring in another sub-display area; a fourth connecting portion, which is on the same layer as the fifth subsegment of the second short-circuit ring, wherein one end of the fourth connecting portion is connected to the fifth subsegment of the second short-circuit ring in one sub-display area, and the other end of the fourth connecting portion is connected to the fifth subsegment of the second short-circuit ring in another sub-display area.

20. The special-shaped display panel according to claim 19, wherein: The third subsegment of the first short-circuit ring includes a first portion and a second portion, wherein the first portion of the third subsegment is on the same layer as the first subsegment of the first short-circuit ring and is connected to the first subsegment of the first short-circuit ring, and the second portion of the third subsegment is on the same layer as the second subsegment of the first short-circuit ring and is connected to the second subsegment of the first short-circuit ring; An orthographic projection of the second portion of the third sub-segment on the substrate overlaps with an orthographic projection of the fourth connecting portion on the substrate.

21. A display device comprising: A cover plate and the special-shaped display panel according to claims 1 to 20, wherein the cover plate is located on the light-emitting side of the special-shaped display panel.

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