Silicon-carbide device isolation structure based on n-epitaxy, and silicon-carbide high and low-voltage integrated device based on n-epitaxy and preparation method therefor

Abstract

A silicon-carbide device isolation structure based on N-epitaxy, and a silicon-carbide high and low-voltage integrated device based on N-epitaxy and a preparation method therefor. The isolation structure comprises an N-type substrate, an N-type drift region, and a first isolation trench and second isolation trench in which oxides are deposited so as to form a high-voltage region, a low-voltage region and a level shift region, wherein a second P-type doped region is provided at the bottom of the low-voltage region and the bottom of the level shift region, and a second N-type doped region is provided on the second P-type doped region in the low-voltage region; and the N-type drift region, the second P-type doped region in the low-voltage region, and the second N-type doped region form a back-to-back PN junction. A DMOS device is provided in a high-voltage region of the integrated device to serve as a power device, a low-voltage device is provided in a low-voltage region thereof to serve as a half-bridge driving circuit and a protection circuit, and an LDMOS device is provided in a level shift region thereof to control the potential of a substrate of the driving circuit. Further comprised is a preparation method for the integrated device. The present invention eliminates the impacts of potentials between silicon-carbide high and low-voltage devices, thereby improving the performance and reliability of silicon-carbide half-bridge driving circuits.

Description

Silicon carbide device isolation structure based on N epitaxy, high and low voltage integrated device and preparation method Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a silicon carbide high- and low-voltage integrated device based on N epitaxy, and also to a method for preparing a silicon carbide high- and low-voltage integrated device based on N epitaxy. Background Art

[0002] The semiconductor industry is increasingly demanding power devices. However, the performance of traditional silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) and silicon-based insulated-gate bipolar transistors (IGBTs) has reached the theoretical limits of their materials, failing to meet the requirements of next-generation power electronics systems. Silicon carbide, a wide-bandgap semiconductor, offers significant advantages over traditional silicon, including a wide bandgap, high critical breakdown electric field, high electron saturation drift velocity, and high thermal conductivity. This makes it an ideal semiconductor material for high-power, high-temperature, high-frequency, and radiation-resistant applications.

[0003] Due to their inherent material advantages, silicon carbide power devices have broad application prospects in high-temperature, high-irradiation fields such as aerospace, new energy vehicles, energy exploration and drilling, and nuclear power. However, the drive circuits and protection circuits currently used with silicon carbide power devices are still silicon-based, which has poor high-temperature and radiation resistance, which seriously limits the application range of silicon carbide power devices. Integrating the silicon carbide half-bridge drive circuit and silicon carbide power devices on the same substrate can reduce parasitic effects and improve system reliability. Although existing silicon carbide integrated devices can achieve monolithic integration, there is severe current crosstalk between high-voltage and low-voltage devices. The potential of the power device and the potential of the drive circuit substrate affect each other, seriously affecting the performance of the device.

[0004] Summary of the Invention

[0005] In view of the deficiencies in the prior art, the present invention provides a silicon carbide device isolation structure based on N epitaxy, a high and low voltage integrated device and a preparation method.

[0006] The present invention discloses an N-epitaxial-based silicon carbide device isolation structure, comprising: an N-type substrate, an N-type drift region provided on the N-type substrate, a first isolation trench with an oxide deposited therein and a second isolation trench with an oxide deposited therein provided on the N-type drift region to form a high-voltage region, a low-voltage region, and a level shift region, a second P-type doped region provided at the bottom of the low-voltage region and the level shift region, a second N-type doped region provided on the second P-type doped region in the low-voltage region, and the N-type drift region, the second P-type doped region in the low-voltage region, and the second N-type doped region forming a back-to-back PN junction.

[0007] The present invention provides a silicon carbide high and low voltage integrated device based on N epitaxy, comprising: an isolation structure,

[0008] The isolation structure includes an N-type substrate, an N-type drift region is provided on the N-type substrate, a first isolation trench with an oxide deposited therein and a second isolation trench with an oxide deposited therein are provided on the N-type drift region to form a high-voltage region, a low-voltage region and a level shift region, a second P-type doping region is provided at the bottom of the low-voltage region and the level shift region, a second N-type doping region is provided on the second P-type doping region in the low-voltage region, and the N-type drift region, the second P-type doping region in the low-voltage region and the second N-type doping region form a back-to-back PN junction;

[0009] A power DMOS device is provided in the high-voltage region, a low-voltage device is provided in the low-voltage region, and a high-voltage LDMOS device is provided in the level shift region;

[0010] A sixth N-type heavily doped region is provided on the second N-type doped region, a third epitaxial layer is provided on the second P-type doped region of the level shifting region, a third N-type doped region is provided on the third epitaxial layer, and a seventh N-type heavily doped region serving as a drain of the high-voltage LDMOS device is provided on the third N-type doped region. The sixth N-type heavily doped region is connected to the seventh N-type heavily doped region via a fifth drain metal electrode to control the potential of the second N-type doped region.

[0011] The method for preparing a silicon carbide high- and low-voltage integrated device based on N epitaxy according to the present invention comprises the following steps:

[0012] Obtaining a silicon carbide N-type substrate;

[0013] Epitaxially growing an N-type drift region on one surface of the N-type substrate; performing ion implantation on the N-type drift region to form a second P-type doping region, a first P-type doping region, and a first N-type doping region;

[0014] Growing a P-type epitaxial layer on the surfaces of the second P-type doping region, a portion of the N-type drift region, the first P-type doping region, and the first N-type doping region to form a first epitaxial layer and a third epitaxial layer;

[0015] Performing ion implantation on a portion of the third epitaxial layer above the second P-type doping region to form a third N-type doping region and a second N-type doping region; then performing ion implantation on the third N-type doping region to form a third P-type doping region and a fourth P-type doping region;

[0016] Performing ion implantation on the first epitaxial layer, the second N-type doping region, the third P-type doping region, the fourth P-type doping region, and the third epitaxial layer above the first N-type doping region to form a first P-type heavily doped region, a second P-type heavily doped region, a third P-type heavily doped region, a fourth P-type heavily doped region, a fifth P-type heavily doped region, a sixth P-type heavily doped region, and a seventh P-type heavily doped region;

[0017] forming, by ion implantation, first N-type heavily doped regions whose number is twice that of the first P-type heavily doped regions in the first epitaxial layer above the first N-type doped region, a second N-type heavily doped region and a sixth N-type heavily doped region in the second N-type doped region, a third N-type heavily doped region and a fourth N-type heavily doped region in the third P-type doped region, a fifth N-type heavily doped region in the fourth P-type doped region, a seventh N-type heavily doped region in the third N-type doped region, and an eighth N-type heavily doped region in the third epitaxial layer;

[0018] After high-temperature annealing, wet oxidation is performed to grow a gate oxide dielectric on the surface of the current local device structure, and a portion of the gate oxide dielectric above the second N-type doped region between the second P-type heavily doped region and the third P-type heavily doped region is used as a second planar gate oxide dielectric, a portion of the gate oxide dielectric above a portion of the third P-type doped region between the third N-type heavily doped region and the fourth N-type heavily doped region is used as a third planar gate oxide dielectric, and a portion of the gate oxide dielectric above a portion of the third epitaxial layer between the third N-type heavily doped region and the eighth N-type heavily doped region is used as a fourth planar gate oxide dielectric;

[0019] Depositing a second polysilicon gate, a third polysilicon gate and a fourth polysilicon gate on the second planar gate oxide dielectric, the third planar gate oxide dielectric and the fourth planar gate oxide dielectric respectively;

[0020] Etching trenches and depositing oxide in the portion of the first epitaxial layer between the first epitaxial layer and the second N-type doped region, between the second N-type doped region and the third epitaxial layer, and above the first P-type doped region, respectively, to form a first isolation trench, a second isolation trench, and an oxide trench; then etching the interior of the oxide trench to form a first trench-type gate oxide dielectric; and depositing polysilicon in the first trench-type gate oxide dielectric to form a first polysilicon gate;

[0021] A layer of oxide is deposited on the surface of the device in the current state to form an interlayer dielectric, a through hole is etched on the interlayer dielectric and a layer of metal is deposited, and then the layer of metal is etched to form a first source metal electrode, a second drain metal electrode, a second source metal electrode, a third drain metal electrode, a third source metal electrode, a fourth drain metal electrode, a first gate metal electrode, a fourth source metal electrode, a fifth drain metal electrode and a fifth source metal electrode; and metal is deposited in a high-voltage area on the other surface of the N-type substrate to form a first drain metal electrode.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The present invention proposes an N-epitaxial silicon carbide high- and low-voltage integrated device. The device can be divided into a high-voltage region, a low-voltage region, and a level-shifting region. Multiple high-energy ion implantations are performed to form a second P-type doped region above the N-type drift region in the low-voltage region and the level-shifting region. The reverse-biased PN junction formed by this second P-type doped region and the drift region completely blocks the influence of the high voltage of the power DMOS drain on the potential of the low-voltage device in the driver circuit. Multiple high-energy ion implantations are performed to form a second N-type doped region deep into the drift region within the epitaxial layer of the low-voltage region, converting the epitaxial layer in the low-voltage region to N-type. The low-voltage device is fabricated within the second N-type doped region. This doped region forms a reverse-biased PN junction with the second P-type doped region formed above the drift region. This ensures that the potential of the power DMOS device is not affected even when the high-side transistor driver substrate potential is at a high voltage. Furthermore, a second isolation trench is provided between the high-voltage and low-voltage regions. This trench extends below the P-type doped region in the drift region, completely blocking lateral current crosstalk between the high-voltage and low-voltage devices. While monolithically integrating the silicon carbide power device with its driver and protection circuits, the device utilizes two back-to-back PN junctions to eliminate vertical potential interference and deep trenches to eliminate lateral current crosstalk, improving the performance and reliability of the silicon carbide half-bridge driver circuit. The device also includes a level-shifting region with an LDMOS device to control the substrate potential in the low-voltage region.

[0024] The N-epitaxial-based silicon carbide device isolation structure, high- and low-voltage integrated device, and fabrication method described herein eliminate crosstalk between high and low voltages through their isolation structure, allowing high- and low-voltage devices to be integrated on the same substrate. The high-voltage DMOS device operates as a power device, while the low-voltage NMOS, PMOS, and JFET devices form a half-bridge drive circuit, protection circuit, and other components. The reverse-biased PN junction formed by the second P-type doped region in the drift region and the N-type drift region completely blocks the effect of the high voltage on the power DMOS drain on the substrate potential of the low-voltage device. The reverse-biased PN junction formed by the second N-type doped region on the epitaxial layer and the second P-type doped region above the drift region eliminates the effect of the driver circuit substrate potential on the power DMOS device. A second isolation trench is provided between the high- and low-voltage regions, and a first isolation trench is provided between the low- and level-shifting regions. The isolation trench extends below the second P-type doped region in the drift region, completely blocking lateral current crosstalk between the low- and high-voltage devices. When the above-mentioned silicon carbide high-low voltage integrated device is used as the gate drive circuit of the half-bridge low-side tube, the potential of the epitaxial layer in the low-voltage area is 0; when used as the gate drive circuit of the half-bridge high-side tube, the LDMOS is turned off, raising the potential of the epitaxial layer in the low-voltage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed inventions, the presently described embodiments and / or examples, and any of the best modes currently understood for these inventions.

[0026] FIG1 is a schematic diagram of a high- and low-voltage isolation structure of a silicon carbide high- and low-voltage integrated device based on N epitaxy in one embodiment of the present application;

[0027] FIG2 is a schematic structural diagram of a silicon carbide high and low voltage integrated device based on N epitaxy in one embodiment of the present application;

[0028] FIG3 is a schematic structural diagram of a silicon carbide high and low voltage integrated device used as a half-bridge low-side transistor driving circuit in one embodiment of the present application;

[0029] FIG4 is a schematic structural diagram of a silicon carbide high and low voltage integrated device used as a half-bridge high-side transistor driving circuit in one embodiment of the present application;

[0030] FIG5 is a flow chart of a method for preparing a silicon carbide high and low voltage integrated device based on N epitaxy in one embodiment of the present application;

[0031] 6( a ) to 6 ( s ) are schematic cross-sectional views of a process for manufacturing a silicon carbide high and low voltage integrated device according to the method shown in FIG. 6 in one embodiment of the present application; DETAILED DESCRIPTION

[0032] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0034] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. In this specification, "connected" should be understood as "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It will also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0038] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0039] In response to the current serious crosstalk problem in the monolithic integration of silicon carbide high-voltage and low-voltage circuits, this application proposes an N-epitaxial-based silicon carbide device isolation structure, a high- and low-voltage integrated device, and a preparation method.

[0040] Example 1

[0041] A silicon carbide device isolation structure based on N-epitaxiality includes: an N-type substrate 110, an N-type drift region 120 provided on the N-type substrate 110, a first isolation trench 23144 with oxide deposited therein and a second isolation trench 12144 with oxide deposited therein provided on the N-type drift region 120 to form a high-voltage region 10, a low-voltage region 20, and a level shifting region 30, a second P-type doping region 122 provided at the bottom of the low-voltage region 20 and the level shifting region 30, a second N-type doping region 20132 provided on the second P-type doping region 122 in the low-voltage region 20, and the N-type drift region 120, the second P-type doping region 122 in the low-voltage region 20, and the second N-type doping region 20132 forming a back-to-back PN junction.

[0042] In this embodiment, the doping concentration of the second P-type doping region 122 at the bottom of the low voltage region 20 and the level shift region 30 should be greater than 1E17 cm -3 , so that the PN junction it forms can withstand a voltage of 1.2kV.

[0043] Example 2

[0044] A silicon carbide high- and low-voltage integrated device based on N epitaxy, comprising:

[0045] An isolation structure includes an N-type substrate 110, an N-type drift region 120 provided on the N-type substrate 110, a first isolation trench 23144 with an oxide deposited therein and a second isolation trench 12144 with an oxide deposited therein provided on the N-type drift region 120, to form a high-voltage region 10, a low-voltage region 20, and a level shifting region 30, a second P-type doping region 122 provided at the bottom of the low-voltage region 20 and the level shifting region 30, a second N-type doping region 20132 provided on the second P-type doping region 122 within the low-voltage region 20, and the N-type drift region 120, the second P-type doping region 122 within the low-voltage region 20, and the second N-type doping region 20132 forming a back-to-back PN junction;

[0046] A power DMOS device 1 is provided in the high voltage region 10 , a low voltage device is provided in the low voltage region 20 , and a high voltage LDMOS device 5 is provided in the level shift region 30 ;

[0047] A sixth N-type heavily doped region 201383 is provided on the second N-type doping region 20132, a third epitaxial layer 30130 is provided on the second P-type doping region 122 of the level shift region 30, a third N-type doping region 30132 is provided on the third epitaxial layer 30130, and a seventh N-type heavily doped region 501381 serving as the drain 50D of the high-voltage LDMOS device 5 is provided on the third N-type doping region 30132. The sixth N-type heavily doped region 201383 is connected to the seventh N-type heavily doped region 501381 via a fifth drain metal electrode 501522 to control the potential of the second N-type doping region 20132.

[0048] In this embodiment:

[0049] The low-voltage devices include a low-voltage PMOS device 2 , a low-voltage NMOS device 3 , and a low-voltage JFET device 4 .

[0050] The low voltage PMOS device 2 includes a second P-type heavily doped region 201361, a third P-type heavily doped region 201362 and a second N-type heavily doped region 20138 provided on the second N-type doped region 20132. A second source metal electrode 201521 is connected to the second N-type heavily doped region 20138 and the third P-type heavily doped region 201362 to form a source 20S of the low voltage PMOS device 2. A second drain metal electrode 201522 is connected to the second P-type heavily doped region 201361 to form a drain 20D of the low voltage PMOS device 2. An interlayer dielectric 140 is provided between the doped region 20132, the second N-type heavily doped region 20138, the second P-type heavily doped region 201361 and the third P-type heavily doped region 201362 and the second source metal electrode 201521 and the second drain metal electrode 201522. A second planar gate oxide dielectric 20146 is provided on the second N-type doped region 20132 between the source 20S and the drain 20D of the low-voltage PMOS device 2. A second polysilicon gate 20147 is provided on the second planar gate oxide dielectric 20146 and serves as the gate 20G of the low-voltage PMOS device 2.

[0051] A third P-type doping region 30134 is provided on the second N-type doping region 20132. The low-voltage NMOS device 3 is provided in the third P-type doping region 30134 and includes a third N-type heavily doped region 301381, a fourth N-type heavily doped region 301382, and a fourth P-type heavily doped region 30136 provided on the third P-type doping region 30134. An interlayer dielectric 140 is provided on the third P-type doping region 30134, the third N-type heavily doped region 301381, the fourth N-type heavily doped region 301382, and the fourth P-type heavily doped region 30136. A third source metal electrode 30152 is provided on the interlayer dielectric 140. 1 and a third drain metal electrode 301522, the third source metal electrode 301521 is connected to the fourth P-type heavily doped region 30136 and the fourth N-type heavily doped region 301382 and forms the source 30S of the low-voltage NMOS device 3, the third drain metal electrode 301522 is connected to the third N-type heavily doped region 301381 and forms the drain 30D of the low-voltage NMOS device 3, a third planar gate oxide dielectric 30146 is provided on the interlayer dielectric 140, and a third polysilicon gate 30147 is provided on the third planar gate oxide dielectric 30146 and serves as the gate 30G of the low-voltage NMOS device 3;

[0052] A fourth P-type doping region 40134 is provided on the second N-type doping region 20132, the low voltage JFET device 4 is provided in the fourth P-type doping region 40134 and includes a fifth P-type heavily doped region 401361, a sixth P-type heavily doped region 401362 and a fifth N-type heavily doped region 40138 provided on the fourth P-type doping region 40134, an interlayer dielectric 140 is provided on the fourth P-type doping region 40134, the fifth P-type heavily doped region 401361, the sixth P-type heavily doped region 401362 and the fifth N-type heavily doped region 40138, and a fourth source is provided on the interlayer dielectric 140. The fourth source metal electrode 401521, the fourth drain metal electrode 401522 and the first gate metal electrode 401523, the fourth source metal electrode 401521 is connected to the sixth P-type heavily doped region 401362 and forms the source 40S of the low-voltage JFET device 4, the fourth drain metal electrode 401522 is connected to the fifth P-type heavily doped region 401361 and forms the drain 40D of the low-voltage JFET device 4, the first gate metal electrode 401523 is connected to the fifth N-type heavily doped region 40138 and forms the gate 40G of the low-voltage JFET device 4.

[0053] The power DMOS device 1 includes a first P-type doped region 10126 provided on an N-type drift region 120 within a high-voltage region 10, with first N-type doped regions 10124 provided on both sides of the first P-type doped region 10126; a first epitaxial layer 10130 provided on the first N-type doped region 10124, a first P-type heavily doped region 10136 provided on the first epitaxial layer 10130, a first polysilicon gate 10147 wrapped by a first trench-type gate oxide dielectric 10146 forming a gate 10G of the power DMOS provided on the first P-type lightly doped region 10126, and first N-type heavily doped regions 10138 provided on both sides of the first trench-type gate oxide dielectric 10146, and The first N-type heavily doped region 10138 is located in the first epitaxial layer 10130, and an interlayer dielectric 140 is provided on the first trench-type gate oxide dielectric 10146, the first polysilicon gate 10147, the first P-type heavily doped region 10136 and the first N-type heavily doped region 10138. A first source metal electrode 101521 is provided on the interlayer dielectric 140, and the first metal electrode 10152 is connected to the first P-type heavily doped region 10136 and the first N-type heavily doped region 10138 and forms the source 10S of the power DMOS device 1. A first drain metal electrode 101522 is provided on the N-type substrate 110 and serves as the drain 10D of the power DMOS device 1.

[0054] The high-voltage LDMOS device 5 further includes a seventh P-type heavily doped region 50136 and an eighth N-type heavily doped region 501382 provided in the third epitaxial layer 30130 of the level shift region 30. An interlayer dielectric 140 is provided on the third epitaxial layer 30130, the seventh P-type heavily doped region 50136, the eighth N-type heavily doped region 501382, the third N-type heavily doped region 30132, and the seventh N-type heavily doped region 501381. A fifth source metal electrode 501521 is provided on the interlayer dielectric 140. The fifth source metal electrode 501521 21 is connected to the seventh P-type heavily doped region 50136 and the eighth N-type heavily doped region 501382 to form the source 50S of the high-voltage LDMOS device 5, a fourth planar gate oxide dielectric 50146 is provided between the interlayer dielectric 140 and the third epitaxial layer 30130, and the fourth planar gate oxide dielectric 50146 is located between the eighth N-type heavily doped region 501382 and the third N-type doped region 30132, a fourth polysilicon gate 50147 is provided on the fourth planar gate oxide dielectric 50146 and serves as the gate 50G of the high-voltage LDMOS device 5.

[0055] In this embodiment, the power DMOS device 1 is used as a power device, the low-voltage PMOS device 2, the NMOS device 3, and the JFET device 4 constitute the driving circuit and protection circuit of the half-bridge low-side tube; the high-voltage LDMOS device 5 constitutes a level shift circuit; when the silicon carbide high-low voltage integrated device is used as the driving circuit of the half-bridge low-side tube, the potential of the epitaxial layer in the low-voltage area is 0; when used as the driving circuit of the half-bridge high-side tube, the LDMOS is turned off, raising the potential of the epitaxial layer in the low-voltage area; a first P-type doped region 10126 is provided in the area below the gate 10G of the DMOS device, which can adjust the electric field in the gate area to prevent premature breakdown; a first N-type doped region 10124 is provided in the drift region of the DMOS device to reduce the on-resistance of the device.

[0056] Example 3

[0057] A method for preparing a silicon carbide high- and low-voltage integrated device based on N epitaxy comprises the following steps:

[0058] Obtaining a silicon carbide N-type substrate 110;

[0059] An N-type drift region 120 is epitaxially grown on one surface of the N-type substrate 110; four ion implantations are performed on the N-type drift region 120 to form a second P-type doping region 122, wherein the four ion implantations have doses of 4E12cm -2 、6E12cm -2 、1E13cm -2 、1.2E13cm -2The energy is 80keV, 120keV, 200keV, and 280keV respectively, and the ion species is Al; by performing three ion implantations and forming the first P-type doping region 10126 and the first N-type doping region 10124 respectively, the three ion implantations have a dose of 1E12cm -2 、1.2E12cm -2 、1.5E12cm -2 , energies are 80keV, 100keV, and 120keV, and the ion species are Al and N, respectively;

[0060] Growing a P-type epitaxial layer on the surfaces of the second P-type doping region 122 , a portion of the N-type drift region 120 , the first P-type doping region 10126 , and the first N-type doping region 10124 to form a first epitaxial layer 10130 and a third epitaxial layer 30130 ;

[0061] Four ion implantations are performed on a portion of the third epitaxial layer 30130 above the second P-type doping region 122 to form a third N-type doping region 30132. The four ion implantations have a dose of 1E12 cm -2 、1.2E12cm -2 、1.5E12cm -2 、2E12cm -2 , the energy is 80keV, 120keV, 180keV, 240keV, and the ion species is N; six ion implantations are performed on the portion of the third epitaxial layer 30130 above the second P-type doping region 122 to form a second N-type doping region 20132, and the six ion implantations have a dose of 1E12cm -2 、1.2E12cm -2 、1.6E13cm -2 、2.0E12cm -2 、2.4E12cm -2 、3E12cm -2 , the energies are 80keV, 150keV, 200keV, 300keV, 400keV, and 500keV, respectively, and the ion species is N; then four ion implantations are performed on the third N-type doping region 30132 to form a third P-type doping region 30134 and a fourth P-type doping region 40134, and the four ion implantation doses are 1E12cm -2 、1.2E12cm -2 、1.5E12cm -2 、2E12cm -2 , energies are 80keV, 120keV, 180keV, and 240keV, and the ion species is Al;

[0062] Ion implantation is performed twice on the first epitaxial layer 10130, the second N-type doping region 20132, the third P-type doping region 30134, the fourth P-type doping region 40134 and the third epitaxial layer 30130 above the first N-type doping region 10124 to form a first P-type heavily doped region 10136, a second P-type heavily doped region 201361, a third P-type heavily doped region 201362, a fourth P-type heavily doped region 30136, a fifth P-type heavily doped region 401361, a sixth P-type heavily doped region 401362 and a seventh P-type heavily doped region 50136. The doses of the two ion implantations are 4E14 cm -2 、5E14cm -2 , energies are 80keV and 100keV respectively, and the ion species is Al;

[0063] By two ion implantations, a first N-type heavily doped region 10138 whose number is twice that of the first P-type heavily doped region 10136 is formed in the first epitaxial layer 10130 above the first N-type doping region 10124, a second N-type heavily doped region 20138 and a sixth N-type heavily doped region 201383 are formed in the second N-type doping region 20132, a third N-type heavily doped region 301381 and a fourth N-type heavily doped region 301382 are formed in the third P-type doping region 30134, a fifth N-type heavily doped region 40138 is formed in the fourth P-type doping region 40134, a seventh N-type heavily doped region 501381 is formed in the third N-type doping region 30132, and an eighth N-type heavily doped region 501382 is formed in the third epitaxial layer 30130. The doses of the two ion implantations are 4E14 cm -2 、5E14cm -2 , energies are 80keV and 100keV respectively, and the ion species is N;

[0064] After high-temperature annealing at 1650° C. for 30 minutes, water vapor is introduced at 1200° C. for 40 minutes for oxidation, and a gate oxide dielectric is grown on the surface of the current local device structure. In addition, a portion of the gate oxide dielectric above the second N-type doped region 20132 between the second P-type heavily doped region 201361 and the third P-type heavily doped region 201362 is used as the second planar gate oxide dielectric 20146, a portion of the gate oxide dielectric above a portion of the third P-type doped region 30134 between the third N-type heavily doped region 301381 and the fourth N-type heavily doped region 301382 is used as the third planar gate oxide dielectric 30146, and a portion of the gate oxide dielectric above a portion of the third epitaxial layer 30130 between the third N-type heavily doped region 30132 and the eighth N-type heavily doped region 501382 is used as the fourth planar gate oxide dielectric 50146. The surface of the current local device structure refers to the surface of the device structure shown in FIG. 6( k );

[0065] Depositing a second polysilicon gate 20147, a third polysilicon gate 30147 and a fourth polysilicon gate 50147 on the second planar gate oxide dielectric 20146, the third planar gate oxide dielectric 30146 and the fourth planar gate oxide dielectric 50146 respectively;

[0066] Trenches are etched and oxide is deposited in the first epitaxial layer 10130 between the first epitaxial layer 10130 and the second N-type doping region 20132, between the second N-type doping region 20132 and the third epitaxial layer 30130, and above the first P-type doping region 10126, respectively, to form a first isolation trench 23144, a second isolation trench 12144, and an oxide trench. The interior of the oxide trench is then etched to form a first trench-type gate oxide dielectric 10146. Polysilicon is deposited in the first trench-type gate oxide dielectric 10146 to form a first polysilicon gate 10147. The number of the first trench-type gate oxide dielectrics 10146 is the same as the number of the first P-type heavily doped regions 10136, which can be one or more. The number shown in the drawings of the present invention is two.

[0067] A layer of oxide is deposited on the surface of the device in the current state to form an interlayer dielectric 140, a through hole is etched on the interlayer dielectric 140 and a layer of metal is deposited, and then the layer of metal is etched to form a first source metal electrode 101521, a second drain metal electrode 201522, a second source metal electrode 201521, a third drain metal electrode 301522, a third source metal electrode 301521, a fourth drain metal electrode 401522, a first gate metal electrode 401523, a fourth source metal electrode 401521, a fifth drain metal electrode 501522 and a fifth source metal electrode 501521; metal is deposited on the high voltage area 10 on the other surface of the N-type substrate 110 to form a first drain metal electrode 101522. The so-called "device surface in the current state" refers to the device surface shown in Figure 6(o).

[0068] In this embodiment, the first P-type doping region 10126 is formed by three ion implantations, with a doping concentration of approximately 1E15 cm -3 The second P-type doping region 122 is formed by four ion implantations, with a doping concentration of approximately 1.1E17 cm -3 The implanted ion species is Al; the third P-type doping region 30134 and the fourth P-type doping region 40134 are formed by four ion implantations, and the doping concentration is about 1E16cm -3 The implanted ion species is Al; the first N-type doping region 10124 is formed by three ion implantations, with a doping concentration of approximately 1E17 cm -3The implanted ion type is N; the second N-type doping region 20132 is formed by six ion implantations, and the doping concentration is about 1E16cm -3 The implanted ion type is N; the third N-type doping region 30132 is formed by four ion implantations, and the doping concentration is about 1E16cm -3 , the type of implanted ions is N; the first P-type heavily doped region 10136, the second P-type heavily doped region 201361, the third P-type heavily doped region 201362, the fourth P-type heavily doped region 30136, the fifth P-type heavily doped region 401361, the sixth P-type heavily doped region 401362, and the seventh P-type heavily doped region 50136 are all formed by two ion implantations, with a doping concentration of approximately 1E19 cm -3 The implanted ion species is Al; the first N-type heavily doped region 10138, the second N-type heavily doped region 20138, the third N-type heavily doped region 301381, the fourth N-type heavily doped region 301382, the fifth N-type heavily doped region 40138, the sixth N-type heavily doped region 201383, and the seventh N-type heavily doped region 501381 are all formed by two ion implantations, with a doping concentration of approximately 1E19 cm -3 , the implanted ion species is N;

[0069] In this embodiment, during the etching of the first isolation trench 23144 and the second isolation trench 12144 , etching of the trench to below the second P-type doping region 122 is achieved by enlarging the mask window.

[0070] In this embodiment, the doping concentration of the second P-type doping region 122 at the bottom of the low voltage region 20 and the level shift region 30 should be greater than 1E17 cm -3 , so that the PN junction it forms can withstand a voltage of 1.2kV.

[0071] In this embodiment, the doping concentration of the N-type drift region 120 is lower than the doping concentration of the substrate 110 .

[0072] The following is a more detailed description of the specific embodiments of the present invention with reference to the accompanying drawings:

[0073] Figure 1 is a schematic diagram of a high-low voltage isolation structure of a silicon carbide high-low voltage integrated device based on N-epitaxiality in an embodiment of the present application; referring to Figure 1, an N-type drift region 120 is provided on an N-type substrate 110, a first isolation trench 23144 with an internally deposited oxide and a second isolation trench 12144 with an internally deposited oxide are provided on the N-type drift region 120 to form a high-voltage region 10, a low-voltage region 20 and a level shift region 30, a second P-type doping region 122 is provided at the bottom of the low-voltage region 20 and the level shift region 30, a second N-type doping region 20132 is provided on the second P-type doping region 122 in the low-voltage region 20, and the N-type drift region 120, the second P-type doping region 122 in the low-voltage region 20 and the second N-type doping region 20132 constitute a back-to-back PN junction.

[0074] In the embodiment shown in FIG1 , the first isolation trench 23144 and the second isolation trench 12144 are deep enough to be below the second P-type doping region 122 of the drift region, which can completely prevent current crosstalk between the high-voltage region 10 and the low-voltage region 20 and between the low-voltage region 20 and the level shift region 30 in the epitaxial layer.

[0075] In the embodiment shown in FIG1 , the reverse-biased PN junction formed by the second P-type doping region 122 and the drift region 120 can completely block the influence of the high-voltage region 10 on the substrate potential of the low-voltage region 20; the reverse-biased PN junction formed by the second P-type doping region 122 and the second N-type doping region 20132 on the epitaxial layer can eliminate the influence of the substrate potential of the low-voltage region 20 on the high-voltage region 10. The doping concentration of the second P-type doping region 122 in the drift region is not less than 1E17 cm -3 , enabling it to withstand a high voltage of 1.2kV.

[0076] FIG2 is a schematic structural diagram of a silicon carbide high- and low-voltage integrated device according to an embodiment of the present application. Referring to FIG2 , the device comprises: an N-type substrate 110, characterized in that an N-type drift region 120 is provided on the N-type substrate 110, a first isolation trench 23144 with oxide deposited therein and a second isolation trench 12144 with oxide deposited therein are provided on the N-type drift region 120 to form a high-voltage region 10, a low-voltage region 20, and a level shifting region 30, a second P-type doping region 122 is provided at the bottom of the low-voltage region 20 and the level shifting region 30, a second N-type doping region 20132 is provided on the second P-type doping region 122 in the low-voltage region 20, and the N-type drift region 120, the second P-type doping region 122 in the low-voltage region 20, and the second N-type doping region 20132 form a back-to-back PN junction; a power DMOS device 1 is provided in the high-voltage region 10, a low-voltage device is provided in the low-voltage region 20, and a high-voltage LDMOS device 5 is provided in the level shifting region 30.

[0077] The low voltage device includes a low voltage PMOS device 2, a low voltage NMOS device 3, and a low voltage JFET device 4. The low voltage PMOS device 2 includes a second P-type doping region 122 provided at the bottom of the low voltage region 30, a second N-type doping region 20132 provided on the second P-type doping region 122, a second N-type heavily doped region 20138, a second P-type heavily doped region 201361, and a third P-type heavily doped region 201362 provided on the second N-type doping region 20132, an interlayer dielectric 140 provided on the second N-type doping region 20132, the second N-type heavily doped region 20138, the second P-type heavily doped region 201361, and the third P-type heavily doped region 201362, and a second source metal electrode 201521 and a second drain metal electrode provided on the interlayer dielectric 140. The metal electrode 201522, the second source metal electrode 201521 is connected to the second N-type heavily doped region 20138 and the third P-type heavily doped region 201362 to form the source 20S of the low-voltage PMOS device 2, the second drain metal electrode 201522 is connected to the second P-type heavily doped region 201361 to form the drain 20D of the low-voltage PMOS device 2, a second planar gate oxide dielectric 20146 is provided on the interlayer dielectric 140, and a second polysilicon gate 20147 is provided on the second planar gate oxide dielectric 20146, which is the gate 20G of the low-voltage PMOS device 2; the low-voltage NMOS device 3 includes a A second N-type doping region 20132 is provided on the second P-type doping region 122 at the bottom of the low-voltage region 30, a third P-type doping region 30134 is provided on the second N-type doping region 20132, a third N-type heavily doped region 301381, a fourth N-type heavily doped region 301382 and a fourth P-type heavily doped region 30136 are provided on the third P-type doping region 30134, the third N-type heavily doped region 301381, the fourth N-type heavily doped region 301382 and the fourth P-type heavily doped region 30136, an interlayer dielectric 140 is provided on the interlayer dielectric 140, and a third source metal is provided on the interlayer dielectric 140. The third source metal electrode 301521 and the third drain metal electrode 301522 are connected to the fourth P-type heavily doped region 30136 and the fourth N-type heavily doped region 301382 to form the source 30S of the low-voltage NMOS device 3. The third drain metal electrode 301522 is connected to the third N-type heavily doped region 301381 to form the drain 30D of the low-voltage NMOS device 3. A third planar gate oxide dielectric 30146 is provided on the interlayer dielectric 140. A third polysilicon gate 30147 is provided on the third planar gate oxide dielectric 30146, which serves as the gate 30G of the low-voltage NMOS device 3.The low voltage JFET device 4 includes a second P-type doping region 122 provided at the bottom of the low voltage region 30, a second N-type doping region 20132 provided on the second P-type doping region 122, a fourth P-type doping region 40134 provided on the second N-type doping region 20132, a fifth P-type heavily doped region 401361, a sixth P-type heavily doped region 401362 and a fifth N-type heavily doped region 40138 provided on the fourth P-type doping region 40134, and a plurality of N-type heavily doped regions 401361, 401362 and 40138 provided on the fourth P-type doping region 40134. An interlayer dielectric 140 is provided on the substrate 138. A fourth source metal electrode 401521, a fourth drain metal electrode 401522, and a first gate metal electrode 401523 are provided on the interlayer dielectric 140. The fourth source metal electrode 401521 is connected to the sixth heavily P-type doped region 401362 and forms the source 40S of the low-voltage JFET device 4. The fourth drain metal electrode 401522 is connected to the fifth heavily P-type doped region 401361 and forms the drain 40D of the low-voltage JFET device 4. The first gate metal electrode 401523 is connected to the fifth heavily N-type doped region 40138 and forms the gate 40G of the low-voltage JFET device 4. A sixth heavily N-type doped region 201383 is provided on the second N-type doped region 20132.

[0078] The power DMOS device 1 includes a first N-type doping region 10124 and a first P-type doping region 10126 provided on an N-type drift region 120, and the first N-type doping region 10124 and the first P-type doping region 10126 are arranged crosswise. A first epitaxial layer 10130 is provided on the first N-type doping region 10124, and a first polysilicon gate 10147 wrapped by a first trench-type gate oxide dielectric 10146 is provided on the first P-type lightly doped region 10126 to form a gate 10G of the power DMOS. A first P-type heavily doped region 10136 and a first N-type heavily doped region 10136 are provided on the outer sides of the first polysilicon gate 10147. 8 and is located on the first epitaxial layer 10130, and an interlayer dielectric 140 is provided on the first trench-type gate oxide dielectric 10146, the first polysilicon gate 10147, the first P-type heavily doped region 10136 and the first N-type heavily doped region 10138, and a first source metal electrode 101521 is provided on the interlayer dielectric 140, the first metal electrode 10152 is connected to the first P-type heavily doped region 10136 and the first N-type heavily doped region 10138 and forms the source 10S of the power DMOS device 1, and the drain 10D of the power DMOS device 1 is the first drain metal electrode 101522 provided on the N-type substrate 110.

[0079] The high-voltage LDMOS device 5 includes a second P-type doping region 122 provided at the bottom of the level shifting region 30, a third epitaxial layer 30130 provided on the second P-type doping region 122, a seventh P-type heavily doped region 50136, an eighth N-type heavily doped region 501382 and a third N-type doped region 30132 provided on the third epitaxial layer 30130, a seventh N-type heavily doped region 501381 provided on the third N-type doped region 30132, an interlayer dielectric 140 provided on the third epitaxial layer 30130, the seventh P-type heavily doped region 50136, the eighth N-type heavily doped region 501382, the third N-type doped region 30132 and the seventh N-type heavily doped region 501381, A fifth source metal electrode 501521 and a fifth drain metal electrode 501522 are provided on the interlayer dielectric 140. The fifth source metal electrode 501521 is connected to the seventh heavily P-type doped region 50136 and the eighth heavily N-type doped region 501382 and forms the source 50S of the high-voltage LDMOS device 5. The fifth drain metal electrode 501522 is connected to the seventh heavily N-type doped region 501381 and forms the drain 50D of the high-voltage LDMOS device 5. A fourth planar gate oxide dielectric 50146 is provided on the interlayer dielectric 140. A fourth polysilicon gate 50147 is provided on the fourth planar gate oxide dielectric 50146, serving as the gate 50G of the high-voltage LDMOS device 5. The fifth drain metal electrode 501522 is connected to the sixth heavily N-type doped region 201383 to control the potential of the second N-type doped region 20132.

[0080] Due to its inherent material advantages, silicon carbide power devices have broad application prospects in high-temperature, high-radiation fields such as aerospace, new energy vehicles, energy exploration and drilling, and nuclear power. However, the drive circuits and protection circuits currently used with silicon carbide power devices are still silicon-based, which has poor high-temperature and radiation resistance, severely limiting their application range.

[0081] The silicon carbide high- and low-voltage integrated device provided in this application eliminates the crosstalk between high and low voltages through its isolation structure, and integrates high-voltage devices and low-voltage devices on the same substrate. The high-voltage DMOS device works as a power device, and the low-voltage NMOS, PMOS, and JFET devices constitute a half-bridge drive circuit, a protection circuit, etc. The reverse-biased PN junction formed by the second P-type doped region in the drift region and the N-type drift region can completely block the influence of the high voltage of the power DMOS drain on the substrate potential of the low-voltage device. The second N-type doped region on the epitaxial layer and the second P-type doped region above the drift region form a reverse-biased PN junction, eliminating the influence of the substrate potential of the drive circuit on the potential of the power DMOS device. A second isolation trench is provided between the high-voltage region and the low-voltage region, and the trench is deep enough to be below the second P-type doped region in the drift region, which can completely block the lateral current crosstalk between the low-voltage device and the high-voltage device. When the above-mentioned silicon carbide high-low voltage integrated device is used as the gate drive circuit of the half-bridge low-side tube, the potential of the epitaxial layer in the low-voltage area is 0; when used as the gate drive circuit of the half-bridge high-side tube, the LDMOS is turned off, raising the potential of the epitaxial layer in the low-voltage area.

[0082] In the embodiment shown in FIG. 2 , region 100 is used as a half-bridge low-side transistor driving circuit, and region 200 is used as a half-bridge high-side transistor driving circuit.

[0083] In the embodiment shown in Figure 2 , the power DMOS device includes a first P-type doped region 10126 beneath the gate oxide 10146, which regulates the electric field in the gate region and prevents premature breakdown. First N-type doped regions 10124 are located on either side of the first P-type doped region 10126 to reduce the device's on-resistance.

[0084] Figure 3 is a schematic diagram of the structure of a silicon carbide high- and low-voltage integrated device used as a half-bridge low-side transistor driver circuit in one embodiment of the present application. In this embodiment, the low-voltage devices within the low-voltage region 20 serve as the gate drive circuit and protection circuit for the half-bridge low-side transistor, while the high-voltage DMOS device 1 serves as the power device. Specifically, the potential of the second N-type doped region 20132 in the low-voltage region is 0.

[0085] Figure 4 is a schematic diagram of the structure of a silicon carbide high- and low-voltage integrated device used as a half-bridge high-side transistor driver circuit in one embodiment of the present application. In this embodiment, the low-voltage devices within the low-voltage region 20 serve as the gate drive circuit and protection circuit for the half-bridge low-side transistor. The high-voltage DMOS device 1 serves as a power device, and the LDMOS device 5 is used to raise the potential of the epitaxial layer. Specifically, when the LDMOS device 5 is in the off state, the drain 50D potential of the LDMOS device 5 is 1.2 kV, and the potential of the second N-type doped region 20132 in the low-voltage region is also raised to 1.2 kV.

[0086] The present application accordingly provides a method for preparing a silicon carbide high- and low-voltage integrated device based on N epitaxy, which can be used to prepare the silicon carbide high- and low-voltage integrated device described in any of the above embodiments. Figure 5 is a flow chart of the method for preparing a silicon carbide high- and low-voltage integrated device in one embodiment of the present application, comprising the following steps:

[0087] S310, obtaining a substrate.

[0088] An N-type silicon carbide substrate is obtained.

[0089] S320 , growing a drift region on the substrate.

[0090] In one embodiment of the present application, the drift region 120 is N-type silicon carbide.

[0091] In one embodiment of the present application, the doping concentration of the drift region 120 is lower than the doping concentration of the substrate 110 .

[0092] S330 , performing ion implantation in the drift region to form different types of doped regions.

[0093] Multiple ion implantations are used to form multiple doping regions of different types on the drift region.

[0094] In one embodiment of the present application, the first P-type doping region 10126 , the second P-type doping region 122 , and the first N-type doping region 10124 are formed by ion implantation;

[0095] S340 , growing an epitaxial layer on the drift region.

[0096] In one embodiment of the present application, the first epitaxial layer 10130 and the third epitaxial layer 30130 are P-type silicon carbide.

[0097] S350 , performing ion implantation in the epitaxial layer to form different types of doped regions.

[0098] In one embodiment of the present application, multiple ion implantations are performed to form a second N-type doping region 20132, a third N-type doping region 30132, a third P-type doping region 30134, a fourth P-type doping region 40134, a first P-type heavily doped region 10136, a second P-type heavily doped region 201361, a third P-type heavily doped region 201362, a fourth P-type heavily doped region 30136, a fifth P-type heavily doped region 401361, and a sixth P-type heavily doped region. the N-type heavily doped region 401362 and the seventh P-type heavily doped region 50136, the first N-type heavily doped region 10138, the second N-type heavily doped region 20138, the third N-type heavily doped region 301381, the fourth N-type heavily doped region 301382, the fifth N-type heavily doped region 40138, the sixth N-type heavily doped region 201383, the seventh N-type heavily doped region 501381 and the eighth N-type heavily doped region 501382, and performing high temperature annealing;

[0099] S360, growing a planar gate oxide dielectric and a polysilicon gate.

[0100] A planar gate oxide dielectric is grown by wet oxidation, and polysilicon is deposited on the gate dielectric.

[0101] In one embodiment of the present application, a second planar gate oxide dielectric 20146, a third planar gate oxide dielectric 30146, and a fourth planar gate oxide dielectric 40146 are grown on the first epitaxial layer 10130, the third epitaxial layer 30130, and the second N-type doped region 20132 by wet oxidation; a second polysilicon gate 20147, a third polysilicon gate 30147, and a fourth polysilicon gate 40147 are deposited on the planar gate oxide dielectrics, respectively.

[0102] S370, etching to form an isolation trench and a trench-type gate.

[0103] In one embodiment of the present application, trenches are etched on the first epitaxial layer 10130, the third epitaxial layer 30130 and the second N-type doped region 20132 and oxide is deposited to form a first isolation trench 23144, a second isolation trench 12144 and an oxide trench; then the interior of the oxide trench is etched to form a first trench-type gate oxide dielectric 10146, and polysilicon is deposited in the first trench-type gate oxide dielectric 10146 to form a first polysilicon gate 10147.

[0104] In one embodiment of the present application, trenches of different depths are achieved by adjusting the mask window. In one embodiment of the present application, the first isolation trench 23144 and the second isolation trench 12144 are deep enough to be below the second P-type doping region 122 of the drift region.

[0105] S380, growing an interlayer dielectric and etching through holes, depositing metal electrodes and etching.

[0106] An oxide layer is deposited on the epitaxial layer as an interlayer dielectric, so that the interlayer dielectric covers the entire device surface. A through hole is etched in the interlayer dielectric so that the through hole reaches the doped region on the epitaxial layer. Metal is deposited in the through hole and etched to form segmented metal electrodes.

[0107] In one embodiment of the present application, an interlayer dielectric 140 is deposited on the second planar gate oxide dielectric 20146, the third planar gate oxide dielectric 30146, and the fourth planar gate oxide dielectric 40146 so that the interlayer dielectric 140 covers the entire surface of the device. A through hole is etched in the interlayer dielectric 140, and metal is deposited in the through hole of the interlayer dielectric 140. The metal is etched to form a first source metal electrode 101521, a first drain metal electrode 101522, a second source metal electrode 201521, a second drain metal electrode 201522, a third source metal electrode 301521, a third drain metal electrode 301522, a fourth source metal electrode 401521, a fourth drain metal electrode 401522, a first gate metal electrode 401523, a fifth source metal electrode 501521, and a fifth drain metal electrode 501522.

[0108] In one embodiment of the present application, the metal electrode is a metal and / or an alloy.

[0109] The above-mentioned method for fabricating silicon carbide high- and low-voltage integrated devices eliminates crosstalk between high and low voltages through its isolation structure, integrating high- and low-voltage devices on the same substrate. The high-voltage DMOS device operates as a power device, while the low-voltage NMOS, PMOS, and JFET devices form a half-bridge drive circuit, protection circuit, and other components. The reverse-biased PN junction formed by the second P-type doped region in the drift region and the N-type drift region completely blocks the effect of the high voltage on the power DMOS drain on the substrate potential of the low-voltage device. The second N-type doped region on the epitaxial layer and the second P-type doped region above the drift region form a reverse-biased PN junction, eliminating the effect of the driver circuit substrate potential on the power DMOS device. A second isolation trench is provided between the high- and low-voltage regions, extending below the second P-type doped region in the drift region to completely block lateral current crosstalk between the low- and high-voltage devices. When the above-mentioned silicon carbide high-low voltage integrated device is used as the gate drive circuit of the half-bridge low-side tube, the potential of the epitaxial layer in the low-voltage area is 0; when used as the gate drive circuit of the half-bridge high-side tube, the LDMOS is turned off, raising the potential of the epitaxial layer in the low-voltage area.

[0110] FIG6(a) to FIG6(s) are cross-sectional schematic diagrams of a process for manufacturing a silicon carbide high and low voltage integrated device according to the method shown in FIG5 in one embodiment of the present application; FIG6(a) is a diagram for obtaining an N-type silicon carbide substrate 110; FIG6(b) is a diagram for epitaxially growing an N-type drift region 120 on the N-type substrate 110; FIG6(c) is a diagram for forming a second P-type doping region 122 by ion implantation; FIG6(d) is a diagram for forming a first P-type doping region 10126 by ion implantation; FIG6(e) is a diagram for forming a first N-type doping region (10124) by ion implantation; FIG6(f) is a diagram for growing a P-type epitaxial layer on the drift region to form a first epitaxial layer 10130 and a third epitaxial layer 30130; FIG6(g) is a diagram for forming a third N-type doping region 30130 by ion implantation. 2; FIG6(h) is a diagram showing a second N-type doped region 20132 formed by ion implantation; FIG6(i) is a diagram showing a third P-type doped region 30134 and a fourth P-type doped region 40134 formed by ion implantation; FIG6(j) is a diagram showing a first P-type heavily doped region 10136, a second P-type heavily doped region 201361, a third P-type heavily doped region 201362, a fourth P-type heavily doped region 30136, a fifth P-type heavily doped region 401361, a sixth P-type heavily doped region 401362 and a seventh P-type heavily doped region 50136 formed by ion implantation; FIG6(k) is a diagram showing a first N-type heavily doped region 10138, a second N-type heavily doped region 20138, a third N-type heavily doped region 301381, a fourth N-type heavily doped region 301382, the fifth N-type heavily doped region 40138, the sixth N-type heavily doped region 201383, the seventh N-type heavily doped region 501381 and the eighth N-type heavily doped region 501382, and high temperature annealing is performed; FIG6 (l) shows that a second planar gate oxide dielectric 20146, a third planar gate oxide dielectric 30146 and a fourth planar gate oxide dielectric 40146 are grown on the first epitaxial layer 10130, the third epitaxial layer 30130 and the second N-type doped region 20132 by wet oxidation; FIG6 (m) shows that a second polysilicon gate 20147, a third polysilicon gate 30147 are deposited on the second planar gate oxide dielectric 20146, the third planar gate oxide dielectric 30146 and the fourth planar gate oxide dielectric 40146 respectively. 47 and a fourth polysilicon gate 40147; FIG6(n) shows etching trenches on the first epitaxial layer 10130, the third epitaxial layer 30130 and the second N-type doped region 20132 and depositing oxide to form a first isolation trench 23144, a second isolation trench 12144 and an oxide trench; FIG6(o) shows etching the interior of the oxide trench to form a first trench-type gate oxide dielectric 10146, and depositing polysilicon in the first trench-type gate oxide dielectric 10146 to form a first polysilicon gate 10147; FIG6(p) shows depositing an interlayer dielectric 140 on the second planar gate oxide dielectric 20146, the third planar gate oxide dielectric 30146 and the fourth planar gate oxide dielectric 40146, so that the interlayer dielectric 140 covers the entire surface of the device;FIG6(q) shows etching a through hole in the interlayer dielectric 140; FIG6(r) shows depositing metal in the through hole in the interlayer dielectric 140; FIG6(s) shows etching metal to form a first source metal electrode 101521, a second source metal electrode 201521, a second drain metal electrode 201522, a third source metal electrode 301521, a third drain metal electrode 301522, a fourth source metal electrode 401521, a fourth drain metal electrode 401522, a first gate metal electrode 401523, a fifth source metal electrode 501521, and a fifth drain metal electrode 501522. Metal is deposited in the high voltage region 10 on the other surface of the N-type substrate 110 to form the first drain metal electrode 101522.

[0111] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0112] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0113] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A silicon carbide device isolation structure based on N epitaxy, comprising: An N-type substrate (110) is characterized in that an N-type drift region (120) is provided on the N-type substrate (110), a first isolation trench (23144) with an internally deposited oxide and a second isolation trench (12144) with an internally deposited oxide are provided on the N-type drift region (120) to form a high-voltage region (10), a low-voltage region (20) and a level shift region (30), a second P-type doping region (122) is provided at the bottom of the low-voltage region (20) and the level shift region (30), a second N-type doping region (20132) is provided on the second P-type doping region (122) in the low-voltage region (20), and the N-type drift region (120), the second P-type doping region (122) in the low-voltage region (20) and the second N-type doping region (20132) form a back-to-back PN junction.

2. A silicon carbide high and low voltage integrated device based on N epitaxy, comprising: An isolation structure, comprising an N-type substrate (110), characterized in that an N-type drift region (120) is provided on the N-type substrate (110), a first isolation trench (23144) with an internally deposited oxide and a second isolation trench (12144) with an internally deposited oxide are provided on the N-type drift region (120) to form a high-voltage region (10), a low-voltage region (20) and a level shift region (30), a second P-type doping region (122) is provided at the bottom of the low-voltage region (20) and the level shift region (30), a second N-type doping region (20132) is provided on the second P-type doping region (122) in the low-voltage region (20), and the N-type drift region (120), the second P-type doping region (122) in the low-voltage region (20) and the second N-type doping region (20132) form a back-to-back PN junction; A power DMOS device (1) is provided in the high-voltage region (10), a low-voltage device is provided in the low-voltage region (20), and a high-voltage LDMOS device (5) is provided in the level shift region (30); A sixth N-type heavily doped region (201383) is provided on the second N-type doped region (20132); a third epitaxial layer (30130) is provided on the second P-type doped region (122) of the level shift region (30); a third N-type doped region (30132) is provided on the third epitaxial layer (30130); a seventh N-type heavily doped region (501381) serving as a drain (50D) of a high-voltage LDMOS device (5) is provided on the third N-type doped region (30132); the sixth N-type heavily doped region (201383) is connected to the seventh N-type heavily doped region (501381) via a fifth drain metal electrode (501522) to control the potential of the second N-type doped region (20132).

3. The N-epitaxial silicon carbide high and low voltage integrated device according to claim 2, characterized in that: The low-voltage devices include a low-voltage PMOS device (2), a low-voltage NMOS device (3), and a low-voltage JFET device (4).

4. The N-epitaxial silicon carbide high and low voltage integrated device according to claim 3, characterized in that: The low-voltage PMOS device (2) comprises a second P-type heavily doped region (201361), a third P-type heavily doped region (201362) and a second N-type heavily doped region (20138) arranged on the second N-type heavily doped region (20132); a second source metal electrode (201521) is connected to the second N-type heavily doped region (20138) and the third P-type heavily doped region (201362) to form a source (20S) of the low-voltage PMOS device (2); a second drain metal electrode (201522) is connected to the second P-type heavily doped region (201361) to form a drain (20D) of the low-voltage PMOS device (2); and a second source metal electrode (201521) is connected to the second N-type heavily doped region (20138) and the third P-type heavily doped region (201362) to form a drain (20D) of the low-voltage PMOS device (2). An interlayer dielectric (140) is provided between the second N-type heavily doped region (20132), the second N-type heavily doped region (20138), the second P-type heavily doped region (201361), and the third P-type heavily doped region (201362) and the second source metal electrode (201521) and the second drain metal electrode (201522); a second planar gate oxide dielectric (20146) is provided on the second N-type heavily doped region (20132) between the source (20S) and the drain (20D) of the low-voltage PMOS device (2); and a second polysilicon gate (20147) is provided on the second planar gate oxide dielectric (20146) and serves as the gate (20G) of the low-voltage PMOS device (2).

5. The N-epitaxial silicon carbide high and low voltage integrated device according to claim 4, characterized in that: A third P-type doping region (30134) is provided on the second N-type doping region (20132); the low-voltage NMOS device (3) is provided in the third P-type doping region (30134) and includes a third N-type heavily doped region (301381), a fourth N-type heavily doped region (301382) and a fourth P-type heavily doped region (30136) provided on the third P-type doping region (30134); An interlayer dielectric (140) is provided on the doped region (30136), and a third source metal electrode (301521) and a third drain metal electrode (301522) are provided on the interlayer dielectric (140), wherein the third source metal electrode (301521) is connected to the fourth P-type heavily doped region (30136) and the fourth N-type heavily doped region (301382) to form the source (30S) of the low-voltage NMOS device (3), and the third drain metal electrode (301522) is connected to the third N-type heavily doped region (301381) to form the low-voltage NMOS device (3). The drain (30D) of the device (3) is provided with a third planar gate oxide dielectric (30146) on the interlayer dielectric (140), and a third polysilicon gate (30147) is provided on the third planar gate oxide dielectric (30146) and is the gate (30G) of the low-voltage NMOS device (3).

6. The N-epitaxial silicon carbide high and low voltage integrated device according to claim 4 or 5, characterized in that: A fourth P-type doping region (40134) is provided on the second N-type doping region (20132); the low-voltage JFET device (4) is provided in the fourth P-type doping region (40134) and includes a fifth P-type heavily doped region (401361), a sixth P-type heavily doped region (401362) and a fifth N-type heavily doped region (40138) provided on the fourth P-type doping region (40134); an interlayer dielectric (140) is provided on the fourth P-type doping region (40134), the fifth P-type heavily doped region (401361), the sixth P-type heavily doped region (401362) and the fifth N-type heavily doped region (40138); and a fourth source electrode is provided on the interlayer dielectric (140). A metal electrode (401521), a fourth drain metal electrode (401522) and a first gate metal electrode (401523), the fourth source metal electrode (401521) being connected to the sixth P-type heavily doped region (401362) and forming the source (40S) of the low-voltage JFET device (4), the fourth drain metal electrode (401522) being connected to the fifth P-type heavily doped region (401361) and forming the drain (40D) of the low-voltage JFET device (4), and the first gate metal electrode (401523) being connected to the fifth N-type heavily doped region (40138) and forming the gate (40G) of the low-voltage JFET device (4).

7. The N-epitaxial silicon carbide high and low voltage integrated device according to claim 6, characterized in that: The power DMOS device (1) comprises a first P-type doping region (10126) provided on an N-type drift region (120) within a high-voltage region (10), first N-type doping regions (10124) being provided on both sides of the first P-type doping region (10126); a first epitaxial layer (10130) being provided on the first N-type doping region (10124), a first P-type heavily doped region (10136) being provided on the first epitaxial layer (10130), a first polysilicon gate (10147) wrapped by a first trench-type gate oxide dielectric (10146) being provided on the first P-type lightly doped region (10126) to form a gate (10G) of the power DMOS, first N-type heavily doped regions (10138) being provided on both sides of the first trench-type gate oxide dielectric (10146), and the The first N-type heavily doped region (10138) is located in the first epitaxial layer (10130); an interlayer dielectric (140) is provided on the first trench-type gate oxide dielectric (10146), the first polysilicon gate (10147), the first P-type heavily doped region (10136) and the first N-type heavily doped region (10138); a first source metal electrode (101521) is provided on the interlayer dielectric (140); the first metal electrode (10152) is connected to the first P-type heavily doped region (10136) and the first N-type heavily doped region (10138) and forms the source (10S) of the power DMOS device (1); and a first drain metal electrode (101522) is provided on the N-type substrate (110) and serves as the drain (10D) of the power DMOS device (1).

8. The N-epitaxial silicon carbide high and low voltage integrated device according to claim 7, characterized in that: The high-voltage LDMOS device (5) further comprises a seventh P-type heavily doped region (50136) and an eighth N-type heavily doped region (501382) provided in the third epitaxial layer (30130) of the level shift region (30); an interlayer dielectric (140) is provided on the third epitaxial layer (30130), the seventh P-type heavily doped region (50136), the eighth N-type heavily doped region (501382), the third N-type doped region (30132) and the seventh N-type heavily doped region (501381); a fifth source metal electrode (501521) is provided on the interlayer dielectric (140); and the fifth source metal electrode (50152 1) connected to the seventh P-type heavily doped region (50136) and the eighth N-type heavily doped region (501382) and forming the source (50S) of the high-voltage LDMOS device (5); a fourth planar gate oxide dielectric (50146) is provided between the interlayer dielectric (140) and the third epitaxial layer (30130); the fourth planar gate oxide dielectric (50146) is located between the eighth N-type heavily doped region (501382) and the third N-type doped region (30132); a fourth polysilicon gate (50147) is provided on the fourth planar gate oxide dielectric (50146) and serves as the gate (50G) of the high-voltage LDMOS device (5).

9. A method for preparing a silicon carbide high and low voltage integrated device based on N epitaxy, characterized in that: The following steps are involved: Obtaining a silicon carbide N-type substrate (110); Epitaxially growing an N-type drift region (120) on one surface of the N-type substrate (110); performing ion implantation on the N-type drift region (120) to form a second P-type doping region (122), a first P-type doping region (10126), and a first N-type doping region (10124); Growing a P-type epitaxial layer on the surfaces of the second P-type doping region (122), a portion of the N-type drift region (120), the first P-type doping region (10126), and the first N-type doping region (10124) to form a first epitaxial layer (10130) and a third epitaxial layer (30130); Ion implantation is performed on a portion of the third epitaxial layer (30130) above the second P-type doping region (122) to form a third N-type doping region (30132) and a second N-type doping region (20132); and ion implantation is performed on the third N-type doping region (30132). Ion implantation to form a third P-type doping region (30134) and a fourth P-type doping region (40134); Ion implantation is performed on the first epitaxial layer (10130), the second N-type doping region (20132), the third P-type doping region (30134), the fourth P-type doping region (40134) and the third epitaxial layer (30130) above the first N-type doping region (10124) to form a first P-type heavily doped region (10136), a second P-type heavily doped region (201361), a third P-type heavily doped region (201362), a fourth P-type heavily doped region (30136), a fifth P-type heavily doped region (401361), a sixth P-type heavily doped region (401362) and a seventh P-type heavily doped region (50136); By ion implantation, a first N-type heavily doped region (10138) whose number is twice that of the first P-type heavily doped region (10136) is formed in the first epitaxial layer (10130) above the first N-type doped region (10124); a second N-type heavily doped region (20138) and a sixth N-type heavily doped region (201383) are formed in the second N-type doped region (20132); a third N-type heavily doped region (301381) and a fourth N-type heavily doped region (301382) are formed in the third P-type doped region (30134); a fifth N-type heavily doped region (40138) is formed in the fourth P-type doped region (40134); a seventh N-type heavily doped region (501381) is formed in the third N-type doped region (30132); and an eighth N-type heavily doped region (501382) is formed in the third epitaxial layer (30130); After high-temperature annealing, wet oxidation is performed to grow a gate oxide dielectric on the surface of the current local device structure, and a portion of the gate oxide dielectric above the second N-type doped region (20132) between the second P-type heavily doped region (201361) and the third P-type heavily doped region (201362) is used as a second planar gate oxide dielectric (20146), a portion of the gate oxide dielectric above a portion of the third P-type doped region (30134) between the third N-type heavily doped region (301381) and the fourth N-type heavily doped region (301382) is used as a third planar gate oxide dielectric (30146), and a portion of the gate oxide dielectric above a portion of the third epitaxial layer (30130) between the third N-type heavily doped region (30132) and the eighth N-type heavily doped region (501382) is used as a fourth planar gate oxide dielectric (50146); Depositing a second polysilicon gate (20147), a third polysilicon gate (30147) and a fourth polysilicon gate (50147) on the second planar gate oxide dielectric (20146), the third planar gate oxide dielectric (30146) and the fourth planar gate oxide dielectric (50146), respectively; Etching trenches and depositing oxide in the first epitaxial layer (10130) between the first epitaxial layer (10130) and the second N-type doping region (20132), between the second N-type doping region (20132) and the third epitaxial layer (30130), and above the first P-type doping region (10126) to form a first isolation trench (23144), a second isolation trench (12144), and an oxide trench, then etching the interior of the oxide trench to form a first trench-type gate oxide dielectric (10146), and depositing polysilicon in the first trench-type gate oxide dielectric (10146) to form a first polysilicon gate (10147); A layer of oxide is deposited on the surface of the device in the current state to form an interlayer dielectric (140), a through hole is etched on the interlayer dielectric (140) and a layer of metal is deposited, and the layer of metal is then etched to form a first source metal electrode (101521), a second drain metal electrode (201522), a second source metal electrode (201521), a third drain metal electrode (301522), a third source metal electrode (301521), a fourth drain metal electrode (401522), a first gate metal electrode (401523), a fourth source metal electrode (401521), a fifth drain metal electrode (501522) and a fifth source metal electrode (501521); and metal is deposited on a high voltage area (10) on the other surface of the N-type substrate (110) to form a first drain metal electrode (101522).

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