Memory structure and method for forming same

Abstract

A memory structure and a method for forming same. The method comprises: forming a barrier layer on a substrate; forming a source-drain layer structure on the barrier layer, wherein the source-drain layer structure comprises: source-drain stacks and first isolation layers, at least three source-drain stacks are sequentially stacked in the direction perpendicular to the surface of the substrate, each source-drain stack comprises two source-drain doped layers and a second isolation layer located between the source-drain doped layers, and each first isolation layer is located between two adjacent source-drain stacks; and forming a gate structure passing through the source-drain layer structure in the direction perpendicular to the surface of the substrate, and channel layers located between the gate structure and any source-drain stack. According to the memory structure, the storage capacity of a memory is increased, and the occupied area of the source-drain layer structure in the direction parallel to the surface of the substrate is only the occupied area of one source-drain stack in the direction parallel to the surface of the substrate, so that the area in the direction parallel to the surface of the substrate is not increased when the storage capacity is increased, improving the storage density of the memory.

Description

Memory structure and method for forming the same

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 23, 2024, with application number 202410206785.1 and invention name “Memory structure and formation method thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to a semiconductor manufacturing process, and in particular to a memory structure and a forming method thereof. Background Art

[0003] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance toward smaller process nodes. This has led to the development of integrated circuits with smaller size, higher circuit density, and greater circuit complexity. During the development of integrated circuits, functional density has generally increased while geometric dimensions have gradually decreased, increasing the difficulty and complexity of integrated circuit manufacturing.

[0004] Flash memory, as a mainstream storage medium, has rapidly gained popularity, and its technology has also experienced rapid development. Flash memory is divided into two types: NOT OR (NOR) and NOT AND (NAND). As a type of flash memory, NOR flash memory has garnered widespread attention due to its high programming speed and erase capabilities.

[0005] Flash memory technology using NOR-type flash arrays with a 1T (1-Transistor) device structure is widely used in various embedded consumer electronics and other applications. Because the 1T structure lacks a select gate transistor, it has a smaller bit area, increasing storage integration density, saving chip area, and reducing manufacturing costs. Because the source and drain of each bit in a NOR-type flash array are directly connected through metal, direct access to each bit is possible, resulting in higher read speeds than NAND-type flash arrays.

[0006] However, with the continuous miniaturization of two-dimensional planar devices, the miniaturization of flash memory devices is gradually approaching the limit of two-dimensional miniaturization, and the storage density of non-native flash memory needs to be improved.

[0007] Summary of the Invention

[0008] The technical problem solved by the present invention is how to improve the storage density of NOR-type flash memory.

[0009] To solve the above technical problems, an embodiment of the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a barrier layer on the substrate; forming a source-drain layer structure on the barrier layer, the source-drain layer structure comprising: a source-drain stack and a first isolation layer, at least three of the source-drain stacks being stacked in sequence along a direction perpendicular to the substrate surface, the source-drain stack comprising two source-drain doped layers and a second isolation layer located between the source-drain doped layers, the first isolation layer being located between two adjacent source-drain stacks; forming a gate structure penetrating the source-drain layer structure along a direction perpendicular to the substrate surface, and a channel layer located between the gate structure and any source-drain stack, wherein an end portion of the first isolation layer protrudes from an end portion of the source-drain stack in a direction toward the gate structure to achieve electrical insulation between adjacent channel layers.

[0010] Optionally, the step of forming a gate structure penetrating the source-drain layer structure in a direction perpendicular to the substrate surface and a channel layer located between the gate structure and any source-drain stack includes: forming a first opening penetrating the source-drain layer structure in a direction perpendicular to the substrate surface, the sidewall of the first opening exposing the source-drain stack and the first isolation layer; etching the source-drain stack exposed by the sidewall of the first opening to form a channel groove on the sidewall of the first opening; forming a channel layer in the channel groove; and forming the gate structure in the first opening of the channel layer formed in the sidewall.

[0011] Optionally, the step of etching the source-drain stack exposed by the sidewall of the first opening to form a channel groove on the sidewall of the first opening includes: etching the second isolation layer exposed by the sidewall of the first opening to form an initial channel groove on the sidewall of the first opening; etching the source-drain doping layer exposed by the sidewall of the first opening to form the channel groove.

[0012] Optionally, the step of forming a channel layer in the channel groove includes: forming an initial channel layer; etching the initial channel layer to expose an end surface of the first isolation layer, and retaining the initial channel layer in the channel groove to form the channel layer.

[0013] Optionally, forming a source-drain layer structure on the barrier layer includes: after forming the barrier layer on the substrate, forming an initial source-drain layer structure on the barrier layer, the initial source-drain layer structure including: an initial source-drain stack and an initial first isolation layer, at least three of the initial source-drain stacks are stacked in sequence along a direction perpendicular to the substrate surface, the initial source-drain stack including two initial source-drain doped layers and an initial second isolation layer located between the initial source-drain doped layers, and the initial first isolation layer is located between two adjacent initial source-drain stacks; after forming a gate structure penetrating the source-drain layer structure along a direction perpendicular to the substrate surface and a channel layer located between the gate structure and any source-drain stack, the initial source-drain layer structure is subjected to multiple connection etching processes to expose the connection area of ​​any source-drain doped layer and form the source-drain layer structure; wherein the connection etching process includes: etching part of the upper source-drain doped structure to expose the connection area of ​​any source-drain doped layer; after exposing the connection area, filling with a protective material, the protective material covering all exposed connection areas of the source-drain doped layers.

[0014] Optionally, it also includes: after forming an initial source-drain layer structure on the barrier layer, forming an initial buffer layer and an initial top isolation layer on the initial source-drain layer structure; etching the initial top isolation layer and the initial buffer layer to expose the connection area of ​​the source-drain stack closest to the buffer layer and the top isolation layer.

[0015] Optionally, the method further includes: forming an interlayer dielectric layer on the barrier layer and covering the source / drain layer structure, the buffer layer and the top isolation layer.

[0016] Optionally, the method further includes: forming an interconnection structure located in the interlayer dielectric layer.

[0017] Optionally, the step of forming an interconnect structure located in the interlayer dielectric layer includes: forming a first conductive plug located in the interlayer dielectric layer, the first conductive plug being electrically connected to the connection area of ​​the source-drain doped layer; forming a second conductive plug located in the interlayer dielectric layer, the second conductive plug being electrically connected to the gate structure; and forming a metal layer located on the interlayer dielectric layer, the metal layer being electrically connected to one of the first conductive plug and the second conductive plug.

[0018] Correspondingly, the technical solution of the present invention also provides a memory structure, including: a substrate; a barrier layer located on the substrate; a source-drain layer structure located on the barrier layer, the source-drain layer structure including: a source-drain stack and a first isolation layer, at least three of the source-drain stacks are stacked in sequence along a direction perpendicular to the substrate surface, the source-drain stack includes two source-drain doped layers and a second isolation layer located between the source-drain doped layers, the first isolation layer is located between two adjacent source-drain stacks; a gate structure penetrating the source-drain layer structure along a direction perpendicular to the substrate surface; a channel layer located between the sidewall of the gate structure and any source-drain stack, wherein the end of the first isolation layer protrudes from the end of the source-drain stack in the direction toward the gate structure to achieve electrical insulation between adjacent channel layers.

[0019] Optionally, a surface of the source / drain doped layer facing away from the substrate has a connection region, and the connection region is exposed to a portion of the upper source / drain doped layer.

[0020] Optionally, the connection region is located at an end of the source / drain doped layer away from the gate structure.

[0021] Optionally, it also includes: a buffer layer located on the source / drain layer structure and a top isolation layer located on the buffer layer; the connection area of ​​the source / drain doping layer closest to the buffer layer and the top isolation layer is exposed to the buffer layer and the top isolation layer.

[0022] Optionally, the method further includes: an interlayer dielectric layer located on the barrier layer and covering the source / drain layer structure, the buffer layer and the top isolation layer.

[0023] Optionally, it further includes: an interconnection structure located in the interlayer dielectric layer.

[0024] Optionally, the interconnect structure includes: a first conductive plug and a second conductive plug located in the interlayer dielectric layer and a metal layer located on the interlayer dielectric layer, the first conductive plug electrically connecting the connection area and the metal layer; the second conductive plug electrically connecting the gate structure and the metal layer.

[0025] Optionally, the barrier layer further extends between the gate structure and the substrate.

[0026] Optionally, the gate structure extends into the barrier layer in a direction toward the substrate.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the method for forming a memory structure of the technical solution of the present invention, the memory structure of the source-drain stacks stacked in sequence in a direction perpendicular to the substrate surface, the gate structure penetrating the source-drain layer structure in a direction perpendicular to the substrate surface, and the channel layer located between the sidewall of the gate structure and any source-drain stack increases the storage capacity of the memory structure, and the area occupied by the source-drain layer structure in the direction parallel to the substrate surface is only the area occupied by one source-drain stack in the direction parallel to the substrate surface. The memory structure does not increase the area in the direction parallel to the substrate surface when increasing the storage capacity, thereby improving the storage density of the memory.

[0029] An optional solution of the present invention further includes forming an interconnect structure within the interlayer dielectric layer. The first conductive plug is electrically connected to the connection region of the source / drain doped layer. The first conductive plug leads out each source / drain doped layer, thereby enabling direct control of each source / drain doped layer of the memory device having multiple source / drain stacks, thereby improving the operating speed of the memory structure.

[0030] In the memory structure of the technical solution of the present invention, the memory structure of the source-drain stacks stacked in sequence in a direction perpendicular to the substrate surface, the gate structure penetrating the source-drain layer structure in a direction perpendicular to the substrate surface, and the channel layer located between the side wall of the gate structure and any source-drain stack increases the storage capacity of the memory structure, and the area occupied by the source-drain layer structure in the direction parallel to the substrate surface is only the area occupied by one source-drain stack in the direction parallel to the substrate surface. The memory structure does not increase the area in the direction parallel to the substrate surface when increasing the storage capacity, thereby improving the storage density of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] 1 to 12 are schematic structural diagrams of various steps of a method for forming a memory structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, with the continuous miniaturization of two-dimensional planar devices, the miniaturization of flash memory devices is gradually approaching the limit of two-dimensional miniaturization, and the storage density of non-volatile flash memory needs to be improved.

[0033] In an embodiment of a memory structure, the memory structure includes: a substrate, the substrate including a base and a well region layer located on the substrate; a source and a drain located in the well region layer; a channel located between the source and the drain; and a gate structure located on the source and the drain, wherein a projection of the gate structure on the substrate surface partially overlaps with a projection of the source on the substrate surface and a projection of the drain on the substrate surface.

[0034] The memory structure further includes: a first conductive plug located on the source and the drain; and a second conductive plug located on the gate structure.

[0035] The memory structure has only one transistor and has a small storage capacity.

[0036] To solve the above technical problems, the technical solution of the present invention provides a method for forming a memory structure, comprising: providing a substrate; forming a barrier layer on the substrate; forming a source-drain layer structure on the barrier layer, the source-drain layer structure comprising: a source-drain stack and a first isolation layer, at least three of the source-drain stacks being stacked in sequence along a direction perpendicular to the substrate surface, the source-drain stack comprising two source-drain doped layers and a second isolation layer located between the source-drain doped layers, the first isolation layer being located between two adjacent source-drain stacks; forming a gate structure penetrating the source-drain layer structure along a direction perpendicular to the substrate surface, and a channel layer located between the gate structure and any source-drain stack, wherein an end portion of the first isolation layer protrudes from an end portion of the source-drain stack in a direction toward the gate structure to achieve electrical insulation between adjacent channel layers.

[0037] The memory structure of the source-drain stacks stacked in sequence along a direction perpendicular to the substrate surface, the gate structure penetrating the source-drain layer structure along a direction perpendicular to the substrate surface, and the channel layer located between the sidewall of the gate structure and any source-drain stack described in the technical solution of the present invention increases the storage capacity of the memory structure, and the area occupied by the source-drain layer structure in the direction parallel to the substrate surface is only the area occupied by one source-drain stack in the direction parallel to the substrate surface. The memory structure does not increase the area in the direction parallel to the substrate surface when increasing the storage capacity, thereby improving the storage density of the memory.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] 1 to 12 are schematic structural diagrams of various steps of a method for forming a memory structure according to an embodiment of the present invention.

[0040] Referring to FIG. 1 , a substrate 101 is provided.

[0041] The substrate 101 may be made of silicon, silicon carbide, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0042] Referring to FIG. 2 , a barrier layer 102 is formed on the substrate 101 .

[0043] The barrier layer 102 is used to isolate the subsequently formed gate structure 117 from the substrate 101, and to isolate the subsequently formed source / drain layer structure from the substrate 101, thereby preventing excessive capacitance between the heavily doped source / drain doped layer 110 and the substrate 101. The heavily doped source / drain doped layer 110 in the source / drain layer structure would result in excessive capacitance between the source / drain doped layer 110 and the substrate 101 without the barrier layer 102.

[0044] The barrier layer 102 has a thickness ranging from 1000 angstroms to 20000 angstroms. The barrier layer 102 is made of silicon oxide.

[0045] Please refer to Figures 3 to 11. A source-drain layer structure is formed on the barrier layer 102. The source-drain layer structure includes: a source-drain stack and a first isolation layer 109 (as shown in Figure 11). At least three source-drain stacks are stacked in sequence along a direction perpendicular to the surface of the substrate 101. The source-drain stack includes two source-drain doped layers 110 (as shown in Figure 11) and a second isolation layer 111 (as shown in Figure 11) located between the source-drain doped layers 110. The first isolation layer 109 is located between two adjacent source-drain stacks.

[0046] The area occupied by the source-drain layer structure in the direction parallel to the surface of the substrate 101 is only the area occupied by one source-drain stack in the direction parallel to the surface of the substrate 101. When the storage capacity of the memory structure is increased, the area in the direction parallel to the surface of the substrate 101 is not increased, thereby improving the storage density of the memory.

[0047] The steps of forming the source-drain layer structure include: as shown in Figure 3, after forming a barrier layer 102 on the substrate 101, forming an initial source-drain layer structure on the barrier layer 102, the initial source-drain layer structure including: an initial source-drain stack and an initial first isolation layer 105, at least three of the initial source-drain stacks are stacked in sequence along a direction perpendicular to the surface of the substrate 101, the initial source-drain stack includes two initial source-drain doped layers 103 and an initial second isolation layer 104 located between the initial source-drain doped layers 103, and the initial first isolation layer 105 is located between two adjacent initial source-drain stacks.

[0048] The initial source-drain layer structure is subsequently used to form the source-drain layer structure, wherein the initial source-drain stack is subsequently used to form a source-drain stack, and the initial first isolation layer 105 is subsequently used to form a first isolation layer 109. Specifically, the initial source-drain doped layer 103 is subsequently used to form a source-drain doped layer 110, and the initial second isolation layer 104 is subsequently used to form a second isolation layer 111.

[0049] The material of the initial source-drain doping layer 103 includes heavily doped polysilicon and metal, and the metal includes aluminum and tungsten. Specifically, in the present embodiment, the material of the initial source-drain doping layer 103 is N-type heavily doped polysilicon. The material of the initial first isolation layer 105 includes silicon nitride; the material of the initial second isolation layer 104 includes silicon oxide. There are at least three source-drain stacks. There are also at least three initial source-drain stacks. Specifically, as shown in Figures 3 to 10, in the present embodiment, the number of the source-drain stacks is three, and in other embodiments, the number of the source-drain stacks is other values. The source-drain stack provides a structural basis for forming a memory cell.

[0050] The thickness of the source / drain doping layer 110 is in the range of 500 angstroms to 1000 angstroms; the thickness of the initial source / drain doping layer 103 is in the range of 500 angstroms to 5000 angstroms.

[0051] The second isolation layer 111 is used to isolate the adjacent source-drain doped layer 110. The thickness of the second isolation layer 111 is in the range of 500 angstroms to 5000 angstroms. The thickness of the initial second isolation layer 104 is in the range of 500 angstroms to 5000 angstroms.

[0052] The first isolation layer 109 is used to isolate a channel layer 115 formed subsequently and located between adjacent source and drain stacks.

[0053] Referring to Figures 4 to 10, a gate structure 117 is formed that penetrates the source-drain layer structure in a direction perpendicular to the substrate surface, and a channel layer 115 is located between the gate structure 117 and any source-drain stack. In the direction toward the gate structure 117, the end of the first isolation layer 109 protrudes from the end of the source-drain stack to achieve electrical insulation between adjacent channel layers 115.

[0054] In some embodiments, the steps of forming a gate structure 117 penetrating the source-drain layer structure in a direction perpendicular to the surface of the substrate 101 and a channel layer 115 located between the gate structure 117 and any source-drain stack include: as shown in FIG4 , forming a first opening 108 penetrating the source-drain layer structure in a direction perpendicular to the surface of the substrate 101, the sidewalls of the first opening 108 exposing the source-drain stack and the first isolation layer 109; as shown in FIG5 to FIG6 , etching the source-drain stack exposed by the sidewalls of the first opening 108 to form a channel groove 113 on the sidewalls of the first opening 108; as shown in FIG7 and FIG8 , forming a channel layer 115 in the channel groove 113; as shown in FIG9 and FIG10 , forming the gate structure 117 in the first opening 108 (as shown in FIG6 ) in which the channel layer 115 is formed on the sidewalls.

[0055] It should be noted that, in this embodiment, after the initial source-drain layer structure is formed on the barrier layer 102, the further step includes: forming an initial buffer layer 106 and an initial top isolation layer 107 on the initial source-drain layer structure; therefore, as shown in FIG4 , in the step of forming the first opening 108, the first opening 108 also penetrates the initial top isolation layer 107 and the initial buffer layer 106 in a direction perpendicular to the surface of the substrate 101.

[0056] The initial buffer layer 106 provides a structural basis for forming a buffer layer 118. The initial top isolation layer 107 provides a structural basis for forming a top isolation layer 119. The material of the initial buffer layer 106 includes silicon oxide; the material of the initial top isolation layer 107 includes silicon nitride.

[0057] The step of forming the first opening 108 includes: forming a first mask layer (not shown) on the initial top isolation layer 107, wherein the first mask layer exposes a portion of the surface of the initial top isolation layer 107; and etching the initial source and drain layer structure, the initial buffer layer 106, and the initial top isolation layer 107 using the first mask layer as a mask to form the first opening 108. The first opening 108 provides a structural foundation for the subsequent formation of the gate structure 117. The first mask layer defines the shape and position of the first opening 108. The etching method for etching the first opening 108 is anisotropic etching, which includes dry etching.

[0058] The barrier layer 102 serves as an etching barrier during the process of etching to form the first opening 108 , thereby preventing the substrate 101 from being etched and causing leakage in the memory structure.

[0059] In some embodiments, the step of etching the source / drain stack exposed by the sidewalls of the first opening 108 to form a channel groove 113 on the sidewalls of the first opening 108 includes: as shown in FIG5 , etching the second isolation layer 111 exposed by the sidewalls of the first opening 108 to form an initial channel groove 112 on the sidewalls of the first opening 108; as shown in FIG6 , etching the source / drain doped layer 110 exposed by the sidewalls of the first opening 108 to form a channel groove 113.

[0060] The etching method for etching the second isolation layer 111 exposed on the sidewall of the first opening 108 is isotropic etching. During the etching process of the second isolation layer 111, a portion of the barrier layer 102 is also consumed.

[0061] The etching method for etching the sidewall of the first opening 108 to expose the source / drain doped layer 110 is isotropic etching.

[0062] Specifically, in this embodiment, the steps of forming the source-drain layer structure include: etching the second isolation layer 111 exposed by the sidewall of the first opening 108 to form an initial channel groove 112 on the sidewall of the first opening 108; after etching the second isolation layer 111, etching the source-drain doped layer 110 exposed by the sidewall of the first opening 108 to form a channel groove 113.

[0063] In other embodiments, the step of forming the source / drain layer structure further includes: etching the source / drain doped layer 110 exposed by the sidewalls of the first opening 108 to form an initial channel groove 112 on the sidewalls of the first opening 108; after etching the source / drain doped layer 110, etching the second isolation layer 111 exposed by the sidewalls of the first opening 108 to form a channel groove 113.

[0064] The step of forming the channel layer 115 in the channel groove 113 includes: as shown in Figure 7, forming an initial channel layer 114 in the channel groove 113 and in the first opening 108; as shown in Figure 8, etching the initial channel layer 114 to expose the end surface of the first isolation layer 109, retaining the initial channel layer 114 in the channel groove 113 to form the channel layer 115.

[0065] The step of forming the gate structure 117 in the first opening 108 (as shown in FIG6 ) of the channel layer 115 formed in the sidewall includes: as shown in FIG9 , forming an initial gate structure 116 in the first opening 108 of the channel layer 115 formed in the sidewall; as shown in FIG10 , flattening the initial gate structure 116 and forming the gate structure 117 in the first opening 108 of the channel layer 115 formed in the sidewall.

[0066] The memory structure comprising source and drain stacks stacked in sequence in a direction perpendicular to the surface of the substrate 101, a gate structure 117 penetrating the source and drain layer structure in a direction perpendicular to the surface of the substrate 101, and a channel layer 115 located between the sidewall of the gate structure 117 and any source and drain stack increases the storage capacity of the memory structure, and the area occupied by the source and drain layer structure in a direction parallel to the surface of the substrate 101 is only the area occupied by one source and drain stack in a direction parallel to the surface of the substrate 101. The memory structure does not increase the area in a direction parallel to the surface of the substrate 101 when increasing the storage capacity, thereby improving the storage density of the memory.

[0067] The initial channel layer 114 fills the channel groove 113 and the first opening 108. The material of the initial channel layer 114 includes a semiconductor material, such as silicon and silicon carbide. Specifically, in this embodiment, the material of the initial channel layer 114 is polysilicon. The method for forming the initial channel layer 114 includes isotropic deposition.

[0068] The step of etching the initial channel layer 114 to form the channel layer 115 includes: using the initial top isolation layer 107 as a mask, etching the initial channel layer 114 until the end surface of the first isolation layer 109 is exposed, and retaining the initial channel layer 114 in the channel groove 113 (as shown in Figure 6); doping the initial channel layer 114 in the channel groove 113 (as shown in Figure 6) to form the channel layer 115.

[0069] The method of etching the initial channel layer 114 includes anisotropic etching. The material of the channel layer 115 includes a semiconductor material, such as silicon and silicon carbide. Specifically, in this embodiment, the material of the channel layer 115 is P-type heavily doped polysilicon.

[0070] The initial gate structure 116 provides a structural basis for forming the gate structure 117. The initial gate structure 116 includes an initial dielectric structure and an initial gate layer (not shown) located on the initial dielectric structure (not shown). The initial dielectric structure is used to isolate the initial gate layer and the channel layer 115. The initial dielectric structure includes a first initial dielectric layer, a second initial dielectric layer located on the first initial dielectric layer, and a third initial dielectric layer located on the second initial dielectric layer. The material of the first initial dielectric layer includes silicon oxide; the material of the second initial dielectric layer includes silicon nitride; and the material of the third initial dielectric layer includes silicon oxide. The material of the initial gate layer includes heavily doped polysilicon and metal, and the metal includes aluminum and tungsten. Specifically, in this embodiment, the material of the initial gate layer is N-type heavily doped polysilicon.

[0071] The gate structure 117 includes a dielectric structure (not shown) and a gate layer (not shown) located on the dielectric structure. The dielectric structure is used to isolate the gate layer from the channel layer 115. The dielectric structure includes a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer. The material of the first dielectric layer includes silicon oxide; the material of the second dielectric layer includes silicon nitride; and the material of the third dielectric layer includes silicon oxide. The material of the gate layer includes heavily doped polysilicon and metal, wherein the metal includes aluminum and tungsten. Specifically, in this embodiment, the material of the gate layer is N-type heavily doped polysilicon.

[0072] In the process of performing a planarization process (Chemical Mechanical Polishing, CMP) on the initial gate structure 116 and forming the gate structure 117 in the first opening 108 of the channel layer 115 formed in the sidewall, the planarization process includes: mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing. Specifically, in this embodiment, the planarization process is a chemical mechanical polishing process. Different from traditional purely mechanical or purely chemical polishing methods, the chemical mechanical polishing process avoids the shortcomings of surface damage caused by pure mechanical polishing and slow polishing speed, poor surface flatness and polishing consistency caused by pure chemical polishing through the combined action of chemistry and mechanics. Chemical mechanical polishing is widely used for high-planarization polishing of various materials at the nanoscale.

[0073] After the planarization treatment, the step of forming a gate structure 117 that penetrates the source-drain layer structure in a direction perpendicular to the surface of the substrate 101 and a channel layer 115 located between the gate structure 117 and any source-drain stack also includes: performing back etching treatment on the gate structure 117 to remove the material of the gate structure 117 located on the initial top isolation layer 107; the initial top isolation layer 107 serves as an etch stop layer for the back etching treatment.

[0074] Please refer to Figure 11. The step of forming a source-drain layer structure on the barrier layer 102 also includes: after forming a gate structure 117 that penetrates the source-drain layer structure in a direction perpendicular to the surface of the substrate 101 and a channel layer 115 located between the gate structure 117 and any source-drain stack, the initial source-drain layer structure is subjected to multiple connection etching processes to expose the connection area of ​​any source-drain doping layer 110 and form the source-drain layer structure.

[0075] The connection region provides a structural basis for forming the first conductive plug 121 .

[0076] The connection etching process includes: etching a portion of the upper layer's source / drain doping structure to expose a connection region of any source / drain doping layer 110; after exposing the connection region, filling the connection region with a protective material. The upper layer's partial source / drain doping structure refers to the portion of the source / drain doping structure located on the side of the exposed source / drain doping layer away from the substrate 101.

[0077] The etching method includes dry etching.

[0078] Specifically, in this embodiment, the formation method further includes etching the initial top isolation layer 107 and the initial buffer layer 106 to expose the connection region of the source / drain doped layer 110 closest to the buffer layer 118 and the top isolation layer 119. The initial top isolation layer 107 remaining after etching and the initial buffer layer 106 remaining after etching form the top isolation layer 119 and the buffer layer 118, respectively.

[0079] It should be noted that, in some embodiments, the formation method further includes: after exposing the connection area of ​​the source-drain doped layer 110 closest to the buffer layer 118 and the top isolation layer 119, removing the protective material to expose the connection area of ​​all source-drain stacks.

[0080] 12 , the side of the source / drain layer structure away from the gate structure 117 is stepped. The distance between the side of the source / drain doped layers of at least three source / drain stacks away from the gate structure 117 and the gate structure 117 decreases layer by layer.

[0081] 12 , after the connection region is exposed and the source / drain structure is formed, an interlayer dielectric layer 120 is formed on the barrier layer 102 to cover the source / drain structure, the buffer layer 118 and the top isolation layer 119 .

[0082] The interlayer dielectric layer 120 is made of silicon oxide. The steps of forming the interlayer dielectric layer 120 include: depositing an initial interlayer dielectric layer (not shown) on the barrier layer 102 to cover the source / drain structure, the buffer layer 118, and the top isolation layer 119; and planarizing the initial interlayer dielectric layer to form the interlayer dielectric layer 120.

[0083] After forming the interlayer dielectric layer 120, the formation method further includes forming an interconnect structure within the interlayer dielectric layer 120. The steps of forming the interconnect structure within the interlayer dielectric layer 120 include forming a first conductive plug 121 within the interlayer dielectric layer 120, the first conductive plug 121 being electrically connected to the connection region of the source-drain doped layer 110; forming a second conductive plug 122 within the interlayer dielectric layer 120, the second conductive plug 122 being electrically connected to the gate structure 117; and forming a metal layer 123 on the interlayer dielectric layer 120, the metal layer 123 being electrically connected to one of the first conductive plug 121 and the second conductive plug 122.

[0084] The steps of forming the first conductive plug 121 and the second conductive plug 122 include: forming a second mask layer (not shown) on the interlayer dielectric layer 120, wherein the second mask layer exposes a portion of the surface of the interlayer dielectric layer 120; etching the interlayer dielectric layer 120 using the second mask layer as a mask to form a second opening (not shown), wherein the second opening exposes a portion of the surface of the connection region and a portion of the surface of the gate structure 117; forming a transition conductive layer (not shown) on the surface of the second opening; annealing the transition conductive layer; and After the treatment, a first conductive plug 121 and a second conductive plug 122 filling the second opening are formed in the second opening with a transition conductive layer formed on the surface, the first conductive plug 121 is electrically connected to the connection area of ​​the source-drain doped layer 110, and the second conductive plug 122 is electrically connected to the gate structure 117; after the first conductive plug 121 and the second conductive plug 122 are formed, the first conductive plug 121 and the second conductive plug 122 are planarized to remove excess material of the first conductive plug 121 and the second conductive plug 122.

[0085] The transition conductive layer is made of titanium and titanium nitride. The first conductive plug 121 is made of tungsten. The second conductive plug 122 is made of tungsten. The metal layer 123 is made of aluminum and copper.

[0086] The purpose of performing planarization processing on the first conductive plug 121 and the second conductive plug 122 to remove excess material of the first conductive plug 121 and the second conductive plug 122 is to prevent the excess material of the first conductive plug 121 and the second conductive plug 122 from causing a short circuit between different first conductive plugs 121.

[0087] Correspondingly, an embodiment of the present invention further provides a memory structure, please refer to Figure 12, including: a substrate 101; a barrier layer 102 located on the substrate 101; a source-drain layer structure located on the barrier layer 102, the source-drain layer structure including: a source-drain stack and a first isolation layer 109, at least three of the source-drain stacks are stacked in sequence along a direction perpendicular to the surface of the substrate 101, the source-drain stack includes two source-drain doped layers 110 and a second isolation layer 111 located between the source-drain doped layers 110, the first isolation layer 109 is located between two adjacent source-drain stacks; a gate structure 117 penetrating the source-drain layer structure along a direction perpendicular to the surface of the substrate 101; a channel layer 115 located between the sidewall of the gate structure 117 and any source-drain stack, and an end of the first isolation layer 109 protrudes from an end of the source-drain stack in a direction toward the gate structure 117 to achieve electrical insulation between adjacent channel layers 115.

[0088] The memory structure of the source-drain stacks stacked in sequence in a direction perpendicular to the surface of the substrate 101, the gate structure 117 penetrating the source-drain layer structure in a direction perpendicular to the surface of the substrate 101, and the channel layer 115 located between the side wall of the gate structure 117 and any source-drain stack described in the technical solution of the present invention increases the storage capacity of the memory structure, and the area occupied by the source-drain layer structure in the direction parallel to the surface of the substrate 101 is only the area occupied by one source-drain stack in the direction parallel to the surface of the substrate 101. The memory structure does not increase the area in the direction parallel to the surface of the substrate 101 when increasing the storage capacity, thereby improving the storage density of the memory.

[0089] The memory structure includes: a substrate 101 .

[0090] The substrate 101 may be made of silicon, silicon carbide, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0091] The memory structure includes a barrier layer 102 located on the substrate 101 .

[0092] The barrier layer 102 has a thickness ranging from 1000 angstroms to 20000 angstroms. The barrier layer 102 is made of silicon oxide.

[0093] The barrier layer 102 also extends between the gate structure 117 and the substrate 101 .

[0094] The memory structure includes: a source-drain layer structure located on the barrier layer 102, the source-drain layer structure including: a source-drain stack and a first isolation layer 109, at least three of the source-drain stacks are stacked in sequence in a direction perpendicular to the surface of the substrate 101, the source-drain stack includes two source-drain doped layers 110 and a second isolation layer 111 located between the source-drain doped layers 110, and the first isolation layer 109 is located between two adjacent source-drain stacks.

[0095] The thickness of the source / drain doped layer 110 ranges from 500 angstroms to 1000 angstroms. The material of the source / drain doped layer 110 includes heavily doped polysilicon and metal, wherein the metal includes aluminum and tungsten. Specifically, in this embodiment, the material of the source / drain doped layer 110 is N-type heavily doped polysilicon.

[0096] The material of the first isolation layer 109 includes silicon nitride.

[0097] The thickness of the second isolation layer 111 ranges from 500 angstroms to 5000 angstroms. The material of the second isolation layer 111 includes silicon oxide.

[0098] The memory structure further includes a buffer layer 118 located on the source / drain layer structure and a top isolation layer 119 located on the buffer layer 118 .

[0099] The material of the buffer layer 118 includes silicon oxide; the material of the top isolation layer 119 includes silicon nitride.

[0100] The memory structure includes a gate structure 117 penetrating the source-drain layer structure in a direction perpendicular to the surface of the substrate 101 .

[0101] The gate structure 117 extends into the barrier layer 102 in a direction toward the substrate 101 .

[0102] The gate structure 117 includes a dielectric structure and a gate layer located on the dielectric structure. The dielectric structure is used to isolate the gate layer from the channel layer 115. The dielectric structure includes a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer located on the second dielectric layer. The first dielectric layer is made of silicon oxide; the second dielectric layer is made of silicon nitride; and the third dielectric layer is made of silicon oxide. The gate layer is made of heavily doped polysilicon and a metal, wherein the metal includes aluminum and tungsten. Specifically, in this embodiment, the gate layer is made of N-type heavily doped polysilicon.

[0103] The surface of the source / drain doped layer 110 facing away from the substrate 101 has a connection region, which is exposed to a portion of the upper source / drain doped layer 110. The connection region is located at one end of the source / drain doped layer 110 away from the gate structure 117.

[0104] Specifically, in this embodiment, the connection region of the source / drain doped layer 110 closest to the buffer layer 118 and the top isolation layer 119 is exposed to the buffer layer 118 and the top isolation layer 119 .

[0105] The memory structure further includes an interlayer dielectric layer 120 located on the barrier layer 102 and covering the source / drain layer structure, the buffer layer 118 and the top isolation layer 119 .

[0106] The material of the interlayer dielectric layer 120 includes silicon oxide.

[0107] The memory structure further includes an interconnect structure within the interlayer dielectric layer 120. The interconnect structure includes a first conductive plug 121 and a second conductive plug 122 within the interlayer dielectric layer 120, and a metal layer 123 on the interlayer dielectric layer 120. The first conductive plug 121 electrically connects the connection region and the metal layer 123; the second conductive plug 122 electrically connects the gate structure 117 and the metal layer 123. Materials for the metal layer 123 include aluminum and copper.

[0108] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A memory structure, characterized in that: include: substrate; a barrier layer on the substrate; a source-drain layer structure located on the barrier layer, the source-drain layer structure comprising: a source-drain stack and a first isolation layer, wherein at least three source-drain stacks are stacked in sequence in a direction perpendicular to the substrate surface, the source-drain stack comprising two source-drain doped layers and a second isolation layer located between the source-drain doped layers, and the first isolation layer is located between two adjacent source-drain stacks; A gate structure extending vertically through the source-drain layer structure; The channel layer is located between the sidewall of the gate structure and any source-drain stack, and along the direction toward the gate structure, the end of the first isolation layer protrudes beyond the end of the source-drain stack to achieve electrical insulation between adjacent channel layers.

2. The memory structure according to claim 1, wherein: A surface of the source / drain doped layer facing away from the substrate has a connection region, and the connection region is exposed to a portion of the upper source / drain doped layer.

3. The memory structure according to claim 2, wherein: The connection region is located at an end of the source / drain doped layer away from the gate structure.

4. The memory structure according to claim 2, wherein: Also includes: A buffer layer is located on the source / drain layer structure and a top isolation layer is located on the buffer layer; a connection region of the source / drain doping layer closest to the buffer layer and the top isolation layer is exposed to the buffer layer and the top isolation layer.

5. The memory structure according to claim 4, wherein: Also includes: An interlayer dielectric layer is located on the barrier layer and covers the source-drain layer structure, the buffer layer and the top isolation layer.

6. The memory structure according to claim 5, wherein: Also includes: An interconnect structure is located in the interlayer dielectric layer.

7. The memory structure according to claim 6, wherein: The interconnect structure includes: a first conductive plug and a second conductive plug located in the interlayer dielectric layer and a metal layer located on the interlayer dielectric layer, the first conductive plug electrically connecting the connection area and the metal layer; the second conductive plug electrically connecting the gate structure and the metal layer.

8. The memory structure according to claim 1, wherein: The barrier layer also extends between the gate structure and the substrate.

9. The memory structure according to claim 8, wherein: The gate structure extends into the barrier layer in a direction toward the substrate.

10. A method for forming a memory structure, characterized in that: include: providing a substrate; forming a barrier layer on the substrate; forming a source-drain layer structure on the barrier layer, the source-drain layer structure comprising: a source-drain stack and a first isolation layer, wherein at least three source-drain stacks are stacked in sequence in a direction perpendicular to the substrate surface, the source-drain stack comprising two source-drain doped layers and a second isolation layer located between the source-drain doped layers, and the first isolation layer is located between two adjacent source-drain stacks; A gate structure is formed that penetrates the source-drain layer structure in a direction perpendicular to the substrate surface, and a channel layer is located between the gate structure and any source-drain stack. In the direction toward the gate structure, the end of the first isolation layer protrudes from the end of the source-drain stack to achieve electrical insulation between adjacent channel layers.

11. The method for forming a memory structure according to claim 10, wherein: The step of forming a gate structure penetrating the source-drain layer structure in a direction perpendicular to the substrate surface and a channel layer located between the gate structure and any source-drain stack comprises: forming a first opening penetrating the source / drain layer structure in a direction perpendicular to the substrate surface, wherein a sidewall of the first opening exposes the source / drain stack and the first isolation layer; Etching the source-drain stack exposed by the sidewall of the first opening to form a channel groove on the sidewall of the first opening; forming a channel layer in the channel groove; The gate structure is formed in the first opening where the channel layer is formed in the sidewall.

12. The method for forming a memory structure according to claim 11, wherein: The step of etching the source / drain stack exposed by the sidewall of the first opening to form a channel groove on the sidewall of the first opening comprises: Etching the second isolation layer exposed by the sidewall of the first opening to form an initial channel groove on the sidewall of the first opening; The source / drain doped layer exposed by the sidewall of the first opening is etched to form the channel groove.

13. The method for forming a memory structure according to claim 11, wherein: The step of forming a channel layer in the channel groove includes: forming an initial channel layer; The initial channel layer is etched to expose an end surface of the first isolation layer, and the initial channel layer in the channel groove is retained to form the channel layer.

14. The method for forming a memory structure according to claim 10, wherein: Forming a source-drain layer structure on the barrier layer includes: After forming a barrier layer on the substrate, an initial source-drain layer structure is formed on the barrier layer, wherein the initial source-drain layer structure comprises: an initial source-drain stack and an initial first isolation layer, wherein at least three initial source-drain stacks are sequentially stacked in a direction perpendicular to the substrate surface, the initial source-drain stack comprises two initial source-drain doped layers and an initial second isolation layer located between the initial source-drain doped layers, and the initial first isolation layer is located between two adjacent source-drain doped layers. Between the initial source and drain stacks; After forming a gate structure penetrating the source-drain layer structure in a direction perpendicular to the substrate surface and a channel layer located between the gate structure and any source-drain stack, the initial source-drain layer structure is subjected to multiple connection etching processes to expose a connection region of any source-drain doped layer to form the source-drain layer structure; The connection etching process includes: etching part of the upper source-drain doping structure to expose the connection area of ​​any source-drain doping layer; after exposing the connection area, filling with a protective material, and the protective material covers all exposed connection areas of the source-drain doping layer.

15. The method for forming a memory structure according to claim 14, wherein: Also includes: After forming an initial source-drain layer structure on the barrier layer, forming an initial buffer layer and an initial top isolation layer on the initial source-drain layer structure; The initial top isolation layer and the initial buffer layer are etched to expose a connection region of the source-drain stack closest to the buffer layer and the top isolation layer.

16. The method for forming a memory structure according to claim 15, wherein: Also includes: An interlayer dielectric layer is formed on the barrier layer and covers the source-drain layer structure, the buffer layer and the top isolation layer.

17. The method for forming a memory structure according to claim 16, wherein: Also includes: An interconnection structure is formed in the interlayer dielectric layer.

18. The method for forming a memory structure according to claim 17, wherein: The step of forming an interconnect structure located in the interlayer dielectric layer includes: forming a first conductive plug in the interlayer dielectric layer, wherein the first conductive plug is electrically connected to the connection region of the source-drain doped layer; A second conductive plug is formed in the interlayer dielectric layer. electrically connected to the gate structure; A metal layer is formed on the interlayer dielectric layer, wherein the metal layer is electrically connected to one of the first conductive plug and the second conductive plug.

19. A storage array, characterized in that: include: The memory structure according to any one of claims 1 to 9.

20. A method for writing into a memory, characterized in that: The memory comprises the memory array of claim 19.

21. A method for reading a memory, characterized in that: The memory comprises the memory array of claim 19.

22. A method for erasing a memory, characterized in that: The memory comprises the memory array of claim 19.

Images