Semiconductor device and preparation method therefor, and chip packaging structure and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a semiconductor device and a preparation method therefor, and a chip packaging structure and an electronic device, which are used for solving the problem of on-resistance being increased due to an increase in the voltage withstand capability of the semiconductor device. The semiconductor device comprises a substrate, and a source doped region, a drain doped region and a drift region, which are formed in the substrate. An isolation region is further provided in the substrate, a conductive layer is provided in the isolation region, and the conductive layer is electrically connected to the source doped region. An electric field region is provided at a lateral side of the drift region, the type of doped ions in the electric field region is the same as the type of doped ions in the drift region, and the ion concentration of the electric field region is greater than the ion concentration of the drift region. The semiconductor device is applied to an electronic device.

Description

Semiconductor device and manufacturing method thereof, chip packaging structure, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 22, 2024, with application number 202410208314.4 and invention name “Semiconductor device and its preparation method, chip packaging structure, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a chip packaging structure, and an electronic device. Background Art

[0003] Many functions in electronic devices rely on semiconductor devices, such as power MOS field-effect transistors (MOSFETs), which can be used for battery charging in electronic devices. However, to improve the voltage resistance of semiconductor devices, it is necessary to reduce the doping concentration of the drift region of the semiconductor device. This increases the on-resistance (Rdson) of the semiconductor device, affecting its performance. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor device and a method for manufacturing the same, a chip packaging structure, and an electronic device, which are used to solve the problem that the voltage resistance of the semiconductor device is improved, resulting in an increase in the on-resistance.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a semiconductor device is provided. The semiconductor device includes a substrate, a source doped region, a drain doped region, and a drift region formed within the substrate. The substrate further includes an isolation region, wherein a conductive layer is disposed within the isolation region and electrically connected to the source doped region. An electric field region is formed on a side of the drift region. The electric field region is doped with the same ion type as the drift region, and the ion concentration in the electric field region is the same as the ion concentration in the drift region.

[0007] The semiconductor device provided in the first aspect of the present application has an electric field region formed within the drift region. The ion doping concentration of the electric field region is greater than the ion doping concentration of the drift region, thereby facilitating an increase in the ion doping concentration of the entire drift region (i.e., the average concentration of the drift region and the electric field region), thereby facilitating a reduction in the on-resistance of the semiconductor device. Furthermore, the presence of a conductive layer within the isolation region ensures that the semiconductor device's voltage withstand capability is not reduced while reducing the on-resistance. This means that while improving the performance of the semiconductor device, the semiconductor device is also able to withstand higher voltages, thereby preventing leakage in the electronic device and mitigating safety risks.

[0008] In one possible implementation of the first aspect of the present application, a channel region is further formed within the substrate, and the channel region is doped with a different ion type than the drift region. In this structure, a unidirectionally conducting diode structure can be formed between the channel region and the drift region, which helps reduce the risk of leakage when the semiconductor device is turned off.

[0009] In one possible implementation of the first aspect of the present application, the conductive layer is electrically connected to the source doped region via the channel region. With this structure, the source electrode can be positioned more flexibly, i.e., the source doped region is electrically connected to the channel region, and the channel region is electrically connected to the conductive layer. This eliminates restrictions on the specific location of the source electrode, thus reducing manufacturing complexity.

[0010] In one possible implementation of the first aspect of the present application, a drift region and an isolation region are disposed on the same side of the channel region, and multiple drift regions are provided. A drift region is disposed between two adjacent isolation regions. A conductive layer is disposed within at least some of the multiple isolation regions, and an electric field region is disposed within the drift region adjacent to the isolation region having the conductive layer. With this structure, the semiconductor device is an integrated structure of multiple MOS transistors, and at least some of the MOS transistors have improved overall performance and withstand voltage capability through the conductive layer and the electric field region. Therefore, the specific MOS transistors to be provided with the conductive layer and the electric field region can be determined based on the actual application scenario, making the application more flexible and diverse.

[0011] In one possible implementation of the first aspect of the present application, a conductive layer is provided within each isolation region, and each drift region has an electric field region on a side adjacent to the adjacent isolation region. This structure improves the voltage withstand capability of each MOS transistor, further enhancing the overall performance of the semiconductor device.

[0012] In a possible implementation of the first aspect of the present application, the multiple drift regions include a first drift region and a second drift region, the multiple isolation regions include a first isolation region, a second isolation region, and a third isolation region, the first drift region is located between the first isolation region and the second isolation region, and the second drift region is located between the second isolation region and the third isolation region. Under this structure, the semiconductor device forms a dual MOS tube device, which can be applied to wireless charging and wired charging scenarios of electronic devices. This can reduce the risk of leakage during charging. For example, during wireless charging, the risk of the wired charging interface being charged can be reduced, which helps to reduce safety hazards.

[0013] In one possible implementation of the first aspect of the present application, the drain doping region includes a first drain doping region and a second drain doping region, the first drain doping region being formed within the first drift region, and the second drain doping region being formed within the second drift region. The first drain doping region and the second drain doping region can both be led out through contact holes to form two drains, respectively. The two drains can be electrically connected to a wireless charging coil and a wired charging interface, respectively, to control the two aforementioned charging modes.

[0014] In a possible implementation of the first aspect of the present application, the drain doping region is formed on a side of the drift region away from the channel region.

[0015] In a possible implementation of the first aspect of the present application, the ion doping type of the electric field region and the drift region is N-type ion doping, and the ion doping type of the channel region is P-type ion doping, that is, the semiconductor device forms an N-type MOS transistor device.

[0016] In a possible implementation of the first aspect of the present application, the semiconductor device further includes a gate doping region, which is disposed in the isolation region and electrically isolated from the conductive layer.

[0017] In a second aspect, a method for fabricating a semiconductor device is provided. The method includes forming a substrate, the substrate including a first surface and a second surface that are opposed to each other. A trench structure is formed on the first surface. A drift region is formed on a side of the substrate that is close to the first surface, with the trench structure located within the drift region. A dielectric layer is formed on a side of the drift region that is away from the second surface. An electric field region is formed on a side of the drift region, the electric field region being doped with the same ion type as the drift region, and the ion concentration in the electric field region being the same as the ion concentration in the drift region. A conductive layer is formed within the trench structure.

[0018] The second aspect of the present application provides a fabrication method that, by providing an electric field region within the drift region and forming a conductive layer within the trench structure, increases the overall ion doping concentration within the drift region. The conductive layer also enhances depletion in the drift region, thereby ensuring that the withstand voltage capability of the semiconductor device is not compromised, thereby improving the overall performance of the semiconductor device.

[0019] In one possible implementation of the second aspect of the present application, before forming the drift region on the side of the substrate proximate to the first surface, the fabrication method further includes: forming a channel region on the side of the substrate proximate to the first surface, wherein the trench structure is located within the channel region; and the drift region is located on the side of the trench region distal to the second surface. In this manner, a unidirectionally conducting diode structure can be formed between the channel region and the drift region, which helps reduce leakage risk when the semiconductor device is turned off.

[0020] In a possible implementation of the second aspect of the present application, after forming a channel region on a side of the substrate close to the first surface, the manufacturing method further includes: forming a gate doping region in the trench structure.

[0021] In a possible implementation of the second aspect of the present application, after forming the conductive layer in the trench structure, the manufacturing method further includes: forming a drain doping region in the drift region.

[0022] In a third aspect, a chip packaging structure is provided, which includes a packaging substrate and a semiconductor device as described in any of the above technical solutions, wherein the semiconductor device is electrically connected to the packaging substrate.

[0023] The chip packaging structure provided in the third aspect of the present application, since it includes the semiconductor device described in any of the above technical solutions, can solve the same technical problems and achieve the same technical effects.

[0024] In a fourth aspect, an electronic device is provided, which includes a circuit board and a chip packaging structure as described in the above technical solution, wherein the chip packaging structure is electrically connected to the circuit board.

[0025] The electronic device provided in the fourth aspect of the present application, because it includes the chip packaging structure described in the above technical solution, can solve the same technical problems and achieve the same technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0027] FIG2 is an exploded view of an electronic device provided in an embodiment of the present application;

[0028] FIG3 is a structural diagram of a chip packaging structure provided in an embodiment of the present application;

[0029] FIG4 is a structural diagram of a semiconductor device provided in an embodiment of the present application;

[0030] FIG5 is a structural diagram of another semiconductor device provided in an embodiment of the present application;

[0031] FIG6 is a structural diagram of another semiconductor device provided in an embodiment of the present application;

[0032] FIG7 is a structural diagram of another semiconductor device provided in an embodiment of the present application;

[0033] FIG8 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0034] FIG9 is a structural diagram of a substrate provided in an embodiment of the present application;

[0035] FIG10 is a structural diagram of a groove structure provided on the substrate provided in FIG9 ;

[0036] FIG11 is a structural diagram of a channel region formed in the substrate provided in FIG10 ;

[0037] FIG12 is a structural diagram of a gate doping region formed in a trench structure on the substrate provided in FIG11;

[0038] FIG13 is a structural diagram showing a drift region formed on one side of the channel region provided in FIG12;

[0039] FIG14 is a structural diagram of a dielectric layer formed on the surface of the drift region provided in FIG13;

[0040] FIG15 is a structural diagram of an electric field region formed in the drift region provided in FIG14;

[0041] FIG16 is a structural diagram of a conductive layer provided in the trench structure provided in FIG15;

[0042] FIG17 is a structural diagram showing a drain doping region formed in the drift region provided in FIG16 .

[0043] Reference numerals: 10 - electronic device; 100 - display module; 110 - light-transmitting cover plate; 120 - display screen; 200 - housing; 210 - back cover; 220 - frame; 230 - middle plate; 300 - circuit board; 400 - chip packaging structure; 410 - packaging substrate; 420 - semiconductor device; 421 - substrate; 421a - first surface; 421b - second surface; 422 - drain doping region; 422a - first drain doping region; 422b -Second drain doping region; 423-channel region; 424-drift region; 424a-first drift region; 424b-second drift region; 425-isolation region; 425a-first isolation region; 425b-second isolation region; 425c-third isolation region; 425d-trench structure; 426-gate doping region; 427-conductive layer; 428-electric field region; 429-dielectric layer; 500-hierarchical structure; 510-contact hole; 520-metal connection point. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0045] In the following, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features.

[0046] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" is two or more. In the embodiments of the present application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more important than other embodiments or design. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a concrete way.

[0047] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0048] An embodiment of the present application provides an electronic device. Specifically, the electronic device may be a portable electronic device or other type of electronic device. For example, the electronic device may be a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a monitor, a camera, a personal computer, a notebook computer, a wearable device, etc. For ease of description, the following examples are all based on the example of a mobile phone as the electronic device.

[0049] Please refer to Figures 1 and 2. Figure 1 is a structural diagram of an electronic device 10 provided in an embodiment of the present application, and Figure 2 is an exploded view of an electronic device 10 provided in an embodiment of the present application. Figures 1 and 2 only schematically illustrate some components included in the electronic device 10, and the actual shape, size, position, and structure of these components are not limited by Figures 1 and 2.

[0050] As can be seen from the above, in this embodiment, the electronic device 10 is a mobile phone and can be in a substantially rectangular plate-shaped structure. The electronic device 10 can include a display module 100 , a housing 200 , a circuit board 300 , and a chip packaging structure 400 .

[0051] The above-mentioned display module 100 is used to display images, videos, etc. The display module 100 may include a translucent cover plate 110 and a display screen 120 (English name: panel, also called a display panel), and the translucent cover plate 110 and the display screen 120 are stacked. The material of the translucent cover plate 110 includes but is not limited to glass. For example, the translucent cover plate 110 can adopt an ordinary translucent cover plate 110 to protect the display screen 120 to prevent the display screen 120 from being damaged by external force, and can play a dust-proof role. Alternatively, the translucent cover plate 110 can also adopt a translucent cover plate 110 with a touch function, so that the electronic device 10 has a touch function, which makes it more convenient for users to use. Therefore, the present application does not specifically limit the specific material of the translucent cover plate 110.

[0052] Furthermore, the display screen 120 may be a flexible display screen 120 or a rigid display screen 120. For example, the display screen 120 may be an organic light-emitting diode (OLED) display screen 120, an active-matrix organic light-emitting diode (AMOLED) display screen 120, a mini organic light-emitting diode (OLED) display screen 120, a micro organic light-emitting diode (OLED) display screen 120, a micro organic light-emitting diode (OLED) display screen 120, a quantum dot light-emitting diode (QLED) display screen 120, or a liquid crystal display (LCD) display screen 120.

[0053] The housing 200 is used to protect the electronic components within the electronic device 10. The housing 200 may include a back cover 210 and a frame 220. The back cover 210 is located on the side of the display screen 120 away from the transparent cover plate 110 and is stacked with the transparent cover plate 110 and the display screen 120. The frame 220 is located between the transparent cover plate 110 and the back cover 210. The frame 220 is fixed to the back cover 210. For example, the frame 220 may be fixed to the back cover 210 by bonding, threading, welding, or snapping. Alternatively, the frame 220 may be integrally formed with the back cover 210, i.e., the frame 220 and the back cover 210 form a single structural unit. The transparent cover plate 110 may be fixed to the frame 220 by gluing, so that the transparent cover plate 110, the back cover 210, and the frame 220 define a housing cavity within the electronic device 10. The circuit board 300 assembly and the electronic components are disposed within this housing cavity.

[0054] In some embodiments, the housing 200 may further include a middle plate 230, which is disposed in the accommodating cavity and is located on the side of the display screen 120 away from the light-transmitting cover plate 110. The middle plate 230 is fixedly connected to the frame 220 to form the middle frame of the electronic device 10. For example, the middle plate 230 and the frame 220 may be fixedly connected by gluing, threading, welding, snapping, etc. Alternatively, the middle plate 230 and the frame 220 may be an integrally molded structure, that is, the middle plate 230 and the frame 220 form a single structural component. The middle plate 230 divides the accommodating cavity into two independent spaces, one of which is located between the light-transmitting cover plate 110 and the middle plate 230, and the display screen 120 is located in this space. The other space is located between the middle plate 230 and the back cover 210, and the circuit board 300 assembly is located in this space.

[0055] The circuit board 300 is used to house the electronic components within the electronic device 10 and to provide electrical connections between the components. The circuit board 300 can be secured to the midplane 230 by gluing, threading, welding, or snapping. Therefore, this application does not impose any particular restrictions on the securing method for the circuit board 300 assembly.

[0056] The chip package structure 400 (also referred to as a chip) is electrically connected to the circuit board 300. Referring to FIG. 3 , FIG. 3 is a structural diagram of the chip package structure 400 provided in an embodiment of the present application. The chip package structure 400 may include a semiconductor device 420 and a package substrate 410, with the semiconductor device 420 electrically connected to the package substrate 410. For example, the semiconductor device 420 may be electrically connected to the package substrate 410 via solder balls, and the package substrate 410 may be electrically connected to the circuit board 300 via solder balls, thereby enabling communication between the semiconductor device 420 and the circuit board 300.

[0057] In some embodiments, please refer to FIG4 , which is a structural diagram of a semiconductor device 420 provided in an embodiment of the present application. The semiconductor device 420 may include a substrate 421, a source doped region (not shown) formed in the substrate 421, a drain doped region 422, a channel region 423, a drift region 424, and an isolation region 425. The isolation region 425 is further provided with a gate doped region 426 and a dielectric layer 429 filled in the isolation region 425. The source doped region is electrically connected to the channel region 423, the drain doped region 422 is provided in the drift region 424, and the source doped region, the drain doped region 422, and the gate doped region 426 can all be led out to metal connection points 520 through contact holes 510 (provided in the hierarchical structure 500) to form a source, a drain, and a gate.

[0058] The semiconductor device 420 is a MOS transistor, and FIG4 shows a dual MOS transistor device. A unidirectionally conducting diode structure is formed between the drift region 424 and the channel region 423. The semiconductor device 420 can be used in various scenarios. Furthermore, the drift region 424 is a high-resistance region where the number of carriers in the PN junction is very small due to the dual effects of drift motion and diffusion. The higher the ion doping concentration in the drift region 424, the lower the on-resistance.

[0059] It should be noted that, in the embodiments of the present invention, the term "doping concentration" may refer to the overall doping concentration or, respectively, to the average doping concentration or the surface charge carrier concentration of a particular semiconductor region or semiconductor segment. For example, if the ion doping concentration of one semiconductor region is higher or lower than the ion doping concentration of another semiconductor region, it may mean that the respective average doping concentrations of the semiconductor regions are different from each other.

[0060] Furthermore, the source doping region is electrically connected to the channel region 423 . The source doping region may be disposed at other locations of the semiconductor device 420 . The cross section shown in the figure does not show the source doping region.

[0061] Exemplarily, in the scenario of battery charging of the electronic device 10, the charging methods of the electronic device 10 include wired charging (electrically connected to one of the two drain doping regions 422 shown in Figure 4) and wireless charging (electrically connected to the other of the two drain doping regions 422 shown in Figure 4). When wireless charging is used to charge the battery of the electronic device 10, the MOS tube device corresponding to the wired charging is in the off state, that is, the voltage applied by wireless charging cannot be transmitted to the drain doping region 422 through the channel region 423 and the drift region 424, thereby avoiding the electronic device 10 from being charged at the wired charging interface during the wireless charging process, thereby reducing safety hazards.

[0062] As the battery capacity of the electronic device 10 continues to increase, and in order to shorten the charging time, the voltage applied during charging also continues to increase. Therefore, the semiconductor device 420 needs to be able to withstand higher voltages, that is, the voltage resistance of the semiconductor device 420 needs to be improved. However, to improve the voltage resistance of the semiconductor device 420, it is necessary to reduce the ion doping concentration of the drift region 424. Reducing the ion doping concentration of the drift region 424 will cause the on-resistance of the semiconductor device 420 to increase, thereby affecting the performance of the semiconductor device 420. If the on-resistance of the semiconductor device 420 is reduced, the ion doping concentration of the drift region 424 needs to be increased, which in turn will reduce the voltage resistance of the semiconductor device 420, posing a safety hazard.

[0063] To solve the above problem, please refer to FIG5 , which is a structural diagram of another semiconductor device 420 provided in an embodiment of the present application. The semiconductor device 420 can be used in the above electronic device 10. The semiconductor device 420 may include the above substrate 421, a source doped region (not shown) formed in the substrate 421, a drain doped region 422, a channel region 423, a drift region 424, and an isolation region 425. A gate doped region 426 is provided in the isolation region 425.

[0064] In addition, the semiconductor device 420 further includes a conductive layer 427 and an electric field region 428. The conductive layer 427 is disposed within the isolation region 425 and is electrically isolated from the gate doping region 426. The conductive layer 427 is electrically connected to the source doping region via the channel region 423. The electric field region 428 is formed on the side of the drift region 424. The ion type doped in the electric field region 428 is the same as that doped in the drift region 424, and the ion doping concentration of the electric field region 428 is greater than the ion doping concentration of the drift region 424.

[0065] In some examples, the ion doping type of the electric field region 428 and the drift region 424 can be N-type ion doping, and the ion doping type of the channel region 423 can be P-type ion doping, so that the semiconductor device 420 forms an N-type MOS transistor. Alternatively, the ion doping type of the electric field region 428 and the drift region 424 can be P-type ion doping, and the ion doping type of the channel region 423 can be N-type ion doping, so that the semiconductor device 420 forms a P-type MOS transistor. Therefore, this application does not impose any particular limitation on this, and the following description will take the semiconductor device 420 as an N-type MOS transistor as an example.

[0066] In this way, since an electric field region 428 is formed in the drift region 424, the ion doping concentration of the electric field region 428 is greater than the ion doping concentration of the drift region 424, which is beneficial to improving the ion doping concentration of the drift region 424 as a whole (that is, the average concentration of the drift region 424 and the electric field region 428), thereby helping to reduce the on-resistance of the semiconductor device 420, that is, helping to improve the performance of the semiconductor device 420.

[0067] In addition, a conductive layer 427 is provided in the isolation region 425, which can reduce the on-resistance of the semiconductor device 420 while ensuring that the voltage resistance of the semiconductor device 420 is not reduced. This can improve the performance of the semiconductor device 420 while ensuring that the semiconductor device 420 can withstand a higher voltage, thereby ensuring that the electronic device 10 will not have leakage, etc., which is beneficial to reducing safety hazards.

[0068] Specifically, when the gate of the semiconductor device 420 is turned off, the drain is connected to high voltage, and a reverse voltage difference is formed between the conductive layer 427 and the drift region 424. The conductive layer 427 will enhance the depletion of the drift region 424. Therefore, while increasing the ion doping concentration of the electric field region 428 (that is, increasing the ion doping concentration of the drift region 424), the breakdown voltage of the semiconductor device 420 is not reduced, that is, the voltage resistance of the semiconductor device 420 is ensured not to be reduced.

[0069] When a high voltage is applied to the gate of the semiconductor device 420 and the semiconductor device 420 is turned on, the total resistance of the drift region 424 can be reduced by increasing the ion doping concentration of the drift region 424, that is, adding an electric field region 428 with a higher ion doping concentration, which is beneficial to reducing the on-resistance of the semiconductor device 420.

[0070] On this basis, please refer to Figure 6, which is a structural diagram of another semiconductor device 420 provided in an embodiment of the present application. The semiconductor device 420 may include multiple drift regions 424 and multiple isolation regions 425, and the multiple drift regions 424 and the multiple isolation regions 425 are all arranged on the same side of the channel region 423, and a drift region 424 is arranged between two adjacent isolation regions 425, that is, the multiple drift regions 424 and the multiple isolation regions 425 are alternately distributed in sequence, and at least part of the multiple isolation regions 425 are provided with a conductive layer 427, and the drift region 424 adjacent to the isolation region 425 provided with the conductive layer 427 has an electric field region 428, and each drift region 424 has the above-mentioned drain doping region 422 on the side away from the channel region 423.

[0071] Under this structure, each of two adjacent isolation regions 425 and the drift region 424 therebetween can form one of the above-mentioned MOS transistors, that is, the semiconductor device 420 includes multiple MOS transistors (the semiconductor device 420 shown in FIG6 includes three MOS transistors), which is conducive to improving the integration of the semiconductor device 420. In addition, at least some of the integrated multiple MOS transistors have improved overall voltage resistance and reduced on-resistance through the conductive layer 427 and the electric field region 428. Therefore, based on the actual application scenario, it can be flexibly decided to set the conductive layer 427 and the electric field region 428 in part of the isolation region 425 and the drift region 424, or to set the conductive layer 427 in each isolation region 425 and each drift region 424 has an electric field region 428 on the side close to the isolation region 425, so as to make the application of the semiconductor device 420 more flexible.

[0072] In some embodiments, refer to FIG. 7 , which illustrates a structure of another semiconductor device 420 according to an embodiment of the present application. The plurality of drift regions 424 may include a first drift region 424a and a second drift region 424b. The plurality of isolation regions 425 include a first isolation region 425a, a second isolation region 425b, and a third isolation region 425c. The first drift region 424a is located between the first isolation region 425a and the second isolation region 425b, and the second drift region 424b is located between the second isolation region 425b and the third isolation region 425c. The conductive layer 427 is disposed within each of the first isolation region 425a, the second isolation region 425b, and the third isolation region 425c, as well as a gate doping region 426.

[0073] The aforementioned drain doping region 422 includes a first drain doping region 422 and a second drain doping region 422. The first drain doping region 422 is formed within the first drift region 424a, and the second drain doping region 422 is formed within the second drift region 424b. Furthermore, both the first drain doping region 422 and the second drain doping region 422 can be connected to metal connection points 520 through contact holes 510, thereby achieving electrical connection to other devices. This means that the semiconductor device 420 forms a dual MOS transistor device, which helps improve the integration of the semiconductor device 420 compared to two independent MOS transistors.

[0074] For example, when the semiconductor device 420 is applied to a battery charging scenario of an electronic device 10, the metal connection point 520 corresponding to the first drain doping region 422 (i.e., the drain corresponding to the first drain doping region 422) can be electrically connected to the wireless charging coil, and the metal connection point 520 corresponding to the second drain doping region 422 (i.e., the drain corresponding to the second drain doping region 422) can be electrically connected to the wired charging interface.

[0075] During wireless charging, a high voltage is applied to the gate doped region 426 corresponding to the first drift region 424a, causing electrical conduction between the first drift region 424a and the channel region 423. Furthermore, the electric field region 428 increases the overall ion doping concentration in the first drift region 424a, thereby reducing on-resistance and improving overall charging efficiency. The gate doped region 426 corresponding to the second drift region 424b is connected to a high voltage, and the second drain doped region 422 (i.e., the corresponding drain) is connected to a high voltage. This creates a reverse voltage differential between the second drift region 424b and the corresponding conductive layer 427. The conductive layer 427 enhances depletion of the second drift region 424b, thereby maintaining the withstand voltage capability and the breakdown voltage. This prevents the wired charging interface from becoming charged, thus reducing safety risks.

[0076] It is understood that the semiconductor device 420 can also be used in other scenarios. In different scenarios, the semiconductor device 420 can form multiple MOS transistors, which can help improve the integration of the semiconductor device 420 and reduce its volume. On the other hand, it can also help improve the performance of the semiconductor device 420 while ensuring the voltage resistance of the semiconductor device 420.

[0077] The structure of the semiconductor device 420 provided in the embodiment of the present application is described in detail above. The following describes in detail the method for manufacturing the semiconductor device 420. Please refer to Figure 8, which is a flow chart of the method for manufacturing the semiconductor device 420 provided in the embodiment of the present application. The method specifically includes steps S1 to S10.

[0078] S1. Add materials to form a substrate 421.

[0079] Please refer to Figure 9, which shows the structure of a substrate 421 provided in an embodiment of the present application. The substrate 421 may include a first surface 421a and a second surface 421b that are spaced apart from each other. For example, the substrate 421 may be made of silicon, gallium nitride, silicon carbide, or other materials. Therefore, this application does not impose any particular limitations on this.

[0080] S2 . Form a trench structure 425 d on the first surface 421 a of the substrate 421 .

[0081] Please refer to Figure 10, which is a structural diagram of a trench structure 425d provided on the substrate 421 shown in Figure 9. The trench structure 425d can be formed on the first surface 421a by processes such as photolithography and etching.

[0082] For example, when the semiconductor device 420 is a dual MOS transistor, three trench structures 425d may be provided. Furthermore, the trench structures 425d may be fabricated using a shallow trench isolation (STI) process, a room temperature (20-80° C.) etching process, a low temperature (<-30° C.) etching process, a dry etching process, or a wet etching process. Therefore, this application does not impose any particular limitation on this.

[0083] S3. Form a channel region 423 on a side of the substrate 421 close to the first surface 421 a.

[0084] Please refer to FIG11, which is a structural diagram of a channel region 423 formed in the substrate 421 provided in FIG10. The trench structure 425d is located in the channel region 423. Exemplarily, P-type ion doping is performed on a side of the substrate 421 close to the first surface 421a through an ion implantation process. For example, the P-type ions may be boron (B) to form the channel region 423.

[0085] It can be understood that only a partial area of ​​the substrate 421 close to the first surface 421a is doped with P-type ions, and the remaining area close to the second surface 421b is not ion implanted, that is, the area can still be in an intrinsic state, and the substrate 421 therefore continues to serve as the substrate 421, that is, the area below the channel region 423 in the figure.

[0086] S4. Form a gate doping region 426 in the trench structure 425d.

[0087] Please refer to FIG12, which is a structural diagram of a gate doped region 426 formed in a trench structure 425d on the substrate 421 provided in FIG11. The gate doped region 426 can be formed in each trench structure 425d by an epitaxial growth process. For example, the epitaxial growth process can include a selective epitaxial growth (SEG) process, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0088] S5. Form a drift region 424 on a side of the channel region 423 away from the substrate 421 .

[0089] Please refer to FIG13 , which is a structural diagram of a drift region 424 formed on one side of the channel region 423 provided in FIG12 . The trench structure 425 d is at least partially located within the drift region 424. For example, an ion implantation process can be used to perform N-type ion doping on a side of the channel region 423 away from the substrate 421. For example, the N-type ions can be phosphorus (P) or arsenic (Ar) to form the drift region 424. That is, in step S1 , ion implantation is performed on a side of the substrate 421 close to the first surface 421 a to form two drift regions 424, so that there is a drift region 424 between each two trench structures 425 d, namely, the first drift region 424 a and the second drift region 424 b.

[0090] S6. Form a dielectric layer 429 on a side of the drift region 424 away from the second surface 421 b.

[0091] Please refer to Figure 14, which is a structural diagram of a dielectric layer 429 formed on the surface of the drift region 424 provided in Figure 13. The dielectric layer 429 can be formed by an epitaxial growth process and covers the inner wall of the trench structure 425d to electrically isolate the gate doped region 426.

[0092] Exemplarily, the dielectric layer 429 may be silicon dioxide (SiO2), and the dielectric layer 429 may be formed by a process such as the above-mentioned selective epitaxial growth (SEG) process, chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD).

[0093] S7 . An electric field region 428 is formed on the surface of the drift region 424 .

[0094] Please refer to Figure 15, which shows a structure diagram of an electric field region 428 formed within the drift region 424 shown in Figure 14. N-type ion doping is performed in the drift region 424 near the dielectric layer 429 through an ion implantation process, thereby forming the electric field region 428. The ion doping concentration of the electric field region 428 is greater than that of the drift region 424.

[0095] For example, the electric field region 428 may be implanted with N-type ions, such as phosphorus (P) or arsenic (Ar), so as to increase the overall ion doping concentration of the drift region 424 .

[0096] S8. Form a conductive layer 427 in the trench structure 425d.

[0097] Please refer to FIG. 16 , which illustrates a structure in which a conductive layer 427 is disposed within the trench structure 425 d shown in FIG. The conductive layer 427 is grown on the dielectric layer 429 within the trench structure 425 d. The dielectric layer 429 electrically isolates the conductive layer 427 from the gate doped region 426. The dielectric layer 429 is then further grown to encapsulate the conductive layer 427, thereby forming the aforementioned isolation region 425 within the trench structure 425 d.

[0098] Exemplarily, the conductive layer 427 can be made of polysilicon material, and the conductive layer 427 can be formed by the above-mentioned selective epitaxial growth (SEG) process, chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD) and other process methods.

[0099] In some examples, when the semiconductor device 420 integrates multiple MOS tubes and only some of the isolation regions 425 have a conductive layer 427, ion implantation can be performed only in the drift region 424 adjacent to the isolation region 425 where the conductive layer 427 is provided to form an electric field region 428, that is, the electric field region 428 is provided corresponding to the conductive layer 427.

[0100] S9. Form a drain doping region 422 in the drift region 424.

[0101] Please refer to Figure 17, which shows the structure of the drain doping region 422 formed in the drift region 424 provided in Figure 16. Ion implantation is performed on one side of each drift region 424 away from the channel region 423 to form the drain doping region 422, namely, the first drain doping region 422 and the second drain doping region 422.

[0102] S10 , forming a hierarchical structure 500 , a contact hole 510 , and a metal connection point 520 on the first surface 421 a .

[0103] Specifically, silicon dioxide is grown in the trench structure 425 d so that the dielectric layer 429 covers the conductive layer 427 , thereby electrically isolating the conductive layer 427 .

[0104] Finally, other hierarchical structures 500 are fabricated on the first surface 421a, contact holes 510 are formed in the hierarchical structures 500, and metal connection points 520 are led out, i.e., drain doping regions 422, gate doping regions 426 and source doping regions are led out, thereby forming a drain, a gate and a source, thereby forming a semiconductor device 420 as shown in FIG7 .

[0105] It is understandable that the subsequent manufacturing processes are all related existing technologies, so they will not be described in detail.

[0106] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0107] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, a source doped region, a drain doped region, and a drift region formed in the substrate; The substrate further comprises an isolation region, wherein a conductive layer is provided in the isolation region, and the conductive layer is electrically connected to the source doping region; An electric field region is provided in the drift region. The ion type doped in the electric field region is the same as the ion type doped in the drift region, and the ion doping concentration in the electric field region is greater than the ion doping concentration in the drift region.

2. The semiconductor device according to claim 1, wherein A channel region is also formed in the substrate, and the type of ions doped in the channel region is different from that in the drift region.

3. The semiconductor device according to claim 2, wherein The conductive layer is electrically connected to the source doping region through the channel region.

4. The semiconductor device according to claim 2, wherein The drift region and the isolation region are arranged on the same side of the channel region, and multiple drift regions are provided. One drift region is provided between two adjacent isolation regions. The conductive layer is provided in at least some of the multiple isolation regions, and the electric field region is provided in the drift region adjacent to the isolation region provided with the conductive layer.

5. The semiconductor device according to claim 4, wherein The conductive layer is provided in each isolation region, and the electric field region is provided on a side of each drift region close to the adjacent isolation region.

6. The semiconductor device according to claim 5, wherein The plurality of drift regions include a first drift region and a second drift region, the plurality of isolation regions include a first isolation region, a second isolation region and a third isolation region, the first drift region is located between the first isolation region and the second isolation region, and the second drift region is located between the second isolation region and the third isolation region.

7. The semiconductor device according to claim 6, wherein: The drain doping region includes a first drain doping region and a second drain doping region. The first drain doping region is formed in the first drift region, and the second drain doping region is formed in the second drift region.

8. The semiconductor device according to any one of claims 4 to 7, wherein: The drain doping region is formed on a side of the drift region away from the channel region.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The ion doping type of the electric field region and the drift region is N-type ion doping, and the ion doping type of the channel region is P-type ion doping.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The semiconductor device further includes a gate doping region, which is disposed in the isolation region and electrically isolated from the conductive layer.

11. A method for manufacturing a semiconductor device, characterized in that: include: forming a substrate comprising a first surface and a second surface facing away from each other; forming a groove structure on the first surface; forming a drift region on a side of the substrate close to the first surface, wherein the trench structure is at least partially located in the drift region; forming a dielectric layer on a side of the drift region away from the second surface; forming an electric field region on the surface of the drift region, wherein the ion type doped in the electric field region is the same as the ion type doped in the drift region, and the ion doping concentration in the electric field region is greater than the ion doping concentration in the drift region; A conductive layer is formed in the trench structure.

12. The manufacturing method according to claim 11, characterized in that: Before forming the drift region on the side of the substrate close to the first surface, the manufacturing method further includes: A channel region is formed on a side of the substrate close to the first surface, and the trench structure is located in the channel region; the drift region is located on a side of the channel region away from the second surface.

13. The manufacturing method according to claim 12, characterized in that: After forming the channel region on the side of the substrate close to the first surface, the manufacturing method further includes: A gate doping region is formed in the trench structure.

14. The production method according to any one of claims 11 to 13, characterized in that: After forming the conductive layer in the trench structure, the manufacturing method further includes: A drain doping region is formed in the drift region.

15. A chip packaging structure, characterized in that: The invention comprises a package substrate and the semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device is electrically connected to the package substrate.

16. An electronic device, characterized in that: It comprises a circuit board and the chip packaging structure according to claim 15, wherein the chip packaging structure is electrically connected to the circuit board.

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