Array substrate, display panel and display module

Abstract

Disclosed herein are an array substrate, a display panel and a display module. The array substrate has a display area (AA) and a first binding area (BA1), and specifically comprises: a base substrate (Sub); binding contact pads (BB) and a plurality of redundant contact pads (DB), which are arranged on the base substrate (Sub) and located in the first binding area (BA1), the binding contact pads (BB) and the redundant contact pads (DB) being used for connecting to a driving integrated circuit; and conductive blocks (CB) arranged on the base substrate (Sub), the conductive blocks (CB) being electrically connected to a power supply voltage signal end and at least two of the redundant contact pads (DB).

Description

Array substrate, display panel and display module CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure claims priority to Chinese patent application number 202410185877.6, filed on February 19, 2024, entitled “Array Substrate, Display Panel, and Display Module,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and specifically to an array substrate, a display panel, and a display module. Background Art

[0003] With the development and application of OLED (Organic Light-Emitting Diode) display technology, OLED display products are becoming increasingly diverse. However, for display products with higher screen resolutions, the power consumption of the driver integrated circuit (IC) increases, reducing the stability and reliability of the display product. Summary of the Invention

[0004] By utilizing the array substrate, display panel, and display module of one or more implementation embodiments of the present disclosure, the driving power consumption corresponding to the power supply voltage signal can be reduced, which is beneficial to improving the stability of display products with higher resolution.

[0005] In the first aspect, the present disclosure provides the following technical solution through an embodiment: an array substrate having a display area and a first binding area, the array substrate comprising: a base substrate; a binding contact pad and a plurality of redundant contact pads, arranged on the base substrate and located in the first binding area, the binding contact pad and the redundant contact pad being used to connect a driving integrated circuit; and a conductive block, arranged on the base substrate; the conductive block electrically connecting the power supply voltage signal terminal and at least two of the redundant contact pads.

[0006] In some embodiments, the redundant contact pad includes a plurality of stacked conductive metal layers, at least one of the plurality of conductive metal layers serves as a connection layer, and the connection layer is electrically connected to the conductive block.

[0007] In some embodiments, the array substrate also includes a driving circuit layer arranged in the display area, the driving circuit layer includes a gate metal layer and at least one source / drain metal layer stacked on the base substrate, and the connecting layer, the conductive block and one of the source / drain metal layers are arranged in the same layer.

[0008] In some embodiments, the driving circuit layer includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence, and the connecting layer, the conductive block, and the second source-drain metal layer are arranged in the same layer.

[0009] In some embodiments, the binding contact pad includes a plurality of input contact pads for binding the input pins of the driver integrated circuit; the redundant contact pad includes a plurality of first redundant contact pads arranged along a first direction; the angle between the first direction and the arrangement direction of the input contact pad does not exceed a set value; at least part of the first redundant contact pads and at least part of the input contact pads are electrically connected to the conductive block.

[0010] In some embodiments, the conductive block includes a plurality of first sub-conductive blocks, at least one first redundant contact pad and at least one input contact pad are electrically connected to the first sub-conductive blocks, and gaps are provided between adjacent first sub-conductive blocks.

[0011] In some embodiments, the first redundant contact pads are arranged in at least two rows along the first direction, and at least one row of the first redundant contact pads close to the input contact pads is electrically connected to the plurality of first sub-conductive blocks.

[0012] In some embodiments, the redundant contact pad further includes a plurality of second redundant contact pads arranged along a second direction, where the second direction intersects with the first direction; the conductive block further includes at least one second sub-conductive block, and at least one first redundant contact pad and at least part of the second redundant contact pads are electrically connected to the second sub-conductive block.

[0013] In some embodiments, the array substrate further has a second binding area, and the array substrate further includes a circuit board contact pad, which is arranged on the base substrate and located in the second binding area, and the circuit board contact pad is used to bind the flexible circuit board; the circuit board contact pad is electrically connected to the second sub-conductive block; the input contact pad electrically connected to the first sub-conductive block is connected to the circuit board contact pad through an internal pin connection.

[0014] In some embodiments, the inner pin connection is provided on the same layer as the first sub-conductive block and the second sub-conductive block.

[0015] In some embodiments, the binding contact pad includes a plurality of output contact pads for binding the output pins of the driver integrated circuit; the array substrate also includes a test contact pad; in a direction parallel to the surface of the array substrate, the test contact pad is located between the input contact pad and the output contact pad; the plurality of first sub-conductive blocks are located between the test contact pad and the input contact pad.

[0016] In some embodiments, the power supply voltage signal terminal is a low-level power supply voltage signal terminal.

[0017] In a second aspect, based on the same inventive concept, the present disclosure provides the following technical solution through an embodiment: A display panel includes the array substrate provided by the embodiment of the first aspect.

[0018] In a third aspect, based on the same inventive concept, the present disclosure provides the following technical solution through an embodiment: A display module includes the display panel provided by the embodiment of the second aspect.

[0019] In some embodiments, the display module includes a source driver integrated circuit arranged in a first binding area; the source driver integrated circuit includes a plurality of binding pins, and the plurality of binding pins are connected to the binding contact pads and redundant contact pads on the array substrate; the redundant contact pads include a plurality of first redundant contact pads arranged along a first direction; the array substrate includes a plurality of first sub-conductive blocks, and each of the first sub-conductive blocks is connected to at least one first redundant contact pad; the total contact resistance between the first redundant contact pad on each of the first sub-conductive blocks and the binding pins of the source driver integrated circuit does not exceed 1Ω.

[0020] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic diagram showing a display area, a peripheral area, a first binding area, and a second binding area of ​​an array substrate according to some embodiments of the present disclosure;

[0022] FIG2 is a schematic diagram showing the layout of the bonding contact pads and the redundant contact pads located in the first bonding area of ​​FIG1 ;

[0023] FIG3 shows a partial enlarged schematic diagram of the A1 area in FIG2 ;

[0024] FIG4 shows a schematic cross-sectional view of the redundant contact pad taken along line AA in FIG3 ;

[0025] FIG5 is a schematic diagram showing the layout of the first redundant contact pad and the first sub-conductive block, and the second redundant contact pad and the second sub-conductive block in the A2 area in FIG3 ;

[0026] FIG6 is a schematic diagram showing an AVSS1 functional area and an AVSS2 functional area formed according to the conductive block layout of FIG2 ;

[0027] FIG7 shows a schematic diagram of wiring between circuit board contact pads and inner pins according to some embodiments of the present disclosure; and

[0028] FIG8 shows a schematic diagram illustrating connections between a source driver IC, a bonding contact pad, and a redundant contact pad of a display module according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0030] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0031] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0033] High-resolution display products present IC power consumption challenges. For example, large-size foldable phones, which are gaining popularity, require more data lines from the source driver integrated circuit (IC) due to their high resolution to meet design requirements. For existing FHD (Full HD, 1920×1080) mobile phone products, two IC approaches can be used to meet higher resolution requirements: 1) using a dual IC (dual driver) solution to increase the total number of IC data lines; 2) employing a multiplexer (data selector) technology to increase the total number of data lines. However, solution 1 requires multiple ICs to work together, which is often costly. Solution 2, using a multiplexer, cuts the data line charging time in half, significantly impacting displays with high refresh rates.

[0034] Therefore, in order to better achieve the reduction of the power consumption of the driver IC, on the first aspect, in an optional embodiment, please refer to Figures 1 to 7, which provide an array substrate Arr, having a display area AA and a first binding area BA1, and the array substrate Arr specifically includes: a base substrate Sub; a binding contact pad BB and a plurality of redundant contact pads DB, which are arranged on the base substrate Sub and located in the first binding area BA1, and the binding contact pad BB and the redundant contact pad DB are used to connect the driver integrated circuit; and, a conductive block CB, which is arranged on the base substrate Sub; the conductive block CB is electrically connected to the power supply voltage signal terminal and at least two redundant contact pads DB.

[0035] In some embodiments, the substrate Sub can be a rigid substrate, such as a glass substrate or a PMMA (polymethyl methacrylate) substrate; or a flexible substrate, such as a PET (polyethylene terephthalate) substrate, a PEN (polyethylene naphthalate diformic acid glycol ester) substrate, or a PI (polyimide) substrate. Flexible substrates have greater flexibility than rigid substrates, and display devices or display products manufactured using flexible substrates can be bent or folded.

[0036] Referring to the schematic layout diagram of the array substrate Arr provided in FIG1 , the array substrate Arr includes a display area AA and a non-display area ZA located at least on one side of the display area AA. A first binding area BA1 is located on one side of the non-display area ZA. Typically, the first binding area BA1 is located on the lower frame side of the display module. The first binding area BA1 refers to the area on the array substrate Arr where the driver integrated circuit (referred to as the driver IC) is bonded. The driver IC can be a source driver integrated circuit (S-IC) or a gate driver integrated circuit (G-IC). In the following description, unless otherwise specified, the source driver IC is used as an example. Corresponding to the first binding area BA1, the non-display area ZA also includes a second binding area BA2. The second binding area BA2 refers to the area on the array substrate Arr where a printed circuit board (PCB) or a flexible printed circuit board (FPC) is bonded. In some embodiments, the area of ​​the first binding area BA1 or the second binding area BA2 is larger than the footprint of the driver IC or PCB bonded to the array substrate Arr. It should be noted that one or more driver ICs may be bonded to the array substrate Arr.

[0037] When the substrate Sub is a flexible substrate, the driver IC can be bound by chip on film. However, COF has the problem of high cost, and the circuits on COF cannot be made too thin, which cannot correspond to high-resolution display products. Therefore, the use of COP (Chip On Plastic, directly binding the chip on a flexible substrate) to bind the driver IC is a better development direction. COP is to directly bind the driver IC on the substrate Sub in the binding area, and then set the FPC. There are multiple binding pins (IC Bonding Bump) on the driver IC, and the binding pins of the driver IC are connected through the corresponding multiple binding contact pads BB (Panel Bonding Bump) set on the substrate Sub, thereby realizing the binding of the driver IC.

[0038] Because the driver IC has a high hardness, when it is bonded by compression bonding, such as hot pressing, it is easy to cause the film layer on the flexible substrate corresponding to the IC bump position to sink, thereby forming a step difference between the bonding area and other areas. In locations where the bonding contact pads BB are not provided, the driver IC may directly contact the inorganic or organic film layer on the flexible substrate, which may cause part of the film layer to break under the action of stress. To solve this problem, please refer to the layout diagram of the bonding contact pads BB and redundant contact pads DB in the first bonding area provided in Figure 2. By providing multiple discretely distributed redundant contact pads DB (Dummy bumps) in some blank areas of the first bonding area BA1 where no bonding contact pads BB are provided, the bonding force between the flexible substrate and the driver IC is balanced or uniformed, reducing the step difference between different areas and the probability of cracking the film layer on the flexible substrate. Discrete distribution means that there is no direct contact between the multiple redundant contact pads DB.

[0039] At the same time, at least two redundant contact pads DB are electrically connected to the conductive block CB, and the conductive block CB is connected to the power supply voltage signal terminal. The power supply voltage signal in the power supply voltage signal terminal can be the digital operating voltage signal DVDD and the corresponding ground voltage DVSS output by the power management integrated circuit (PMIC) to each IC, as well as the analog operating voltage AVDD and the corresponding ground voltage AVSS provided to the Gamma circuit and the common electrode voltage Vcom circuit. The way in which the conductive block CB is connected to the power supply voltage signal terminal can be achieved through the metal routing on the array substrate Arr. Taking the source driver IC as an example, it needs to use the AVSS voltage signal when resetting the Data voltage. Therefore, the conductive block CB can be connected to the power supply voltage signal terminal through the data signal line. As an example, in the following content, unless otherwise specified, the conductive block CB is electrically connected to the low-level power supply voltage signal terminal, that is, the redundant contact pad DB is connected to the AVSS signal as an example for explanation.

[0040] Therefore, the above solution short-circuits multiple discretely distributed redundant contact pads DB through conductive blocks CB, thereby forming a power supply voltage signal network. This power supply voltage network structure helps reduce the trace impedance of the power supply voltage signal during transmission, reduces the power supply voltage signal load, and thus reduces the corresponding driving power consumption of the power supply voltage signal, which helps improve the stability of high-resolution display products.

[0041] The structure of the redundant contact pad DB and the binding contact pad BB can be the same, so the redundant contact pad DB is used as an example for explanation below. In some embodiments, the redundant contact pad DB can be connected to the conductive block CB by directly forming the redundant contact pad DB on the conductive block CB. However, considering the process and technology of the array substrate Arr, in order not to add additional mask processes and avoid increasing process costs, a redundant metal pad can be formed by graphic formation during the process of the array substrate Arr. In other optional embodiments, the redundant contact pad DB includes a plurality of conductive metal layers Con stacked together, and at least one layer of the plurality of conductive metal layers Con is electrically connected to the conductive block CB as a connecting layer.

[0042] In some embodiments, the multiple conductive metal layers Con in the redundant metal pad include at least one first metal layer, at least one second metal layer, and a touch metal layer stacked sequentially on the base substrate Sub. The plane of the touch metal layer is higher than the surrounding array substrate Arr, forming a protruding contact pad. The first metal layer can be a gate metal, and the second metal layer can be a source / drain metal. Considering that the power supply voltage signal is connected, the redundant metal pad can be connected to the conductive block CB through the second metal layer, and the conductive block CB is connected to the source / drain metal traces on the array substrate Arr to realize the access of the power supply voltage signal.

[0043] Correspondingly, in some embodiments, referring to FIG. 1 , the array substrate Arr further includes a driving circuit layer DC provided in the display area AA. Taking OLED as an example, the driving circuit layer DC includes a pixel circuit and corresponding signal routing stacked on the base substrate Sub for driving the organic light-emitting device to emit light. In some embodiments, the driving circuit layer DC includes a gate metal layer and at least one source-drain metal layer stacked on the base substrate Sub, and the connection layer, the conductive block CB and one of the source-drain metal layers are provided on the same layer, and the source-drain metal layer can be any source-drain metal layer in the driving circuit layer DC. In other words, the connection layer, the conductive block CB and a source-drain metal layer in the driving circuit layer DC are formed in a single mask process, and the conductive block CB is electrically connected to the source-drain metal layer. The second metal layer in the redundant contact pad DB, which is on the same layer as the conductive block CB, serves as a connection layer to connect the conductive block CB, thereby realizing access to the power supply voltage signal.

[0044] For example, in some display products, the driving circuit layer DC on the array substrate Arr includes a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer stacked in sequence. The first source-drain metal layer is patterned to form the source and drain electrodes of the thin-film transistor, the second source-drain metal layer is patterned to form the data signal lines, and the third source-drain metal layer is patterned to form the data signal crossover structure.

[0045] Correspondingly, referring to FIG4 , the conductive metal layer Con in the redundant contact pad DB includes at least one first metal layer, Gate, and three second metal layers: SD1, SD2, and SD3. An interlayer dielectric layer ILD is also stacked around the periphery of the first metal layer, Gate. The three second metal layers (SD1, SD2, and SD3) correspond to and are co-located with the first, second, and third source / drain metal layers of the array substrate Arr, respectively. A touch metal layer TMB is stacked on the top second metal layer SD3. The periphery of the touch metal layer TMB is elevated by a planarization layer PLN and a touch inorganic layer TLD to form a contact pad structure connected to the driver IC's binding pins.

[0046] For the redundant contact pad DB shown in Figure 4, in some embodiments, the second metal layer SD2 of the intermediate layer is used as a connecting layer and is arranged on the same layer as the conductive block CB and the second source-drain metal layer of the array substrate Arr. That is, the connecting layer of the redundant contact pad DB and the conductive block CB and the second source-drain metal layer connected to the power supply voltage signal line are patterned through the same MASK process. This can save a step of forming the conductive block CB and the connecting layer mask, which is beneficial to reducing production costs.

[0047] For the binding contact pads BB, please refer to Figures 3 and 5, which include multiple input contact pads IB (Input Bump) and multiple output contact pads OB (Output Bump), which correspond to the input pins and output pins of the driver IC, respectively. That is, the input contact pads IB are used to bind the input pins of the driver IC, and the output contact pads OB are used to bind the output pins of the driver IC. It can be understood that the input contact pads IB and the output contact pads OB are connected to the source and drain metal layers of the array substrate Arr, which can enable the input and output signals of the driver IC to be normally transmitted on the array substrate Arr. In some embodiments, there are multiple input contact pads IB and output contact pads OB, and different input contact pads IB or output contact pads OB can be connected to different source and drain metal layers according to signal transmission requirements.

[0048] As can be seen from Figure 3, for high-resolution large-size display products, such as foldable display products, the output contact pads OB of the driver IC are arranged in multiple rows. Compared with FHD non-foldable display products, there are at least 2 to 3 more rows of output contact pads OB. That is, compared with ordinary display products, the driver IC of foldable display products has more source drive binding structures Source Pad to meet the needs of higher resolution. However, outputting more Source Pads means an increase in driving power consumption for the driver IC. Therefore, for foldable display products, the power consumption and reliability of the driver IC are particularly important. For the data voltage V dataWhen the source driver IC is working, it will continuously jump the voltage and reset the voltage. For foldable display products, more jumps and resets are required, and the power consumption will increase accordingly. Therefore, the power supply voltage signal network formed by the redundant contact pad DB can effectively reduce V data The power consumed by the transition.

[0049] In some embodiments, referring to FIG. 5 , the redundant contact pads DB include a plurality of first redundant contact pads DB1 arranged along a first direction 11. The angle between the first direction 11 and the arrangement direction of the input contact pads IB does not exceed a predetermined value. At least some of the first redundant contact pads DB1 and at least some of the input contact pads IB are electrically connected to the conductive block CB. The arrangement direction of the plurality of input contact pads IB can be considered as the direction in which the plurality of input contact pads IB extend in sequence. In FIG. 5 , the arrangement direction of the input contact pads IB is the same as the arrangement direction of the output contact pads OB, which is the lateral or horizontal direction in FIG. In some embodiments, the first direction 11 can be parallel or nearly parallel to the arrangement direction of the input contact pads IB, such that the angle between the first and second directions does not exceed 3°.

[0050] By connecting some input contact pads IB to the same type of power supply voltage signal as the redundant contact pads DB, the signal requirements of the source driver IC during the display driving process can be met. The remaining input contact pads IB can be connected to other source and drain metal layers in the array substrate Arr as needed.

[0051] In some embodiments, the conductive block CB includes multiple first sub-conductive blocks CB1 , at least one first redundant contact pad DB1 and at least one input contact pad IB are electrically connected to the first sub-conductive blocks CB1 , and gaps are provided between adjacent first sub-conductive blocks CB1 .

[0052] On this basis, by providing at least one first sub-conductive block CB1, and providing at least one first redundant contact pad DB1 and at least one input contact pad IB on each first sub-conductive block CB1, a power supply voltage signal network is formed within the region of each first sub-conductive block CB1. On the basis of reducing the driving power consumption of the driver IC, the number, position and area of ​​the first sub-conductive blocks CB1 can also be adjusted to obtain multiple functional areas of the power supply voltage signal network to meet the usage requirements of different functional modules on the driver IC. Therefore, the above solution reduces the power consumption of the power supply voltage signal routing in different regions and functional modules, and has better driving control benefits and power consumption benefits for large-size foldable products. As an example, the AVSS1 functional area and AVSS2 functional area formed by the two first sub-conductive blocks CB1 in Figure 6, that is, each first sub-conductive block CB1 is connected to the AVSS signal through the input contact pad IB.

[0053] To further reduce the trace impedance of the power supply voltage signal, the area and number (or density) of the first redundant contact pads DB1 on the first conductive sub-block CB1 can be designed based on the total contact resistance between each first redundant contact pad DB1 on the first conductive sub-block CB1 and the binding pins of the source driver IC. Research has shown that reducing the total contact resistance to less than 1Ω significantly reduces the trace impedance and load of the power supply voltage signal.

[0054] In some embodiments, the first redundant contact pads DB1 are arranged in at least two rows along the first direction 11. At least one row of first redundant contact pads DB1 proximate to the input contact pad IB is electrically connected to a plurality of first conductive sub-blocks CB1. As an example, the first redundant contact pads DB1 in FIG5 are arranged in two rows, with the row of first redundant contact pads DB1 proximate to the input contact pad IB being disposed on the first conductive sub-block CB1. This design minimizes the adverse effects of the conductive blocks CB on the metal traces on the array substrate Arr.

[0055] In some embodiments, referring to FIG. 3 or FIG. 5 , a test contact pad TB (Test Bump) is further provided on the substrate Sub of the first binding area BA1. In a direction parallel to the surface of the array substrate Arr, the test contact pad TB is located between the input contact pad IB and the output contact pad OB; and a plurality of first sub-conductive blocks CB1 are located between the test contact pad TB and the input contact pad IB. The test contact pad TB is used to connect the test pins during a test phase, such as a lighting test (Cell Test, CT), to perform a lighting test on the display panel. Disposing the first sub-conductive block CB1 between the test contact pad TB and the input contact pad IB can avoid affecting the metal routing under the test contact pad TB or make routing design more convenient, resulting in better process costs.

[0056] In some embodiments, referring to FIG. 5 , the redundant contact pad DB further includes a plurality of second redundant contact pads DB2 arranged along a second direction 12, where the second direction 12 intersects with the first direction 11; the conductive block CB further includes at least one second sub-conductive block CB2, and at least one first redundant contact pad DB1 and at least part of the second redundant contact pads DB2 are electrically connected to the second sub-conductive block CB2.

[0057] The second direction 12 can be perpendicular or nearly perpendicular to the first direction 11. Providing multiple second redundant contact pads DB2 along the second direction 12 helps reduce the driver IC's impact on the flexible substrate in the second direction 12, minimizing step differences and film cracking. Furthermore, by providing a second sub-conductive block CB2, some of the second redundant contact pads DB2 are short-circuited with the first redundant contact pad DB1. Once the second sub-conductive block CB is connected to the power supply voltage signal, it can serve as an additional power supply voltage signal network for use by other functional modules of the driver IC.

[0058] It should be noted that the functional modules of the driver IC corresponding to the different power supply voltage signal networks formed by the first sub-conductive block CB1 and the second sub-conductive block CB2 are matched according to driving requirements, which is not limited in the present disclosure.

[0059] In some embodiments, referring to FIG. 7 , the array substrate Arr further includes a circuit board contact pad FB, which is disposed on the base substrate Sub and located in the second binding area BA2 . The circuit board contact pad FB is used to bind the flexible circuit board. The circuit board contact pad FB is electrically connected to the second sub-conductive block CB2 . The input contact pad IB electrically connected to the first sub-conductive block CB1 is connected to the circuit board contact pad FB through the inner pin wiring ILB.

[0060] Specifically, the internal pin bonding (ILB) refers to a connection formed using an internal pin bonding (ILB) process. This ILB facilitates signal transmission between the input contact pad IB and the flexible circuit board. In some embodiments, the ILB is provided on the same layer as the first conductive sub-block CB1 and the second conductive sub-block CB2. This means that the ILB can also be formed by patterning the source and drain metal layer, saving a mask process.

[0061] In summary, the array substrate Arr provided in the embodiment of the first aspect proposes a layout design of the contact pads in the binding area of ​​the driver IC for large-size display products, such as large-size folding OLED products. The redundant contact pads DB are used to form a power supply voltage signal network, which is beneficial to reducing the power consumption of the driver IC and improving the reliability of the display product. On the other hand, the power consumption of the power supply voltage signal lines of different regions and different functional modules is reduced through multiple first sub-conductive blocks CB1, which has better power consumption reduction benefits for large-size folding products.

[0062] Based on the same inventive concept, in a second aspect, in an optional embodiment, a display panel is provided, comprising the array substrate Arr provided in the embodiment of the first aspect. The display panel can be a flexible OLED display panel, used in various foldable display products, such as foldable mobile phones, tablet computers, or in-vehicle displays.

[0063] Based on the same inventive concept, in a third aspect, in an optional embodiment, a display module is provided, comprising the display panel provided in the embodiment of the second aspect, wherein a driver IC and a flexible circuit board (FPC) are bound to the display panel.

[0064] FIG8 shows a partial cross-sectional view of a display module in which an active driver integrated circuit S-IC is bonded in a first bonding area BA1. It can be seen that the S-IC has a plurality of bonding pins ICB, which are connected to bonding contact pads BB and redundant contact pads DB on the array substrate Arr for bonding.

[0065] In some optional embodiments, the total contact resistance between the first redundant contact pads DB1 on each first conductive sub-block CB1 and the binding pins of the source driver integrated circuit does not exceed 1Ω. By adjusting the area, number, or density of the first redundant contact pads DB1 on each first conductive sub-block CB1 based on this contact resistance, the routing impedance and load of the power supply voltage signal can be further reduced. The number of first redundant contact pads DB1 and second redundant contact pads DB2 on the second conductive sub-block CB2 can be similarly adjusted.

[0066] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0067] The present disclosure provides an array substrate, a display panel and a display module, by arranging a binding contact pad BB and a plurality of redundant contact pads DB on a base substrate Sub located in a first binding area BA1, wherein the binding contact pad BB is used to connect a driver integrated circuit (IC), and the redundant contact pad DB is used to balance the binding stress between the driver IC and the array substrate when the driver IC is bound to the array substrate, thereby reducing the probability of film breakage on the base substrate Sub; then at least two redundant contact pads DB are electrically connected to a conductive block CB, and the conductive block CB is connected to a power supply voltage signal end to access the power supply voltage signal, and a power supply voltage signal network can be formed through a plurality of short-circuited redundant contact pads DB. The power supply voltage network structure is conducive to reducing the routing impedance of the power supply voltage signal during transmission, reducing the load of the power supply voltage signal, thereby reducing the driving power consumption corresponding to the power supply voltage signal, and is conducive to improving the stability of display products with higher resolution.

[0068] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. An array substrate having a display area and a first binding area, the array substrate comprising: substrate; A binding contact pad and a plurality of redundant contact pads are provided on the substrate and located in the first binding area, the binding contact pad and the redundant contact pad being used to connect to a driver integrated circuit; as well as, A conductive block is provided on the substrate; the conductive block is electrically connected to the power supply voltage signal terminal and at least two of the redundant contact pads.

2. The array substrate according to claim 1, wherein: The redundant contact pad includes a plurality of stacked conductive metal layers, at least one of the plurality of conductive metal layers serves as a connection layer, and the connection layer is electrically connected to the conductive block.

3. The array substrate as described in claim 2 further includes a driving circuit layer arranged in the display area, the driving circuit layer includes a gate metal layer and at least one source and drain metal layer stacked on the base substrate, and the connecting layer, the conductive block and one of the source and drain metal layers are arranged in the same layer.

4. The array substrate according to claim 3, wherein: The driving circuit layer includes a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer stacked in sequence, and the connecting layer, the conductive block and the second source-drain metal layer are arranged in the same layer.

5. The array substrate according to claim 1, wherein: The binding contact pads include a plurality of input contact pads for binding input pins of the driver integrated circuit; The redundant contact pads include a plurality of first redundant contact pads arranged along a first direction; the angle between the first direction and the arrangement direction of the input contact pads does not exceed a set value; at least some of the first redundant contact pads and at least some of the input contact pads are electrically connected to the conductive block.

6. The array substrate according to claim 5, wherein: The conductive block includes a plurality of first sub-conductive blocks, at least one first redundant contact pad and at least one input contact pad are electrically connected to the first sub-conductive blocks, and gaps are provided between adjacent first sub-conductive blocks.

7. The array substrate according to claim 6, wherein: The first redundant contact pads are arranged in at least two rows along the first direction, and at least one row of the first redundant contact pads close to the input contact pads is electrically connected to the plurality of first sub-conductive blocks.

8. The array substrate according to claim 6, wherein: The redundant contact pad further includes a plurality of second redundant contact pads arranged along a second direction, the second direction intersecting the first direction; The conductive block further includes at least one second sub-conductive block, and at least one of the first redundant contact pads and at least some of the second redundant contact pads are electrically connected to the second sub-conductive block.

9. The array substrate according to claim 8, further comprising a second binding area, the array substrate further comprising a circuit board contact pad disposed on the base substrate and located in the second binding area, the circuit board contact pad being used to bind a flexible circuit board; The circuit board contact pad is electrically connected to the second sub-conductive block; The input contact pad electrically connected to the first sub-conductive block is connected to the circuit board contact pad via an inner pin connection.

10. The array substrate according to claim 9, wherein: The inner pin connection is provided on the same layer as the first sub-conductive block and the second sub-conductive block.

11. The array substrate according to claim 6, wherein: The binding contact pads include a plurality of output contact pads for binding output pins of the driver integrated circuit; The array substrate further includes a test contact pad; in a direction parallel to the surface of the array substrate, the test contact pad is located between the input contact pad and the output contact pad; the plurality of first sub-conductive blocks are located between the test contact pad and the input contact pad.

12. The array substrate according to claim 1, wherein: The power supply voltage signal terminal is a low-level power supply voltage signal terminal.

13. A display panel comprising the array substrate according to any one of claims 1 to 12.

14. A display module comprising the display panel according to claim 13.

15. The display module according to claim 14, further comprising a source driver integrated circuit disposed in the first bonding area; the source driver integrated circuit comprising a plurality of bonding pins, the plurality of bonding pins being connected to the bonding contact pads and the redundant contact pads on the array substrate; The redundant contact pad includes a plurality of first redundant contact pads arranged along a first direction; the array substrate includes a plurality of first sub-conductive blocks, each of the first sub-conductive blocks is connected to at least one first redundant contact pad; the total contact resistance between the first redundant contact pad on each first sub-conductive block and the binding pin of the source driver integrated circuit does not exceed 1Ω.

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