Semiconductor device and manufacturing method therefor

Abstract

The present invention provides a semiconductor device and a manufacturing method therefor. The method comprises: providing a substrate, and forming a drift region in the substrate; forming a plurality of channel spacing regions in the drift region, a gap being present between every two channel spacing regions to form a channel region; forming a source contact region, a drain contact region and a gate contact region in the drift region, and forming a substrate contact region in the substrate, the substrate contact region and the drift region being spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel regions are connected to the source contact region and the drain contact region. According to the solution of the present invention, a plurality of channel spacing regions are formed, and a gap is present between every two channel spacing regions to form a channel region, so that the pinch-off voltage of devices can be adjusted by adjusting the width of the channel regions, and devices are also ensured to have sufficiently high conduction current when turned on, thereby further decreasing the conduction resistance of the devices, reducing the power consumption of the devices, and improving the performance of the devices.

Description

Semiconductor device and preparation method thereof Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] With the continuous development of integrated circuits, multiple devices are often fabricated simultaneously on the same substrate to save area. For example, in the BCD (Bipolar-CMOS-DMOS) process, high-voltage power devices such as bipolar transistors, complementary metal oxide semiconductors (CMOS), and diffused metal oxide semiconductors (DMOS) can be fabricated on the same substrate. The BCD process has been widely used in mobile devices, home appliances, displays, automobiles, data centers, and other fields.

[0003] The junction field-effect transistor (JFET) is a device commonly used in the BCD process. It has a very high input impedance, allowing a high degree of isolation between the input and output circuits. It does not have the inherent noise of electron tubes and transistors, and its negative temperature coefficient can avoid the risk of thermal runaway. In addition, it also has a very high power gain.

[0004] In JFETs, pinch-off voltage is a crucial parameter, playing a key role in regulating the source-to-drain current and controlling the JFET's operating state. However, the pinch-off voltage of JFETs in related art is generally uncontrollable. Alternatively, while the pinch-off voltage can be controlled, the on-current of the JFET is low when the pinch-off voltage is low, resulting in an increase in the JFET's on-resistance. This, in turn, increases the JFET's power consumption in practical applications, reducing device performance. Summary of the Invention

[0005] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention is not intended to limit the key features and essential features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] In order to solve the existing problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] a substrate having a first conductivity type;

[0008] a drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type;

[0009] a plurality of channel spacers located in the drift region and exposed to the first surface, wherein a gap exists between every two adjacent channel spacers to form a channel region, and the channel spacers have a first conductivity type;

[0010] A source contact region, a drain contact region, and a gate contact region are located in the drift region, the gate contact region is located between the source contact region and the drain contact region, the channel region communicates with the source contact region and the drain contact region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type;

[0011] A substrate contact region is located in the substrate and spaced apart from the drift region, and the substrate contact region has the first conductivity type.

[0012] In one embodiment, the drain contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or,

[0013] The source contact region and the gate contact region are ring-shaped. The gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

[0014] In one embodiment, the semiconductor device further comprises:

[0015] A first field oxide layer and a second field oxide layer are located in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region;

[0016] A first gate structure and a second gate structure, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

[0017] In one embodiment, the second gate structure is a floating gate structure.

[0018] In one embodiment, the semiconductor device further includes a source gradual change region and a drain gradual change region located in the drift region, the source contact region is located in the source gradual change region, the drain contact region is located in the drain gradual change region, and the source contact region and the drain contact region have the second conductivity type.

[0019] Another aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0020] providing a substrate having a first conductivity type;

[0021] forming a drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type;

[0022] forming a plurality of channel spacer regions of the first conductivity type in the drift region, wherein a gap exists between every two channel spacer regions to form a channel region;

[0023] A source contact region, a drain contact region and a gate contact region with a first conductivity type are formed in the drift region, and a substrate contact region with a first conductivity type is formed in the substrate, wherein the substrate contact region and the drift region are spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region connects the source contact region and the drain contact region.

[0024] In one embodiment, the drain contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or,

[0025] The source contact region and the gate contact region are ring-shaped. The gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

[0026] In one embodiment, the method further comprises:

[0027] forming a first field oxide layer and a second field oxide layer in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region;

[0028] A first gate structure and a second gate structure are formed, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

[0029] In one embodiment, the second gate structure is a floating gate structure.

[0030] In one embodiment, before forming the source contact region and the drain contact region, the method further includes:

[0031] A source graded region and a drain graded region of the second conductivity type are formed in the drift region, the source contact region is located in the source graded region, and the drain contact region is located in the drain graded region.

[0032] The semiconductor device and preparation method of the embodiment of the present invention form multiple channel spacer regions, and there is a gap between each two adjacent channel spacer regions to form a channel region. Each channel region can be pinched off from two directions. While adjusting the pinch-off voltage of the device by adjusting the width of the channel region, it is possible to ensure that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0034] FIG1 shows a flow chart of a method for manufacturing a semiconductor device according to a specific embodiment of the present invention;

[0035] 2A-2J are schematic cross-sectional views of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention;

[0036] 3 shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for preparing a semiconductor device according to another specific embodiment of the present invention;

[0037] FIG4 shows a schematic diagram of a layout of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention;

[0038] FIG5 is a schematic top view of a semiconductor device when pinched off according to a specific embodiment of the present invention;

[0039] FIG6 shows a schematic top view of a semiconductor device when pinched off according to another specific embodiment of the present invention;

[0040] 7 shows a cross-sectional view of a semiconductor device when pinched off according to a specific embodiment of the present invention;

[0041] FIG8 shows a cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention;

[0042] FIG9 is a schematic cross-sectional view of a semiconductor device when pinched off according to another embodiment of the present invention. DETAILED DESCRIPTION

[0043] Next, the present invention will be described more fully with reference to the accompanying drawings, which illustrate embodiments of the present invention. However, the present invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0044] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present invention. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0049] In order to fully understand the present invention, detailed steps and structures will be provided in the following description to illustrate the technical solutions proposed by the present invention. Preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0050] In view of the existence of the aforementioned technical problems, an embodiment of the present invention provides a semiconductor device, comprising: a substrate having a first conductivity type;

[0051] a drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type;

[0052] a plurality of channel spacers located in the drift region and exposed to the first surface, wherein a gap exists between every two adjacent channel spacers to form a channel region, and the channel spacers have a first conductivity type;

[0053] A source contact region, a drain contact region, and a gate contact region are located in the drift region, the gate contact region is located between the source contact region and the drain contact region, the channel region communicates with the source contact region and the drain contact region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type;

[0054] A substrate contact region is located in the substrate and spaced apart from the drift region, and the substrate contact region has the first conductivity type.

[0055] The present invention also provides a method for preparing a semiconductor device, which mainly comprises the following steps:

[0056] Providing a substrate having a first conductivity type, forming a drift region having a second conductivity type extending from a first surface of the substrate to the interior of the substrate;

[0057] forming a plurality of channel spacer regions of a first conductivity type in the drift region, wherein a gap exists between every two adjacent channel spacer regions to form a channel region;

[0058] A source contact region, a drain contact region and a gate contact region with a first conductivity type are formed in the drift region, and a substrate contact region with a first conductivity type is formed in the substrate and extends from the first surface of the substrate to the substrate, wherein the substrate contact region and the drift region are spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region connects the source contact region and the drain contact region.

[0059] The semiconductor device and preparation method of the embodiment of the present invention form multiple channel spacer regions, and there is a gap between each two adjacent channel spacer regions to form a channel region. Each channel region is connected to the source contact region and the drain contact region to form a current channel. While adjusting the pinch-off voltage of the device by adjusting the width of the channel region, it is possible to ensure that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance.

[0060] Example 1

[0061] 1 to 9 , wherein FIG1 shows a flow chart of a method for preparing a semiconductor device according to a specific embodiment of the present invention, FIG2A to FIG2J show cross-sectional schematic diagrams of a semiconductor device obtained by sequentially implementing the method for preparing a semiconductor device according to a specific embodiment of the present invention, FIG3 shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing the method for preparing a semiconductor device according to another specific embodiment of the present invention, FIG4 shows a layout schematic diagram of a semiconductor device obtained by sequentially implementing the method for preparing a semiconductor device according to a specific embodiment of the present invention, FIG5 shows a top view schematic diagram of a semiconductor device according to a specific embodiment of the present invention when pinched off, FIG6 shows a top view schematic diagram of a semiconductor device according to another specific embodiment of the present invention when pinched off, FIG7 shows a cross-sectional schematic diagram of a semiconductor device according to a specific embodiment of the present invention when pinched off, FIG8 shows a cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention, and FIG9 shows a cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention when pinched off.

[0062] Illustratively, the method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps:

[0063] First, step S1 is performed to provide a substrate having a first conductivity type; and form a drift region having a second conductivity type extending from a first surface of the substrate into the substrate.

[0064] Illustratively, the semiconductor device of the present application includes a JFET device, and the semiconductor device can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the present application is mainly explained and illustrated by taking the case where the semiconductor device is a JFET device as an example.

[0065] In one example, as shown in FIG2A , substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, or substrate 200 may further include silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form substrate 200 are described herein, any material that can be used as substrate 200 falls within the spirit and scope of the present application.

[0066] Illustratively, substrate 200 includes a semiconductor base and an epitaxial layer formed on the semiconductor base. Optionally, the semiconductor base and the epitaxial layer may have the same conductivity type. Illustratively, the semiconductor base and the epitaxial layer may have different doping concentrations; for example, the doping concentration of the epitaxial layer may be lower than the doping concentration of the semiconductor base. Illustratively, substrate 200 has a first conductivity type, which may be N-type or P-type.

[0067] In one example, as shown in FIG2A , before forming the drift region 202, the process further includes forming a shallow trench isolation structure 201. Exemplarily, forming the shallow trench isolation structure 201 may include the following steps: etching the substrate 200 to a certain depth from the first surface of the substrate 200 to form a shallow trench; and forming a silicon oxide layer within the shallow trench to form the shallow trench isolation structure 201. Exemplarily, the shallow trench isolation structure 201 is located between active regions of the device.

[0068] In one example, as shown in FIG2B , a drift region 202 having a second conductivity type is formed extending from the first surface of the substrate 200 into the substrate 200. Specifically, the drift region 202 can be formed by the following steps: forming a patterned mask layer on the first surface of the substrate 200; performing an ion implantation process using the mask layer as a mask to form the drift region 202; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, when the first conductivity type is P-type, the second conductivity type is N-type; and when the first conductivity type is N-type, the second conductivity type is P-type. Exemplarily, the doping concentration of the drift region 202 is greater than the doping concentration of the substrate 200, and therefore has a lower resistivity. Exemplarily, the drift region 202 is located within the active region of the device.

[0069] As shown in Figure 2D , after forming the drift region 202 and before performing step S2, the method of the present application further includes forming a first implantation region 204 in the drift region 202, wherein the first implantation region 204 has the second conductivity type. Specifically, the first implantation region 204 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the first implantation region 204; and finally, removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the doping concentration of the first implantation region 204 is greater than the doping concentration of the drift region 202, thereby further reducing the resistivity.

[0070] Next, step S2 is performed to form a plurality of channel spacer regions of the first conductivity type in the drift region, with a gap existing between every two adjacent channel spacer regions to form a channel region.

[0071] Specifically, as shown in Figures 2E, 4, 5 and 6, a plurality of channel spacers 205 having a first conductivity type are formed in the drift region 202, and the plurality of channel spacers 205 are exposed to the first surface of the substrate and are arranged at intervals along the first surface of the substrate; there is a gap between every two adjacent channel spacers 205 to form a channel region, and when a first injection region 204 is formed in the drift region 202, the gap between every two channel spacers 205 is the first injection region 204, or in other words, the first injection region 204 between every two channel spacers 205 is the channel region.

[0072] In one example, as shown in FIG2E , the trench spacer 205 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the trench spacer 205; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer.

[0073] In one example, as shown in FIG2E and FIG5 and FIG6, the depth of the channel spacer 205 is less than the depth of the drift region 202. Furthermore, the depth of the channel spacer 205 is also less than the depth of the first implantation region 204. In this case, the first implantation region 204 and the drift region 202 between the channel spacer 205 and the substrate 200 also constitute a channel region. In other examples, the depth of the channel spacer 205 may also be greater than or equal to the depth of the drift region 202. In this case, the channel region is located between two adjacent channel spacers 205.

[0074] Next, step S3 is performed, as shown in FIG2H , to form a source contact region 211 and a drain contact region 210 of the second conductivity type in the drift region, with the channel region connecting the source contact region 211 and the drain contact region 210. Specifically, the source contact region 211 and the drain contact region 210 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the source contact region 211 and the drain contact region 210; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer.

[0075] As shown in FIG2I , a gate contact region 212 having a first conductivity type is formed in the drift region, and a substrate contact region 213 having the first conductivity type is formed in the substrate 200, extending from the first surface of the substrate 200 into the substrate 200. The gate contact region 212 is located between the source contact region 211 and the drain contact region 210, and the substrate contact region 213 is spaced apart from the drift region 202. Specifically, the gate contact region 212 and the substrate contact region 213 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the gate contact region 212 and the substrate contact region 213; and finally, removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the source contact region 211, the drain contact region 210, the gate contact region 212, and the substrate contact region 213 are all heavily doped regions, effectively reducing contact resistance when subsequently electrically connected to the contact plug 214. Exemplarily, the substrate contact region 213 is located between the shallow trench isolation structures 201 .

[0076] In one example, as shown in Figures 2C and 2G, the method of the present application also includes: forming a first field oxide layer 2031 and a second field oxide layer 2032 in the drift region 202, wherein the first field oxide layer 2031 is located between the gate contact region 212 and the drain contact region 210, and the second field oxide layer 2032 is located between the gate contact region 212 and the source contact region 211; forming a first gate structure 2091 and a second gate structure 2092, wherein the first gate structure 2091 is located on the first field oxide layer 2031 and partially extends onto the drift region 202, and the second gate structure 2092 is located on the first field oxide layer 2031 and is located on the side of the first gate structure 2091 close to the drain contact region 210.

[0077] For example, the first field oxide layer 2031 and the second field oxide layer 2032 may be formed by any suitable method known to those skilled in the art, for example, by thermal oxidation.

[0078] Illustratively, both the first gate structure 2091 and the second gate structure 2092 include a gate layer and sidewall spacers located on either side of the gate layer. Illustratively, the gate layer is composed of polysilicon. Generally, metals, metal nitrides, metal silicides, or similar compounds may also be used as the gate layer material. Illustratively, the sidewall spacers include insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, and may be a single-layer structure or a multi-layer structure.

[0079] In one example, as shown in FIG2J , the gate contact region 212 and the first gate structure 2091 are electrically connected to the same external metal layer via contact plugs to form a gate. That is, the gate contact region 212 and the first gate structure 2091 are electrically connected via the contact plugs, so that when a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a biased field plate structure to increase the average electric field in the drift region 202 and reduce the electric field peak, thereby achieving the purposes of suppressing hot carrier effects and improving breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure, that is, the second gate structure 2092 does not need to be connected to an external electrode. The second gate structure 2092 can form a floating field plate structure with the first field oxide layer 2031, making the electric field distribution in the drift region 202 more uniform, ensuring that the corners where the electric field is concentrated are not easily broken down, thereby further improving the breakdown voltage.

[0080] In one example, as shown in FIG2J , contact plug 214 further electrically connects source contact region 211 with an external metal layer to form a source, further electrically connects drain contact region 210 with an external metal layer to form a drain, and further electrically connects substrate contact region 213 with an external metal layer to lead substrate 200 out to form a substrate terminal. Exemplarily, materials for contact plug 214 include, but are not limited to, copper, tungsten, gold, silver, aluminum, and the like.

[0081] In one example, as shown in FIG2F , before forming the source contact region 211 and the drain contact region 210, the method of the present application further includes: forming a source-tapered region 208 and a drain-tapered region 207 having the second conductivity type in the drift region 202, wherein the source contact region 211 is located in the source-tapered region 208, and the drain contact region 210 is located in the drain-tapered region 207. Specifically, the source-tapered region 208 and the drain-tapered region 207 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the source-tapered region 208 and the drain-tapered region 207; and finally, removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. For example, the doping concentration of the source graded region 208 is lower than the doping concentration of the source contact region 211, and the doping concentration of the drain graded region 207 is lower than the doping concentration of the drain contact region 210. By forming the source graded region 208 and the drain graded region 207, the antistatic performance of the device can be improved, and the phenomenon of excessive carrier concentration can be effectively reduced, thereby effectively alleviating the thermoelectric effect. For example, the first field oxide layer 2031 and the second field oxide layer 2032 can be formed first, followed by the source graded region 208 and the drain graded region 207, and then the first gate structure 2091 and the second gate structure 2092.

[0082] In one example, as shown in FIG2E , the method of the present application further includes forming a second implantation region 206 in the substrate 200, wherein the substrate contact region 213 is located in the second implantation region 206. Specifically, the second implantation region 206 can be formed by the following steps: forming a patterned mask layer; performing an ion implantation process using the mask layer as a mask to form the second implantation region 206; and finally, removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the second implantation region 206 has the first conductivity type.

[0083] In one example, as shown in FIG2J and FIG4 , the drain contact region 210 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the source contact region 211, and the drain contact region 210 surrounds the outside of the gate contact region 212; or, as shown in FIG3 , the source contact region 211 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the drain contact region 210, and the source contact region 211 surrounds the outside of the gate contact region 212. FIG3 shows a cross-sectional view of a semiconductor device obtained by another embodiment of the present application, which can achieve the same function as the semiconductor device obtained by FIG2A to FIG2J . This overall annular surrounding structure can effectively save device area. For example, at this time, the first gate structure 2091 and the second gate structure 2092 also have an annular structure. For example, as shown in FIG5 , the gate contact region 212 may also be located in the channel spacer region 205 instead of in the first implantation region 204 . In this case, the gate contact region 212 is in a ring shape with intervals arranged therebetween.

[0084] In one example, each region formed by the ion implantation process is subjected to a rapid temperature ramp annealing process immediately after the ion implantation process to activate dopants in the ion implanted region and simultaneously repair the lattice structure damaged during the ion implantation process.

[0085] In one example, the pinch-off voltage of the device can be adjusted by adjusting the width of the channel region between the channel spacers 205 to meet actual needs.

[0086] 5 , the gate contact region 212 may be located in the channel spacer 205 but not in the first implant region 204 . Alternatively, as shown in FIG6 , the gate contact region 212 may be located in both the channel spacer 205 and the first implant region 204 .

[0087] In one example, as shown in Figures 4, 5 and 6, taking the case where the first conductivity type is P-type and the second conductivity type is N-type as an example, when no reverse bias voltage is applied to the gate and substrate ends, current can flow from the source through the channel region between the channel spacer regions 205 to the drain. Since the present application forms channel regions between the channel spacer regions 205, multiple current channels can be formed, thereby ensuring that the device can still have a higher on-state current when having a smaller pinch-off voltage, thereby reducing the on-state resistance of the device, reducing the power consumption of the device, and improving the device performance. When a reverse bias voltage is applied to the gate and substrate ends, the depletion layer between the channel spacer region 205 and the channel region gradually widens until it completely fills the channel region. At this time, the channel region is pinched off and the device is also in a pinch-off state. The arrows shown in Figures 5 and 6 are the directions in which the depletion layer pinches off the channel region.

[0088] For example, as shown in FIG7 , when the depth of the channel spacer 205 is less than the depth of the drift region 202, a channel region can be formed between the channel spacer 205 and the substrate 200. The channel region between the channel spacer 205 and the substrate 200 can also form a current path, thereby further improving the on-current of the device. The arrow in FIG7 indicates the direction in which the depletion layer pinches off the channel region between the channel spacer 205 and the substrate 200. For example, as shown in FIG8 , when the depth of the channel spacer 205 is equal to or greater than the depth of the drift region 202, a channel region cannot be formed between the channel spacer 205 and the substrate 200.

[0089] In addition, as shown in Figure 9, when the gate contact region 212 is located in the channel spacer region 205 and the first injection region 204, between adjacent channel spacers 205, the conductivity type of the gate contact region 212 and the substrate 200 are both P-type, and the conductivity type of the first injection region 204 between the two is N-type. Therefore, a channel region can also be formed between the gate contact region 212 and the substrate 200. Specifically, the first injection region 204 between the gate contact region 212 and the substrate 200 can form a channel region, and the channel region between the gate contact region 212 and the substrate 200 is pinched off at the same time through the gate contact region 212 and the substrate 200 and the channel spacers 205 on both sides of the first injection region 204. The arrow in Figure 9 indicates the direction in which the depletion layer pinches off the channel region between the gate contact region 212 and the substrate 200.

[0090] This completes the description of the key steps of the method for preparing the semiconductor device of the present invention. The preparation of a complete semiconductor device may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0091] In summary, the method for fabricating a semiconductor device according to an embodiment of the present invention forms multiple channel spacers, with a space between each two channel spacers to form a channel region. Each channel region connects the source contact region and the drain contact region to form a current channel, that is, multiple current channels can be formed. While adjusting the pinch-off voltage of the device by adjusting the width of the channel region, it can ensure that the device has a sufficiently high on-current when it is turned on, thereby reducing the on-resistance of the device, reducing the power consumption of the device, and improving the device performance. For example, when the depth of the channel spacer is less than the depth of the drift region, a channel region is also formed between the channel spacer and the substrate, and a current channel can also be formed, thereby further improving the on-current of the device. For example, the drain contact region and the gate contact region are annular, with the gate contact region surrounding the outside of the source contact region, and the drain contact region surrounding the outside of the gate contact region; or, the source contact region and the gate contact region are annular, with the gate contact region surrounding the outside of the drain contact region, and the source contact region surrounding the outside of the gate contact region. This annular surrounding structure can effectively save device area. Exemplarily, the second gate structure can form a biased field plate structure with the first field oxide layer, which can increase the average electric field in the drift region and reduce the electric field peak, thereby achieving the purpose of suppressing the hot carrier effect and increasing the breakdown voltage; the second gate structure can form a floating field plate structure with the first field oxide layer, so that the electric field distribution in the drift region is more uniform, ensuring that the corners where the electric field is concentrated are not easily broken down, thereby further improving the breakdown voltage.

[0092] Example 2

[0093] The present invention further provides a semiconductor device, which can be manufactured by the method of the aforementioned embodiment 1. Specifically, as shown in FIG2J , the semiconductor device includes:

[0094] a substrate 200 having a first conductivity type;

[0095] a drift region 202 extending from the first surface of the substrate 200 into the substrate 200 , the drift region 202 having a second conductivity type;

[0096] a plurality of channel spacers 205 located in the drift region 202 and exposed to the first surface of the substrate, wherein a gap exists between every two channel spacers 205 to form a channel region, and the channel spacers 205 have a first conductivity type;

[0097] A source contact region 211, a drain contact region 210, and a gate contact region 212 are located in the drift region 202. The gate contact region 212 is located between the source contact region 211 and the drain contact region 210. A channel region connects the source contact region 211 and the drain contact region 210. The source contact region 211 and the drain contact region 210 have the second conductivity type, and the gate contact region 212 has the first conductivity type.

[0098] The substrate contact region 213 extends from the first surface of the substrate 200 into the substrate 200 and is spaced apart from the drift region 202 . The substrate contact region 213 has a first conductivity type.

[0099] For example, the substrate 200 may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, or the substrate 200 may also include silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form the substrate 200 are described herein, any material that can be used as the substrate 200 falls within the spirit and scope of the present application.

[0100] Exemplarily, the first conductivity type may be N-type, and the second conductivity type may be P-type; or the first conductivity type may also be P-type, and in this case the second conductivity type may be N-type.

[0101] In one example, as shown in FIG2J , the semiconductor device of the present application further includes a first implantation region 204 located in the drift region 202, wherein the first implantation region 204 has the second conductivity type. For example, when the first implantation region 204 is formed in the drift region 202, the space between every two channel spacers 205 is the first implantation region 204, or in other words, the first implantation region 204 between every two channel spacers 205 is the channel region.

[0102] In one example, the depth of the channel spacer 205 is less than the depth of the drift region 202. Furthermore, the depth of the channel spacer 205 is also less than the depth of the first implant region 204. In this case, the first implant region 204 and the drift region 202 between the channel spacer 205 and the substrate 200 also serve as channel regions. In other examples, the depth of the channel spacer 205 may also be greater than or equal to the depth of the drift region 202.

[0103] In one example, the semiconductor device of the present application further includes a shallow trench isolation structure 201, which is located between active regions of the device. Exemplarily, a substrate contact region 213 is located between the shallow trench isolation structures 201. Exemplarily, a drift region 202 is located within the active region of the device.

[0104] In one example, the semiconductor device of the present application also includes a first field oxide layer 2031 and a second field oxide layer 2032 located in the drift region 202, wherein the first field oxide layer 2031 is located between the gate contact region 212 and the drain contact region 210, and the second field oxide layer 2032 is located between the gate contact region 212 and the source contact region 211; at the same time, the semiconductor device of the present application also includes a first gate structure 2091 and a second gate structure 2092, wherein the first gate structure 2091 is located on the first field oxide layer 2031 and partially extends onto the drift region 202, and the second gate structure 2092 is located on the first field oxide layer 2031 and on the side of the first gate structure 2091 close to the drain contact region 210.

[0105] In one example, both the first gate structure 2091 and the second gate structure 2092 include a gate layer and sidewall spacers located on both sides of the gate layer.

[0106] In one example, the gate contact region 212 and the first gate structure 2091 are electrically connected to the same external metal layer via contact plugs to form a gate. That is, the gate contact region 212 and the first gate structure 2091 are electrically connected via the contact plugs, so that when a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a biased field plate structure to increase the average electric field in the drift region 202 and reduce the electric field peak, thereby achieving the purposes of suppressing hot carrier effects and improving breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure, that is, the second gate structure 2092 does not need to be connected to an external electrode. The second gate structure 2092 can form a floating field plate structure with the first field oxide layer 2031, making the electric field distribution in the drift region 202 more uniform, ensuring that the corners where the electric field is concentrated are not easily broken down, thereby further improving the breakdown voltage.

[0107] In one example, the gate contact region 212 and the first gate structure 2091 are electrically connected to the same external metal layer via contact plugs to form a gate. That is, the gate contact region 212 and the first gate structure 2091 are electrically connected via the contact plugs, so that when a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a biased field plate structure to increase the average electric field in the drift region 202 and reduce the electric field peak, thereby achieving the purposes of suppressing hot carrier effects and improving breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure, that is, the second gate structure 2092 does not need to be connected to an external electrode. The second gate structure 2092 can form a floating field plate structure with the first field oxide layer 2031, making the electric field distribution in the drift region 202 more uniform, ensuring that the corners where the electric field is concentrated are not easily broken down, thereby further improving the breakdown voltage.

[0108] In one example, as shown in FIG2J , contact plug 214 further electrically connects source contact region 211 with an external metal layer to form a source, further electrically connects drain contact region 210 with an external metal layer to form a drain, and further electrically connects substrate contact region 213 with an external metal layer to lead substrate 200 out to form a substrate terminal. Exemplarily, materials for contact plug 214 include, but are not limited to, copper, tungsten, gold, silver, aluminum, and the like.

[0109] In one example, as shown in FIG2F , the semiconductor device of the present application further includes a source-tapered region 208 and a drain-tapered region 207 located in the drift region 202. A source contact region 211 is located in the source-tapered region 208, and a drain contact region 210 is located in the drain-tapered region 207. The source-tapered region 208 and the drain-tapered region 207 have the second conductivity type. Exemplarily, the doping concentration of the source-tapered region 208 is lower than the doping concentration of the source contact region 211, and the doping concentration of the drain-tapered region 207 is lower than the doping concentration of the drain contact region 210. By forming the source-tapered region 208 and the drain-tapered region 207, the antistatic performance of the device can be enhanced, and the phenomenon of excessive carrier concentration can be effectively reduced, thereby effectively alleviating the thermoelectric effect.

[0110] In one example, as shown in FIG. 2E , the semiconductor device of the present application further includes a second implantation region 206 , the substrate contact region 213 is located in the second implantation region 206 , and the second implantation region 206 has the first conductivity type.

[0111] In one example, as shown in FIG2J and FIG4 , the drain contact region 210 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the source contact region 211, and the drain contact region 210 surrounds the outside of the gate contact region 212; or, as shown in FIG3 , the source contact region 211 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the drain contact region 210, and the source contact region 211 surrounds the outside of the gate contact region 212. FIG3 shows a cross-sectional view of a semiconductor device obtained by another embodiment of the present application, which can achieve the same function as the semiconductor device obtained by FIG2A to FIG2J . This overall annular surrounding structure can effectively save device area. For example, at this time, the first gate structure 2091 and the second gate structure 2092 also have an annular structure. For example, as shown in FIG5 , the gate contact region 212 may also be located in the channel spacer region 205 instead of in the first implantation region 204 . In this case, the gate contact region 212 is in a ring shape with intervals arranged therebetween.

[0112] In one example, the pinch-off voltage of the device can be adjusted by adjusting the width of the channel region between the channel spacers 205 to meet actual needs.

[0113] 5 , the gate contact region 212 may be located in the channel spacer 205 but not in the first implant region 204 . Alternatively, as shown in FIG6 , the gate contact region 212 may be located in both the channel spacer 205 and the first implant region 204 .

[0114] In one example, as shown in Figures 4, 5 and 6, taking the case where the first conductivity type is P-type and the second conductivity type is N-type as an example, when no reverse bias voltage is applied to the gate and substrate ends, current can flow from the source through the channel region between the channel spacer regions 205 to the drain. Since the present application forms channel regions between the channel spacer regions 205, multiple current channels can be formed, thereby ensuring that the device can still have a higher on-state current when having a smaller pinch-off voltage, thereby reducing the on-state resistance of the device, reducing the power consumption of the device, and improving the device performance. When a reverse bias voltage is applied to the gate and substrate ends, the depletion layer between the channel spacer region 205 and the channel region gradually widens until it completely fills the channel region. At this time, the channel region is pinched off and the device is also in a pinch-off state. The arrows shown in Figures 5 and 6 are the directions in which the depletion layer pinches off the channel region.

[0115] For example, as shown in FIG7 , when the depth of the channel spacer 205 is less than the depth of the drift region 202, a channel region can be formed between the channel spacer 205 and the substrate 200. The channel region between the channel spacer 205 and the substrate 200 can also form a current path, thereby further improving the on-current of the device. The arrow in FIG7 indicates the direction in which the depletion layer pinches off the channel region between the channel spacer 205 and the substrate 200. For example, as shown in FIG8 , when the depth of the channel spacer 205 is equal to or greater than the depth of the drift region 202, a channel region cannot be formed between the channel spacer 205 and the substrate 200.

[0116] In addition, as shown in Figure 9, when the gate contact region 212 is located in the channel spacer region 205 and the first injection region 204, between adjacent channel spacers 205, the conductivity types of the gate contact region 212 and the substrate 200 are both P-type, and the conductivity type of the first injection region 204 between the two is N-type. Therefore, a channel region can also be formed between the gate contact region 212 and the substrate 200. Specifically, the first injection region 204 between the gate contact region 212 and the substrate 200 can form a channel region, and the channel region between the gate contact region 212 and the substrate 200 is pinched off at the same time through the gate contact region 212 and the substrate 200 and the channel spacers 205 on both sides of the first injection region 204. The arrow in Figure 9 indicates the direction in which the depletion layer pinches off the channel region between the gate contact region 212 and the substrate 200.

[0117] Illustratively, the semiconductor device of the present application includes a JFET device, which may be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the application is mainly explained and illustrated by taking the case where the semiconductor device is a JFET device as an example.

[0118] This concludes the introduction to the structure of the semiconductor device of the present invention. A complete device may also include other components, which will not be detailed here.

[0119] Example 3

[0120] Another embodiment of the present invention provides an electronic device including the aforementioned semiconductor device.

[0121] The electronic device of this embodiment can be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigation system, camera, camcorder, voice recorder, MP3, MP4, PSP, or any other intermediate product that includes the semiconductor device. The electronic device of this embodiment of the present invention, due to the use of the semiconductor device described above, has improved performance.

[0122] Although a number of embodiments have been described herein, it should be understood that a variety of other modifications and embodiments may be devised by those skilled in the art, all of which fall within the spirit and scope of the concepts disclosed herein. More particularly, various modifications and changes may be made to the arrangements and / or component parts of the subject matter within the scope of the present disclosure, the accompanying drawings, and the appended claims. In addition to modifications and changes to the component parts and / or arrangements, the use of alternatives will also be readily apparent to those skilled in the art.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; a drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type; a plurality of channel spacers located in the drift region and exposed to the first surface, wherein a gap exists between every two adjacent channel spacers to form a channel region, and the channel spacers have a first conductivity type; A source contact region, a drain contact region, and a gate contact region are located in the drift region, the gate contact region is located between the source contact region and the drain contact region, the channel region communicates with the source contact region and the drain contact region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type; A substrate contact region is located in the substrate and spaced apart from the drift region, and the substrate contact region has the first conductivity type.

2. The semiconductor device according to claim 1, wherein The drain contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or, The source contact region and the gate contact region are ring-shaped. The gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

3. The semiconductor device according to claim 1, wherein Also includes: A first field oxide layer and a second field oxide layer are located in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region; A first gate structure and a second gate structure, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

4. The semiconductor device according to claim 3, wherein The second gate structure is a floating gate structure.

5. The semiconductor device according to claim 1, wherein It also includes a source graded region and a drain graded region located in the drift region, the source contact region is located in the source graded region, the drain contact region is located in the drain graded region, and the source contact region and the drain contact region have the second conductivity type.

6. A method for preparing a semiconductor device, characterized in that: The method comprises: providing a substrate having a first conductivity type; forming a drift region extending from the first surface of the substrate into the substrate, the drift region having a second conductivity type; forming a plurality of channel spacer regions of the first conductivity type in the drift region, wherein a gap exists between every two channel spacer regions to form a channel region; A source contact region, a drain contact region and a gate contact region with a first conductivity type are formed in the drift region, and a substrate contact region with a first conductivity type is formed in the substrate, wherein the substrate contact region and the drift region are spaced apart from each other, wherein the gate contact region is located between the source contact region and the drain contact region, and the channel region connects the source contact region and the drain contact region.

7. The preparation method according to claim 6, characterized in that The drain contact region and the gate contact region are ring-shaped, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region; or, The source contact region and the gate contact region are ring-shaped. The gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

8. The preparation method according to claim 6, characterized in that The method further comprises: forming a first field oxide layer and a second field oxide layer in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region; A first gate structure and a second gate structure are formed, wherein the first gate structure is located on the first field oxide layer and partially extends onto the drift region, and the second gate structure is located on the first field oxide layer and on a side of the first gate structure close to the drain contact region.

9. The preparation method according to claim 8, characterized in that The second gate structure is a floating gate structure.

10. The preparation method according to claim 6, characterized in that Before forming the source contact region and the drain contact region, the method further includes: A source graded region and a drain graded region of the second conductivity type are formed in the drift region, the source contact region is located in the source graded region, and the drain contact region is located in the drain graded region.

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