Semiconductor device and method for producing semiconductor device

Abstract

Provided are a transistor having favorable electrical characteristics, a transistor having a large on-state current, and a transistor having low parasitic capacitance. A semiconductor device according to the present invention comprises: an oxide semiconductor layer; a first electroconductive layer; a second electroconductive layer; a third electroconductive layer; a first insulating layer over the first electroconductive layer; a second insulating layer over the oxide semiconductor layer and the first insulating layer; and a third electroconductive layer over the second insulating layer. The first insulating layer and the second electroconductive layer have a first opening at a position overlapping the first electroconductive layer. The second electroconductive layer has a first layer and a second layer covering the upper surface and side surface of the first layer. The oxide semiconductor layer has a portion positioned over the second layer, a portion positioned over the first electroconductive layer within the first opening, a portion covering a side wall of the first insulating layer within the first opening, and a portion opposing the side surface of the first layer with the second layer sandwiched therebetween within the first opening. The third electroconductive layer opposes the oxide semiconductor layer with the second insulating layer sandwiched therebetween within the first opening.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, a display device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have integrated circuits (including transistors and memories) formed as chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in an off state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] In addition, with the recent trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in an overlapping manner. Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0011] An object of one embodiment of the present invention is to provide a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a transistor with large on-state current.An object of one embodiment of the present invention is to provide a transistor with small parasitic capacitance.An object of one embodiment of the present invention is to provide a highly reliable transistor, semiconductor device, memory device, or display device.An object of one embodiment of the present invention is to provide a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a semiconductor device, memory device, or display device with low power consumption.An object of one embodiment of the present invention is to provide a memory device with high operating speed.An object of one embodiment of the present invention is to provide a display device with high definition or a high aperture ratio.An object of one embodiment of the present invention is to provide a manufacturing method of the transistor, semiconductor device, memory device, or display device.

[0012] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0013] One embodiment of the present invention includes an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer, wherein the first insulating layer is located over the first conductive layer, and the second conductive layer is located over the first insulating layer, and the first insulating layer and the second conductive layer have a first opening at a position overlapping with the first conductive layer, and the second conductive layer includes a first layer and a second layer over the first layer, and the second layer has a portion covering a top surface of the first layer, a portion covering a side surface of the first layer, and the oxide semiconductor layer has a portion located on the second layer, a portion located on the first conductive layer within the first opening, a portion covering the sidewall of the first insulating layer within the first opening, and a portion facing a side surface of the first layer within the first opening with the second layer sandwiched therebetween; the second insulating layer is located on the oxide semiconductor layer; the third conductive layer is located on the second insulating layer, and the third conductive layer faces the oxide semiconductor layer within the first opening with the second insulating layer sandwiched therebetween.

[0014] In the above aspect, it is preferable that the first conductive layer has a first recess, and the first openings of the first insulating layer and the second conductive layer overlap with the first recess.

[0015] In the above embodiment, it is preferable that the first layer contains a metal or an alloy, and the second layer contains a conductive material containing oxygen or a conductive material containing nitrogen.

[0016] In the above embodiment, it is preferable that the first layer contains tungsten, and the second layer contains indium tin oxide containing silicon.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a first insulating layer over a first conductive layer; forming a second conductive layer over the first insulating layer; removing part of the second conductive layer and part of the first insulating layer to form a first opening reaching the first conductive layer and exposing a top surface of the first conductive layer; forming a third conductive layer to cover the top surface of the second conductive layer and a side surface of the second conductive layer in the first opening; forming a first oxide semiconductor layer to cover the top surface of the first conductive layer, the side surface of the first insulating layer in the first opening, the side surface of the third conductive layer, and a top surface of the third conductive layer; forming a third insulating layer over the first oxide semiconductor layer; and forming a fourth conductive layer over the third insulating layer.

[0018] In the above aspect, in forming the first opening, it is preferable that a portion of the second conductive layer is removed using a dry etching process, and that after the dry etching process and before forming the third conductive layer, a portion of the upper end of the first opening in the second conductive layer is removed using a reverse sputtering process.

[0019] In the above aspect, it is preferable that, in forming the first opening, a recess overlapping the first opening is formed in the first conductive layer.

[0020] In the above embodiment, it is preferable that the third conductive layer contains a conductive material containing oxygen or a conductive material containing nitrogen, and is formed by a sputtering method.

[0021] In the above embodiment, it is preferable that the third conductive layer contains indium tin oxide containing silicon and be formed by a sputtering method.

[0022] According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a transistor with large on-state current can be provided. According to one embodiment of the present invention, a transistor with small parasitic capacitance can be provided. According to one embodiment of the present invention, a highly reliable transistor, semiconductor device, memory device, or display device can be provided. According to one embodiment of the present invention, a transistor, semiconductor device, or memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device, memory device, or display device with low power consumption can be provided. According to one embodiment of the present invention, a memory device with high operating speed can be provided. According to one embodiment of the present invention, a display device with high definition or a high aperture ratio can be provided. According to one embodiment of the present invention, a manufacturing method of the above transistor, semiconductor device, memory device, or display device can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0024] FIGS. 1A and 1B are plan views showing an example of a semiconductor device. FIGS. 1C to 1E are cross-sectional views showing an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views showing an example of a semiconductor device. FIG. 3 is a cross-sectional view showing an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing an example of a semiconductor device. FIGS. 5A to 5D are cross-sectional views showing an example of a semiconductor device. FIGS. 6A to 6D are cross-sectional views showing an example of a semiconductor device. FIG. 7 is a cross-sectional view showing an example of a semiconductor device. FIGS. 8A to 8C are cross-sectional views showing an example of a semiconductor device. FIGS. 9A to 9C are cross-sectional views showing an example of a semiconductor device. FIGS. 10A to 10D are cross-sectional views showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIG. 12 is a cross-sectional view showing an example of a semiconductor device. FIGS. 13A and 13B are cross-sectional views showing an example of a semiconductor device. FIGS. 14A and 14B are cross-sectional views showing an example of a semiconductor device. FIGS. 15A to 15C are cross-sectional views showing an example of a semiconductor device. FIG. 16 is a cross-sectional view showing an example of a semiconductor device. 17A and 17B are cross-sectional views showing an example of a semiconductor device. FIG. 18A is a plan view showing an example of a semiconductor device. FIGS. 18B and 18C are cross-sectional views showing an example of a semiconductor device. FIG. 19A is a plan view showing an example of a semiconductor device. FIGS. 19B and 19C are cross-sectional views showing an example of a semiconductor device. FIGS. 20A and 20B are cross-sectional views showing an example of a semiconductor device. FIGS. 21A to 21C are cross-sectional views showing an example of a semiconductor device. FIG. 22A is a plan view showing an example of a semiconductor device. FIGS. 22B and 22C are cross-sectional views showing an example of a semiconductor device. FIGS. 23A and 23B are cross-sectional views showing an example of a semiconductor device. FIGS. 24A and 24B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 25A and 25B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 26A and 26B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 27A to 27C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIGS. 28A and 28B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. 29A and 29B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.30A and 30B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 31A is a plan view illustrating an example of a memory device. FIGS. 31B and 31C are cross-sectional views illustrating an example of a memory device. FIGS. 32A and 32B are cross-sectional views illustrating an example of a memory device. FIG. 33A is a plan view illustrating an example of a memory device. FIG. 33B is a cross-sectional view illustrating an example of a memory device. FIG. 34 is a cross-sectional view illustrating an example of a memory device. FIG. 35 is a cross-sectional view illustrating an example of a memory device. FIG. 36 is a block diagram illustrating a structural example of a semiconductor device. FIGS. 37A to 37G are diagrams illustrating an example of a circuit structure of a memory cell. FIGS. 38A and 38B are perspective views illustrating an example of a structure of a semiconductor device. FIG. 39 is a block diagram illustrating a CPU. FIGS. 40A and 40B are perspective views of a semiconductor device. FIGS. 41A and 41B are perspective views of a semiconductor device. FIGS. 42A and 42B are circuit diagrams of a semiconductor device according to one embodiment of the present invention, and FIG. 42C is a diagram illustrating an example of an electronic component using a semiconductor device according to one embodiment of the present invention.

[0111] Figs. 43A and 43B are perspective views showing an example of a display device. Fig. 44 is a cross-sectional view showing an example of a display device. Fig. 45 is a cross-sectional view showing an example of a display device. Figs. 46A to 46C are diagrams showing an example of the configuration of a display device. Fig. 47 is a diagram showing an example of an electronic component. Figs. 48A to 48C are a diagram showing an example of a mainframe computer. Fig. 48D is a diagram showing an example of space equipment. Fig. 48E is a diagram showing an example of a storage system applicable to a data center. Figs. 49A to 49F are diagrams showing an example of electronic equipment. Figs. 50A to 50G are diagrams showing an example of electronic equipment. Figs. 51A to 51F are diagrams showing an example of electronic equipment. Fig. 52A shows a STEM image. Fig. 52B shows the results of EDX analysis. Fig. 53A shows a STEM image. Fig. 53B shows the results of EDX analysis. Fig. 54A shows a STEM image. Fig. 54B shows the results of EDX analysis. Fig. 55 shows the results of resistance measurement.

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0026] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0027] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0028] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0029] A transistor is a type of semiconductor element that can amplify current or voltage, and perform a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0030] In this specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer and a transistor having an oxide semiconductor or a metal oxide for a channel formation region may be referred to as an OS transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0031] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0032] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0033] Note that impurities in a semiconductor refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities may increase the density of defect states in the semiconductor or reduce the crystallinity, for example. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water may also function as an impurity. For example, the inclusion of impurities may cause oxygen deficiency (V) in the oxide semiconductor. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0034] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0035] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical techniques.

[0036] In this specification and the like, the term "content" refers to the ratio of a component contained in a film. For example, when an oxide semiconductor layer contains a metal element X, a metal element Y, and a metal element Z, the number of atoms of each of the metal elements X, Y, and Z contained in the oxide semiconductor layer is expressed as A Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the oxide semiconductor layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0037] The terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0038] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0039] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0040] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0042] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0043] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0044] In this specification, the term "normally-on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the term "normally-off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0045] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0046] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0047] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0048] In this specification and the like, a structure in which different light-emitting layers are formed for light-emitting elements (also referred to as light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0049] In this specification and the like, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or an electron injection layer may be referred to as a "carrier injection layer," a hole transport layer or an electron transport layer may be referred to as a "carrier transport layer," and a hole block layer or an electron block layer may be referred to as a "carrier block layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Furthermore, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

[0050] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (a hole injection layer and an electron injection layer), a carrier transport layer (a hole transport layer and an electron transport layer), and a carrier block layer (a hole block layer and an electron block layer). In this specification and the like, one of the pair of electrodes may be referred to as a pixel electrode, and the other may be referred to as a common electrode.

[0051] In this specification and the like, the sacrificial layer (which may also be referred to as a mask layer) is located above at least the light-emitting layer (more specifically, a layer that is processed into an island shape among the layers that make up the EL layer), and has the function of protecting the light-emitting layer during the manufacturing process.

[0052] In this specification and the like, the term "step discontinuity" refers to a phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0053] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0054] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described.

[0055] A semiconductor device according to one embodiment of the present invention includes a transistor, an oxide semiconductor layer, first to third conductive layers, and first and second insulating layers.

[0056] The oxide semiconductor layer functions as a semiconductor layer of a transistor, the first conductive layer functions as one of a source electrode and a drain electrode of the transistor, the second conductive layer functions as the other of the source electrode and the drain electrode of the transistor, and the third conductive layer functions as a gate electrode of the transistor. The second insulating layer functions as a gate insulating layer of the transistor.

[0057] A first insulating layer is located on the first conductive layer, and a second conductive layer is located on the first insulating layer.

[0058] In the transistor of one embodiment of the present invention, the source electrode and the drain electrode are located at different heights (for example, heights in a direction perpendicular to a substrate surface or an insulating plane on which the transistor is provided), and a current flows in the height direction through the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel transistor.

[0059] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0060] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thickness of the first insulating layer, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0061] Furthermore, since a transistor including an oxide semiconductor has a small off-state current, when used in a memory device, for example, stored data can be retained for a long time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, high integration and low power consumption of the memory device can be achieved.

[0062] <Structural Example 1-1 of Semiconductor Device> A structure of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 8B. FIG.

[0063] FIG. 1A is a plan view of a semiconductor device having a transistor 200. FIG. 1B is a plan view showing an example in which a plurality of transistors 200 are arranged. FIG. 1C is a cross-sectional view taken along dashed dotted line A1-A2 in FIG. 1A. FIG. 1D is a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 1A. FIG. 1E is a cross-sectional view taken along dashed dotted line A5-A6 in FIGS. 1C and 1D. FIG. 1E is a view seen from the Z direction. Note that some elements are omitted in the plan views of FIGS. 1A and 1B for clarity. Some elements may also be omitted in the subsequent plan views.

[0064] Fig. 2A is a cross-sectional view taken along dashed line A3-A4 in Fig. 1A. Fig. 2B is an enlarged view of Fig. 1E. Figs. 2A and 2B correspond to examples of enlarged views of Figs. 1D and 1E, respectively.

[0065] 1A to 2B includes an insulating layer 210 over a substrate (not shown), a transistor 200 over the insulating layer 210, and an insulating layer 280 over the insulating layer 210. The insulating layer 210 and the insulating layer 280 function as interlayer films.

[0066] [Transistor 200] The transistor 200 includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The insulating layer 280 is located over the conductive layer 220.

[0067] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode. The conductive layer 260 has a region that functions as a gate wiring.

[0068] As shown in FIGS. 1C and 1D, an opening 290 is provided in the insulating layer 280 and the conductive layer 240, reaching the conductive layer 220.

[0069] 3 shows a diagram in which the hatching patterns of components other than the oxide semiconductor layer 230 in FIG. 2A are omitted. As shown in FIG. 3 , the opening 290 includes an opening 290a in the insulating layer 280 and an opening 290b in the conductive layer 240. The opening 290a in the region where the insulating layer 280 overlaps with the conductive layer 220 is part of the opening 290, and the opening 290b in the region where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290.

[0070] As shown in FIG. 3, a recess 290c is provided in the conductive layer 220_2.

[0071] The opening 290 overlaps with the recess 290c in the conductive layer 220_2. Here, the bottom of the opening 290 includes the bottom surface of the recess 290c in the conductive layer 220_2, and the sidewall of the opening 290 includes the side surface of the recess in the conductive layer 220_2, the side surface of the opening 290a in the insulating layer 280, and the side surface of the opening 290b in the conductive layer 240.

[0072] The shape and size of the opening 290 in a plan view may differ depending on the layer. When the top surface shape of the opening 290 is circular, the openings in each layer may or may not be concentric.

[0073] At least some of the components of the transistor 200 are disposed within the opening 290. Specifically, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed so that at least some of them are located within the opening 290. Furthermore, the portions of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 that are disposed within the opening 290 are provided so as to reflect the shape of the opening 290.

[0074] The oxide semiconductor layer 230 is provided so as to cover the bottom and sidewalls of the opening 290. The oxide semiconductor layer 230 also has a recess that reflects the shape of the opening 290.

[0075] The conductive layer 240 can function as a wiring of the semiconductor device. By increasing the conductivity of the conductive layer 240, the characteristics of the semiconductor device can be improved. For example, the operating speed can be increased. Therefore, it is preferable to use a highly conductive material for the conductive layer 240.

[0076] The conductive layer 240 can function as one of a source and a drain of a transistor. The conductive layer 240 has a region in contact with the oxide semiconductor layer 230. Therefore, the conductive layer 240 preferably has low contact resistance with the oxide semiconductor layer 230.

[0077] 1C and 1D show an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. The conductive layer 240_1 is made of, for example, a material with high conductivity, and the conductive layer 240_2 is made of, for example, a material with low contact resistance with the oxide semiconductor layer 230.

[0078] Here, the material used for the conductive layer 240_1 may have a property of extracting oxygen from the oxide semiconductor layer 230. For example, when a metal material is used for the conductive layer 240_1, there is a concern that oxygen in the oxide semiconductor layer 230 might be extracted by the conductive layer 240_1.

[0079] On the other hand, examples of materials that can be suitably used for the conductive layer 240_2 include conductive materials containing oxygen, which can remain stable even when in contact with the oxide semiconductor layer 230, and therefore oxygen is unlikely to be extracted from the oxide semiconductor layer 230 by the conductive layer 240_2.

[0080] In one embodiment of the present invention, the conductive layer 240_2 preferably covers at least part of the side surface of the conductive layer 240_1 on the opening 290 side. This can reduce the area in which the oxide semiconductor layer 230 is in contact with the conductive layer 240_1. When the conductive layer 240_1 has a property of extracting oxygen from the oxide semiconductor layer 230, oxygen vacancies (V Ｏ In addition, an increase in the electrical resistance of the conductive layer 240 due to oxidation of the conductive layer 240 caused by extraction of oxygen from the oxide semiconductor layer 230 can be suppressed.

[0081] The conductive layer 240_2 covers at least a part of the side surface of the conductive layer 240_1 in the opening 290b. The side surface of the conductive layer 240_2 constitutes at least a part of the side surface of the opening 290b in the conductive layer 240. Furthermore, as shown in FIG. 4B described later, when the side surface of the conductive layer 240_1 has a region that is not covered with the conductive layer 240_2, the region constitutes a part of the side surface of the opening 290b in the conductive layer 240.

[0082] The insulating layer 250 is provided to cover the oxide semiconductor layer 230. The insulating layer 250 is provided on the insulating layer 280 to cover the top surface and side surfaces of the oxide semiconductor layer 230. The insulating layer 250 has a recess that reflects the shape of the recess that the oxide semiconductor layer 230 has.

[0083] The conductive layer 260 is provided so as to fill at least a part of the recessed portion of the insulating layer 250. The conductive layer 260 has a region in the opening 290 that faces the oxide semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0084] 1C and 1D show an example in which the conductive layer 220 has a two-layer structure of a conductive layer 220_1 and a conductive layer 220_2 on the conductive layer 220_1, and the conductive layer 260 has a two-layer structure of a conductive layer 260_1 and a conductive layer 260_2 on the conductive layer 260_1.

[0085] The oxide semiconductor layer 230 has a region facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween. At least part of the region functions as a channel formation region of the transistor 200. A region of the oxide semiconductor layer 230 near the conductive layer 220 functions as one of a source region and a drain region, and a region of the oxide semiconductor layer 230 near the conductive layer 240 functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region.

[0086] The oxide semiconductor layer 230 is provided inside the opening 290. The transistor 200 has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, so that current flows vertically. That is, a channel is formed along the side surface of the opening 290.

[0087] For example, at least part of a region of the oxide semiconductor layer 230 that is in contact with the conductive layer 240 can function as the other of the source region and the drain region of the transistor.

[0088] For example, at least part of a region of the oxide semiconductor layer 230 that is not in contact with the conductive layer 240 can function as a channel formation region of a transistor.

[0089] Note that due to convenience of the manufacturing process, a conductor derived from the material of the conductive layer 240 might remain inside the opening 290 between the oxide semiconductor layer 230 and the insulating layer 280. The conductor has, for example, at least one material in common with the conductive layer 240. In such a case, the remaining conductor is preferably insulated from a region in the conductive layer 240 that serves as the other of the source electrode and the drain electrode. For example, the remaining conductor is preferably separated from a region in the conductive layer 240 that serves as the other of the source electrode and the drain electrode.

[0090] The transistor 200 includes the oxide semiconductor layer 230 in a channel formation region. That is, the transistor 200 can be said to be an OS transistor.

[0091] When oxygen vacancies and impurities exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0092] The extraction of oxygen from the oxide semiconductor layer 230 by the conductive layer 240 can be a cause of oxygen vacancies in the oxide semiconductor layer 230. Therefore, it is preferable to use a material that is resistant to oxidation for the conductive layer 240. More specifically, for example, a material that is resistant to oxidation is used for at least a part of the region of the conductive layer 240 that is in contact with the oxide semiconductor layer 230.

[0093] The conductive layer 240_2 has a larger area in contact with the oxide semiconductor layer 230 than the conductive layer 240_1. The conductive layer 240_2 is preferably less likely to be oxidized than the conductive layer 240_1 when in contact with the oxide semiconductor layer 230. This can suppress extraction of oxygen from the oxide semiconductor layer 230 by the conductive layer 240. The conductive layer 240_2 is preferably made of, for example, a conductive material that is less likely to be oxidized or a conductive material that has a function of suppressing diffusion of oxygen.

[0094] The conductive layer 240_2 is preferably made of a conductive material that keeps low electrical resistance even when in contact with the oxide semiconductor layer 230. For example, the conductive layer 240_2 is preferably made of a conductive material that keeps low electrical resistance even when oxidized.

[0095] The conductive layer 240_2 can be formed using a conductive material containing oxygen, a conductive material containing nitrogen, or the like. A conductive metal oxide (also referred to as an oxide conductor) can be preferably used for the conductive layer 240_2. For example, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (In—Si—Sn oxide, also referred to as ITSO), indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)), or the like can be preferably used for the conductive layer 240_2.

[0096] It is preferable to use a conductive material with low electrical resistance for the conductive layer 240_1. For the conductive layer 240_1, a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or the like, an alloy containing the above metal element, or an alloy combining the above metal elements, can be used. Using a conductive material with low electrical resistance for the conductive layer 240_1 is preferable because it can increase the circuit operation speed when the conductive layer 240 is used for wiring, etc. The conductive layer 240_1 is, for example, a conductive material with lower electrical resistance than the conductive layer 240_2. For example, tungsten, copper, aluminum, an alloy containing aluminum, or the like can be preferably used for the conductive layer 240_1.

[0097] A low-resistance material used for the conductive layer 240_1 may be more easily oxidized than the conductive layer 240_2 when in contact with the oxide semiconductor layer 230. There is a concern that the electrical resistance of the conductive layer 240_1 may increase due to oxidation of the conductive layer 240_1.

[0098] In the semiconductor device of one embodiment of the present invention, the contact area between the region that is easily oxidized in the conductive layer 240 and the oxide semiconductor layer 230 is reduced, whereby the conductivity of the conductive layer 240 can be increased and oxygen vacancies in the channel formation region of the oxide semiconductor layer 230 can be reduced.

[0099] Note that oxygen vacancies in the oxide semiconductor layer 230 can be reduced by supplying oxygen to the oxide semiconductor layer 230 from each layer included in the transistor 200 (e.g., insulating layers such as the insulating layer 250) and each layer disposed around the transistor 200 (e.g., insulating layers such as the insulating layer 280). Consider a case where multiple transistors are arranged in a certain region of a semiconductor device. In this case, when the ratio of the volume of each layer that supplies oxygen to the volume occupied by the transistor 200 decreases, the amount of oxygen supplied to each transistor 200 decreases. As the integration density of a circuit increases, the transistors 200 are arranged more densely, and the amount of oxygen supplied to each transistor 200 decreases. Therefore, in a highly integrated circuit, there is a concern that the extraction of oxygen from the oxide semiconductor layer 230 by the conductive layer 240 may have a more significant effect on the characteristics of the transistor 200.

[0100] The semiconductor device of one embodiment of the present invention can achieve excellent transistor characteristics even when applied to a memory device having a memory cell array with high element density, a display device having a high-definition display portion, or the like.

[0101] The source and drain regions of an OS transistor preferably have a higher carrier concentration and lower resistance than the channel formation region. For example, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The region has a low resistance due to an increased carrier concentration caused by a large amount of H or a high concentration of impurities such as hydrogen, nitrogen, or a metal element. When the conductive layer 240_1 and the oxide semiconductor layer 230 are in appropriate contact with each other, oxygen vacancies for forming source and drain regions can be introduced into the oxide semiconductor layer 230.

[0102] The conductive layer 240_2 is a region of the conductive layer 240 that is mainly in contact with the oxide semiconductor layer 230. Therefore, the conductive layer 240_2 is preferably a material that can form a good bond with the oxide semiconductor layer 230 and has low contact resistance with the oxide semiconductor layer 230. For example, a material that can form ohmic contact with the oxide semiconductor layer 230 can be used as the conductive layer 240_2.

[0103] In the transistor of one embodiment of the present invention, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be preferably reduced in some cases when the conductive layer 240_2 is sandwiched between the oxide semiconductor layer 230 and the conductive layer 240_1 rather than when the oxide semiconductor layer 230 and the conductive layer 240_1 are in direct contact with each other.

[0104] The conductive layer 240_2 is preferably made of a material that can form good bond with the conductive layer 240_1 as well as with the oxide semiconductor layer 230. This can favorably reduce contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.

[0105] The conductive layer 240_1 is preferably formed using any of the above-described materials, and particularly preferably using tungsten for the conductive layer 240_1. The conductive layer 240_2 is preferably formed using any of the above-described materials, and particularly preferably using ITSO for the conductive layer 240_2.

[0106] 16 illustrates an example in which the side surfaces of the conductive layer 240_1 are not covered with the conductive layer 240_2 in the transistor 200. In FIG. 16, the oxide semiconductor layer 230 is in contact with the side surfaces of the openings 290 in the conductive layer 240_1, the side surfaces of the openings 290 in the conductive layer 240_2, and the top surface of the conductive layer 240_2.

[0107] 1C, 1D, 2A, and the like, the conductive layer 240_2 covers at least part of the side surface of the conductive layer 240_1 on the opening 290 side, whereby the area where the oxide semiconductor layer 230 is in contact with the conductive layer 240_1 can be reduced. ＯIn addition, oxidation of the conductive layer 240_1 can be suppressed, and therefore, the effect of suitably reducing the electrical resistance of the conductive layer 240_1 can also be obtained.

[0108] 2A and 3 , by providing a recess in the conductive layer 220_2 at a position overlapping with the opening 290, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be lower than the height of the top surface of the conductive layer 220_2 in contact with the insulating layer 280, relative to the top surface of the insulating layer 210, as compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the top surface of the insulating layer 210 is used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0109] The oxide semiconductor layer 230 is in contact with the bottom surface and side surfaces of the recessed portion of the conductive layer 220_2 and the top surface of the conductive layer 240_2. The recessed portion of the conductive layer 220_2 can increase the area where the oxide semiconductor layer 230 and the conductive layer 220_2 are in contact with each other. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 220_2 can be reduced.

[0110] 1C shows a structure in which the end of the conductive layer 240 and the end of the oxide semiconductor layer 230 are aligned outside the opening 290. The conductive layer 240 and the oxide semiconductor layer 230 can be manufactured by processing using the same mask. This is preferable because the number of masks required for manufacturing a semiconductor device can be reduced. Note that the present invention is not limited to this. For example, a structure may be possible in which any one of the end of the oxide semiconductor layer 230, the end of the conductive layer 240_1, and the end of the conductive layer 240_2 is located inside or outside the other in the X direction or Y direction.

[0111] As described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a display device, the resolution of the display portion can be improved.

[0112] FIG. 1B also shows an example in which a plurality of transistors 200 are arranged in a matrix. Specifically, FIG. 1B shows an example in which 4×4 transistors are arranged in the X and Y directions. As shown in FIG. 1B , the transistor 200 is provided at the intersection of a conductive layer 260 extending in the X direction and a conductive layer 240 extending in the Y direction. As shown in FIG. 1B , the diameter of the opening 290 can be made smaller than both the width of the short side of the conductive layer 240 and the width of the short side of the conductive layer 260. In this way, the transistor 200 can be said to have a structure that allows for high integration and miniaturization.

[0113] As shown in FIG. 2B , the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side surface of the conductive layer 260 located at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire periphery of the oxide semiconductor layer 230 forms a channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the periphery length of the oxide semiconductor layer 230. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIGS. 2A and 2B , the width D of the opening 290 is shown, and in FIG. 2B , the channel width W of the transistor 200 is shown.

[0114] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. On the other hand, the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200, thereby enabling a semiconductor device to be highly integrated.

[0115] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290 in the conductive layer 240 is used as the width D of the opening 290. Alternatively, the width of the opening 290 at the highest position in the conductive layer 240, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290 in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening 290 side may be used as the width D. Alternatively, the width of the opening 290 at the highest position in the insulating layer 280, the width of the opening 290 at the lowest position, the width of the opening 290 at a midpoint between these, or the average value of these three widths may be used as the width D.

[0116] When the opening 290 is formed using photolithography, the width D of the opening 290 is limited by the exposure limit of photolithography. The width D of the opening 290 is set depending on the film thickness of each of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided in the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D × π".

[0117] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 2A , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L can be considered to be the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 face each other and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240 face each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0118] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0119] Note that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 over the conductive layer 220, and therefore the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. Setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less can improve productivity and yield in forming the insulating layer 280, forming the opening 290 in the insulating layer 280, and the like.

[0120] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm or more, 1 nm or more, or 5 nm or more, and is preferably 1 μm or less, 500 nm or less, or 300 nm or less.

[0121] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0122] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the oxide semiconductor layer 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor layer 230 approximately uniformly.

[0123] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle, an approximately circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees). As shown in FIG. 1A and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing accuracy during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0124] 1D shows a configuration in which the lower end of the side surface of the conductive layer 240 in the opening 290 and the upper end of the side surface of the insulating layer 280 in the opening 290 are aligned and form a continuous side surface, but the present invention is not limited to this. For example, the side surface of the conductive layer 240 in the opening 290 and the side surface of the insulating layer 280 in the opening 290 may be discontinuous.

[0125] 4A is an enlarged view of a region Q1 shown in FIG. 2A. The top surface and the side surface of the conductive layer 240_1 on the opening 290 side are covered with the conductive layer 240_2. The conductive layer 240_2 has a region sandwiched between the side surface of the conductive layer 240_1 and the oxide semiconductor layer 230. The oxide semiconductor layer 230 covers the side surface of the conductive layer 240_1 with the conductive layer 240_2 sandwiched therebetween.

[0126] The conductive layer 240_2 can be formed by a method in which the deposition rate is slower on a surface where the surface is perpendicular to the substrate surface than on a surface where the surface is parallel to the substrate surface. Such a deposition method can also be expressed as a deposition method in which the deposition rate is anisotropic. By using such a method, the conductive layer 240_2 is not formed in a region where the sidewall of the opening 290 is steep, but is formed in a region where the sidewall of the opening 290 is gentle and on the top surface of the conductive layer 240_1.

[0127] The upper corner of the conductive layer 240_1 is rounded at the end of the opening 290. The rounded corner makes it easier to cover the rounded region with the conductive layer 240_2.

[0128] Even if a film formation method with anisotropic deposition rate is used, a thin conductive layer that becomes the conductive layer 240_2 may be formed in the region where the sidewalls of the opening 290 are steep. In such a case, after forming the conductive layer, etching may be performed under conditions with a slow etching rate to remove the thin conductive layer formed in the region where the sidewalls are steep, while leaving the conductive layer formed in other regions. This type of etching is sometimes called slight etching. Various techniques, such as dry etching, wet etching, and plasma treatment, may be used for slight etching.

[0129] When part of the conductive layer 240_2 remains between the channel formation region of the oxide semiconductor layer 230 and the sidewall of the insulating layer 280 in the opening 290, the remaining conductive layer is preferably insulated from a region which functions as the other of the source electrode and the drain electrode in the conductive layer 240. For example, the remaining conductive layer is preferably separated from a region which functions as the other of the source electrode and the drain electrode in the conductive layer 240.

[0130] The conductive layer 240_2 can be formed in a self-aligned manner with respect to the top surface and side surface of the conductive layer 240_1 without using a mask by utilizing the anisotropy of the deposition rate. Therefore, there is no need to consider the accuracy of overlay with the conductive layer 240_1, and the area occupied by the transistor 200 is not increased. Therefore, the transistor 200 shown in FIGS. 1A to 2B has a structure suitable for a highly integrated semiconductor device.

[0131] 1A to 2B, the top surface of the insulating layer 210 can be approximately parallel to the substrate surface, and the top surface of the conductive layer 220 can be approximately parallel to the substrate surface.

[0132] The conductive layer 240_2 can be formed by a film formation method having an anisotropic deposition rate. Therefore, when the top surface of the conductive layer 220 is approximately parallel to the substrate surface, a conductor derived from the material of the conductive layer 240_2 may also be formed on the conductive layer 220 during the formation of the conductive layer 240_2. The conductor may, for example, contain at least one material in common with the conductive layer 240_2. The conductor may function as part of the conductive layer 220. In this case, it is preferable that the conductive layer formed on the top surface and side surfaces of the conductive layer 240_1 and functioning as the conductive layer 240_2 is separated from the conductor formed on the top surface of the conductive layer 220. On the other hand, when the width of the opening 290 is small and the aspect ratio of the opening 290 is high, even when the top surface of the conductive layer 220 is approximately parallel to the substrate surface, the conductor derived from the material of the conductive layer 240_2 may not be formed on the top surface of the conductive layer 220, or the coverage of the conductor may be reduced.

[0133] In the configurations shown in FIGS. 1A to 2B , the conductive layer 240_2 is not formed on the top surface of the conductive layer 220 in the opening 290 or on the side surface of the insulating layer 280 at a deep position in the opening 290. By reducing the width of the opening 290, the deposition rate of the conductive layer 240_2 on the sidewall of the opening 290 at a deep position in the opening 290 can be slowed in some cases. For example, a method such as sputtering, which has a high deposition rate and is preferably used as a method for forming a thick conductive layer, has excellent productivity, but may have poor coverage at a deep position in the opening 290 with a high aspect ratio and a small opening diameter. This makes it easier to selectively form the conductive layer 240_2 at the top end of the opening 290 and its vicinity. For example, the width D of the opening 290 may be 100 nm or less, and the channel length L of the transistor 200 may be 0.5 times or more, preferably 0.8 times or more, the width D of the opening.

[0134] When sputtering is used, it is possible to easily coat the deep region of the opening by using a collimated sputtering method, a long-throw sputtering method in which the distance between the target and the substrate is increased, etc. The distance between the target and the substrate can be set in consideration of the width of the opening 290.

[0135] When the conductive layer 240_2 is formed on the top surface of the conductive layer 220, the conductive layer formed on the top surface is preferably separated from a region functioning as the other of the source electrode and the drain electrode in the conductive layer 240. For example, the conductive layer 240_2 may be selectively formed on the top surface of the conductive layer 220 and the top surface and side surfaces of the conductive layer 240_1, and the conductive layer 240_2 may not be formed in a region on the side surface of the opening 290 in the insulating layer 280 that covers the channel formation region of the oxide semiconductor layer 230.

[0136] Furthermore, when a portion of the conductive layer 240_2 is formed on the upper surface of the conductive layer 220, it may be difficult to distinguish the boundary between the two layers depending on the materials used for the uppermost conductive layer of the conductive layer 220 (conductive layer 220_2 in FIGS. 1C, 1D, etc.) and the conductive layer 240_2. For example, when the material of the conductive layer 240_2 and the material of the uppermost layer of the conductive layer 220 are the same, or when some of the elements constituting the materials are the same, it may be difficult to distinguish the portion of the conductive layer 240_2 from the conductive layer 220.

[0137] Note that if sufficient characteristics of the transistor 200 can be obtained, the side surface of the conductive layer 240_1 on the opening 290 side may have a region that is not covered with the conductive layer 240_2. Figure 4B is a modification of Figure 4A, and includes a region Q11 that is not covered with the conductive layer 240_2 on the side surface of the conductive layer 240_1 on the opening 290 side. The structure shown in Figure 4B may make it easier to form the conductive layer 240_2 than the structure shown in Figure 4A.

[0138] 4B , the conductive layer 240_2 covers the side surface of the conductive layer 240_1 from the top to a depth of at least half the thickness of the conductive layer 240_1. For example, as shown in FIG. 4B , the conductive layer 240_2 covers the side surface of the conductive layer 240_1 from the height of the top surface of the conductive layer 240_1 to a depth d_c2, and the value of the depth d_c2 is at least 0.3 times, or at least half (0.5 times) the value of the film thickness t240_1 of the conductive layer 240_1.

[0139] The conductive layer 240_2 is a region of the conductive layer 240 that is mainly in contact with the oxide semiconductor layer 230, and is preferably made of a material that can form a good bond with the oxide semiconductor layer 230, as described above.

[0140] Fig. 5A shows an example in which the cross section shown in Fig. 4A is not rounded. Note that at least some corners may be rounded in the structure shown in Fig. 5A. Fig. 5B shows the insulating layer 280, the conductive layer 240_1, and the conductive layer 240_2 extracted from Fig. 5A, and further shows the conductive layer 220_2.

[0141] In FIG. 5B , the angle between the top surface of the conductive layer 220_2 and the side surface of the conductive layer 240_1 is indicated as angle An1, and the angle between the top surface of the conductive layer 220_2 and the side surface of the insulating layer 280 is indicated as angle An0. Preferably, angles An0 and An1 are greater than 45 degrees and less than 90 degrees, and angle An1 is preferably smaller than angle An0. In FIGS. 5B to 5D , for example, the difference between angle An1 and angle An0 is greater than 0 degrees and less than 10 degrees, or greater than 0 degrees and less than 5 degrees. Also, in FIGS. 5B to 5D , for example, angle An0 is preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees. Angle An1 is preferably greater than 45 degrees and less than 90 degrees, more preferably greater than 45 degrees and less than 85 degrees, and even more preferably greater than 45 degrees and less than 80 degrees.

[0142] 5B shows a configuration in which the conductive layer 240_2 covers the side surface of the conductive layer 240_1, but as shown in Fig. 5C, the lower part of the side surface of the conductive layer 240_1 (the region closer to the insulating layer 280) may not be covered with the conductive layer 240_2. Also, as shown in Fig. 5D, in addition to the side surface of the conductive layer 240_1, the upper part of the side surface of the insulating layer 280 (the region closer to the conductive layer 240_1) may be covered with the conductive layer 240_2.

[0143] Note that angle An1 may be approximately equal to angle An0. For example, the difference between angle An1 and angle An0 may be 0 degrees or greater and less than 5 degrees, or 0 degrees or greater and less than 3 degrees. Figures 6A, 6B, 6C, and 6D show examples in which angle An1 and angle An0 are approximately equal to each other in Figures 5A, 5B, 5C, and 5D.

[0144] 6A to 6D, the side surface of the conductive layer 240_2 protrudes beyond the side surface of the insulating layer 280. Because the side surface of the conductive layer 240_1 is steeper than that of FIGS. 5A to 5D, the conductive layer 240_2 is formed on the side surface of the conductive layer 240_1, resulting in the side surface of the conductive layer 240_2 protruding beyond the side surface of the insulating layer 280. FIG. 6A shows an example in which the angle An1 is approximately perpendicular. In FIGS. 6B to 6D, the angles An0 and An1 are each preferably greater than 75 degrees and less than or equal to 90 degrees, more preferably greater than 80 degrees and less than or equal to 90 degrees, and even more preferably greater than 85 degrees and less than or equal to 90 degrees.

[0145] 6B, the side surface of the conductive layer 240 protrudes by a width Ts compared to the side surface of the insulating layer 280. Therefore, the width of the opening 290 in the conductive layer 240 is narrowed by the protrusion amount.

[0146] Fig. 7 shows an overall image of the opening 290 including the structure shown in Fig. 6A. Note that the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are omitted in Fig. 7.

[0147] The width Dp of the protruding portion of the conductive layer 240 in the opening 290 is narrower than the width D of the opening 290 in the insulating layer 280 by Ts×2. That is, it can be expressed as Dp=D−(Ts×2).

[0148] The conductive layer 240_2 is preferably formed by an anisotropic deposition method, and the thickness Tu of the region covering the top surface of the conductive layer 240_1 is thicker than the width Ts. The width Ts is, for example, preferably greater than 0 and less than 0.8 times the thickness Tu, more preferably greater than 0 and less than 0.5 times the thickness Tu, even more preferably greater than 0 and less than 0.4 times the thickness Tu, and still more preferably greater than 0 and less than 0.3 times the thickness Tu.

[0149] If the width Dp is too narrow, the coverage of the opening 290 with the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 will decrease. Therefore, it is preferable to reduce the difference between the width Dp and the width D. Specifically, since D - Dp = Ts × 2, the difference between the width D and the width Dp (D - Dp) is preferably greater than 0 and less than 1.6 times the thickness Tu, more preferably greater than 0 and less than 1 time the thickness Tu, even more preferably greater than 0 and less than 0.8 times the thickness Tu, and even more preferably greater than 0 and less than 0.6 times the thickness Tu.

[0150] Depending on the film formation conditions and the etching conditions during the formation of the opening 290, the corners of the conductive layer 240_1 and the conductive layer 240_2 may be rounded. FIGS. 8A, 8B, and 8C show examples in which the upper corners of the conductive layer 240_1 and the upper corners of the conductive layer 240_2 are rounded, respectively. FIG. 8B shows an example in which the lower part of the side surface of the conductive layer 240_1 (the region closer to the insulating layer 280) is not covered with the conductive layer 240_2, and FIG. 8C shows an example in which the upper part of the side surface of the insulating layer 280 is covered with the conductive layer 240_2 in addition to the side surface of the conductive layer 240_1. FIG. 8A can correspond to the structure shown in FIG. 4A, for example, and FIG. 8B can correspond to the structure shown in FIG. 4B, for example. In FIGS. 8A to 8C, the difference between the angle An1 and the angle An0 is greater than 0 degrees and less than or equal to 10 degrees, or greater than 0 degrees and less than or equal to 5 degrees, for example. 8A to 8C, for example, angle An0 is preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees; angle An1 is preferably greater than 45 degrees and less than 90 degrees, more preferably greater than 45 degrees and less than 85 degrees, and even more preferably greater than 45 degrees and less than 80 degrees.

[0151] 9A, 9B, and 9C each show an example in which the upper corners of the conductive layer 240_1 in FIGS. 6B to 6D are rounded and the side surfaces of the conductive layer 240_2 protrude beyond the side surfaces of the insulating layer 280. FIG. 9B shows an example in which the lower part of the side surface of the conductive layer 240_1 (the region closer to the insulating layer 280) is not covered with the conductive layer 240_2, and FIG. 9C shows an example in which the upper part of the side surface of the insulating layer 280 is covered with the conductive layer 240_2 in addition to the side surface of the conductive layer 240_1. In FIGS. 9A to 9C, the angles An0 and An1 are each preferably greater than 75 degrees and less than or equal to 90 degrees, more preferably greater than 80 degrees and less than or equal to 90 degrees, and even more preferably greater than 85 degrees and less than or equal to 90 degrees.

[0152] 10A and 10B are modified examples of FIGS. 5A and 5B, respectively, in which the side surface of the conductive layer 240_1 has a region with an angle An1_1 and a region with an angle An1_2. In FIG. 10B, the insulating layer 280, the conductive layer 240_1, and the conductive layer 240_2 are extracted from FIG. 10A, and the conductive layer 220_2 is further added.

[0153] 10B , the side surface of the conductive layer 240_1 has a region where the angle with the top surface of the conductive layer 220_2 is angle An1_1 and a region where the angle with the top surface of the conductive layer 220_2 is angle An1_2. Angle An1_2 is preferably smaller than angle An1_1. Angle An1_1 is preferably greater than 75 degrees and less than 90 degrees, more preferably greater than 80 degrees and less than 90 degrees, and even more preferably greater than 85 degrees and less than 90 degrees. Angle An1_2 is preferably greater than 45 degrees and less than 90 degrees, more preferably greater than 45 degrees and less than 85 degrees, and even more preferably greater than 45 degrees and less than 80 degrees.

[0154] 10B shows a configuration in which the conductive layer 240_2 covers a region of the side surface of the conductive layer 240_1 that is angled at angle An1_2, but as shown in Fig. 10C, the conductive layer 240_2 may cover a region that is angled at angle An1_1 in addition to the region that is angled at angle An1_2. Furthermore, as shown in Fig. 10D, in addition to the side surface of the conductive layer 240_1, an upper portion of the side surface of the insulating layer 280 (a region closer to the conductive layer 240_1) may be covered by the conductive layer 240_2.

[0155] 11A illustrates an example in which the width of the opening 290 in the conductive layer 240 is narrower than the width of the opening 290 in the insulating layer 280. Fig. 11B is an enlarged view of a region Q1B illustrated in Fig. 11A. Fig. 12 omits the hatching patterns of components other than the oxide semiconductor layer 230 in Fig. 11A, and indicates the widest portion of the opening 290 as width D and the narrowest portion of the opening 290 in the conductive layer 240 as width Dp.

[0156] 11A , the side surface of opening 290 in insulating layer 280 has an area where the angle is slightly gentler than perpendicular. The angle between the top surface of conductive layer 220 and the side surface of insulating layer 280 is less than 90 degrees, for example, greater than or equal to 80 degrees and less than 90 degrees.

[0157] Referring to Figure 7, etc., the difference between the width D and the width Dp (D - Dp) is preferably less than 1.6 times the thickness Tu, more preferably less than 1 time the thickness Tu, even more preferably less than 0.8 times the thickness Tu, and even more preferably less than 0.6 times the thickness Tu.

[0158] Furthermore, when the oxide semiconductor layer 230 and the insulating layer 250 are formed using a method with high coverage, a change in the width of the opening 290 is reflected in the shape of the conductive layer 260. For example, in the cross section shown in Figure 12, the difference between the widest and narrowest regions in the opening 290 of the conductive layer 260 may roughly match the difference (D-Dp) between the width D and the width Dp.

[0159] Furthermore, when the conductive layer 260_1 is formed using a method with high coverage in addition to the oxide semiconductor layer 230 and the insulating layer 250, a change in the width of the opening 290 is reflected in the shape of the conductive layer 260_2. As an example, FIG. 12 shows a width De1 of the widest region and a width De2 of the narrowest region of the conductive layer 260_2 in the opening 290. The difference between the width De1 and the width De2 (De1 - De2) is, for example, preferably less than 1.6 times the thickness Tu of the conductive layer 240_2, more preferably less than 1 time the thickness Tu, still more preferably less than 0.8 times the thickness Tu, and still more preferably less than 0.6 times the thickness Tu.

[0160] Furthermore, it is preferable that the thickness Tu of the conductive layer 240_2 is smaller than the width D of the opening 290.

[0161] 13A shows an example in which the angle of at least a part of the sidewall of the insulating layer 280 in the opening 290 is gentler than those in FIGS. 2A, 11A, etc. By making the angle of the sidewall of the opening 290 gentler, the coverage of the oxide semiconductor layer 230, the insulating layer 250, etc. can be improved and defects such as voids can be reduced. For example, if the angle An0 described above is 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in the opening 290 is improved, which is preferable.

[0162] On the other hand, as the angle An0 becomes smaller, the conductive layer 240_2 may also be formed on part of the sidewall of the insulating layer 280. In such a case, for example, it is preferable to increase the aspect ratio of the opening 290 so that the conductive layer 240_2 is not formed in a deep region of the opening 290. Alternatively, it is preferable to remove the conductive layer formed on the sidewall by using the above-mentioned slight etching.

[0163] 13B , the oxide semiconductor layer 230 may have a different ratio between a film thickness (hereinafter referred to as a first film thickness) at a portion where the top surface of the conductive layer 240 or the conductive layer 220 is to be formed and a film thickness (hereinafter referred to as a second film thickness) at a portion where the sidewall of the opening 290 is to be formed. For example, when part of the oxide semiconductor layer 230 is formed by a sputtering method, the oxide semiconductor layer 230 may have a different ratio between the first film thickness and the second film thickness. For example, as shown in FIG. 13B , the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the closer the angle between the top surface of the conductive layer 220_2 and the side surface of the opening 290 is to 90 degrees, the smaller the ratio of the second film thickness to the first film thickness in the oxide semiconductor layer 230 tends to be.

[0164] <Structural Example 2 of Semiconductor Device> The cross section of the transistor 200 shown in Figure 14A is different from that shown in Figure 2A mainly in that the conductive layer 240 includes a conductive layer 240_3 between the conductive layer 240_1 and the conductive layer 240_2. Figure 14B is an enlarged view of a region Q2 shown in Figure 14A. Note that the description of Figure 2A can be appropriately referred to for components, layers, and the like that are common to those in Figure 2A.

[0165] 14A, the edge of the conductive layer 240_3 on the opening 290 side is aligned with the edge of the conductive layer 240_1 on the opening 290 side. In addition, in FIG. 14A, the conductive layer 240_3 covers the top surface of the conductive layer 240_1 but does not cover the side surface of the conductive layer 240_3 on the opening 290 side.

[0166] In FIG. 14A, the upper end of the conductive layer 240_3 on the opening 290 side is rounded.

[0167] The conductive layer 240_1 and the conductive layer 240_3 can be formed using the same mask. Alternatively, the conductive layer 240_1 can be formed using the conductive layer 240_3 as a mask.

[0168] The conductive layer 240_2 is provided so as to cover the top surface of the conductive layer 240_3 and the side surface of the conductive layer 240_3 on the opening 290 side. The conductive layer 240_2 is provided so as to cover at least a part of the side surface of the conductive layer 240_1.

[0169] The conductive layer 240_2 can be formed in a self-aligned manner with respect to the top surface of the conductive layer 240_3, the side surface of the conductive layer 240_3, and the side surface of the conductive layer 240_1 without using a mask, by utilizing the anisotropy of the deposition rate.

[0170] Fig. 15A shows an example in which the cross section shown in Fig. 14B is not rounded. Note that at least some corners may be rounded in the structure shown in Fig. 15A. Fig. 15B shows an example in which the insulating layer 280, the conductive layer 240_1, the conductive layer 240_2, and the conductive layer 240_3 are extracted from Fig. 15A, and the conductive layer 220_2 is further added.

[0171] 15B, the angle between the top surface of the conductive layer 220_2 and the side surface of the conductive layer 240_3 is indicated as angle An4, the angle between the top surface of the conductive layer 220_2 and the side surface of the conductive layer 240_1 is indicated as angle An3, and the angle between the top surface of the conductive layer 220_2 and the side surface of the insulating layer 280 is indicated as angle An0. Angle An4 is preferably smaller than angle An3.

[0172] The conductive layer 240_3 can be formed using any of the materials described in the section [Conductive Layer] below. It is particularly preferable to refer to the materials that can be used for the conductive layer 240_2 as the materials that can be used for the conductive layer 240_3.

[0173] Fig. 15C shows an example in which the upper corners of the conductive layer 240_2 in Fig. 15B are rounded. Fig. 15C can correspond to the structure shown in Fig. 14B, for example.

[0174] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0175] [Oxide Semiconductor Layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0176] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0177] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for the oxide semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the OS transistor has high frequency characteristics, the semiconductor device can operate at high speed.

[0178] For an oxide semiconductor layer that can be used as a semiconductor layer of a transistor according to one embodiment of the present invention, refer to the description in Embodiment 2. Detailed description thereof will be omitted here.

[0179] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0180] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0181] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0182] In addition, a transistor in which a layer material functioning as a semiconductor is used for a channel formation region may be applied to the semiconductor device of this embodiment mode. Note that the layer material will be described in detail in Embodiment Mode 5.

[0183] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, a yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layers included in the semiconductor device.

[0184] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, it is advisable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0185] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0186] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0187] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms may be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0188] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0189] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0190] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0191] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer 130 described in the third embodiment can have a layered structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0192] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0193] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0194] Ferroelectricity is believed to be manifested by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the manifestation of ferroelectricity depends on the crystalline structure of the crystals contained in the ferroelectric layer. Therefore, for the insulating layer to exhibit ferroelectricity, the insulating layer 130 must contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystalline structure, as this will result in the manifestation of ferroelectricity. The crystalline structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0195] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0196] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0197] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also included are nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Also included are nitride oxides such as silicon nitride oxide.

[0198] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0199] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0200] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0201] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0202] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0203] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0204] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0205] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0206] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0207] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0208] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0209] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0210] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0211] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0212] 2A shows an example in which the insulating layer 210 has a single-layer structure. Note that the insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0213] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0214] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0215] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least some of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0216] Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0217] FIG. 2A shows an example in which the insulating layer 280 has a single-layer structure. The insulating layer 280 can have a stacked structure of two or more layers. For example, as shown in FIG. 17A , the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 on the insulating layer 280_1, and an insulating layer 280_3 on the insulating layer 280_2. In this case, it is preferable to use the aforementioned material with a low dielectric constant for the insulating layer 280_2, and to use barrier insulating layers against oxygen for the insulating layers 280_1 and 280_3. This can suppress oxidation of the conductive layer 220 and the conductive layer 240, thereby preventing high resistance.

[0218] For example, it is preferable to use a silicon nitride film or an aluminum oxide film for the insulating layer 280_1 and the insulating layer 280_3, and a silicon oxide film for the insulating layer 280_2. Note that each of the insulating layer 280_1 and the insulating layer 280_3 may have a stacked structure of two or more layers.

[0219] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0220] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0221] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. In this way, oxygen can be supplied from the insulating layer 250 to the oxide semiconductor layer 230, and oxygen vacancies in the oxide semiconductor layer 230 can be reduced. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0222] FIG. 2A shows an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0223] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0224] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0225] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0226] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0227] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including the fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0228] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0229] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0230] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0231] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0232] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0233] Note that the insulating layer 250 having a four-layer structure may not include the second insulating layer. For example, an insulating layer having a barrier property against oxygen can be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant can be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side can be used.

[0234] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0235] [Conductive Layer] The conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, etc.) included in the semiconductor device preferably include a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element, or an alloy combining the above-mentioned metal elements. Alternatively, nitrides of alloys containing the above-mentioned metal elements or oxides of such alloys may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0236] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, ITSO, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0237] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0238] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0239] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0240] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0241] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 210, the conductive layer 220 is preferably able to maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 220 and the conductive layer 240.

[0242] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230 can be reduced.

[0243] The conductive layer 220_1 can also have a stacked structure of two or more layers. When the conductive layer 220_1 has a stacked structure of two layers, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion as a lower layer of the conductive layer 220_1, a material with high conductivity as an upper layer of the conductive layer 220_1, and a conductive material containing oxygen (more preferably, an oxide conductor) as the conductive layer 220_2. Specifically, it is preferable to use titanium nitride as a lower layer of the conductive layer 220_1, tungsten as an upper layer of the conductive layer 220_1, and an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) as the conductive layer 220_2. In this case, the titanium nitride film is in contact with the insulating layer 210, and the oxide conductive film is in contact with the oxide semiconductor layer 230. Furthermore, an oxide conductor is used for the layer closest to the channel formation region of the oxide semiconductor layer 230. Compared to tungsten, an oxide conductor has lower contact resistance with the oxide semiconductor layer 230; therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased. When an oxide insulating layer is used for the insulating layer 210, the insulating layer 210 can prevent the conductive layer 220 from being excessively oxidized. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as an upper layer of the conductive layer 220_1, the conductivity of the conductive layer 220 can be increased.

[0244] 2A has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1. In this case, for example, it is preferable to use an oxide conductor for the conductive layer 240_2 and a material having higher conductivity than the conductive layer 240_2 for the conductive layer 240_1. Specifically, it is preferable to use ITO, ITSO, or In—Zn oxide for the conductive layer 240_2, and it is particularly preferable to use ITSO for the conductive layer 240_2. It is preferable to use tungsten, copper, aluminum, or an alloy containing aluminum for the conductive layer 240_1, and it is particularly preferable to use tungsten for the conductive layer 240_1. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 240_1. By using an oxide conductor for the conductive layer 240_2 that is mainly in contact with the oxide semiconductor layer 230, the contact resistance with the oxide semiconductor layer 230 can be reduced. Furthermore, when a material having higher conductivity than an oxide conductor is used for the layer forming the conductive layer 240, the conductivity of the conductive layer 240 can be increased.

[0245] Note that the conductive layer 240_1 may be formed using a conductive material containing oxygen, and the conductive layer 240_2 may be formed using a material having higher conductivity than the conductive layer 240_1. In this case, an oxide conductor is used for the layer of the conductive layer 240 that is closest to the channel formation region of the oxide semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0246] The conductive layer 260 has a region that functions as a gate wiring. The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0247] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0248] 2A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, it is preferable to use a titanium nitride film as the conductive layer 260_1 and a tungsten film as the conductive layer 260_2. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260_1 and a copper film as the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0249] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0250] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0251] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0252] 17A , the semiconductor device of one embodiment of the present invention may include an insulating layer 283 over the transistor 200. Specifically, the insulating layer 283 may be provided over the conductive layer 260 and the insulating layer 250.

[0253] A barrier insulating layer against hydrogen is preferably used for the insulating layer 283. With such a structure, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0254] 2A , both the conductive layer 260_1 and the conductive layer 260_2 are located in the opening 290. Note that as the transistor 200 is miniaturized and the width of the opening 290 becomes smaller, it becomes more difficult to arrange all of the layers that form the conductive layer 260 in the opening 290. Depending on the width of the opening 290 and the thicknesses of the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260_1, the conductive layer 260_1 may be provided in the opening 290 and the conductive layer 260_2 may be provided so as to overlap with the opening 290 (see FIG. 17B ).

[0255] 18A to 22C , examples of transistor configurations that are partially different from the transistor 200 will be described. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0256] [Transistor 200A] Fig. 18A is a plan view of a semiconductor device including a transistor 200A. Fig. 18B is a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 18A. Fig. 18C is a cross-sectional view taken along dashed dotted line A3-A4 in Fig. 18A. Note that Fig. 1E can be referred to for cross-sectional views taken along dashed dotted line A5-A6 in Figs. 18B and 18C.

[0257] 18A to 18C includes an insulating layer 210 over a substrate (not shown), a transistor 200A over the insulating layer 210, an insulating layer 280 over the insulating layer 210, an insulating layer 284, an insulating layer 285 over the insulating layer 284, and a conductive layer 265 over the transistor 200A, the insulating layer 284, and the insulating layer 285. The insulating layer 210, the insulating layer 280, the insulating layer 284, and the insulating layer 285 function as interlayer films.

[0258] The semiconductor device shown in FIGS. 18A to 18C differs from the semiconductor device shown in FIGS. 1A to 1E in that it includes a conductive layer 265, an insulating layer 284, and an insulating layer 285.

[0259] The conductive layer 265 functions as a gate wiring. For the conductive layer 265, a material that can be used for the conductive layer 260 can be used.

[0260] The transistor 200A includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The conductive layer 265 has a region in contact with the conductive layer 260. Note that the conductive layer 265 may be considered a component of the transistor 200A. The insulating layer 284 is provided over the insulating layer 250.

[0261] In the transistor 200A, the stacked structure from the conductive layer 220 to the insulating layer 250 is similar to that of the above-described transistor 200, and therefore detailed description thereof will be omitted.

[0262] 18B and 18C , insulating layer 284 is provided so as to be located on insulating layer 250. Furthermore, insulating layer 284 is provided with openings 270 that reach insulating layer 250 at positions overlapping openings 290. Conductive layer 260 is disposed so that at least a portion thereof is located within opening 270. Conductive layer 260 contacts insulating layer 250 within opening 270.

[0263] The conductive layer 260 is provided to fill the openings 290 and 270. The conductive layer 260 has a portion that faces the oxide semiconductor layer 230 in the opening 290 with the insulating layer 250 interposed therebetween, and a portion that is located in the opening 270.

[0264] 18B and 18C show an example in which both the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 290. Note that as transistors are miniaturized and the widths of the openings 290 and 270 become smaller, it becomes more difficult to arrange all of the layers constituting the conductive layer 260 in the openings 290 and 270. For example, there is a case in which only the conductive layer 260_1 is provided in the opening 290, and the conductive layer 260_1 and the conductive layer 260_2 are provided in the opening 270. There is also a case in which only the conductive layer 260_1 is provided in the opening 270.

[0265] The portion of the conductive layer 265 that does not overlap with the opening 290 is mainly located on the insulating layer 285. Therefore, the conductive layer 265 mainly overlaps with the conductive layer 240 via the insulating layers 284 and 285. This makes it possible to increase the physical distance between the conductive layer 265 and the conductive layer 240, and to reduce the parasitic capacitance that occurs between the conductive layer 265 and the conductive layer 240. Note that the conductive layer 240 and the conductive layer 265 may have an overlapping portion without the insulating layer 285 being therebetween.

[0266] 18B and 18C show an example in which the width of the opening 270 is smaller than the width of the opening 290. The smaller the width of the opening 270, the greater the physical distance between the conductive layer 240 and the conductive layer 260 can be, and the smaller the parasitic capacitance that occurs between the conductive layer 240 and the conductive layer 260 can be, which is preferable. For example, the width of the opening 270 is preferably the same as or smaller than the width of the opening 290.

[0267] It is preferable that the height of the top surface of the conductive layer 260 and the height of the top surface of the insulating layer 285 are the same or approximately the same. The conductive layer 265 is provided over the insulating layer 285, the insulating layer 284, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. It can also be said that the conductive layer 260 and the conductive layer 265 are connected to each other.

[0268] That is, the transistor 200A has a structure in which parasitic capacitance generated between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit including the transistor.

[0269] In this embodiment, an example in which the opening 270 is circular in plan view has been shown, but the present invention is not limited to this. Shapes that can be applied to the opening 270 are the same as the shapes that can be applied to the opening 290 described above.

[0270] The width of the opening 270 may vary in the depth direction. In particular, the width of the opening 270 used here is the maximum width of the opening 270 provided in the insulating layer 284 in a cross-sectional view.

[0271] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 284. With such a structure, diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230 can be suppressed, and further, hydrogen contained in the oxide semiconductor layer 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced. As the insulating layer 284, an aluminum oxide film, a hafnium oxide film, a hafnium silicate film, or the like can be used.

[0272] Furthermore, a barrier insulating layer against hydrogen can be used as the insulating layer 284. This can suppress diffusion of hydrogen from above the insulating layer 284 to the oxide semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being less permeable to oxygen and hydrogen, and therefore can be suitably used for the insulating layer 284.

[0273] When a silicon nitride film is used as the insulating layer 284, the silicon nitride film is preferably formed by a sputtering method. The sputtering method does not require the use of molecules containing hydrogen in the film formation gas, and therefore can reduce the hydrogen concentration in the insulating layer 284. Furthermore, by forming the insulating layer 284 by a sputtering method, a silicon nitride film with high density can be formed.

[0274] Alternatively, the insulating layer 284 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 284 may be a stacked film of an aluminum oxide film and a silicon nitride film over the aluminum oxide film.

[0275] The insulating layer 285 functions as an interlayer film, and therefore is preferably made of the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably includes a silicon oxide film.

[0276] Note that a structure similar to that of the transistor 200 can also be applied to the transistor 200A. For example, the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 over the insulating layer 280_1, and an insulating layer 280_3 over the insulating layer 280_2. An insulating layer 283 can be provided over the insulating layer 285 and the conductive layer 265.

[0277] [Transistor 200B] Fig. 19A is a plan view of a semiconductor device including transistor 200B. Fig. 19B is a cross-sectional view taken along dashed dotted lines A1-A2 and A3-A4 shown in Fig. 19A.

[0278] An enlarged view of Fig. 19C is shown in Fig. 20A. Fig. 20B shows an enlarged view of a cross section between dashed dotted lines A5-A6 shown in Fig. 19B and Fig. 19C. Fig. 20B can also be said to be a cross section of the XY plane including the insulating layer 280.

[0279] The semiconductor device shown in FIGS. 19A to 19C includes an insulating layer 210 on a substrate (not shown), a transistor 200B on the insulating layer 210, and an insulating layer 280 on the insulating layer 210.

[0280] The transistor 200B includes a conductive layer 220, a conductive layer 240 over an insulating layer 280, an insulating layer 225, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0281] The transistor 200B shown in FIGS. 19A to 19C differs from the transistor 200 shown in FIGS. 1A to 1E in that it includes an insulating layer 225.

[0282] As illustrated in FIG. 20B, the transistor 200B has a configuration in which an insulating layer 225 is disposed between the insulating layer 280 and the oxide semiconductor layer 230 in a plan view.

[0283] The insulating layer 225 is provided along at least a part of the sidewall of the opening 290. The insulating layer 225 has at least a region located between the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 225 can also be called a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0284] As described above, it is preferable that oxygen vacancies and impurities be reduced as much as possible in the channel formation region of the oxide semiconductor. In particular, it is preferable that hydrogen be reduced as much as possible in the channel formation region of the oxide semiconductor.

[0285] Therefore, a barrier insulating layer against hydrogen is preferably used as the insulating layer 225 provided outside the oxide semiconductor layer 230. This can suppress diffusion of hydrogen into the oxide semiconductor layer 230 and improve the reliability of the transistor 200. For example, a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used as the insulating layer 225, and a silicon nitride film is more preferably used.

[0286] Note that a silicon nitride film also has a barrier property against oxygen. Therefore, by using a silicon nitride film for the insulating layer 225, oxygen can be prevented from being extracted from the oxide semiconductor layer 230, which can prevent oxygen vacancies from being formed in the oxide semiconductor layer 230. Furthermore, by using a silicon nitride film for the insulating layer 225, excessive oxygen can be prevented from being supplied to the oxide semiconductor layer 230. Therefore, the channel formation region of the oxide semiconductor layer 230 can be prevented from becoming oxygen-excessive, thereby improving the reliability of the transistor 200B. Furthermore, the insulating layer 225 may be in contact with the side surface of the conductive layer 240 in the opening 290. In this case, by using a silicon nitride film for the insulating layer 225, it is possible to prevent the side surface of the conductive layer 240 in the opening 290 from being oxidized and an oxide film from being formed on the side surface.

[0287] The silicon nitride film of the insulating layer 225 is preferably formed using the PEALD method, which can improve the coverage of the insulating layer 225 on the sidewall of the opening 290 and form an insulating layer 225 with a uniform thickness.

[0288] The insulating layer 225 may be made of the above-mentioned material that can have ferroelectricity.

[0289] In the configuration shown in FIG. 19B and other figures, the conductive layer 220_2 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 210) than the bottom surface of the second recess. When forming the opening 290, the second recess is provided in the conductive layer 220_2. Then, when processing the insulating layer 225, the first recess is provided in the conductive layer 220_2. Therefore, in FIG. 19B and other figures, the side surface of the second recess is aligned with the side surface of the insulating layer 280 in the opening 290, and the side surface of the first recess is aligned with the surface of the insulating layer 225 facing the oxide semiconductor layer 230. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0290] 19B and other drawings, the insulating layer 225 is in contact with the bottom surface and side surfaces of the recess (specifically, the second recess) of the conductive layer 220, and is in contact with the side surfaces of the insulating layer 280, the conductive layer 240_1, and the conductive layer 240_2 within the opening 290. The oxide semiconductor layer 230 is located inside the insulating layer 225 within the opening 290, the insulating layer 250 is located inside the oxide semiconductor layer 230 within the opening 290, and the conductive layer 260 is located inside the insulating layer 250 within the opening 290.

[0291] 20A , the shortest distance Tc from the top surface of the insulating layer 210 to the top surface of the conductive layer 220_2 that is in contact with the insulating layer 280 is preferably longer than the shortest distance Ta from the top surface of the insulating layer 210 to the bottom surface of the insulating layer 250. This increases the area where the side surface of the conductive layer 220_2 faces the oxide semiconductor layer 230, thereby reducing the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230. Therefore, a decrease in the on-state current of the transistor 200B due to the contact resistance between the conductive layer 220_2 and the oxide semiconductor layer 230 can be suppressed. Note that the shortest distance Ta can be determined based on the bottom surface of the insulating layer 250 in the opening 290.

[0292] 20A , the shortest distance Tc is preferably equal to or greater than the shortest distance Tb from the top surface of the insulating layer 210 to the bottom surface of the conductive layer 260, and more preferably longer than the shortest distance Tb. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 230, thereby improving the electrical characteristics of the transistor 200B. Furthermore, since the gate electric field is also easier to apply to a region of the oxide semiconductor layer 230 facing the conductive layer 220_2, the on-state current of the transistor 200B can be increased. Furthermore, regardless of whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 200B can be improved. Note that the shortest distance Tb can be determined based on the bottom surface of the conductive layer 260 in the opening 290.

[0293] 20A , the width (film thickness) of the insulating layer 225 is denoted by width Ts. A small width Ts is preferable. By reducing the width Ts, the channel width of the transistor 200B can be prevented from being reduced, and the on-state current can be prevented from being reduced. On the other hand, by increasing the width Ts, the function of the insulating layer 225 can be improved. From the above, the width Ts is preferably, for example, 1 nm to 20 nm, more preferably 2 nm to 15 nm, and even more preferably 3 nm to 10 nm.

[0294] 20B also shows the channel width W of transistor 200B. When opening 290 is circular in plan view, width D of opening 290 corresponds to the diameter of opening 290, and channel width W can be calculated as "(D-2×Ts)×π".

[0295] The channel length of transistor 200B can be considered to be the distance between the source region and the drain region. In other words, it can be said that the channel length of transistor 200B is determined by the height of insulating layer 225. It can also be said that the channel length of transistor 200B is determined by the depth of the recess (specifically, the second recess) in conductive layer 220, the thickness of insulating layer 280 on conductive layer 220, and the thickness of conductive layer 240. When the channel length of transistor 200B is considered to be the distance between the source region and the drain region, it can be said that the channel length of transistor 200B is the length L shown in FIG. 20A .

[0296] 20A illustrates a configuration in which the conductive layer 220_2 has a first recess and a second recess, but the present invention is not limited to this. For example, the conductive layer 220_2 may have a configuration in which the second recess is not formed.

[0297] 21A shows an enlarged view of a region Q3 shown in Fig. 20A. The insulating layer 225 contacts the side surfaces of the insulating layer 280 and the conductive layer 240_2 in the opening 290. The top end of the insulating layer 225 is lower than the top surface of the conductive layer 240_1.

[0298] Fig. 21B shows a modification of Fig. 21A, in which the top end of the insulating layer 225 is lower than the top surface of the insulating layer 280, and the insulating layer 225 does not contact the side surface of the conductive layer 240_2 within the opening 290.

[0299] Fig. 21C shows a modification of Fig. 21A, which differs from Fig. 21A in that the top end of the insulating layer 225 is higher than the top surface of the conductive layer 240_1.

[0300] [Transistor 200C] Fig. 22A is a plan view of a semiconductor device including transistor 200C. Fig. 22B is a cross-sectional view taken along dashed dotted lines A1-A2 and A3-A4 shown in Fig. 22A.

[0301] The semiconductor device shown in Figures 22A to 22C has an insulating layer 210 on a substrate (not shown), a transistor 200C on the insulating layer 210, an insulating layer 280 on the insulating layer 210, and an insulating layer 281 on the insulating layer 280.

[0302] The transistor 200C includes a conductive layer 220, a conductive layer 255 on the insulating layer 280, a conductive layer 240 on the insulating layer 281, an insulating layer 225, an oxide semiconductor layer 230, an insulating layer 250 on the oxide semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0303] 22A to 22C differ from the semiconductor device illustrated in FIGS. 1A to 1E mainly in that a conductive layer 255 and an insulating layer 281 are included. In addition, a transistor 200C illustrated in FIGS. 22A to 22C differs from the transistor 200B illustrated in FIGS. 19A to 19C mainly in that a conductive layer 255 is included.

[0304] The conductive layer 255 is located over the insulating layer 280, and the insulating layer 281 is located over the conductive layer 255 and the insulating layer 280. In addition, the conductive layer 240_1 is located over the insulating layer 281.

[0305] An opening 290 reaching the conductive layer 220 is provided in the insulating layer 280 , the conductive layer 255 , the insulating layer 281 , and the conductive layer 240 .

[0306] In transistor 200C, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a first gate electrode, the insulating layer 250 functions as a first gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, the conductive layer 240 functions as the other of the source electrode and the drain electrode, the conductive layer 255 functions as a second gate electrode, and the insulating layer 225 functions as a second gate insulating layer.

[0307] The oxide semiconductor layer 230 has a region that faces the conductive layer 255 with the insulating layer 225 interposed therebetween and that faces the conductive layer 260 with the insulating layer 250 interposed therebetween. At least part of the region functions as a channel formation region of the transistor 200C.

[0308] Since the transistor 200C includes a conductive layer that functions as a backgate electrode, the threshold voltage of the transistor 200C can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0309] In the transistor 200C, one of the conductive layer 255 and the conductive layer 260 may be used as a gate electrode and the other as a back gate electrode. The transistor 200C may have a particularly preferable structure in which the conductive layer 260 is used as a gate electrode and the conductive layer 255 is used as a back gate electrode. When the conductive layer 260, which has a wider region facing the oxide semiconductor layer 230 than the conductive layer 255, is used as the gate electrode, a gate electric field is applied to the oxide semiconductor layer 230 more efficiently, which may improve the electrical characteristics of the transistor. When the conductive layer 260 functions as a gate electrode and the conductive layer 255 functions as a back gate electrode, the insulating layer 250 functions as a gate insulating layer and the insulating layer 225 functions as a back gate insulating layer.

[0310] The conductive layer 255 can be made of a conductive material that can be used for the conductive layer 260 .

[0311] The insulating layer 281 functions as an interlayer film. The insulating layer 281 can be formed using an insulating material that can be used for the insulating layer 280.

[0312] The insulating layer 281 can have a stacked structure of two or more layers. For example, the insulating layer 281 can have a three-layer structure. In this case, it is preferable to use barrier insulating layers against oxygen as the first insulating layer and the third insulating layer, and to use the above-mentioned material with a low relative dielectric constant as the second insulating layer sandwiched between the first insulating layer and the second insulating layer. This can suppress oxidation of the conductive layer 255 and the conductive layer 240 and prevent high resistance.

[0313] Note that the transistor 200C can have a structure similar to that of at least one of the transistors 200, 200A, and 200B. For example, the insulating layer 280 can have a three-layer structure including an insulating layer 280_1, an insulating layer 280_2 over the insulating layer 280_1, and an insulating layer 280_3 over the insulating layer 280_2. An insulating layer 283 can be provided over the insulating layer 250 and the conductive layer 260.

[0314] <Configuration Example 2 of Semiconductor Device> Below, a configuration example of a semiconductor device that is partially different in configuration from the semiconductor device described above will be described using Figures 23A and 23B. Note that descriptions of parts that overlap with the above will be omitted, and only the differences will be described in detail. Furthermore, even if components differ in position or shape, if their functions are the same, they may be assigned the same reference numerals and their descriptions may be omitted.

[0315] 23A is a plan view of a semiconductor device including a transistor 200. Note that the configuration of the transistor 200 is similar to that of the above-described <Configuration example 1 of semiconductor device>, and therefore detailed description thereof will be omitted.

[0316] 23A includes a conductive layer 241 connected to the conductive layer 240. In addition, an insulating layer 286 is provided over the transistor 200.

[0317] The insulating layer 286 functions as an interlayer film. The insulating layer 286 is preferably made of the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For example, the insulating layer 286 preferably includes a silicon oxide film.

[0318] The concentration of impurities such as water and hydrogen in the insulating layer 286 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the oxide semiconductor layer 230.

[0319] An opening 275 reaching the conductive layer 240_1 is provided in the insulating layer 286, the insulating layer 250, the oxide semiconductor layer 230, and the conductive layer 240_2. A bottom of the opening 275 includes a top surface of the conductive layer 240_1, and a sidewall of the opening 275 includes a side surface of the conductive layer 240_2, a side surface of the oxide semiconductor layer 230, a side surface of the insulating layer 250, and a side surface of the insulating layer 286.

[0320] The conductive layer 241 is provided in the opening 275. The conductive layer 241 functions as a via that connects a wiring or the like provided over the transistor 200 to the other of the source electrode and the drain electrode of the transistor 200.

[0321] A single layer or a stack of layers containing the conductive material described above in [Conductive Layer] can be used for the conductive layer 241. For the conductive layer 241, a conductive material containing tungsten, copper, or aluminum as a main component, for example, can be preferably used.

[0322] 23A , the conductive layer 241 can have a three-layer structure including a conductive layer 241_1, a conductive layer 241_2 over the conductive layer 241_1, and a conductive layer 241_3 over the conductive layer 241_2. The conductive layer 241_1 is provided to cover the bottom and sidewalls of the opening 275, the conductive layer 241_2 is provided to cover the conductive layer 241_1, and the conductive layer 241_3 is provided to cover the conductive layer 241_2.

[0323] The conductive layer 241_1 is preferably made of a material having high conductivity. A conductive material containing tungsten, copper, or aluminum as a main component is preferable because of its high conductivity. In addition, the conductive layer 241_1 is preferably made of the same material as the conductive layer 240_1 because the conductive layer 241_1 is in contact with the conductive layer 240_1. This can reduce wiring resistance.

[0324] The conductive layer 241_2 is preferably formed using a conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. The conductive material that has a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a stacked layer. The conductive layer 241_2 can suppress impurities such as water and hydrogen from entering the oxide semiconductor layer 230 through the conductive layer 241_3.

[0325] The conductive layer 241_3 is preferably formed using a material with high conductivity. The conductive layer 241_3 can be formed using a conductive material that can be used for the conductive layer 241_1.

[0326] Also, as shown in FIG. 23A, the upper surface of the conductive layer 241 can be formed so as to coincide or approximately coincide with the upper surface of the insulating layer 286.

[0327] In the step of forming the opening 275, a metal oxide used for the oxide semiconductor layer 230 reacts with an etching gas to become a by-product, which may remain inside the opening 275. Therefore, after the opening 275 is formed, cleaning treatment is preferably performed.

[0328] The cleaning treatment may be wet cleaning using a cleaning liquid or the like, plasma treatment using plasma, or cleaning by heat treatment, and the above cleaning treatments may be combined as appropriate.

[0329] Wet cleaning may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, or hydrofluoric acid diluted with carbonated water or pure water, or pure water, or warm water prepared by heating pure water. The temperature of the warm water is 25°C or higher and 95°C or lower, preferably 25°C or higher and 85°C or lower, and preferably 30°C or higher and 65°C or lower. Ultrasonic cleaning may also be performed using these aqueous solutions, pure water, warm water, or carbonated water. It is preferable to use a frequency of 100 kHz or higher and 1 MHz or lower for ultrasonic cleaning. Cleaning using such frequencies is sometimes called ultrasonic cleaning or megasonic cleaning. These cleaning methods may also be used in combination as appropriate.

[0330] For example, a QDR (Quick Dump Rinse) cleaning process may be performed using the above aqueous solution, pure water, or carbonated water in a batch cleaning device.

[0331] QDR cleaning includes, for example, a first step of supplying pure water or carbonated water into the cleaning tank in a shower-like manner while draining the pure water or carbonated water from the cleaning tank, a second step of rapidly supplying pure water or carbonated water into the cleaning tank, and a third step of supplying pure water or carbonated water so that it overflows from the cleaning tank. The first, second, and third steps constitute one cycle, and the number of cycles is set appropriately as necessary. It is preferable to perform the third step before or after QDR cleaning.

[0332] By performing the cleaning treatment, it is possible to remove by-products remaining in the opening 275. By removing the by-products remaining in the opening 275, it is possible to suppress an increase in the contact resistance between the conductive layer 240 and the conductive layer 241. Furthermore, when a plurality of connection portions between the conductive layer 240 and the conductive layer 241 are provided in the semiconductor device, it is possible to reduce variations in the contact resistance between the conductive layer 240 and the conductive layer 241.

[0333] Note that the generation of the by-products can be suppressed by configuring the oxide semiconductor layer 230 so as not to be exposed in the opening 275. Therefore, for example, as shown in Fig. 23B , it is preferable to provide an opening 274 in the oxide semiconductor layer 230 that is larger in width than the opening 275. This allows a configuration in which the side surface of the oxide semiconductor layer 230 is not exposed in the opening 275.

[0334] For example, before forming the insulating layer 250, a region of the oxide semiconductor layer 230 overlapping with at least a part of the conductive layer 240 is removed, so that the opening 274 can be formed. Furthermore, by forming the insulating layer 250 after forming the opening 274, the side surface of the oxide semiconductor layer 230 can be covered with the insulating layer 250 in the opening 274. Furthermore, by forming the opening 275 having a width smaller than that of the opening 274 after forming the insulating layer 286, the side surface of the oxide semiconductor layer 230 can be prevented from being exposed in the opening 275. At this time, the sidewall of the opening 274 includes the side surface of the conductive layer 240_2, the side surface of the insulating layer 250, and the side surface of the insulating layer 286.

[0335] The above structure can suppress the formation of by-products in the opening 275. Therefore, it is possible to suppress an increase in the contact resistance between the conductive layer 240 and the conductive layer 241. Furthermore, when a plurality of connection portions between the conductive layer 240 and the conductive layer 241 are provided in the semiconductor device, it is possible to reduce variations in the contact resistance between the conductive layer 240 and the conductive layer 241.

[0336] 23A and 23B illustrate a structure in which the opening 275 is provided in the conductive layer 240_2, but the present invention is not limited to this. A structure in which the opening 275 is not provided in the conductive layer 240_2 is also possible. In this case, the conductive layer 241 is in contact with the top surface of the conductive layer 240_2. With the above structure, the opening 275 can be easily processed with high accuracy.

[0337] In the semiconductor device of one embodiment of the present invention, an oxide layer having higher resistivity than an oxide semiconductor layer is provided between a source electrode or a drain electrode and the oxide semiconductor layer, whereby the electrical characteristics of the transistor can be improved and the reliability of the transistor can be improved.

[0338] In a semiconductor device according to one embodiment of the present invention, an oxide semiconductor layer is surrounded by a barrier insulating layer against hydrogen, and one or both of an insulating layer having a function of capturing or adhering hydrogen and an insulating layer having a region containing excess oxygen are provided near the oxide semiconductor layer, whereby oxygen vacancies and / or impurities in the oxide semiconductor layer can be reduced, thereby improving the electrical characteristics and reliability of the transistor.

[0339] The semiconductor device according to one embodiment of the present invention has a structure in which parasitic capacitance between the other of the source electrode and the drain electrode and between the gate electrode and the other of the source electrode and the drain electrode and between the other of the source electrode and the drain electrode and the gate wiring is reduced, thereby improving the frequency characteristics of a circuit using the semiconductor device.

[0340] <Example of Manufacturing Method of Semiconductor Device> A manufacturing method of a semiconductor device will be described with reference to Figures 24A to 30B. Here, as an example, a manufacturing method of the structure shown in Figures 1C and 1D will be described. Note that with regard to the materials and forming methods of each element, descriptions of parts that are the same as those previously described may be omitted. (A) in each figure corresponds to an enlarged view of the structure shown in Figure 1C, and (B) in each figure corresponds to an enlarged view of the structure shown in Figure 1D.

[0341] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, an ALD method, a pulsed laser deposition (PLD) method, a molecular beam epitaxy (MBE) method, a vacuum deposition method, or the like.

[0342] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF-superimposed DC sputtering, which superimposes RF and DC, is also available. RF sputtering is preferred for film formation using insulating targets. DC sputtering is primarily used when forming films using conductive targets. DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering, in addition to forming conductive films. Specifically, pulsed DC sputtering can be used primarily when forming films of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows for control of ion energy and target potential during film formation. Therefore, compared to RF sputtering, damage caused by film formation is reduced. Furthermore, high-quality films can be obtained.

[0343] The sputtering method is a film formation method that uses the deposition of particles emitted from a target, and can be said to be a film formation method in which the deposition rate is likely to be anisotropic.

[0344] As a sputtering method, for example, ionization sputtering can be used, which is a method in which sputtering particles generated from a target are ionized by RF or the like, and a film is formed with high anisotropy by self-bias or the like.

[0345] Furthermore, by using a sputtering method such as long-throw sputtering or collimated sputtering, it is possible to form a film with higher anisotropy. The long-throw sputtering method is a technique for forming a film with higher anisotropy by increasing the distance between the sputtering target and the substrate.

[0346] CVD methods can be classified into plasma enhanced CVD (PECVD), thermal CVD (TCVD), and photo CVD (photo CVD), and can be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.

[0347] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0348] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD (Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0349] Furthermore, the ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. The PEALD (Plasma Enhanced ALD) method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). In the method for forming a metal oxide film according to one embodiment of the present invention, an ALD method is used. However, since the ALD method employs a high substrate temperature during film formation and / or an impurity removal treatment, the amount of carbon and chlorine contained in the film may be smaller than that in the case of using an ALD method without employing these conditions.

[0350] Unlike film formation methods in which particles emitted from a target or the like are deposited, ALD and CVD are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. Furthermore, ALD can be used to form an isotropic film. ALD can also be described as a film formation method with low anisotropy in deposition rate. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as sputtering or CVD, which have a faster film formation rate. For example, when forming a metal oxide into a layered structure of a first metal oxide and a second metal oxide, a method can be used in which the first metal oxide is formed by sputtering, and then the second metal oxide is formed on the first metal oxide by ALD. For example, when the first metal oxide has a crystalline portion, the second metal oxide may grow as a crystal, using the crystalline portion as a nucleus.

[0351] The CVD method and the ALD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method and the ALD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method and the ALD method can form a film whose composition changes continuously by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0352] Furthermore, in the ALD method, a film of any composition can be formed by adjusting the amount of source gas introduced, the number of introductions (also referred to as the number of pulses), the time required for one pulse (also referred to as the pulse time), etc. Also, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.

[0353] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0354] Furthermore, when processing a thin film that constitutes a semiconductor device, a lithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0355] There are two typical lithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0356] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, and ArF laser light. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0357] The thin film can be etched by dry etching, wet etching, ashing, plasma treatment, reverse sputtering, etc. Alternatively, the thin film can be etched by sandblasting.

[0358] As an etching gas for the dry etching process, for example, a gas containing halogen can be used.

[0359] The halogen-containing gas may be, for example, an etching gas containing one or more of fluorine, chlorine, and bromine, such as a fluorocarbon gas, a hydrofluorocarbon gas, or SF ６ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３ The fluorocarbon gas may be a single gas or a mixture of two or more gases. ｘ F ｙ A gas represented by (y≦2x+2) can be used. An example of a fluorocarbon gas that satisfies y=2x+2 is CF. ４ , C ２ F ６ , C ３ F ８ , C ４ F １０ , C ５ F １２Examples of fluorocarbon gases that satisfy the condition y<2x+2 include saturated fluorocarbon compounds such as C ２ F ４ , C ２ F ２ , C ３ F ７ , C ３ F ４ , C ４ F ８ , C ４ F ６ , C ４ F ４ , C ４ F ２ , C ５ F １０ , C ５ F ８ , C ５ F ６ , C ５ F ４ Examples of hydrofluorocarbon gases include unsaturated fluorocarbon compounds such as CHF ３ Gas, CH ２ F ２ Gas, etc.

[0360] When a gas containing halogen is used as an etching gas, oxygen (O ２ ) gas, carbon dioxide, nitrogen (N ２ ) gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas, or the like can be added as appropriate.

[0361] Alternatively, a gas containing no halogen gas but containing hydrocarbon gas or hydrogen gas can be used as the etching gas.

[0362] Examples of hydrocarbon gases include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２Ｈ２ ), and propyne (C ３H ４ ) can be used.

[0363] When a hydrocarbon gas is used as the etching gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like may be added as appropriate.

[0364] Furthermore, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used. The etching apparatus can be appropriately configured depending on the object to be etched.

[0365] First, the conductive layer 220 is formed over the insulating layer 210 , the insulating layer 280 is formed over the conductive layer 220 , and the conductive layer 240_1f is formed over the insulating layer 280 .

[0366] Note that after the insulating layer 280 is formed, it is preferable to perform planarization treatment (also referred to as CMP treatment) using a chemical mechanical polishing (CMP) method to planarize the top surface of the insulating layer 280. By performing the planarization treatment on the insulating layer 280, the surface on which the conductive layer 240, which functions as a wiring, is formed can be flattened, and discontinuity of the conductive layer 240 can be suppressed. Note that the planarization treatment is not necessarily performed, and in that case, manufacturing costs can be reduced.

[0367] Next, a mask 278 is formed over the conductive layer 240_1f (FIGS. 24A and 24B). The mask 278 can have a structure in which a spin-on-carbon (SOC) film, a spin-on-glass (SOG) film, and a resist mask are stacked in this order, for example.

[0368] Subsequently, using a mask 278, openings 290b and 290a are formed in the conductive layer 240_1f and the insulating layer 280 at positions overlapping with the conductive layer 220 (FIGS. 25A and 25B). At this time, recesses 290c are formed in the conductive layer 220 at positions overlapping with the openings 290.

[0369] Because the opening 290 has a large aspect ratio, it is preferable to process part of the conductive layer 240_1f and part of the insulating layer 280 by anisotropic etching. In particular, dry etching is preferable because it is suitable for fine processing. Furthermore, the processing may be performed under different conditions depending on the layer.

[0370] 25A and 25B show an example in which the difference in the slope of the sidewalls of the conductive layer 240_1f and the insulating layer 280 is small (for example, the difference between the angle between the top surface of the conductive layer 220 and the conductive layer 240_1f and the angle between the top surface of the conductive layer 220 and the insulating layer 280 is small).

[0371] As shown in Figures 26A and 26B, the sidewalls of the conductive layer 240_1f can also be processed so that they have a gentler angle than the sidewalls of the insulating layer 280 (for example, so that the angle between the top surface of the conductive layer 220 and the conductive layer 240_1f is smaller than the angle between the top surface of the conductive layer 220 and the insulating layer 280).

[0372] Subsequently, a heat treatment may be performed. The heat treatment may be performed, for example, at a temperature of 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. For example, the treatment may be performed at a temperature of 350° C. to 550° C. for 1 minute to 1 hour, or 10 minutes to 30 minutes.

[0373] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above heat treatment, impurities such as water contained in the insulating layer 280 and the like can be reduced before the formation of the oxide semiconductor layer 230.

[0374] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 280 and the like as much as possible.

[0375] Here, an example is shown in which the conductive layer 240_1f and the insulating layer 280 are opened using the same mask; however, the conductive layer 240_1f and the insulating layer 280 can also be opened using different masks.

[0376] Subsequently, a part of the conductive layer 240_1f is removed so that the upper end of the conductive layer 240_1f has a rounded shape (FIGS. 27A and 27B).

[0377] For the removal, dry etching treatment, wet etching treatment, ashing treatment, plasma treatment, reverse sputtering treatment, or the like can be used. Here, by performing reverse sputtering treatment before the formation of the conductive layer 240_2f, part of the conductive layer 240_1f can be removed. By performing the reverse sputtering treatment, for example, part of the upper end of the opening of the conductive layer 240_1f can be removed.

[0378] 27C shows an enlarged view of region Q4 shown in FIG. 27A. In the cross-sectional view shown in FIG. 27C, angle An1_r, which is the angle between the tangent to the rounded corner at the upper end of conductive layer 240_1f and the upper surface of conductive layer 220_2, can be reduced. In FIG. 27C, angle An1_r is smaller than angle An0, which is the angle between the side surface of insulating layer 280 in opening 290 and the upper surface of conductive layer 220_2. Also, in FIG. 27C, angle An1_r is smaller than angle An1, which is the angle between the lower end of the side surface of conductive layer 240_1f and the region near it and the upper surface of conductive layer 220_2.

[0379] Subsequently, a conductive layer 240_2f is formed over the conductive layer 240_1f (FIGS. 28A and 28B).

[0380] The conductive layer 240_2f is preferably formed by a deposition method having anisotropy in deposition rate, such as a sputtering method.

[0381] In sputtering, increasing the distance between the sputtering target and the substrate can result in more anisotropic film formation. On the other hand, increasing the distance between the sputtering target and the substrate can result in the conductive layer being formed deeper in openings with a high aspect ratio, potentially resulting in the formation of the conductive layer 240_2f on the upper surface of the conductive layer 220_2 exposed in the recess 290c. If desired, the coverage of the upper surface of the conductive layer 220_2 can be reduced by appropriately adjusting the distance between the sputtering target and the substrate. For example, if the width of the upper end of the opening 290a is 40 nm or more and 100 nm or less and the thickness of the insulating layer 280 is 40 nm or more and 300 nm or less, the distance between the target and the substrate in the sputtering method can be set to 50 mm or more and 1000 mm or less. For example, setting the distance to 200 mm or more and 400 mm or less can result in highly anisotropic film formation with excellent productivity.

[0382] Here, the conductive layer 240_2f is formed by a sputtering method. It is preferable to use the same apparatus for the reverse sputtering process performed before the formation of the conductive layer 240_2f and for the formation of the conductive layer 240_2f. By using the same apparatus, for example, the conductive layer 240_2f can be formed while maintaining a reduced pressure atmosphere after the reverse sputtering process. This can suppress oxidation of the surface of the conductive layer 240_1f between the reverse sputtering process and the formation of the conductive layer 240_2f. Suppressing oxidation can sometimes further reduce the resistance at the interface between the conductive layer 240_1f and the conductive layer 240_2f, which is preferable. Furthermore, using the same apparatus can omit a transfer process between the apparatuses, thereby simplifying the manufacturing process.

[0383] The conductive layer 240_2f has an anisotropic deposition rate, and therefore the deposition rate is slow on steep side surfaces, more specifically, on side surfaces that form a perpendicular angle or an angle close to the perpendicular angle with the top surface of the conductive layer 220. In contrast, the deposition rate is relatively high on gentle side surfaces, more specifically, on side surfaces that form a small angle with the top surface of the conductive layer 220. By forming the upper end of the conductive layer 240_1f into a rounded shape, the conductive layer 240_2f can be selectively formed thicker at the rounded upper end.

[0384] Subsequently, an oxide semiconductor layer 230f is formed so as to cover the opening 290 and the upper surface of the conductive layer 240_2 (FIGS. 29A and 29B). The oxide semiconductor layer 230f is a layer that will become the oxide semiconductor layer 230. The oxide semiconductor layer 230f is formed in contact with the upper surface of the conductive layer 220, the side surface of the insulating layer 280, the side surface of the conductive layer 240_2, and the upper surface of the conductive layer 240_2. When the side surface of the conductive layer 240_1 is exposed in the opening 290, the oxide semiconductor layer 230 is formed in contact with the exposed side surface.

[0385] The oxide semiconductor layer 230f can be formed by stacking a plurality of layers. Here, the oxide semiconductor layer 230f is formed by depositing a first layer, a second layer, and a third layer in this order.

[0386] It is preferable to use a film formation method for the first layer that causes little damage to the insulating layer 280 and does not cause alloying with the insulating layer 280. For example, it is preferable to form the first layer using an ALD method, a PECVD method, a thermal CVD method, an MOCVD method, an MBE method, or the like.

[0387] Furthermore, it is preferable that the oxide semiconductor layer 230f has a high aspect ratio and high coverage on the sidewalls and bottom of the opening 290 having a small diameter. Therefore, it is preferable that at least some of the layers formed as the oxide semiconductor layer 230f be formed using a method with excellent coverage. In particular, by using the ALD method, it is possible to form a film with small thickness variation within the opening 290 along the top surface of the conductive layer 220, the side surface of the insulating layer 280, and the side surface of the conductive layer 240.

[0388] Furthermore, the oxide semiconductor layer 230f preferably has high crystallinity. By increasing the crystallinity of the oxide semiconductor layer 230f, diffusion of impurities in the oxide semiconductor layer 230f is suppressed, and therefore, the electrical characteristics of the transistor are less likely to fluctuate, and reliability can be improved. For example, a metal oxide formed by a sputtering method tends to have high crystallinity. Therefore, by forming at least some of the layers formed as the oxide semiconductor layer 230f by a sputtering method, the oxide semiconductor layer 230f can have crystallinity.

[0389] On the other hand, the sputtering method may have poorer coverage than methods such as the ALD method, etc. Therefore, in consideration of the coverage on the sidewalls and bottom of the opening 290, when the sputtering method is used for one of the layers formed as the oxide semiconductor layer 230f, it is preferable to use a layer formed by a method having excellent coverage in combination with the other layer.

[0390] For a method for forming the oxide semiconductor layer 230f, refer to Embodiment 2.

[0391] Here, first, a first layer is formed by ALD, then a second layer is formed by sputtering, and then a third layer is formed by ALD.

[0392] After the oxide semiconductor layer 230f is formed, heat treatment may be performed. By performing the heat treatment, for example, the crystallinity of the oxide semiconductor layer 230f can be increased. For example, the heat treatment conditions and the heat treatment method described in Embodiment 2 can be used for the heat treatment. Furthermore, the heat treatment does not necessarily have to be performed after the oxide semiconductor layer 230f is formed. For example, the heat treatment may be performed after the insulating layer 250, which will be described later, is formed. Alternatively, the crystallinity of the oxide semiconductor layer 230f can be increased by using heat generated during the formation of the conductive layer 260, which will be described later. Furthermore, impurities in the oxide semiconductor layer 230f can be reduced by performing the heat treatment.

[0393] Furthermore, microwave treatment may be performed after the formation of the oxide semiconductor layer 230f. By performing the microwave treatment, for example, impurities in the oxide semiconductor layer 230f can be reduced. Furthermore, the crystallinity of the oxide semiconductor layer 230f may be improved.

[0394] In the method for manufacturing a semiconductor device of one embodiment of the present invention, the conductive layer 240_2f covers the side surfaces of the conductive layer 240_1f, thereby reducing the contact area between the conductive layer 240_1f and the oxide semiconductor layer 230f. Therefore, for example, extraction of oxygen from the oxide semiconductor layer 230 by the conductive layer 240_1f can be suppressed during the formation of the oxide semiconductor layer 230f and various treatments (heat treatment, microwave treatment, etc.) after the formation of the oxide semiconductor layer 230f. Therefore, formation of oxygen vacancies in the oxide semiconductor layer 230f can be suppressed. Furthermore, consumption of oxygen supplied to the oxide semiconductor layer 230f by microwave treatment can be suppressed by the conductive layer 240_1f.

[0395] Next, the conductive layer 240_1f, the conductive layer 240_2f, and the oxide semiconductor layer 230f are processed into island shapes to form the conductive layer 240_1, the conductive layer 240_2, and the oxide semiconductor layer 230 (FIGS. 30A and 30B). Here, the conductive layer 240_1, the conductive layer 240_2, and the oxide semiconductor layer 230 can be processed collectively using the same mask.

[0396] Note that the steps of processing the conductive layer 240_1f, the conductive layer 240_2f, and the oxide semiconductor layer 230 into island shapes can be performed independently. For example, the step of processing the conductive layer 240_1f and the conductive layer 240_2f into island shapes and the step of processing the oxide semiconductor layer 230f into island shapes can be performed independently.

[0397] Subsequently, the insulating layer 250 is formed on the oxide semiconductor layer 230 and the insulating layer 280. The insulating layer 250 is formed in contact with the oxide semiconductor layer 230.

[0398] Heat generated during the formation of the insulating layer 250 can be used to enhance the crystallinity of the oxide semiconductor layer 230. When the temperature for forming the insulating layer is, for example, 250° C. or higher, more preferably 350° C. or higher, the heat generated during the formation of the insulating layer can enhance the crystallinity of the oxide semiconductor layer 230.

[0399] After the insulating layer 250 is formed, heat treatment may be performed. By performing the heat treatment, for example, the crystallinity of the oxide semiconductor layer 230 can be increased. Furthermore, by performing the heat treatment, the impurity concentration in the insulating layer 250 can be reduced. Note that after the insulating layer 250 is formed, heat treatment is not necessarily performed.

[0400] When heat treatment is performed, it can be performed, for example, at 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. For example, the treatment can be performed at a temperature of 350° C. to 550° C. for 1 minute to 1 hour, or 10 minutes to 30 minutes.

[0401] The heat treatment can be performed in an atmosphere of nitrogen gas or an inert gas, or an oxidizing gas. For example, the heat treatment can be performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. By the heat treatment containing oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor layer 230 can be reduced.

[0402] The heat treatment may be carried out under reduced pressure.

[0403] The conditions for the heat treatment can be determined by reference to the conditions described above.

[0404] Furthermore, microwave treatment is preferably performed after the formation of the insulating layer 250. The insulating layer 250 functions as a gate insulating layer, and therefore preferably has a low impurity concentration. This can prevent impurities from being mixed into a channel formation region of the oxide semiconductor layer. By performing microwave treatment after the formation of the insulating layer 250, the impurity concentration in the insulating layer 250 can be reduced. Furthermore, by performing microwave treatment, the crystallinity of the oxide semiconductor layer 230 may be improved.

[0405] Furthermore, the microwave treatment performed through the insulating layer 250 reduces V in the oxide semiconductor layer. Ｏ By splitting H into oxygen vacancies and hydrogen, it is possible to remove hydrogen as an impurity from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. Furthermore, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the oxide semiconductor layer through the insulating layer 250, thereby further reducing the oxygen vacancies in the oxide semiconductor layer.

[0406] For the conditions of the microwave treatment, reference can be made to the descriptions of microwave treatment in other embodiments.

[0407] In the case where the insulating layer 280 contains oxygen, oxygen is preferably supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230 by heat treatment. Ｏ H can be reduced.

[0408] Subsequently, a conductive layer 260 is formed on the insulating layer 250 .

[0409] In this manner, the semiconductor device shown in FIGS. 1C and 1D can be manufactured.

[0410] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0411] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described. The oxide semiconductor layer of one embodiment of the present invention has a stacked-layer structure. Note that, as will be described later, it may be difficult to identify boundaries between stacked films.

[0412] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0413] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, an oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts.

[0414] For example, the CAAC structure is formed so that the c-axis is perpendicular or substantially perpendicular to the surface or surface of the oxide semiconductor layer on which the oxide semiconductor layer is to be formed. In the CAAC structure, metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is to be formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the oxide semiconductor layer is to be formed.

[0415] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0416] When the oxide semiconductor layer has a CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image. Specifically, the bright spots are observed to be arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed.

[0417] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern.

[0418] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0419] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0420] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to a surface on which the oxide semiconductor layer is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the oxide semiconductor layer has crystallinity.

[0421] Note that the crystallinity of the metal oxide included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0422] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. The metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide may contain indium and zinc as main components and may further contain element M. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0423] Examples of metal oxides that can be used according to one embodiment of the present invention include In—Zn oxide, ITO, indium titanium oxide (In—Ti oxide), In—Ga oxide, indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), In—Ga—Zn oxide, ITSO, indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as IGAZO or IAGZO). Alternatively, Ga—Zn oxide, Al—Zn oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, or the like can be used as the metal oxide according to one embodiment of the present invention.

[0424] By increasing the content of indium in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0425] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element having a higher period number in the periodic table, the field-effect mobility of a transistor may be improved. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0426] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0427] Furthermore, by increasing the zinc content in the metal oxide, the metal oxide can be made highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0428] Furthermore, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0429] In the present embodiment, an In-M-Zn oxide may be used as an example of the metal oxide.

[0430] [Method for Forming Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide by two film formation methods, for example. That is, the oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide by a first film formation method and a second film formation method.

[0431] For example, when the oxide semiconductor layer has a two-layer structure of a first layer and a second layer over the first layer, the oxide semiconductor layer can be manufactured by forming the first layer on a surface to be formed by the second film formation method and then forming the second layer above the first layer by the first film formation method.

[0432] For example, when the oxide semiconductor layer has a three-layer structure including a first layer, a second layer over the first layer, and a third layer over the second layer, the oxide semiconductor layer can be manufactured by forming the first layer on a surface to be formed by the second film formation method, then forming the second layer by the first film formation method, and then forming the third layer by the second film formation method.

[0433] The second film formation method is preferably a film formation method that causes less damage to the surface on which the oxide semiconductor layer is formed than the first film formation method. This can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and a layer on which the oxide semiconductor layer is formed. Furthermore, since impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, the crystallinity of the oxide semiconductor layer can be further improved in some cases.

[0434] Examples of the second film formation method include ALD, CVD, and MBE. Examples of CVD methods include plasma CVD, thermal CVD, photo-assisted CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystalline structure that reflects the crystalline system of the substrate, and can be considered one of the film formation methods that causes less damage to the surface on which the film is formed. A wet method can also be used as the second film formation method. The wet method is one of the film formation methods that causes less damage to the surface on which the film is formed. Examples of the wet method include spray coating.

[0435] The first film formation method is preferably a method capable of forming a crystalline metal oxide film. In this case, it is particularly preferable that the metal oxide film formed has a CAAC structure. Examples of the first film formation method include a sputtering method and a PLD method. Since a metal oxide film formed by a sputtering method is likely to have crystallinity, the sputtering method is suitable as the first film formation method.

[0436] When a metal oxide is formed on a surface to be formed using the first film formation method, damage to the surface to be formed may cause alloying between components contained in the metal oxide and components contained in the layer on the surface to be formed. This alloying may result in the formation of a mixed layer at the interface between the metal oxide and the layer on the surface to be formed. This mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0437] For example, when a sputtering method is used as the first film-forming method, a mixed layer may be formed by particles (also referred to as sputtering particles) emitted from a target or the like, or by energy imparted to a substrate by the sputtering particles or the like. Specifically, when a metal oxide film is formed by the first film-forming method on a silicon-containing insulating layer, such as a silicon oxide film, as a formation surface, silicon may be mixed into the metal oxide. There is a concern that the inclusion of impurities such as silicon into the metal oxide may inhibit the crystallization of the metal oxide. Furthermore, there is a concern that using an oxide semiconductor layer containing impurities in a transistor may adversely affect the initial characteristics or reliability of the transistor. Furthermore, even when heat treatment, which will be described later, is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0438] Therefore, as described above, by forming a metal oxide by the second film formation method before forming a metal oxide by the first film formation method, it is possible to prevent impurities from being mixed into the oxide semiconductor layer. Furthermore, alloying can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor layer can be further increased.

[0439] The ALD method is suitable as the second film formation method because it can suppress damage to the formation surface compared to the sputtering method. Furthermore, the ALD method is a film formation method with better coverage than the sputtering method, and by using the ALD method as the film formation method for the first layer and the third layer, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well covered on steps, openings, etc. with a high aspect ratio.

[0440] Here, a method for forming an In-M-Zn oxide as the first layer or the third layer by ALD will be described.

[0441] First, a source gas containing an indium precursor is introduced into a reaction chamber, and the precursor is adsorbed onto the surface to be formed. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby removing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0442] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and is adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0443] Next, a source gas containing a zinc-containing precursor is introduced into the reaction chamber and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidizing agent is introduced into the reaction chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0444] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor layer on a layer that is a formation surface by an ALD method.

[0445] When an oxide semiconductor layer is formed by the ALD method, ozone (O ３ ), oxygen (O ２ ), water (H２ O) and the like can be used. ３ ), oxygen (O ２ ) or the like is used as an oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor layer can be reduced.

[0446] Here, the temperature to which the substrate is heated when the precursor is introduced into the reaction chamber is defined as a first temperature, and the temperature to which the substrate is heated when the oxidizing agent is introduced into the reaction chamber is defined as a second temperature.

[0447] The first temperature is preferably set to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the first temperature is, for example, 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0448] Note that the second temperature is preferably higher than the first temperature. For example, when the oxidizing agent contains ozone, the second temperature is preferably higher than 200° C. and lower than 450° C., more preferably higher than or equal to 250° C. and lower than or equal to 400° C., and further preferably higher than or equal to 300° C. and lower than or equal to 350° C. With such a configuration, the hydrogen concentration in the oxide semiconductor layer can be reduced. Furthermore, by setting the first temperature lower than the second temperature, particles generated by decomposition of the precursor can be suppressed.

[0449] It is preferable that the reaction chamber into which the precursor is introduced and the reaction chamber into which the oxidizing agent is introduced are the same. This configuration allows for film formation without the need to load and unload the substrate, thereby improving productivity. It is also possible to use different reaction chambers for the introduction of the precursor and the introduction of the oxidizing agent. By providing a first reaction chamber set to a first temperature and a second reaction chamber set to a second temperature, the first temperature and the second temperature can be maintained, respectively. This facilitates temperature control, improving work efficiency and safety.

[0450] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the reaction chamber, and then discharge excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, after the adsorbed precursor is reacted with the oxidant, purge the reaction chamber, and then discharge excess reactant, reaction products, etc. from the reaction chamber.

[0451] Furthermore, in the present specification and elsewhere, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or oxidant, it is not limited to the gas or molecular state, but also includes the plasma state, radical state, and ion state.

[0452] By using the above-described configuration, the thickness of the mixed layer can be reduced, or the thickness can be reduced to such an extent that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and even more preferably 0 nm or more and less than 0.3 nm.

[0453] The thickness of the alloyed region may be calculated by performing a line analysis of the composition of the alloyed region and its surroundings using SIMS or energy dispersive X-ray spectroscopy (EDX).

[0454] For example, EDX line analysis is performed on the alloyed region and its periphery, with the direction perpendicular to the surface on which the first layer is formed as the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer that will become the surface on which the layer is formed (In if the first layer contains In) becomes half-value is defined as the depth (position) of the interface between the region and the first layer. Furthermore, the depth at which the quantitative value of an element that is the main component of the layer that will become the surface on which the layer is formed and is not the main component of the first layer (e.g., Si) becomes half-value is defined as the depth (position) of the interface between the region and the layer that will become the surface on which the layer is formed. From the above, the thickness of the alloyed region can be calculated.

[0455] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the alloyed region is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0456] For example, when SIMS analysis is performed on an oxide semiconductor layer formed on a silicon oxide film that is a surface to be formed, the depth at which the silicon concentration is 50% of the maximum concentration of the silicon oxide film is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the depth at which the thickness decreases to 3 nm and the interface is defined as thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0457] By reducing the thickness of the alloyed region, the thickness t_s2 can be set to a value within the above range.

[0458] Note that by reducing the alloyed region, it is possible to form a CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region that is more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm, approximately perpendicularly from the formation surface of the oxide semiconductor layer.

[0459] Note that the CAAC structure near the formation surface can be confirmed in some cases by observation using a TEM. For example, in cross-sectional observation of an oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed near the formation surface.

[0460] The first layer may be, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure. The crystallinity of the first layer may be increased by forming a second layer with high crystallinity on the first layer with low crystallinity or by performing heat treatment after forming the second layer, with the second layer acting as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which the oxide semiconductor layer is formed.

[0461] Since the second layer has high crystallinity, the third layer can grow using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0462] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0463] When the oxide semiconductor layer is used as a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor layer, may be in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is on.

[0464] The oxide semiconductor layer in this embodiment can be used as the oxide semiconductor layer 230 or the like included in each transistor described in Embodiment 1. The layer serving as a formation surface corresponds to one or more of the conductive layer 220, the insulating layer 280, the conductive layer 240, the insulating layer 225, or the like described in Embodiment 1.

[0465] The layer serving as the formation surface is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film, or a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the formation surface does not need to have crystallinity. When the layer has crystallinity, it may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor layer.

[0466] Furthermore, after the oxide semiconductor layer is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer. The heat treatment here is not limited to heat treatment. For example, heat applied during a manufacturing process may be used.

[0467] After the formation of the first layer, a microwave plasma treatment is preferably carried out.

[0468] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0469] It is preferable to perform microwave plasma treatment in an atmosphere containing oxygen to reduce the impurity concentration in the oxide semiconductor layer 230. Examples of impurities include hydrogen and carbon. Although the above example illustrates a structure in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0470] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, more preferably from 50 to 700 Pa, and even more preferably from 100 to 400 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and can be from 400 to 450°C.

[0471] When performing microwave plasma treatment, the substrate may be heated to a temperature of at least room temperature (e.g., 25°C), at least 100°C, at least 200°C, at least 300°C, or at least 400°C, and preferably at most 500°C or at most 450°C.

[0472] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and not greater than 10%, more preferably 0.5% to 5%, more preferably 0.5% to 3%, and typically more preferably 1%.

[0473] By performing microwave plasma treatment in an atmosphere containing oxygen, oxygen gas is converted into plasma using microwaves or high frequency waves such as RF, and oxygen radicals generated by converting the oxygen gas into plasma can act on the oxide semiconductor layer. By the action of plasma, microwaves, oxygen radicals, or the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ By splitting V (sometimes referred to as H) into oxygen vacancies and hydrogen, the hydrogen impurities can be removed from the oxide semiconductor layer. Ｏ H can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this way, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, by supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor layer, the oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0474] Furthermore, microwave plasma treatment can improve the crystallinity of the first layer. Here, the principle of how microwave plasma treatment improves the crystallinity of an oxide semiconductor will be described. First, activated species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the activated species and oxygen in the oxide semiconductor. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable that the activated species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, thereby improving the crystallinity of the oxide semiconductor.

[0475] On the other hand, a reaction occurs between part of the oxygen in the oxide semiconductor that exists before the microwave plasma treatment and hydrogen in the oxide semiconductor. In other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0476] After the microwave plasma treatment, a heat treatment may be performed without exposing the substrate to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0477] It should be noted that the crystallinity can be improved by plasma treatment containing oxygen gas instead of microwave plasma treatment.

[0478] The increased crystallinity of the first layer can further increase the crystallinity of the second layer formed over the first layer, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0479] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions having an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer may be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals.

[0480] The second layer is preferably formed by sputtering.

[0481] An In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0482] Furthermore, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during deposition (hereinafter also referred to as oxygen flow rate ratio), the more crystalline the metal oxide that can be formed.

[0483] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0484] When forming a metal oxide using a sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during metal oxide formation, a metal oxide with high crystallinity may be formed. When forming a metal oxide using a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0485] When a third layer is formed on a second layer having a CAAC structure by ALD, the third layer may grow epitaxially using the second layer as a nucleus. Therefore, during the formation of the third layer, the third layer may have a region having the CAAC structure. Furthermore, the region having the CAAC structure is preferably formed throughout the entire third layer.

[0486] After forming the third layer, a heat treatment step may be performed.

[0487] The heat treatment temperature may be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. A typical temperature is 400°C ± 25°C (375°C or higher and 425°C or lower). The treatment time may be 10 hours or less, for example, 1 minute or higher and 5 hours or lower, or 1 minute or higher and 2 hours or lower. When an RTA apparatus is used, the treatment time may be, for example, 1 second or higher and 5 minutes or lower. It is expected that the heat treatment will repair gaps in the atomic-level crystalline portions of the CAAC structure of the second layer with the third layer (in other words, molecules having each crystallinity formed using the ALD method).

[0488] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0489] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the third layer. Furthermore, if the region is formed only below the third layer after film formation by the ALD method, the heat treatment step may cause the region to expand upward. That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire third layer.

[0490] Furthermore, it is preferable that at least a portion of the first layer is converted into CAAC by the heat treatment process. It is expected that the CAAC conversion is facilitated by the mixed layer formed in the first layer during the formation of the second layer acting as a nucleus or seed. It is preferable that the region in the first layer that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the surface to be formed.

[0491] Furthermore, because the CAAC is formed from the top to the bottom of the first layer, the CAAC can be formed up to the vicinity of the layer regardless of the material or crystallinity of the layer on which the CAAC is formed. For example, even if the layer has an amorphous structure, the first layer can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer on which the CAAC is formed has an amorphous structure.

[0492] After the third layer is formed, microwave plasma treatment may be performed.

[0493] Further, by performing one or both of the above-described heat treatment and microwave plasma treatment, the crystallinity of the entire oxide semiconductor layer can be increased.

[0494] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0495] Note that one or both of the heat treatment and the microwave plasma treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0496] The first layer and the third layer each have high crystallinity using the highly crystalline second layer as a nucleus or seed. Specifically, the crystallinity of the first layer may be increased by heat treatment during the deposition of the second layer or after the deposition of the third layer. The crystallinity of the third layer may be increased by heat treatment during the deposition of the third layer or after the deposition of the third layer. The heat treatment has an assisting effect of increasing the crystallinity.

[0497] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower metal oxides (the first layer and the third layer in this case) can be increased by using the second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower metal oxides can be grown in a solid phase using the second layer as a nucleus or seed to form an oxide semiconductor layer with high crystallinity. An oxide semiconductor layer formed by such a film formation method, i.e., a CAAC film in this case, can be referred to as an axial growth CAAC (AG CAAC).

[0498] In the oxide semiconductor layer, a region having a CAAC structure is preferably present widely throughout the layer. The region having the CAAC structure in the first layer is crystallinely connected to the region having the CAAC structure in the second layer. The region having the CAAC structure in the third layer is crystallinely connected to the region having the CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Furthermore, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor layer may be expressed as a single layer whose interface is not clearly observed. The oxide semiconductor layer may be expressed as a single layer.

[0499] In each of the first to third layers, in a region having the CAAC structure, for example, bright spots aligned parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed are observed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure in each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0500] Furthermore, a portion of the first layer or the third layer may not be crystallized.

[0501] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0502] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor layer, the boundaries between the stacked films of the first to third layers may not be visible. In particular, it may be difficult to identify the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional scanning transmission electron microscope (STEM), or the like.

[0503] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the first layer and the third layer, crystals that reflect the crystal orientation of the second layer are formed, and polycrystallization can be suppressed.

[0504] Furthermore, it is preferable that the lattice mismatch between the crystals of the second layer and the crystals of the first layer or the third layer is small. This allows the first layer or the third layer to have crystals that reflect the orientation of the crystals of the second layer. In this case, for example, in cross-sectional observation of the oxide semiconductor layer using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the first layer or the third layer.

[0505] The crystal structure of the first layer or the third layer is not particularly limited as long as the lattice mismatch between the crystals of the second layer and the crystals of the first layer or the third layer is small. The crystal structure of the first layer or the third layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0506] The oxide semiconductor layer of one embodiment of the present invention can be formed by using the second film formation method and one or both of microwave plasma treatment and heat treatment. In other words, the oxide semiconductor layer of one embodiment of the present invention can be formed without forming a second layer. In this case, the oxide semiconductor layer has a two-layer structure including a first layer and a third layer. For example, by performing one or both of microwave plasma treatment and heat treatment after forming the first layer, the crystallinity of the first layer can be increased, and the crystallinity of the third layer can be increased using the first layer as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the third layer, the crystallinity of the oxide semiconductor layer can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer.

[0507] As described above, even in a structure in which the second layer is not provided, the oxide semiconductor layer above can be grown by solid-phase growth using the first layer as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a deposition method can also be called an AG CAAC.

[0508] [Composition of Oxide Semiconductor Layer] The second layer preferably has a different composition from the first layer. The second layer preferably has a different composition from the third layer. The first layer may have the same composition as the third layer. Alternatively, the first layer and the third layer may have different compositions.

[0509] The second layer preferably contains In, and more preferably has a high content of In. By using a metal oxide with a high content of In as the oxide semiconductor layer 230b, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0510] As described above, the second layer preferably has a composition suitable for forming a CAAC structure. The second layer preferably contains, for example, zinc. By containing zinc, the second layer becomes a metal oxide with high crystallinity.

[0511] The second layer may be, for example, an In-Zn oxide. Specifically, the second layer may have a composition of In:Zn=1:1 (atomic ratio) or a composition close thereto, an In:Zn=2:1 (atomic ratio) or a composition close thereto, or an In:Zn=4:1 (atomic ratio) or a composition close thereto. Alternatively, an indium oxide may be used. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0512] The second layer preferably contains the element M. When the second layer contains the element M, for example, oxygen vacancies can be suppressed from being formed in the metal oxide. Therefore, the reliability of a transistor using the oxide semiconductor layer can be improved. Specifically, the second layer may be formed of a metal oxide having a composition of In:M:Zn=1:1:1 (atomic ratio) or a composition therearound, an In:M:Zn=1:1:1.2 (atomic ratio) or a composition therearound, an In:M:Zn=1:1:0.5 (atomic ratio) or a composition therearound, an In:M:Zn=1:1:2 (atomic ratio) or a composition therearound, an In:M:Zn=4:2:3 (atomic ratio) or a composition therearound, an In:M:Zn=1:3:2 (atomic ratio) or a composition therearound, or an In:M:Zn=1:3:4 (atomic ratio) or a composition therearound.

[0513] The second layer may also be configured to contain a trace amount of element M. For example, the second layer may have a composition of In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition thereabout, or In:Ga:Zn=1:0.1:1 (atomic ratio) or a composition thereabout. Furthermore, the second layer may have a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition thereabout, In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition thereabout, or In:Sn:Zn=1:0.1:1 (atomic ratio) or a composition thereabout.

[0514] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease by up to about 50% compared to the sputtering target.

[0515] The first and third layers may each use a metal oxide that can be used for the second layer.

[0516] For example, the first layer and the third layer can be made of a metal oxide having a higher In content than the second layer. By using a metal oxide having a higher In content, when the oxide semiconductor layer is used in a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0517] Furthermore, for example, metal oxides having a higher Ga content than the second layer can be used for the first layer and the third layer. For example, it is preferable to use a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition thereabout, a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or a composition thereabout, or a metal oxide having a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or a composition thereabout for the first layer and the third layer, respectively. By increasing the Ga content, for example, the band gaps of the first layer and the third layer can be made larger than that of the second layer in some cases. As a result, the second layer is sandwiched between the first layer and the third layer, which have larger band gaps, and the second layer functions mainly as a current path (channel). By sandwiching the second layer between the first layer and the third layer, it is possible to reduce trap levels at the interface of the second layer and its vicinity. This allows for a buried-channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may form on the back channel side is reduced, suppressing light degradation (e.g., negative-bias light degradation) of the transistor and improving its reliability.

[0518] Alternatively, one of the first layer and the third layer may be a metal oxide having a higher In content than the second layer, and the other may be a metal oxide having a higher Ga content than the second layer.

[0519] The first layer, the second layer, and the third layer may each have a plurality of layers having the above-described composition stacked together. For example, the third layer may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0520] When forming a metal oxide film containing multiple metal elements, such as In—Ga—Zn oxide, using the ALD method, the ratio of the number of cycles of precursors containing each metal element can be set to match the target composition. For example, when forming an In—Ga—Zn oxide film with an atomic ratio of In:Ga:Zn=1:3:2, one cycle of forming an In-containing precursor and treating it with an oxidizing agent can be performed, three cycles of forming a Ga-containing precursor and treating it with an oxidizing agent can be performed, and two cycles of forming a Zn-containing precursor and treating it with an oxidizing agent can be performed. However, the ratio of the number of cycles of precursors containing each metal element and the atomic ratio of each metal element in the formed metal oxide film may not necessarily match.

[0521] In the oxide semiconductor layer of one embodiment of the present invention, even when the first layer and the third layer are formed using compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the second layer as a nucleus, so that the entire oxide semiconductor layer including the first layer and the third layer can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of each of the first layer and the third layer and the second layer.

[0522] In particular, even when the first layer and the third layer have a high In content, the oxide semiconductor layer can have suitable crystallinity for a semiconductor layer of a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0523] The first and third layers may be made of a metal oxide having the same composition as that of the second layer. Using the same composition may make it easier for the first and third layers to become CAAC after heat treatment.

[0524] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0525] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0526] The composition of the metal oxide used in the oxide semiconductor layer can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0527] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of this embodiment can be used as a semiconductor layer of a transistor.

[0528] The oxide semiconductor layer of this embodiment has a CAAC structure. In the oxide semiconductor layer having the CAAC structure, metal atoms are arranged in a layered manner in a direction parallel or substantially parallel to a surface on which the oxide semiconductor layer is formed in a crystal portion.

[0529] It is estimated that an oxide semiconductor layer having a CAAC structure exhibits current anisotropy. For example, in an IGZO crystal, current flows more easily in the a-axis direction than in the c-axis direction. That is, it is estimated that in an oxide semiconductor layer having a CAAC structure, current flows more easily in the horizontal direction than in the vertical direction.

[0530] In the semiconductor device described in the above embodiment, the oxide semiconductor layer 230 has metal atoms arranged in a layered manner in a direction parallel or substantially parallel to the surface where the oxide semiconductor layer 230 is formed. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel or substantially parallel to the surface where the oxide semiconductor layer 230 is formed. Here, the oxide semiconductor layer 230 is provided along the sidewall of the opening 290. Therefore, in the oxide semiconductor layer 230, the metal atoms are arranged in a layered manner in a direction parallel or substantially parallel to the sidewall of the opening 290. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0531] When the oxide semiconductor layer of this embodiment is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer is preferably 1 nm to 20 nm, further preferably 3 nm to 15 nm, further preferably 5 nm to 12 nm, and further preferably 5 nm to 10 nm. Furthermore, the average thickness of the oxide semiconductor layer in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0532] The second layer preferably has a thickness of, for example, 200 nm or less. When the second layer is lamellar, the thickness is preferably, for example, 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and more preferably 2 nm or more and 100 nm or less.

[0533] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not exist in a layered structure but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer exist discretely.

[0534] The first layer and the third layer each preferably have a thickness of 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm. The first layer is further preferably 0.5 nm to 3 nm.

[0535] [Impurities in Oxide Semiconductor] Here, the influence of each impurity in an oxide semiconductor will be described.

[0536] As described in the above embodiment, in a transistor including an oxide semiconductor for a semiconductor layer, oxygen vacancies (V Ｏ The presence of impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of an OS transistor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0537] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably１９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0538] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5×10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10１７ atoms / cm ３ The following applies.

[0539] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0540] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0541] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0542] This embodiment mode can be combined with other embodiment modes or examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0543] 31A to 35. The memory device of one embodiment of the present invention includes a memory cell. The memory cell includes a transistor and a capacitor.

[0544] <Configuration Example 1 of Memory Device> The configuration of a memory device including a transistor and a capacitor will be described with reference to Figures 31A to 31C. Figure 31A is a plan view of a memory device including a transistor 200 and a capacitor 100. Figure 31B is a cross-sectional view taken along dashed line A1-A2 in Figure 31A. Figure 31C is a cross-sectional view taken along dashed line A3-A4 in Figure 31A.

[0545] 31A to 31C includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a memory cell 150 over the conductive layer 110, and an insulating layer 180 and an insulating layer 280 over the conductive layer 110. The insulating layer 140, the insulating layer 180, and the insulating layer 280 function as interlayer films. The conductive layer 110 functions as a wiring.

[0546] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0547] The capacitor 100 includes a conductive layer 115 over the conductive layer 110, an insulating layer 130 over the conductive layer 115, and a conductive layer 220_1 over the insulating layer 130. The conductive layer 220_1 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. That is, the capacitor 100 forms a metal-insulator-metal (MIM) capacitor. Note that the conductive layer 220_2 provided over the conductive layer 220_1 can also be considered as part of the upper electrode of the capacitor 100.

[0548] As shown in FIGS. 31B and 31C , an opening 190 reaching the conductive layer 110 is provided in the insulating layer 180. At least a portion of the conductive layer 115 is disposed in the opening 190. Note that the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the top surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion of it is located in the opening 190. The conductive layer 220_1 is disposed so that at least a portion of it is located in the opening 190. Note that, as shown in FIGS. 31B and 31C , the conductive layer 220_1 is preferably provided so as to fill the opening 190. Note that the films provided inside the opening 190 are preferably formed using an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 220_1 are preferably formed by an ALD method.

[0549] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric sandwiched between them on the side surfaces as well as the bottom surface within the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, this can promote miniaturization or high integration of memory devices.

[0550] 31B and 31C show an example in which the sidewall of the opening 190 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a structure, miniaturization or high integration of the memory device can be achieved.

[0551] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the top surface of the conductive layer 110. In addition, a conductive layer 220_1 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor 100 having such a configuration may be called a trench capacitor.

[0552] In addition, an insulating layer 280 is disposed over the capacitor 100. The insulating layer 280 has a portion located over the insulating layer 130 and a portion located over the conductive layer 220_2.

[0553] The transistor 200 includes a conductive layer 220 including a conductive layer 220_1 and a conductive layer 220_2, a conductive layer 240 over an insulating layer 280, an oxide semiconductor layer 230, an insulating layer 250 over the oxide semiconductor layer 230, and a conductive layer 260 over the insulating layer 250.

[0554] In the transistor 200, the oxide semiconductor layer 230 functions as a semiconductor layer, the conductive layer 260 functions as a gate electrode, the insulating layer 250 functions as a gate insulating layer, the conductive layer 220 functions as one of a source electrode and a drain electrode, and the conductive layer 240 functions as the other of the source electrode and the drain electrode.

[0555] The detailed description of the transistor 200 will be omitted because the description in Embodiment 1 ( FIG. 2A ) can be referred to. The transistor included in the memory cell 150 is not limited to the transistor 200, and each of the transistors exemplified in Embodiment 1 can be applied.

[0556] As shown in FIGS. 31A to 31C , the transistor 200 is provided so as to overlap with the capacitor 100. Furthermore, an opening 290 in which part of the structure of the transistor 200 is provided overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. In particular, the conductive layer 220 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be densely arranged and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated. FIGS. 31B and 31C show an example in which the width of the opening 190 is smaller than the width of the opening 290. The relationship between the width of the opening 190 and the width of the opening 290 is not particularly limited. From the viewpoint of miniaturization, it is preferable that the width of the opening 190 be equal to or smaller than the width of the opening 290 .

[0557] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0558] 37A shows a circuit diagram of the memory device described in this embodiment. As shown in FIG. 37A, the configurations shown in FIGS. 31A to 31C function as memory cells. The memory cell 951 includes a transistor M1 and a capacitor CA. Here, the transistor M1 corresponds to the transistor 200, and the capacitor CA corresponds to the capacitor 100.

[0559] One of the source and drain of the transistor M1 is connected to one of a pair of electrodes of the capacitor CA. The other of the source and drain of the transistor M1 is connected to a wiring BIL. The gate of the transistor M1 is connected to a wiring WOL. The other of the pair of electrodes of the capacitor CA is connected to a wiring CAL.

[0560] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. As shown in FIGS. 31A to 31C , it is preferable that the conductive layer 260 is provided extending in the X direction, and the conductive layer 240 is provided extending in the Y direction. With this configuration, the wiring BIL and the wiring WOL are provided so as to intersect with each other. Also, in FIG. 31A , the wiring CAL (conductive layer 110) is provided in a planar shape, but the present invention is not limited to this. For example, the wiring CAL may be provided parallel to the wiring WOL (conductive layer 260) or parallel to the wiring BIL (conductive layer 240).

[0561] The memory cells will be described in detail in a later embodiment.

[0562] [Capacitor 100] The capacitor 100 includes a conductive layer 115, an insulating layer 130, and a conductive layer 220_1. The conductive layer 110 is provided below the conductive layer 115. The conductive layer 115 has a region in contact with the conductive layer 110.

[0563] The conductive layer 110 is provided over the insulating layer 140. The conductive layer 110 functions as a wiring CAL and can be provided in a planar shape, for example. The conductive layer 110 can be formed as a single layer or a stacked layer using the conductive material described in the section [Conductive Layer] of Embodiment 1. For example, a conductive material with high conductivity, such as tungsten, can be used as the conductive layer 110. By using such a conductive material with high conductivity, the conductivity of the conductive layer 110 can be improved, allowing the conductive layer 110 to function sufficiently as a wiring CAL.

[0564] The conductive layer 115 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion, and is used in a single layer or a stacked layer. For example, titanium nitride or ITSO may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. With such a structure, when an oxide is used for the insulating layer 130, the insulating layer 130 can suppress oxidation of the conductive layer 110. Furthermore, when an oxide is used for the insulating layer 180, the insulating layer 180 can suppress oxidation of the conductive layer 110.

[0565] The insulating layer 130 is provided on the conductive layer 115. The insulating layer 130 is provided so as to be in contact with the top surface and side surfaces of the conductive layer 115. In other words, the insulating layer 130 preferably has a structure that covers the side end portions of the conductive layer 110. This can prevent a short circuit between the conductive layer 115 and the conductive layer 220_1.

[0566] Alternatively, a structure may be used in which the side edges of the insulating layer 130 coincide with the side edges of the conductive layer 115. With such a structure, the insulating layer 130 and the conductive layer 115 can be formed using the same mask, which can simplify the manufacturing process of the memory device.

[0567] It is preferable to use a material with a high relative dielectric constant (high-k) for the insulating layer 130. By using a high-k material for the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently ensured.

[0568] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a high-k material, and preferably by using a stack structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0569] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material that can have ferroelectricity, the description in the first embodiment can also be referred to.

[0570] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when they are as thin as a few nanometers, and are therefore preferred as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0571] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0572] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0573] The conductive layer 220_1 is provided in contact with a part of the upper surface of the insulating layer 130. The side end of the conductive layer 220_1 is preferably located inside the side end of the conductive layer 115 in both the X direction and the Y direction. Note that in a structure in which the insulating layer 130 covers the side end of the conductive layer 115, the side end of the conductive layer 220_1 may be located outside the side end of the conductive layer 115.

[0574] Since the insulating layer 180 functions as an interlayer film, it preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced. As the insulating layer 180, an insulating layer containing a material with a low dielectric constant can be used in a single layer or a stacked layer. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0575] 31B and 31C, the insulating layer 180 is shown as a single layer, but the present invention is not limited to this. The insulating layer 180 may have a stacked structure of two layers, or a stacked structure of three or more layers.

[0576] <Structure Example 2 of Memory Device> FIGS. 32A and 32B are cross-sectional views of a memory device including a transistor 200a and a transistor 200b.

[0577] 32A and 32B includes an insulating layer 140 over a substrate (not shown), a memory cell 150 over the insulating layer 140, an insulating layer 280a over the insulating layer 140, and an insulating layer 280b above the insulating layer 280a. The insulating layer 140, the insulating layer 280a, and the insulating layer 280b function as interlayer films.

[0578] The memory cell 150 includes a transistor 200a on the insulating layer 140 and a transistor 200b on the transistor 200a.

[0579] For the transistor 200a and the transistor 200b, the description of the transistor 200 ( FIG. 2A ) in Embodiment 1 can be referred to, and detailed description thereof will be omitted. For example, the configuration of the conductive layer 220a, the oxide semiconductor layer 230a, and the like can be referred to by replacing the conductive layer 220 with the conductive layer 220a and the oxide semiconductor layer 230 with the oxide semiconductor layer 230a, etc. Furthermore, for example, the configuration of the conductive layer 220b, the oxide semiconductor layer 230b, and the like can be referred to by replacing the conductive layer 220 with the conductive layer 220b and the oxide semiconductor layer 230 with the oxide semiconductor layer 230b, etc.

[0580] The insulating layer 280a and the insulating layer 280b can have the same structure as that used for the insulating layer 280.

[0581] The transistors included in the memory cell 150 are not limited to the combination of the transistor 200a and the transistor 200b, and one or more types of the transistors exemplified in Embodiment 1 can be used.

[0582] In the memory cell 150 shown in FIGS. 32A and 32B, capacitance generated between the conductive layer 220b and the conductive layer 240a can be used; therefore, data can be held without forming a separate capacitor.

[0583] The shortest distance from the top surface of the conductive layer 240a to the conductive layer 220b is preferably shorter than the shortest distance from the top surface of the conductive layer 240b to the gate wiring (conductive layer 260b in FIG. 32A ). This can increase the capacitance generated between the conductive layer 220b and the conductive layer 240a. Furthermore, the parasitic capacitance generated between the conductive layer 240b and the gate wiring can be reduced. For example, the structure of the transistor 200A described in Embodiment 1 may be applied to the transistor 200b.

[0584] As shown in FIGS. 32A and 32B , the transistor 200b is provided so as to overlap with the transistor 200a. An opening 290 in which part of the structure of the transistor 200b is provided overlaps with an opening 290a in which part of the structure of the transistor 200a is provided. In particular, the conductive layer 220b functions as one of the source electrode and drain electrode of the transistor 200b and as the gate electrode of the transistor 200a. Therefore, the transistors 200b and 200a share part of their structures. With this structure, the transistors 200b and 200a can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cells 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0585] 37E shows a circuit diagram of the memory device described in this embodiment. As shown in FIG. 37E, the configuration shown in FIGS. 32A and 32B functions as a memory cell. The memory cell 955 includes a transistor M2 and a transistor M3. Here, the transistor M2 corresponds to the transistor 200b, and the transistor M3 corresponds to the transistor 200a.

[0586] One of the source and drain of transistor M2 is connected to the gate of transistor M3. The other of the source and drain of transistor M1 is connected to wiring WBL. The gate of transistor M2 is connected to wiring WOL. One of the source and drain of transistor M3 is connected to wiring RBL. The other of the source and drain of transistor M3 is connected to wiring SL.

[0587] Here, the wiring WBL corresponds to the conductive layer 240b, and the wiring WOL corresponds to the conductive layer 260b. As shown in Figures 32A and 32B, it is preferable that the conductive layer 260b is provided extending in the X direction, and the conductive layer 240b is provided extending in the Y direction. With this configuration, the wiring WBL and the wiring WOL are provided so as to intersect with each other.

[0588] The transistor M2 may have a back gate, and similarly, the transistor M3 may have a back gate.

[0589] <Configuration Example 3 of Memory Device> The memory cell 150 including the transistor 200 and the capacitor 100 described in this embodiment can be used as a memory cell of a memory device. The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 has a low off-state current; therefore, by using the transistor 200 in a memory device, stored data can be retained for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low; therefore, the power consumption of the memory device can be sufficiently reduced. Furthermore, the high frequency characteristics of the transistor 200 enable high-speed reading and writing of data from and to the memory device.

[0590] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix.

[0591] 33A is a plan view of a memory device, showing an example in which 2×2 memory cells (memory cells 150a to 150d) are arranged in the X and Y directions.

[0592] Fig. 33B is a cross-sectional view taken along dashed line A3-A4 in Fig. 33A. In Fig. 33A and Fig. 33B, two memory cells (memory cell 150a and memory cell 150b in Fig. 33B) are connected to a common wiring (conductive layer 246).

[0593] A circuit diagram corresponding to two memory cells is shown in Figure 37B. As shown in Figure 37B, the memory device 952 has two memory cells, one of which has a transistor M1 and a capacitor CA1, and the other of which has a transistor M2 and a capacitor CA2. For example, when comparing Figure 37B with Figure 33B, the transistor M1 corresponds to the transistor 200a, the capacitor CA1 corresponds to the capacitor 100a, the transistor M2 corresponds to the transistor 200b, and the capacitor CA2 corresponds to the capacitor 100b.

[0594] One of the source and drain of transistor M1 is connected to one of a pair of electrodes of capacitor CA1. The other of the source and drain of transistor M1 is connected to wiring BIL. The gate of transistor M1 is connected to wiring WOL1. The other of the pair of electrodes of capacitor CA1 is connected to wiring CAL. One of the source and drain of transistor M2 is connected to one of a pair of electrodes of capacitor CA2. The other of the source and drain of transistor M2 is connected to wiring BIL. The gate of transistor M2 is connected to wiring WOL2. The other of the pair of electrodes of capacitor CA2 is connected to wiring CAL.

[0595] Here, the wiring BIL corresponds to the conductive layer 240 , the wiring WOL 1 corresponds to the conductive layer 260 , the wiring WOL 2 corresponds to another conductive layer 260 , and the wiring CAL corresponds to the conductive layer 110 .

[0596] Each of the memory cells 150a and 150b shown in Figures 33A and 33B has a configuration similar to that of the memory cell 150. The memory cell 150a includes a capacitor 100a and a transistor 200a, and the memory cell 150b includes a capacitor 100b and a transistor 200b. The memory cells 150c and 150d shown in Figure 33A also have a configuration similar to that of the memory cell 150. Therefore, in the memory device shown in Figures 33A and 33B, structures having the same functions as those of the structures constituting the memory device shown in Figure 31 are denoted by the same reference numerals. For details of the memory cells 150a to 150d, the description of the memory cell 150 in <Configuration Example 1 of Memory Device> can be referred to.

[0597] 33A and 33B , a conductive layer 260 functioning as a wiring WOL is provided in each of the memory cells 150a and 150b. As shown in FIG. 33A , one conductive layer 260 is provided in common to the memory cells 150a and 150c, and another conductive layer 260 is provided in common to the memory cells 150b and 150d. One conductive layer 240 functioning as part of a wiring BIL is provided in common to the memory cells 150a and 150b. That is, the conductive layer 240 is in contact with the oxide semiconductor layer 230 of the memory cell 150a and the oxide semiconductor layer 230 of the memory cell 150b. The other conductive layer 240 is provided in common to the memory cells 150c and 150d.

[0598] FIG. 33B shows an example in which the conductive layer 240 has a two-layer structure including a conductive layer 240_1 and a conductive layer 240_2 over the conductive layer 240_1.

[0599] 33A and 33B includes conductive layers 245 and 246 which are connected to the memory cell 150a and the memory cell 150b and function as plugs (also referred to as connection electrodes). The conductive layer 245 is disposed in openings formed in the insulating layer 140, the insulating layer 180, the insulating layer 130, and the insulating layer 280, and is in contact with the bottom surface of the conductive layer 240_1. The conductive layer 246 is disposed in openings formed in the insulating layer 286, the insulating layer 250, and the oxide semiconductor layer 230, and is in contact with the top surface of the conductive layer 240_2. Note that the conductive layers 245 and 246 can be formed using a conductive material that can be used for the conductive layer 240, or the like.

[0600] The conductive layer 246 can be in contact with the top surface of the conductive layer 240_1. Alternatively, the conductive layer 246 can be in contact with the top surface of the oxide semiconductor layer 230. That is, the conductive layer 240_2 may have an opening at a position overlapping with the conductive layer 246. The oxide semiconductor layer 230 does not necessarily have an opening at a position overlapping with the conductive layer 246. As a connection portion between the memory cell and the plug, a layer having low contact resistance with the conductive layer 246 among the layers constituting the conductive layer 240 and the oxide semiconductor layer 230 is preferably in contact with the conductive layer 246.

[0601] Similarly, the conductive layer 245 can be in contact with a bottom surface of the conductive layer 240_2 or a bottom surface of the oxide semiconductor layer 230. That is, the conductive layer 240_1 may have an opening at a position overlapping with the conductive layer 246. Of the layers constituting the conductive layer 240 and the oxide semiconductor layer 230, a layer having low contact resistance with the conductive layer 245 is preferably in contact with the conductive layer 245.

[0602] Of the layers constituting the conductive layer 240 and the oxide semiconductor layer 230 , a layer having low wiring resistance is preferably in contact with the conductive layer 245 and the con...

Claims

an oxide semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer; the first insulating layer is located on the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have a first opening at a position where they overlap with the first conductive layer; the second conductive layer includes a first layer and a second layer on the first layer; the second layer has a portion covering a top surface of the first layer and a portion covering a side surface of the first layer, the oxide semiconductor layer has a portion located on the second layer, a portion located on the first conductive layer within the first opening, a portion covering a sidewall of the first insulating layer within the first opening, and a portion facing the side surface of the first layer within the first opening with the second layer interposed therebetween; the second insulating layer is located on the oxide semiconductor layer; the third conductive layer is located on the second insulating layer; the third conductive layer faces the oxide semiconductor layer in the first opening with the second insulating layer therebetween; Semiconductor device. 　 In claim 1, the first conductive layer has a first recess; the first opening of the first insulating layer and the second conductive layer overlaps with the first recess; Semiconductor device. 　 In claim 1, the first layer comprises a metal or an alloy; the second layer comprises an oxygen-containing conductive material or a nitrogen-containing conductive material; Semiconductor device. 　 In claim 1, the first layer comprises tungsten; the second layer comprises indium tin oxide containing silicon; Semiconductor device. 　 forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; removing a portion of the second conductive layer and a portion of the first insulating layer to form a first opening reaching the first conductive layer and exposing an upper surface of the first conductive layer; forming a third conductive layer so as to cover an upper surface of the second conductive layer and a side surface of the second conductive layer within the first opening; forming a first oxide semiconductor layer so as to cover the top surface of the first conductive layer, a side surface of the first insulating layer within the first opening, a side surface of the third conductive layer, and a top surface of the third conductive layer; forming a third insulating layer on the first oxide semiconductor layer; forming a fourth conductive layer on the third insulating layer; A method for manufacturing a semiconductor device. 　 In claim 5, In forming the first opening, the removal of the portion of the second conductive layer is performed using a dry etching process; after the dry etching process and before forming the third conductive layer, removing a portion of an upper end of the first opening of the second conductive layer using a reverse sputtering process; A method for manufacturing a semiconductor device. 　 In claim 5, In forming the first opening, a recess overlapping the first opening is formed in the first conductive layer. A method for manufacturing a semiconductor device. In claim 5 or claim 6, the third conductive layer includes a conductive material containing oxygen or a conductive material containing nitrogen, the third conductive layer is formed by using a sputtering method. A method for manufacturing a semiconductor device. 　 In claim 5 or claim 6, the third conductive layer comprises indium tin oxide containing silicon; the third conductive layer is formed by using a sputtering method. A method for manufacturing a semiconductor device.

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