Computer system and deployment material deployment method therefor

Abstract

In a computer system (101), a device scheduler (220) allocates a computer (320) serving as a location where a circuit (400) that operates on one node of a plurality of nodes (300) is to be pre-positioned. A controller (210) acquires spare circuit information (410) from a deployment material database (211) and transfers the spare circuit information to the node having the computer serving as the preposition location. Each node, upon receiving an instruction from the controller, transfers spare circuit information stored in a storage (310) within the node to an empty computer.

Description

Computer system and method for deploying its deployment materials

[0001] The present invention relates to a computer system and a method for deploying deployment materials therefor, and more particularly to a computer system with fault prevention measures and a method for deploying deployment materials therefor.

[0002] In a networked system with multiple field-programmable gate arrays (FPGAs), a power-efficient data processing platform can be realized by flexibly switching the FPGA function allocation according to the usage status of the applications running on the system. When deploying functions to FPGAs, a device scheduler must allocate free FPGAs and transfer circuit information to local storage.

[0003] In conventional technologies, it is possible to recover from a failure by using, for example, the Kubernetes mechanism (see, for example, Non-Patent Document 1). In container technology, the failure recovery process involves rebuilding a pod on the same node or a different node, and the work required for this is performed after the failure occurs. Here, the required work includes, for example, pulling (obtaining) a container image (application container image).

[0004] “Deployment”, Kubernetes, September 17, 2023, [online], [Retrieved January 19, 2024], Internet〈URL: https: / / kubernetes.io / ja / docs / concepts / workloads / controllers / deployment / 〉

[0005] If the target system were to undergo the same disaster recovery procedures as container technology, after a disaster occurs, it would be necessary to allocate a new FPGA device, download deployment materials (applications), write circuits to the FPGA, and so on, which would take time to recover.

[0006] Therefore, an object of the present invention is to solve the above problems and improve the speed of recovery when a failure occurs in a computer system.

[0007] The computer system of the present invention comprises a plurality of nodes, each having at least one computer and a storage that stores circuit information for the computer to realize a function; a device scheduler that, when requested to assign a predetermined function to be executed by the computer, refers to a device management database, calculates a score based on the specifications and / or resource usage of each computer, and assigns the computer with the highest score; and a controller that obtains circuit information for realizing the predetermined function from a deployment material database and transfers the circuit information to a node that includes the computer to be assigned, wherein the device scheduler assigns a computer to be used as a location for pre-deployment of a function that operates on one of the plurality of nodes, the controller obtains spare circuit information from the deployment material database and transfers the spare circuit information to the node that includes the computer to be used as the pre-deployment location, and the node, when instructed by the controller, migrates the spare circuit information stored in the storage within the node to an empty computer.

[0008] According to the present invention, it is possible to improve the recovery speed when a fault occurs in a system having an FPGA in a network.

[0009] 1 is a schematic configuration diagram of a computer system according to a first embodiment. FIG. 2 is a sequence diagram showing the operation of the computer system according to the first embodiment. FIG. 3 is a schematic configuration diagram of a computer system according to a comparative example. FIG. 4 is a schematic diagram showing an example of circuit allocation in the event of a failure in the computer system according to the comparative example. FIG. 5 is a schematic diagram showing an example of circuit information pre-deployed in the computer system according to the first embodiment. FIG. 6 is a schematic diagram showing an example of circuit allocation in the event of a failure in the computer system according to the first embodiment. FIG. 7 is a schematic diagram showing an example of some circuit information being concentrated and deployed in only one node. FIG. 8 is a schematic diagram showing an example of some circuit information being distributed and deployed to multiple nodes. FIG. 9 is a flowchart showing the flow of processing by a device scheduler in a computer system according to a second embodiment. FIG. 10 is an explanatory diagram of processing by a device scheduler according to the second embodiment, showing three candidate deployment destinations. FIG. 11 is an explanatory diagram of processing by a device scheduler according to the second embodiment, showing node 3 having been filtered out. FIG. 12 is an explanatory diagram of processing by a device scheduler according to the second embodiment, showing node 1 having also been filtered out. FIG. 13 is a schematic diagram showing an example of circuit information pre-deployed in the computer system according to the second embodiment. FIG. 14 is a hardware configuration diagram showing an example of a computer that realizes the functions of each unit of the computer system according to the embodiment.

[0010] The computer system according to this embodiment will be described in detail below with reference to the drawings. [System Configuration] As shown in Fig. 1, the computer system 101 includes a plurality of nodes 300 and a central control unit 200 that controls each of the nodes 300. Each node 300 includes a storage 310 and at least one computer. In this embodiment, the computer included in the node 300 is described as an FPGA 320. The storage 310 stores circuit information 410 that enables the FPGA (computer) 320 to realize its functions.

[0011] Here, the circuit information is a bitstream, and when simply referred to as a circuit, it refers to something deployed in a node. A circuit is hardware in the node's FPGA that has circuit information written to it. In other words, a circuit can be said to be an FPGA when the FPGA is executing the function specified by the circuit information. When no circuit information is written to an FPGA, it is called an empty FPGA. An empty FPGA cannot execute a specified function. When the node 300 receives an instruction from the controller 210, it transfers the circuit information 410 stored in the storage 310 within the node 300 to the empty FPGA 320.

[0012] The number of multiple nodes in the computer system 101 is arbitrary. When nodes are to be distinguished, they are written as node 1, node 2, etc., and when they are not distinguished, they are written as node 300. Similarly, when storages are to be distinguished, they are written as storage 1, storage 2, etc., and when they are not distinguished, they are written as storage 310. When FPGAs are to be distinguished, the FPGA included in node 1 is written as FPGA 1-1, FPGA 1-2, etc., and the FPGA included in node 2 is written as FPGA 2-1, FPGA 2-2, etc., and when they are not distinguished, they are written as FPGA 320. When circuits are to be distinguished, they are written as circuit 1, circuit 2, etc., and when they are not distinguished, they are written as circuit 400. When circuit information is to be distinguished, they are written as circuit information 1, circuit information 2, etc., and when they are not distinguished, they are written as circuit information 410.

[0013] The central control unit 200 includes a controller 210 and a device scheduler 220. The controller 210 assigns a predetermined function to each FPGA 320. To do this, the controller 210 requests the device scheduler 220 to assign the predetermined function. The controller 210 acquires circuit information 410 for realizing the predetermined function from a deployment material database (hereinafter referred to as deployment material DB) 211, and transfers the circuit information 410 to the node 300 including the FPGA 320 to which the predetermined function is to be assigned.

[0014] The controller 210 detects a failure in a node 300. In this embodiment, the node failure detection unit that detects a node failure may be installed either inside or outside the controller 210, but as an example, it is assumed that a node failure detection unit (not shown) is installed externally. When the node failure detection unit (not shown) detects a node failure, it notifies the controller 210 of an alarm. The controller 210 determines that a node failure has occurred by receiving this alarm.

[0015] As a countermeasure against failures, the controller 210 requests the device scheduler 220 to assign spare circuit information 410 to be pre-deployed. The spare circuit information 410 is spare information for the circuit information 410 that realizes a function that operates on any one of the multiple nodes 300. The controller 210 acquires the spare circuit information 410 from the deployment material DB 211, and transfers the spare circuit information 410 to the node 300 that includes the FPGA 320 where a predetermined function is to be pre-deployed.

[0016] When the controller 210 detects a failure in the node 300, it notifies a migration instruction to the node 300 having the spare circuit information 410 that realizes the function of the failed node 300. The migration instruction is an instruction to migrate the spare circuit information 410 stored in the storage 310 to the empty FPGA 320. When the node 300 receives the instruction from the controller 210, it migrates the spare circuit information 410 stored in the storage 310 within the node 300 to the empty FPGA 320.

[0017] In this embodiment, the controller 210 transfers the spare circuit information 410 to the FPGA 320 where the spare circuit information 410 will be pre-placed, and then updates the pre-placement management database (hereinafter, pre-placement management DB) 225. The pre-placement management DB 225 stores pre-placement information indicating the correspondence between the spare circuit information 410 and the FPGA 320 where the spare circuit information 410 will be placed.

[0018] The device scheduler 220 assigns an allocation destination for a predetermined function in response to a request from the controller 210. When the device scheduler 220 is requested to assign an allocation destination for a predetermined function executed by the FPGA 320, the device scheduler 220 refers to a device management database (hereinafter referred to as device management DB) 221, calculates a score based on the specifications and / or resource usage status of each FPGA 320, and assigns the FPGA 320 with the highest score. As a fault prevention measure, the device scheduler 220 assigns an FPGA 320 where spare circuit information 410 is to be pre-placed in response to a request from the controller 210.

[0019] In this embodiment, the device scheduler 220 refers to the device management DB 221 and the pre-arrangement management DB 225 to assign the FPGA 320 where the spare circuit information 410 is to be pre-arranged.

[0020] [Operation of the Computer System] Next, the operation of the computer system will be described with reference to Fig. 2 (and Fig. 1 as appropriate). Assume that when a specific circuit 400 is operating on a specific node 300, spare circuit information 410 is placed on another node before a failure occurs. At this time, the controller 210 requests the device scheduler 220 to provide a pre-placement location for the spare circuit information (step S10).

[0021] The device scheduler 220 then executes a calculation process to determine an appropriate node (step S20). In this calculation process, the device scheduler 220 references the device management DB 221 (step S22) and the pre-disposition management DB 225 (step S23). The device scheduler 220 then determines an appropriate node based on the nodes 300 that have free FPGAs 320 and the deployment status of the spare circuit information 410 in each node 300. The device scheduler 220 then determines the placement location where the spare circuit information 410 is to be pre-placed (step S10R).

[0022] After assigning the allocation location, the device scheduler 220 updates the pre-arrangement management DB 225 (step S30). The pre-arrangement management DB 225 notifies the device scheduler 220 of the completion of the update (step S30R).

[0023] The controller 210 then acquires spare circuit information 410 from the deployment material DB 211 (see FIG. 1 ) and transfers the spare circuit information 410 to the node 300 that includes the FPGA 320 where the spare circuit information 410 will be placed in advance (step S40). At this time, the controller 210 instructs the node that has stored the same circuit information as the transferred spare circuit information in its storage to delete the same circuit information. The node 300 notifies the controller 210 of the completion of the transfer or instruction reception (step S40R).

[0024] After transferring the spare circuit information 410, the controller 210 updates the pre-arrangement management DB 225 (step S50). The pre-arrangement management DB 225 notifies the completion of the update (step S50R).

[0025] Subsequently, if a failure occurs in, for example, node 1, the controller 210 detects the failure in node 1 (step S60). The controller 210 then references the pre-deployment location of the spare circuit information for the circuit of node 1 based on the pre-deployment management DB 225 (step S70). If the pre-deployment location of the spare circuit information is, for example, node 2, the controller 210 instructs node 2 to deploy the function of node 1 (step S80). Upon receiving the instruction from the controller 210, node 2 performs migration processing (step S90). That is, node 2 migrates the spare circuit information 410 (circuit information 1: see FIG. 6 ) stored in storage 2 within node 2 to empty FPGA 2-2. Node 2 then notifies the controller 210 of the completion of the migration processing (step S80R).

[0026] Each time a node failure occurs, the controller 210 repeats the request for a pre-arrangement location. Also, each time the device management DB 221 is updated due to the replacement or addition of a node 300, the controller 210 requests the device scheduler 220 for a pre-arrangement location.

[0027] (Comparative Example) Here, in order to provide a comparison with the computer system 101 according to the first embodiment, a computer system (comparative example) that recovers from a failure using the mechanism of the conventional technology described in Non-Patent Document 1 will be described. In the comparative example, (1) an ideal state, such as the operating state of a Pod, is always maintained using a Replica Set. (2) If a Pod stops operating normally due to a node failure or the like, the Replica Set automatically redeploys the Pod to a normal node. (3) When redeploying after a failure occurs, a node allocation request is made to the scheduler and the container image is pulled. Note that a Pod is a component of an application workload and is an object. A Replica Set is the owner of a set of Pods.

[0028] This comparative example will be described with reference to Figures 3 and 4. The computer system 501 shown in Figure 3 does not pre-install deployment materials, but has a configuration similar to that of the computer system 101. Here, the computer system 501 includes nodes 1, 2, 3, and 4, and a central control unit 500. The central control unit 500 includes a controller 510 and a device scheduler 520.

[0029] The state shown in Figure 3 is a state after transition from the initial state in which all nodes have empty storage and FPGAs, as follows: First, the controller 510 requests the device scheduler 520 to assign circuits 1, 2, and 3. The device scheduler 520 then references the device management DB 521, calculates scores based on the specifications and / or resource usage status, and assigns the FPGA with the highest score. The controller 510 then obtains circuit information (Bitstream) to be written to the FPGA from the deployment material DB 511. The deployment material DB 511 stores container image (circuit information 1), container image (circuit information 2), container image (circuit information 3), and so on.

[0030] Then, when the controller 510 transfers circuit information 1 to node 1, node 1 stores circuit information 1 (corresponding to circuit 1) in storage 1. When the controller 510 transfers circuit information 2 to node 2, node 2 stores circuit information 2 (corresponding to the allocation destination of circuit 2) in storage 2. When the controller 510 transfers circuit information 3 to node 3, node 3 stores circuit information 3 (corresponding to the allocation destination of circuit 3) in storage 3.

[0031] Then, in response to an instruction from the controller 510, node 1 writes circuit information 1 stored in storage 1 to FPGA 1-1, and circuit 1 operates in node 1. In response to an instruction from the controller 510, node 2 writes circuit information 2 stored in storage 2 to FPGA 2-1, and circuit 2 operates in node 2. In response to an instruction from the controller 510, node 3 writes circuit information 3 stored in storage 3 to FPGA 3-1, and circuit 3 operates in node 3. Note that node 4 remains in the initial state.

[0032] The state shown in Fig. 4 is the state after transition from the state shown in Fig. 3 by the following operations. Note that X in Fig. 4 indicates a fault. First, the controller 510 detects the fault in node 1. Then, the controller 510 requests the device scheduler 520 to allocate circuit 1 (function 1) running in node 1 as deployment material. Then, the device scheduler 520 issues a new FPGA (FPGA4-1) to the controller 510.

[0033] The controller 510 then obtains circuit information 1 (corresponding to circuit 1) to be written to the new FPGA (FPGA 4-1) from the deployment material DB 511. The controller 510 then transfers the circuit information 1 to node 4, which then stores the circuit information 1 (corresponding to circuit 1) in storage 4. Then, in response to an instruction from the controller 510, node 4 writes the circuit information 1 stored in storage 4 to FPGA 4-1, and circuit 1 begins operating in node 4.

[0034] In this way, in the comparative example, circuit 1 (function 1) that was running on node 1 runs on node 4, which is the new allocation destination (redeployment destination), so circuit 1 can be restored. However, in the comparative example, circuit information 1 is included in the container image and transferred to node 4, the redeployment destination, after a failure occurs. In other words, the comparative example has the disadvantage that after a failure occurs, it is necessary to download deployment materials with a large data size, and recovery takes time.

[0035] Next, an example of the computer system 101 according to the first embodiment will be described with reference to FIGS. 5 and 6. The state shown in FIG. 5 is a state after transition from the state shown in FIG. 1 by the following operations. First, the controller 210 requests the device scheduler 220 to provide pre-placement locations for each of circuit 1, circuit 2, circuit 3, and circuit 4. The device scheduler 220 then references the device management DB 121 and pre-placement management DB 125. The device scheduler 220 then assigns the nodes (assignment information 1 to 4) on which circuit 1, circuit 2, circuit 3, and circuit 4 are to be pre-placed. Assignment information 1 indicates that the pre-placement node for circuit 1 is node 2. Assignment information 2 indicates that the pre-placement node for circuit 2 is node 1. Assignment information 3 indicates that the pre-placement node for circuit 3 is node 1. Assignment information 4 indicates that the pre-placement node for circuit 4 is node 2.

[0036] The controller 210 then transfers the circuit information (spare circuit information) to the pre-deployment nodes in accordance with each assignment information. Specifically, the controller 210 transfers circuit information 2 and circuit information 3 to node 1 as spare circuit information. The controller 210 also transfers circuit information 4 and circuit information 1 to node 2 as spare circuit information. Additionally, the controller 210 instructs nodes that have stored the same circuit information as the transferred spare circuit information in their storage to delete that circuit information. Accordingly, the controller 210 instructs node 1 to delete circuit information 1 (see FIG. 1), instructs node 2 to delete circuit information 2 (see FIG. 1), and instructs node 3 to delete circuit information 3 (see FIG. 1). After pre-deployment of the deployment materials, the controller 210 updates the pre-deployment management DB 225. In this way, the state shown in FIG. 1 transitions to the state shown in FIG. 5.

[0037] The state shown in FIG. 6 is the state after transition from the state shown in FIG. 5 by the following operation. Note that X in FIG. 6 indicates a failure. When the controller 210 detects that a failure has occurred in node 1, it references the pre-placement management DB 225 to check the pre-placement destination of the corresponding circuit (circuit 1). The controller 210 then instructs the node (node ​​2) that was already pre-placed at the time of the failure to migrate circuit information 1 stored in storage 2 to FPGA 2-2. After the migration is complete, the controller 210 instructs the device scheduler 220 to recalculate the pre-placement destination for the spare circuit information in the computer system 101. The device scheduler 220 then references the device management DB 221 and the pre-placement management DB 225 and updates the pre-placement destination information for the spare circuit information after the recalculation.

[0038] 3 to 6, in the comparative example, the transfer of circuit information is required after issuing a deploy command, whereas in the computer system 101 according to the first embodiment, the transfer of circuit information is performed in advance, thereby shortening the recovery time. In this way, when a failure occurs in one of the multiple nodes 300, the computer system 101 can quickly recover the computing function assigned to the node where the failure occurred by using the deployment materials that have been pre-deployed.

[0039] (Variation) In the computer system 101, when a node 300 fails, the multiple circuits 400 operating on the failed node 300 are migrated at the same time. Therefore, if the multiple circuits 400 operating on the failed node 300 are migrated to the same node 300, there is a possibility that the migration destination node 300 will lack free FPGAs 320, making it impossible to migrate when a failure occurs.

[0040] This will be explained in detail using the examples shown in the upper part of Figure 7 and the upper part of Figure 8. As shown in the figure, node 1 has FPGA 1-1, FPGA 1-2, and FPGA 1-3, and circuit 1, circuit 2, and circuit 3 are active, respectively. Node 2 has FPGA 2-1 and FPGA 2, both of which are empty FPGAs. Node 3 has FPGA 3-1 and FPGA 3-2, and circuit 4 is active in FPGA 3-1. FPGA 3-2 is an empty FPGA. Note that before the spare circuit information is placed, no circuit information is stored in storages 1 to 3.

[0041] For example, suppose that in computer system 101, the pre-deployment destinations (pre-deployment nodes) for spare circuit information are randomly determined, and the pre-deployment locations (FPGAs) for circuits 1 to 4 end up concentrated on node 2 by chance. This state is shown in the lower part of Figure 7. In this case, if a failure occurs in node 3, for example, circuit 4 can be migrated to node 2, so there is no problem. On the other hand, if a failure occurs in node 1, attempts are made to migrate circuits 1, 2, and 3 to node 2, but the number of available FPGAs is insufficient, making the migration impossible.

[0042] Also, for example, in computer system 101, assume that the pre-deployment locations of circuit 1, circuit 2, and circuit 3 of node 1 are distributed to node 2 and node 3. This state is shown in the lower part of Figure 8. In this case, for example, if a failure occurs in node 3, circuit 4 can be migrated to node 2, so there is no problem. Also, if a failure occurs in node 1, circuit 1 and circuit 2 can be migrated to node 2, and circuit 3 can be migrated to node 3, so there is no problem. For this reason, it is preferable to distribute the pre-deployment locations of multiple circuits operating on the same node.

[0043] Second Embodiment A computer system according to the second embodiment differs from the first embodiment in that it performs processing to distribute the pre-deployment destinations of multiple circuits operating on the same node. Note that the same components as in the first embodiment are assigned the same reference numerals and descriptions thereof will be omitted. A device scheduler 220 according to the second embodiment distributes each of multiple circuits (functions) operating on the same node 300 to FPGAs 320 belonging to mutually different nodes 300. The procedure by which the device scheduler 220 according to the second embodiment determines the nodes to which deployment materials are to be pre-deployed will be described with reference to FIG. 9 (and also with reference to FIG. 1 as appropriate).

[0044] The device scheduler 220 receives a request for a placement location from the controller 210 (step S21). The device scheduler 220 then references the device management DB 221 (step S22) and the pre-placement management DB 225 (step S23). The device scheduler 220 then filters out nodes in which the same circuit as the requested circuit is running (step S24). The device scheduler 220 then filters out, from the remaining nodes, nodes that satisfy the following formula (1) (step S25):

[0045] N-M ≦ 0... Formula (1)

[0046] Here, N indicates the number of free FPGAs in the node, and M indicates the number of pre-deployed circuits that operate in the same node as the circuit for which pre-deployment location is requested.

[0047] Then, the device scheduler 220 randomly assigns a node from among the nodes where an empty FPGA exists (step S10R).

[0048] Next, a specific example of the operation of the device scheduler 220 will be described in detail with reference to Figures 10A to 10C. Figure 10A shows an example of the initial state. In the initial state, circuit 4 is operating in node 3. As a countermeasure against a failure in node 3, it is assumed that spare circuit information 4 is previously deployed in a node other than node 3. Note that circuit 3 is also operating in node 3.

[0049] Here, the controller 210 requests a pre-placement location for circuit information 4 from the device scheduler 220. The device scheduler 220 receives the pre-placement location request for circuit information 4. In step S24 described above, the device scheduler 220 filters out nodes in which the same circuit as the circuit (circuit 4) that is the target of the pre-placement location request is operating. In this example, circuit 4 is operating in node 3. Therefore, the device scheduler 220 filters out node 3 as shown in FIG. 10B.

[0050] Next, in step S25, the device scheduler 220 determines whether the above-mentioned formula (1) is satisfied for each node. For example, in node 1, the number of free FPGAs N is 1. Also, in node 1, the pre-deployment number M of the circuit information (circuit information 3) for the circuit (circuit 3) that operates in the same node (node ​​3) as the circuit (circuit 4) for which a pre-deployment location is requested is 1. That is, in node 1, N-M = 0≦0, which satisfies formula (1). Therefore, the device scheduler 220 filters node 1 as shown in FIG. 10C.

[0051] On the other hand, in node 2, the number of free FPGAs N is 1. Also, in node 2, the number of pre-deployed circuits M in the circuit information (circuit information 3) for the circuit (circuit 3) that operates in the same node (node ​​3) as the circuit (circuit 4) for which a pre-deployment location is requested is 0. That is, in node 2, N - M = 1, which does not satisfy the relational expression. Therefore, the device scheduler 220 does not filter node 2.

[0052] Then, in step S10R, the device scheduler 220 randomly selects one node from the nodes with free FPGAs and assigns it as a pre-placement node. As a result, the device scheduler 220 assigns node 2 in response to the pre-placement request from the controller 210.

[0053] Next, an example of pre-deployed circuit information will be described as an example of a computer system according to the second embodiment. The configuration of the computer system according to the second embodiment is the same as that shown in FIG. 1, but the number of the following components differs from that shown in FIG. 1: Total number of FPGAs 320: 10 Total number of circuits 400: 7 Number of nodes 300: 5

[0054] The components of the computer system according to the second embodiment will be described with reference to FIG. 11 . As shown in the upper part of FIG. 11 , node 1 includes FPGAs 1-1 and 1-2, with circuit 1 running in FPGA 1-1. FPGA 1-2 is an empty FPGA. Node 2 includes FPGAs 2-1 and 2-2, with circuits 2 and 3 running, respectively. Node 3 includes FPGAs 3-1 and 3-2, with circuits 4 and 5 running, respectively. Node 4 includes FPGAs 4-1 and 4-2, with circuit 6 running in FPGA 4-1. FPGA 4-2 is an empty FPGA. Node 5 includes FPGAs 5-1 and 5-2, with circuit 7 running in FPGA 5-1. FPGA 5-2 is an empty FPGA. It is assumed that no circuit information is stored in storages 1 to 5 before the spare circuit information is allocated.

[0055] The bottom part of Figure 11 shows the result of the device scheduler 220 according to the second embodiment determining the pre-deployment destination (pre-deployment node) of spare circuit information. The assignment information, the redeployment destination in the event of a failure, and the distribution status are as follows: (Assignment Information) The pre-deployment node for circuit 1 is node 4. The pre-deployment node for circuit 2 is node 1. The pre-deployment node for circuit 3 is node 5. The pre-deployment node for circuit 4 is node 1. The pre-deployment node for circuit 5 is node 5. The pre-deployment node for circuit 6 is node 5. The pre-deployment node for circuit 7 is node 1.

[0056] (Redeployment destination when a failure occurs) When node 1 fails, the redeployment destination is node 4. When node 2 fails, the redeployment destination is node 1 and node 5. When node 3 fails, the redeployment destination is node 1 and node 5. When node 4 fails, the redeployment destination is node 5. When node 5 fails, the redeployment destination is node 1.

[0057] (Distribution status) Circuit 2 of node 2 was pre-deployed to node 1, and circuit 3 of node 2 was pre-deployed to node 5. Both node 1 and node 5 have one free FPGA, so it was confirmed that the spare circuit information can be migrated when a node 2 fails. Circuit 4 of node 3 was pre-deployed to node 1, and circuit 5 of node 3 was pre-deployed to node 5. Both node 1 and node 5 have one free FPGA, so it was confirmed that the spare circuit information can be migrated when a node 2 fails.

[0058] [Hardware Configuration] The central control unit 200 and each unit within the central control unit 200 of the computer system 101 according to the embodiment are realized by a computer 900 configured as shown in Fig. 12. The computer 900 has a CPU 901, a RAM (Random Access Memory) 902, a ROM (Read Only Memory) 903, an HDD (Hard Disk Drive) 904, an accelerator 905, an input / output I / F (Interface) 906, a media I / F 907, and a communication I / F 908.

[0059] The accelerator 905 processes at high speed at least one of data from the communication I / F 908 and data from the RAM 902. Note that the accelerator 905 may be of a type (look-aside type) that executes processing from the CPU 901 or RAM 902 and then returns the execution results to the CPU 901 or RAM 902. Alternatively, the accelerator 905 may be of a type (in-line type) that performs processing between the communication I / F 908 and the CPU 901 or RAM 902.

[0060] The accelerator 905 is connected to an external device 915 via a communication I / F 908. The input / output I / F 906 is connected to an input / output device 916. The media I / F 907 reads and writes data from and to a recording medium 917.

[0061] The CPU 901 operates based on a program stored in the ROM 903 or HDD 904, and controls each part of the central control unit 200 shown in Fig. 1 by executing a program loaded into the RAM 902. This program can also be distributed via a communication line or recorded on a recording medium 917 such as a CD-ROM. The ROM 903 stores a boot program executed by the CPU 901 when the computer 900 starts up, programs related to the hardware of the computer 900, and the like.

[0062] The CPU 901 controls an input / output device 916, which is made up of input units such as a mouse and a keyboard, and output units such as a display and a printer, via an input / output I / F 906. The CPU 901 acquires data from the input / output device 916 via the input / output I / F 906, and outputs generated data to the input / output device 916. Note that a GPU or the like can also be used as a processor together with the CPU 901.

[0063] The HDD 904 stores programs executed by the CPU 901 and data used by the programs. The communication I / F 908 receives data from other devices via a communication network and outputs the data to the CPU 901, and also transmits data generated by the CPU 901 to other devices via the communication network.

[0064] The media I / F 907 reads a program or data stored in a recording medium 917 and outputs it to the CPU 901 via the RAM 902. The CPU 901 loads a program related to a target process from the recording medium 917 onto the RAM 902 via the media I / F 907, and executes the loaded program. The recording medium 917 is an optical recording medium such as a DVD (Digital Versatile Disc) or a PD (Phase Change Rewritable Disc), a magneto-optical recording medium such as an MO (Magneto Optical Disk), a magnetic recording medium, or a semiconductor memory.

[0065] For example, when the computer 900 functions as the central control unit 200 of the computer system 101 according to the embodiment, the CPU 901 executes a program loaded onto the RAM 902 to realize the functions of the central control unit 200 of the computer system 101. The HDD 904 also stores data in the RAM 902. The CPU 901 reads and executes a program related to a target process from the recording medium 917. Alternatively, the CPU 901 may read a program related to a target process from another device via a communication network.

[0066] [Effects] As described above, the computer system 101 includes a plurality of nodes 300 each having at least one computer 320 and a storage 310 storing circuit information 410 for the computer 320 to realize a function, a device scheduler 220 that, when requested to allocate a predetermined function executed by the computer 320, refers to the device management database 221, calculates a score based on the specifications and / or resource usage status of each computer 320, and assigns the computer 320 with the highest score, and a node 300 that obtains the circuit information 410 for realizing the predetermined function from the deployment material database 211 and assigns the computer 320 to be allocated. and a controller 210 that transfers the circuit information 410 to the node 300, wherein the device scheduler 220 assigns a computer 320 that will be the location where a function that operates on one of the multiple nodes 300 will be pre-deployed, the controller 210 acquires the spare circuit information 410 from the deployment material database 211 and transfers the spare circuit information 410 to the node 300 that has the computer 320 that will be the location where the function will be pre-deployed, and when the node 300 receives an instruction from the controller 210, the node 300 migrates the spare circuit information 410 stored in the storage 310 within the node 300 to the empty computer 320.

[0067] In this way, the computer system 101 allocates spare circuit information 410 in advance to other nodes 300 based on the operating status and availability of the computers 320 included in a specified node 300. When a failure occurs in a specified node 300, by using the circuit information 410 that has already been allocated to other nodes 300, it is possible to reduce the time required to restore the functions of the computer 320 in the node 300 where the failure occurred. Therefore, it is possible to speed up failure recovery in the computer system 101.

[0068] The computer system 101 is characterized in that, after the controller 210 transfers the spare circuit information 410 to the computer 320 where the spare circuit information 410 is to be pre-placed, the controller 210 updates the pre-placement management database 225 that stores pre-placement information indicating the correspondence between the spare circuit information 410 and the computer 320 where the spare circuit information 410 is to be pre-placed, and the device scheduler 220 refers to the device management database 221 and the pre-placement management database 225 to assign the computer 320 where the spare circuit information 410 is to be pre-placed.

[0069] In this way, the device scheduler 220 can refer to the pre-arrangement management database 225, take into consideration the correspondence between the spare circuit information 410 that has already been arranged and the computer 320 where that circuit information will be arranged, and assign an appropriate computer 320 for pre-arranging the spare circuit information 410. Therefore, the computer system 101 can speed up failure recovery and improve the reliability of failure recovery.

[0070] The computer system 101 is characterized in that the device scheduler 220 distributes each of a plurality of functions operating on the same node 300 to computers 320 belonging to different nodes 300 .

[0071] This prevents a situation in which migration becomes impossible when a failure occurs due to an insufficient number of computers 320 in the destination node 300 that are provided with functions for the circuit 400 operating in the failed node 300. Therefore, the computer system 101 can speed up failure recovery and improve the reliability of failure recovery.

[0072] The present invention is not limited to the above-described embodiment, and many modifications within the technical spirit of the present invention are possible for those skilled in the art. For example, in the above embodiment, the computer included in node 300 is an FPGA 320. However, accelerators other than FPGAs, such as programmable logic devices (PLDs) and graphics processing units (GPUs), can also be used. The system having an FPGA in a network described in the above embodiment is one example of application of the present invention. Furthermore, the present invention is applicable not only to network systems, but also to systems requiring high-speed recovery, for example. Furthermore, the present invention is applicable to any system that requires the transfer of some kind of material during deployment.

[0073] 101 Computer system 200 Central control unit 210 Controller 211 Deployment material DB (Deployment material database) 220 Device scheduler 221 Device management DB (Device management database) 225 Pre-deployment management DB (Pre-deployment management database) 300 Node 310 Storage 320 FPGA (computer) 400 Circuit 410 Circuit information

Claims

1. A computer system comprising: a plurality of nodes each having at least one computer and storage for storing circuit information for the computer to realize a function; a device scheduler that, when requested to assign a predetermined function to be executed by the computer, refers to a device management database, calculates a score based on the specifications and / or resource usage of each computer, and assigns the computer with the highest score; and a controller that obtains circuit information for realizing the predetermined function from a deployment material database and transfers the circuit information to a node equipped with the computer to which the function will be assigned, wherein the device scheduler assigns a computer to be used in advance to deploy a function that operates on one of the plurality of nodes; the controller obtains from the deployment material database information on a spare circuit to be used in advance and transfers the spare circuit information to the node equipped with the computer to be used in advance; and the node, when instructed by the controller, migrates the spare circuit information stored in the storage within the node to an empty computer.

2. The computer system according to claim 1, wherein the controller, after transferring the spare circuit information to the computer where the spare circuit information is to be pre-placed, updates a pre-placement management database that stores pre-placement information indicating the correspondence between the spare circuit information and the computer where the spare circuit information is to be pre-placed, and the device scheduler refers to the device management database and the pre-placement management database to assign a computer where the spare circuit information is to be pre-placed.

3. The computer system according to claim 1 or 2, wherein said device scheduler distributes each of a plurality of functions operating on the same node to computers belonging to mutually different nodes.

4. A method for deploying deployment materials in a computer system comprising: a plurality of nodes each having at least one computer and storage for storing circuit information for the computer to realize a function; a device scheduler that, when requested to assign a predetermined function executed by the computer, refers to a device management database, calculates a score based on the specifications and / or resource usage of each computer, and assigns the computer with the highest score; and a controller that obtains circuit information for implementing the predetermined function from a deployment material database and transfers the circuit information as deployment material to a node comprising the computer to which the function is to be assigned, wherein the device scheduler assigns a computer to be used in advance for deploying a function that operates on one of the plurality of nodes; the controller obtains from the deployment material database information on spare circuit information to be used in advance and transfers the spare circuit information to the node comprising the computer to be used in advance; and the node, when instructed by the controller, migrates the spare circuit information stored in the storage within the node to an empty computer.

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