Semiconductor substrate, semiconductor device, and method for manufacturing semiconductor device

Abstract

[Problem] To provide a semiconductor substrate that comprises a group III-V compound semiconductor having few crystal defects above a group IV semiconductor substrate, a semiconductor device, and a method for manufacturing the semiconductor device. [Solution] The semiconductor substrate according to the present disclosure comprises a group IV semiconductor substrate, a first material layer that includes a group III-V material or a group II-VI material provided on the group IV semiconductor substrate, a first two-dimensional substance layer that is provided on the first material layer, and a second material layer that includes a group III-V material provided above the first two-dimensional substance layer.

Description

Semiconductor substrate, semiconductor device, and method of manufacturing semiconductor device

[0001] The present disclosure relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor device.

[0002] 2. Description of the Related Art Semiconductor devices such as semiconductor lasers, light-emitting diodes, infrared image sensors, and infrared SPADs (Single Photon Avalanche Diodes) are often formed on III-V group compound semiconductors such as GaAs and InP.

[0003] JP 2018-535536 A JP 2021-175694 A JP 2022-541490 A JP 2022-541284 A

[0004] Since III-V compound semiconductor substrates are expensive, it has been considered to grow III-V compound semiconductors on relatively inexpensive silicon substrates.

[0005] However, III-V compound semiconductors formed on silicon substrates have a high density of crystal defects, which degrade the characteristics of the semiconductor device and reduce its reliability.

[0006] Therefore, the present disclosure provides a semiconductor substrate including a group III-V compound semiconductor with low crystal defects above a group IV semiconductor substrate, a semiconductor device, and a method for manufacturing the semiconductor device.

[0007] A semiconductor substrate according to one aspect of the present disclosure includes a group IV semiconductor substrate, a first material layer including a group III-V material or a group II-VI material provided on the group IV semiconductor substrate, a first two-dimensional material layer provided on the first material layer, and a second material layer including a group III-V material provided above the first two-dimensional material layer.

[0008] The group IV semiconductor substrate is a silicon substrate or a germanium substrate, and the first material layer includes any one of GaP, AlGaAs, ZnSSe, MgSSe, and CdSSe.

[0009] The first two-dimensional material layer is either graphene, a single layer of hexagonal boron nitride (h-BN), amorphous graphene, or amorphous hexagonal boron nitride.

[0010] The second material layer is one of AlGaInAs, InP, AlGaInSb, and GaAs.

[0011] The semiconductor substrate further comprises a third material layer including a III-V material disposed between the first layer of two-dimensional material and the second layer of material, and a second layer of two-dimensional material disposed between the third layer of material and the second layer of material.

[0012] When the group IV semiconductor substrate is a silicon substrate, the first material layer includes GaP, the second material layer includes GaAs, InP or GaSb, and the third material layer includes GaAs or GaAsP.

[0013] The semiconductor substrate further comprises a fourth material layer including a III-V material disposed between the second layer of two-dimensional material and the second material layer, and a third layer of two-dimensional material disposed between the fourth material layer and the second material layer.

[0014] When the group IV semiconductor substrate is a silicon substrate, the first material layer includes GaP, the second material layer includes GaSb, the third material layer includes GaAs, and the fourth material layer includes InP.

[0015] When the group IV semiconductor substrate is a germanium substrate and the second material layer includes GaAs, the first material layer includes MgS, and when the group IV semiconductor substrate is a germanium substrate and the second material layer includes InP, the first material layer includes MgSe, GaAs, or CdS.

[0016] A semiconductor device according to one aspect of the present disclosure includes: a semiconductor substrate including a group IV semiconductor substrate; a first material layer including a group III-V material or a group II-VI material provided on the group IV semiconductor substrate; a first two-dimensional material layer provided on the first material layer; and a second material layer including a group III-V material provided on the first two-dimensional material layer; a first reflecting mirror or a first waveguide provided on the second material layer; a second reflecting mirror or a second waveguide provided above the first reflecting mirror; and an active layer provided between the first reflecting mirror and the second reflecting mirror or between the first waveguide and the second waveguide, which emits light when electric power is applied thereto.

[0017] The semiconductor device further includes a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type that are provided between the first reflecting mirror and the second reflecting mirror and that form a pn junction.

[0018] The active layer includes quantum dots.

[0019] A semiconductor device according to another aspect of the present disclosure includes: a group IV semiconductor substrate; a second material layer including an n-type group III-V material provided on the group IV semiconductor substrate; a fifth material layer including a p-type group III-V material provided above the second material layer; and a light absorption layer provided between the second material layer and the fifth material layer, which generates charges in response to incident light when electric power is applied.

[0020] The second material layer includes n-type InP, the fifth material layer includes n-type InP, and the light absorption layer includes InGaAs.

[0021] The semiconductor device further includes an amplification layer including a III-V material disposed between the second material layer and the light absorbing layer.

[0022] The second material layer includes p+ type InP, the fifth material layer includes n+ type InP, the light absorption layer includes InGaAs, and the amplification layer includes intrinsic InP.

[0023] A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes forming a first material layer including a group III-V material or a group II-VI material on a group IV semiconductor substrate, forming a first two-dimensional material layer above the first material layer, forming a second material layer including a group III-V material on the first two-dimensional material layer, forming a device structure above the second material layer, and peeling the second material layer and the device structure from the group IV semiconductor substrate and the first material layer in the first two-dimensional material layer.

[0024] The method for manufacturing a semiconductor device further comprises, after forming the first material layer and before forming the first two-dimensional material layer, forming a first sacrificial layer on the first material layer, and after peeling the second material layer and device structure from the group IV semiconductor substrate and first material layer in the first two-dimensional material layer, removing the first sacrificial layer and the first two-dimensional material layer from the first material layer and the group IV semiconductor substrate.

[0025] The method for manufacturing a semiconductor device further comprises, after forming the second material layer and before forming the device structure, forming a second sacrificial layer on the second material layer, and after peeling the second material layer and the device structure from the Group IV semiconductor substrate and the first material layer in the first thickness of two-dimensional material, removing the second sacrificial layer and the second material layer from the device structure.

[0026] A method for manufacturing a semiconductor device according to another aspect of the present disclosure includes forming a first material layer including a III-V material or a II-VI material on a group IV semiconductor substrate, forming a first two-dimensional material layer on the first material layer, forming a third material layer including a III-V material on the first two-dimensional material layer, forming a second two-dimensional material layer on the third material layer, forming a second material layer including a III-V material on the second two-dimensional material layer, forming a device structure on the second material layer, and peeling the group IV semiconductor substrate, the first material layer, the first two-dimensional material layer, and the third material layer from the second material layer and the device structure in the second two-dimensional material layer.

[0027] 10A and 10B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the first embodiment. 11A and 11B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the first embodiment. 12A and 12B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the first embodiment. 13A and 13B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the first embodiment. 14A and 14B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the first embodiment. 15A and 15B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the second embodiment. 16A and 16B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the third embodiment. 17A and 17B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the fourth embodiment. 18A and 18B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the fifth embodiment. 19A and 19B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the sixth embodiment. 20A and 20B are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to the seventh embodiment. 21A and 21B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the ninth embodiment. 22A and 22B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the ninth embodiment. 23A and 23B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the ninth embodiment. 24A and 24B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the ninth embodiment. 25A and 25B are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the tenth embodiment. 26A and 10. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a tenth embodiment. A cross-sectional view showing an example of a configuration of a semiconductor device according to the tenth embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an eleven ... configuration of a semiconductor device according to the eleventh embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a twelfth embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the twelfth embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the twelfth embodiment. A cross-sectional view showing an example of a configuration of a semiconductor device according to the twelfth embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a thirteenth embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the thirteenth embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the thirteenth embodiment. A cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the thirteenth embodiment.13. A cross-sectional view showing a configuration example of a semiconductor device according to the 13th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 14th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 14th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 15th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 15th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 15th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 15th embodiment. A cross-sectional view showing an example of a configuration of a semiconductor device according to the 15th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 16th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 16th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 17 ...8th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 18th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 19th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 20th embodiment. A cross-sectional view showing an example of a manufacturing method of a semiconductor device according to the 20th embodiment. A cross-sectional view showing an example of a reclamation process of a semiconductor substrate 1. A cross-sectional view showing an example of a reclamation The present invention relates to a semiconductor substrate, a method for manufacturing a semiconductor substrate, and a method for manufacturing the semiconductor substrate.

[0028] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0029] 1 to 3 are cross-sectional views showing an example of a method for manufacturing a semiconductor substrate according to a first embodiment. Fig. 3 shows an example of the configuration of a semiconductor substrate according to the first embodiment.

[0030] In this embodiment, a group IV semiconductor substrate 10 is used. The group IV semiconductor substrate 10 is, for example, a silicon substrate or a germanium substrate. In this embodiment, the group IV semiconductor substrate 10 is a silicon substrate.

[0031] As shown in FIG. 1, a first material layer 20 is heteroepitaxially grown on a group IV semiconductor substrate 10. The first material layer 20 includes a group III-V material or a group II-VI material. The group III-V material may be, for example, GaP containing arsenic (As) and nitrogen (N). As shown in FIG. 9, the group II-VI material may be, for example, ZnSSe. GaP and ZnSSe have lattice constants close to those of a silicon substrate, allowing them to be heteroepitaxially grown on a silicon substrate in a lattice-matched state. In this way, a group III-V material such as GaP or a group II-VI material such as ZnSSe can be grown on a silicon substrate with low crystal defects. The first material layer 20 may also be GaP, AlGaAs, ZnSSe, MgSSe, or CdSSe.

[0032] When GaAs is directly epitaxially grown on a silicon substrate, the threading dislocation density in GaAs is 10 ７ cm －２ On the other hand, the threading dislocation density in the second material layer 40 formed by the manufacturing method according to this embodiment is 10 ３ cm －２ In other words, the second material layer 40 according to this embodiment is formed above the silicon substrate, but contains only low crystal defects equivalent to a GaAs layer formed on a GaAs substrate. This allows a semiconductor device with excellent characteristics to be formed on the semiconductor substrate 1.

[0033] 4 and 5 are graphs showing the relationship between the band gap and the lattice constant of each material. As shown in FIG. 4, silicon is lattice-matched to GaP and ZnSSe. Therefore, the first material layer 20 made of GaP or ZnSSe can be epitaxially grown with low crystal defects on the group IV semiconductor substrate 10 made of a silicon substrate.

[0034] Next, as shown in FIG. 2 , a two-dimensional material layer 30 is formed on the first material layer 20. The two-dimensional material layer 30 is a single-layer crystal in which atoms (e.g., carbon) are arranged two-dimensionally (planarly). The constituent elements of the two-dimensional material layer 30 are relatively strongly bonded within the layer, but weakly bonded in the direction perpendicular to the layer (plane) of the two-dimensional material layer 30. Therefore, the two-dimensional material layer 30 is strongly bonded within the layer, but the chemical bonds with the first material layer 20 and the second material layer 40 are weak. The two-dimensional material layer 30 is a crystal such as a single layer of graphene or hexagonal boron nitride (h-BN). The two-dimensional material layer 30 may also be an amorphous material such as an amorphous graphene thin film or an amorphous hexagonal boron nitride thin film. The two-dimensional material layer 30 may be attached to the surface of the first material layer 20 from another substrate, or may be formed by a chemical mechanical polishing (CVD) method, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or the like. The two-dimensional material layer 30 does not necessarily have to cover the entire top surface of the first material layer 20, and a portion of the top surface of the first material layer 20 may be exposed. Even in such a case, the second material layer 40 can be grown heteroepitaxially.

[0035] Next, as shown in FIG. 3 , a second material layer 40 including a group III-V material is heteroepitaxially grown on the two-dimensional material layer 30. GaAs, for example, is used as the group III-V material. It is difficult to epitaxially grow the second material layer 40 through the two-dimensional material layer 30 on the surface of a group IV semiconductor substrate 10 such as silicon. On the other hand, it is relatively easy to epitaxially grow the second material layer 40 through the two-dimensional material layer 30 on the surface of a group III-V material such as GaP or a group II-VI material such as ZnSSe. That is, a group III-V material such as GaP or a group II-VI material such as ZnSSe can be remotely epitaxially grown on a group III-V material such as GaAs through the two-dimensional material layer 30. This is because it is difficult for a group IV semiconductor substrate 10 such as silicon to transmit a potential across the two-dimensional material layer 30, whereas it is relatively easy for a group III-V material such as GaP or a group II-VI material such as ZnSSe to transmit a potential across the two-dimensional material layer 30.

[0036] As described above, according to this embodiment, a semiconductor layer made of a group III-V material such as GaAs can be formed above a group IV semiconductor substrate 10 such as silicon. This makes it possible to obtain a group III-V compound semiconductor layer with low crystal defects such as GaAs using a relatively inexpensive group IV semiconductor substrate 10, without using an expensive group III-V compound semiconductor substrate such as a GaAs substrate. The group III-V compound semiconductor layer can be used as a formation layer for light-emitting or light-receiving elements such as VCSELs, semiconductor lasers, image sensors, and SPADs.

[0037] After forming the second material layer 40 on the two-dimensional material layer 30, the two-dimensional material layer 30 may be diffused into the first or second material layer 20, 40 using heat treatment, implant treatment, or the like. This can improve the adhesion between the two-dimensional material layer 30 and the first or second material layer 20, 40. As a result, peeling between the first material layer 20 and the second material layer 40 at the interface of the two-dimensional material layer 30 can be suppressed.

[0038] 3, the semiconductor substrate 1 according to this embodiment includes a group IV semiconductor substrate 10, a first material layer 20 including a group III-V material (e.g., GaP) provided on the group IV semiconductor substrate 10, a two-dimensional material layer 30 provided on the first material layer 20, and a second material layer 40 including a group III-V material (e.g., GaAs) provided on the two-dimensional material layer 30. The semiconductor substrate 1 according to this embodiment is a low-cost semiconductor substrate including a group III-V compound semiconductor layer with low crystal defects. The semiconductor substrate 1 is based on an inexpensive group IV semiconductor substrate 10 such as a silicon substrate, and can provide a GaAs layer suitable for light-emitting or light-receiving elements such as VCSELs, semiconductor lasers, image sensors, and SPADs.

[0039] Furthermore, when the group IV semiconductor substrate 10 includes a readout circuit, the readout circuit and the light emitting element or the light receiving element can be formed on the same substrate. In this case, there is no need to bond the readout circuit chip and the light emitting element chip, and a high-definition image sensor or a multi-emitter can be manufactured.

[0040] 6 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to the second embodiment. In the second embodiment, a third material layer 50 is provided between the two-dimensional material layer 30 and the second material layer 40, and a two-dimensional material layer 31 is provided between the third material layer 50 and the second material layer 40.

[0041] The group IV semiconductor substrate 10, first material layer 20, and two-dimensional material layer 30 have the same configuration as those in the first embodiment. A third material layer 50 is provided on the two-dimensional material layer 30, and a two-dimensional material layer 31 is provided on the third material layer 50. Furthermore, a second material layer 40, in which a semiconductor element will be formed, is provided on the two-dimensional material layer 31.

[0042] The third material layer 50 includes a III-V group material, such as GaAsP.

[0043] The material of the two-dimensional material layer 31 may be the same as that of the two-dimensional material layer 30 .

[0044] In the semiconductor substrate 1 according to the second embodiment, after forming the group IV semiconductor substrate 10, first material layer 20, and two-dimensional material layer 30 shown in FIG. 2, a third material layer 50 is heteroepitaxially grown on the two-dimensional material layer 30. Next, a two-dimensional material layer 31 is formed on the third material layer 50. Next, a second material layer 40 is heteroepitaxially grown on the two-dimensional material layer 31. This completes the semiconductor substrate 1 shown in FIG. 6. The second material layer 40 is used to form a light-emitting element or a light-receiving element.

[0045] According to the second embodiment, a third material layer 50 is interposed between the first material layer 20 and the second material layer 40. If the first material layer 20 is, for example, GaP and the second material layer 40 is, for example, GaAs, the third material layer 50 is, for example, GaAsP having a lattice constant between that of GaP and that of GaAs (see FIG. 4 ). That is, the lattice constant of GaAs > the lattice constant of GaAsP > the lattice constant of GaP. Furthermore, a two-dimensional material layer 30 is provided between the first material layer 20 and the third material layer 50, and a two-dimensional material layer 31 is provided between the third material layer 50 and the second material layer 40. Therefore, when the third material layer 50 is heteroepitaxially grown, the potential of the first material layer 20 is transmitted to the third material layer 50 via the two-dimensional material layer 30. When the second material layer 40 is heteroepitaxially grown, the potential of the third material layer 50 is transmitted to the second material layer 40 via the two-dimensional material layer 31. The third material layer 50 has a lattice constant between the first material layer 20 and the second material layer 40, and therefore can alleviate the lattice mismatch (difference in lattice constant) between the first material layer 20 and the second material layer 40. This can further reduce crystal defects that occur in the second material layer 40. The second material layer 40 may be AlGaInAs, InP, or AlGaInSb.

[0046] Furthermore, the semiconductor substrate 1 according to the second embodiment includes a semiconductor layer made of a group III-V material such as GaAs above a group IV semiconductor substrate 10 such as silicon. Therefore, the second embodiment can achieve the same effects as the first embodiment.

[0047] 7 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to a third embodiment. In the third embodiment, the second material layer 40 is made of a semiconductor layer of a III-V group material such as InP. The third material layer 50 is made of a semiconductor layer of a III-V group material such as GaAs.

[0048] The group IV semiconductor substrate 10, first material layer 20, and two-dimensional material layers 30 and 31 have the same configuration as those in the second embodiment. A third material layer 50 is provided on the two-dimensional material layer 30, and a two-dimensional material layer 31 is provided on the third material layer 50. Furthermore, a second material layer 40, in which a semiconductor element will be formed, is provided on the two-dimensional material layer 31.

[0049] The method for manufacturing the semiconductor substrate 1 of the third embodiment may be similar to that of the second embodiment, although the materials of the second material layer 40 and the third material layer 50 are different.

[0050] According to the third embodiment, a third material layer 50 is interposed between the first material layer 20 and the second material layer 40. If the first material layer 20 is, for example, GaP and the second material layer 40 is, for example, InP, the third material layer 50 is, for example, GaAs having a lattice constant between the lattice constants of GaP and InP. That is, as shown in FIG. 4 , the lattice constant of InP > the lattice constant of GaAs > the lattice constant of GaP. Furthermore, a two-dimensional material layer 30 is provided between the first material layer 20 and the third material layer 50, and a two-dimensional material layer 31 is provided between the third material layer 50 and the second material layer 40. Therefore, when the third material layer 50 is heteroepitaxially grown, the potential of the first material layer 20 is transmitted to the third material layer 50 via the two-dimensional material layer 30. When the second material layer 40 is grown heteroepitaxially, the potential of the third material layer 50 is transmitted to the second material layer 40 via the two-dimensional material layer 31. Since the third material layer 50 has a lattice constant between the first material layer 20 and the second material layer 40, the lattice mismatch (difference in lattice constant) between the first material layer 20 and the second material layer 40 can be alleviated.

[0051] For example, as shown in FIG. 4 , the lattice constant of InP is farther from that of silicon than that of GaAs. Therefore, forming an InP semiconductor layer with low crystal defects above a silicon substrate is more difficult than forming a GaAs semiconductor layer with low crystal defects above a silicon substrate. However, according to the third embodiment, GaAs is provided as a third material layer 50 between a first material layer 20 (e.g., GaP) and a second material layer 40 (e.g., InP). This allows the third material layer 50 to alleviate the lattice mismatch between the first material layer 20 and the second material layer 40. This allows a semiconductor material such as InP, whose lattice constant is farther from that of silicon, to be formed with low crystal defects.

[0052] 8 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to a fourth embodiment. In the fourth embodiment, the second material layer 40 is made of a semiconductor layer of a III-V group material such as GaSb.

[0053] The group IV semiconductor substrate 10, first material layer 20, two-dimensional material layers 30 and 31, and third material layer 50 have the same configurations as those in the third embodiment. A fourth material layer 60 is provided on the two-dimensional material layer 31, and a two-dimensional material layer 32 is provided on the fourth material layer 60. Furthermore, a second material layer 40, in which a semiconductor element will be formed, is provided on the two-dimensional material layer 32.

[0054] The fourth material layer 60 includes, for example, a III-V material such as InP, and the second material layer 40 includes, for example, a III-V material such as GaSb.

[0055] The method for manufacturing a semiconductor substrate 1 of the fourth embodiment involves forming up to the two-dimensional material layer 31 in the same manner as in the third embodiment, and then heteroepitaxially growing a fourth material layer 60 on the two-dimensional material layer 31. Next, a two-dimensional material layer 32 is formed on the fourth material layer 60. Next, a second material layer 40 is heteroepitaxially grown on the two-dimensional material layer 32. This completes the semiconductor substrate 1 shown in FIG. 8. The second material layer 40 is used to form a light-emitting element or a light-receiving element.

[0056] According to the fourth embodiment, a third material layer 50 and a fourth material layer 60 are interposed between the first material layer 20 and the second material layer 40. If the first material layer 20 is, for example, GaP and the second material layer 40 is, for example, GaSb, the third material layer 50 and the fourth material layer 60 are, for example, GaAs and InP, respectively, which have lattice constants between those of GaP and GaSb. Furthermore, of the third material layer 50 and the fourth material layer 60, the third material layer 50 closer to the first material layer 20 (e.g., GaP) is made of GaAs, which has a lattice constant close to GaP. The fourth material layer 60 closer to the second material layer 40 (e.g., GaSb) is made of InP, which has a lattice constant close to GaSb. That is, as shown in FIG. 5, the materials of the third and fourth material layers 50, 60 are selected in accordance with the following order: lattice constant of GaSb>lattice constant of InP>lattice constant of GaAs>lattice constant of GaP.

[0057] Furthermore, a two-dimensional material layer 30 is provided between the first material layer 20 and the third material layer 50, a two-dimensional material layer 31 is provided between the third material layer 50 and the fourth material layer 60, and a two-dimensional material layer 32 is provided between the fourth material layer 60 and the second material layer 40. Therefore, when the third material layer 50 is heteroepitaxially grown, the potential of the first material layer 20 is transmitted to the third material layer 50 via the two-dimensional material layer 30. When the fourth material layer 60 is heteroepitaxially grown, the potential of the third material layer 50 is transmitted to the fourth material layer 60 via the two-dimensional material layer 31. When the second material layer 40 is heteroepitaxially grown, the potential of the fourth material layer 60 is transmitted to the second material layer 40 via the two-dimensional material layer 32. The third material layer 50 and the fourth material layer 60 have lattice constants between those of the first material layer 20 and the second material layer 40, and the lattice constants gradually increase in the order of the first material layer 20, the third material layer 50, the fourth material layer 60, and the second material layer 40. As a result, the third material layer 50 and the fourth material layer 60 alleviate the lattice mismatch (difference in lattice constants) between the first material layer 20 and the second material layer 40.

[0058] For example, as shown in FIG. 5 , the lattice constant of GaSb is further away from that of silicon than the lattice constants of GaAs and InP. Therefore, forming a GaSb semiconductor layer with low crystal defects above a silicon substrate is more difficult than forming a GaAs or InP semiconductor layer with low crystal defects above a silicon substrate. However, according to the fourth embodiment, GaAs is provided as the third material layer 50 and InP is provided as the fourth material layer 60 between the first material layer 20 (e.g., GaP) and the second material layer 40 (e.g., GaSb). This allows the third and fourth material layers 50 and 60 to reduce the lattice mismatch between the first material layer 20 and the second material layer 40. This allows a semiconductor material such as GaSb, whose lattice constant is significantly different from that of silicon, to be formed with low crystal defects.

[0059] Fifth Embodiment FIG. 9 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to a fifth embodiment. In the fifth embodiment, the first material layer 20 is made of a II-VI group material such as ZnSSe. Referring to FIG. 4, it can be seen that the lattice constant of ZnSSe is between the lattice constants of GaP and GaAs. Therefore, even if a II-VI group material such as ZnSSe is used for the first material layer 20, the second material layer 40 made of GaAs can be heteroepitaxially grown via the two-dimensional material layer 30.

[0060] Other configurations of the fifth embodiment may be the same as those of the semiconductor substrate 1 of the first embodiment. Therefore, the fifth embodiment can obtain the same effects as the first embodiment.

[0061] Sixth Embodiment FIG. 10 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to a sixth embodiment. In the sixth embodiment, the group IV semiconductor substrate 10 is, for example, a germanium substrate. The first material layer 20 is made of, for example, a II-VI material such as MgS. The second material layer 40 is made of, for example, a III-V material such as GaAs. Referring to FIGS. 4 and 5, it can be seen that the lattice constants of Ge, MgS, and GaAs are approximately equal. Therefore, the first material layer 20 of MgS can be formed on the germanium substrate, and then the second material layer 40 of GaAs can be heteroepitaxially grown with low crystal defects on the first material layer 20 via the two-dimensional material layer 30.

[0062] In this way, the semiconductor substrate 1 according to the sixth embodiment is based on a group IV semiconductor substrate 10 such as a germanium substrate, and can use GaAs for the second material layer 40, which is suitable for light-emitting or light-receiving elements such as VCSELs, semiconductor lasers, image sensors, and SPADs.

[0063] Seventh Embodiment FIG. 11A is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to a seventh embodiment. In the seventh embodiment, the group IV semiconductor substrate 10 is, for example, a germanium substrate. The first material layer 20 is made of, for example, a II-VI material such as MgSe. The second material layer 40 is made of, for example, a III-V material such as InP. Referring to FIGS. 4 and 5 , the MgSe of the first material layer 20 has a lattice constant between that of Ge and InP. That is, the lattice constant of InP > the lattice constant of MgSe > the lattice constant of Ge. Furthermore, a two-dimensional material layer 30 is provided between the first material layer 20 and the third material layer 50. Therefore, when the second material layer 40 is heteroepitaxially grown, the potential of the first material layer 20 is transmitted to the second material layer 40 via the two-dimensional material layer 30. The first material layer 20 (e.g., MgSe) has a lattice constant between that of the group IV semiconductor substrate 10 (e.g., Ge) and that of the second material layer 40 (e.g., InP), thereby alleviating the lattice mismatch between the group IV semiconductor substrate 10 and the second material layer 40. This reduces crystal defects that occur in the second material layer 40. FIG. 11B is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to a modification of the seventh embodiment. In this modification, the group IV semiconductor substrate 10 is, for example, a germanium substrate. The first material layer 20 is made of, for example, a III-V material such as GaAs. The second material layer 40 is made of, for example, a III-V material such as InP. Referring to FIGS. 4 and 5 , GaAs in the first material layer 20 has a lattice constant equivalent to that of Ge. That is, the lattice constant of InP is greater than the lattice constant of GaAs, and the lattice constant of Ge is equal to the lattice constant of InP. Furthermore, the two-dimensional material layer 30 is provided between the first material layer 20 and the third material layer 50. Therefore, when the second material layer 40 is heteroepitaxially grown, the potential of the first material layer 20 is transmitted to the second material layer 40 via the two-dimensional material layer 30.

[0064] Eighth Embodiment FIG. 12 is a cross-sectional view showing an example of the configuration of a semiconductor substrate according to an eighth embodiment. In the eighth embodiment, the first material layer 20 is made of a II-VI group material such as CdS. The other configurations of the eighth embodiment may be the same as those of the seventh embodiment. Referring to FIG. 4, the CdS of the first material layer 20 has a lattice constant between that of Ge and that of InP. That is, the lattice constant of InP > the lattice constant of CdS > the lattice constant of Ge. Therefore, the first material layer 20 (e.g., CdS) reduces the lattice mismatch between the group IV semiconductor substrate 10 and the second material layer 40, similar to the first material layer 20 (e.g., MgSe) of the seventh embodiment. This reduces crystal defects occurring in the second material layer 40.

[0065] Next, a description will be given of a semiconductor device manufactured using the semiconductor substrate 1 according to the above embodiment. The semiconductor device is, for example, a light emitting element or a light receiving element such as a VCSEL, a semiconductor laser, an image sensor, or a SPAD.

[0066] 13 to 16 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a ninth embodiment. Fig. 16 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the ninth embodiment.

[0067] In the ninth embodiment, a VCSEL, which is a light emitting element, is formed on the semiconductor substrate 1 according to the first embodiment.

[0068] The second material layer 40 of the semiconductor substrate 1 is made of, for example, a III-V group material including n-type GaAs.

[0069] Next, the materials for the first reflector 70 , the active layer 80 , the conductive layer 90 , the second reflector 100 , and the electrode layer 110 are epitaxially grown on the second material layer 40 .

[0070] The first reflecting mirror 70 is a so-called Distributed Bragg Reflector (DBR), and is formed by alternately stacking multiple materials with different refractive indices. For example, the first reflecting mirror 70 is formed by alternately epitaxially growing multiple semiconductor materials (e.g., GaAs and AlGaAs).

[0071] The active layer 80 is made of, for example, AlGaInAs, InGaAs, or InGaAsP, and has a multiple quantum well (MQW) structure.

[0072] The conductive layer 90 is formed of a conductive material such as AlAs, AlInAs, etc. The end of the conductive layer 90 is oxidized in a later process and functions as a current confinement portion that confines and passes a current between the second material layer 40 and the electrode layer 110.

[0073] The second reflecting mirror 100 is a DBR, and is formed by alternately stacking a plurality of materials having different refractive indices. For example, the second reflecting mirror 100 is made of a plurality of dielectric materials (e.g., SiO ２ and TiO ２ ) are alternately grown epitaxially.

[0074] Next, as shown in FIG. 14, the electrode layer 110, the second reflector 100, the conductive layer 90, the active layer 80, and the first reflector 70 are processed using lithography and etching techniques.

[0075] 15, the conductive layer 90 is laterally oxidized to form an oxide film 91 around the current confinement portion. ２ O ３ and is in a non-conducting or high resistance state.

[0076] Next, the second material layer 40, the two-dimensional material layer 30 and the first material layer 20 are processed using lithography and etching techniques.

[0077] Next, a protective film 120 is formed to cover the side surfaces of the active layer 80 , the first and second reflectors 70 and 100 , the electrode layer 110 , the oxide film 91 , the first material layer 20 , the two-dimensional material layer 30 and the second material layer 40 .

[0078] Next, the protective film 120 is processed using lithography and etching techniques to expose parts of the electrode layer 110 and the second material layer 40 from the protective film 120 .

[0079] Next, materials for the lower electrode 130 and the upper electrode 140 are formed on the electrode layer 110 and the second material layer 40 .

[0080] Next, the materials of the lower electrode 130 and the upper electrode 140 are processed using lithography and etching techniques. This results in the structure shown in FIG. 16 . The lower electrode 130 electrically connects the second material layer 40 to any semiconductor element (not shown) formed on the group IV semiconductor substrate 10. The upper electrode 140 electrically connects the electrode layer 110 to any semiconductor element (not shown) formed on the group IV semiconductor substrate 10. The lower electrode 130 and the upper electrode 140 are electrically isolated from each other.

[0081] Thereafter, although not shown, an interlayer insulating film, a multilayer wiring layer, and the like are formed to complete the light emitting element (for example, a VCSEL) according to this embodiment.

[0082] The light-emitting device according to the ninth embodiment is formed on an inexpensive group IV semiconductor substrate 10 such as a silicon substrate, and is formed on a second material layer 40 made of a group III-V material with few crystal defects. Therefore, a high-quality light-emitting device can be formed while suppressing manufacturing costs.

[0083] 16, the light-emitting element according to the ninth embodiment is provided on a second material layer 40 (e.g., n-type GaAs) of the semiconductor substrate 1 of the first embodiment. The light-emitting element includes a first reflecting mirror 70, an active layer 80, a conductive layer 90, an oxide film 91, a second reflecting mirror 100, an electrode layer 110, a protective film 120, a lower electrode 130, and an upper electrode 140.

[0084] The first reflecting mirror 70 is provided on the second material layer 40. As described above, the first reflecting mirror 70 is a DBR configured by alternately laminating a plurality of semiconductor materials having different refractive indices.

[0085] The active layer 80 is provided on the first reflecting mirror 70. When power is applied to the second material layer 40 and the electrode layer 110, electrons from the second material layer 40 and holes from the electrode layer 110 recombine inside the active layer 80, causing the active layer 80 to emit light. The active layer 80 is made of, for example, AlGaInAs, InGaAs, or InGaAsP, and has a multiple quantum well (MQW) structure.

[0086] The conductive layer 90 is provided on the active layer 80. The end of the conductive layer 90 will be oxidized in a later process to function as a current confinement portion that confines and passes a current between the second material layer 40 and the electrode layer 110. The current flowing between the second material layer 40 and the electrode layer 110 is concentrated in the current confinement portion. This can promote light emission in the active layer 80 directly below the current confinement portion.

[0087] The oxide film 91 is provided on the active layer 80 around the conductive layer 90. The conductive layer 90 functions as a current confinement portion.

[0088] The second reflecting mirror 100 is provided on the conductive layer 90 and the oxide film 91. As described above, the second reflecting mirror 100 is a DBR formed by alternately stacking a plurality of dielectric materials having different refractive indices. That is, the first reflecting mirror 70 is a semiconductor DBR formed from a semiconductor material, and the second reflecting mirror 100 is a dielectric DBR formed from a dielectric material. In this embodiment, laser light generated in the resonator between the first reflecting mirror 70 and the second reflecting mirror 100 is emitted from the second reflecting mirror 100.

[0089] The protective film 120 covers the side surfaces of the active layer 80, the first and second reflecting mirrors 70 and 100, the electrode layer 110, the oxide film 91, the first material layer 20, the two-dimensional material layer 30, and the second material layer 40. In this way, the protective film 120 protects and electrically isolates the active layer 80, the first and second reflecting mirrors 70 and 100, the electrode layer 110, the oxide film 91, the first material layer 20, the two-dimensional material layer 30, and the second material layer 40 from the lower electrode 130 and the upper electrode 140.

[0090] The lower electrode 130 is provided on the second material layer 40 and is electrically connected to the second material layer 40. The lower electrode 130 electrically connects the second material layer 40 to any semiconductor element (not shown) formed on the group IV semiconductor substrate 10. The lower electrode 130 is made of a conductive metal material such as tungsten or copper.

[0091] The upper electrode 140 is provided on the electrode layer 110 and electrically connected to the electrode layer 110. The upper electrode 140 electrically connects the electrode layer 110 to any semiconductor element (not shown) formed on the group IV semiconductor substrate 10. The upper electrode 140 is made of a conductive metal material such as tungsten or copper.

[0092] The light-emitting device according to the ninth embodiment is formed on an inexpensive group IV semiconductor substrate 10 such as a silicon substrate, and on a second material layer 40 made of a group III-V material with few crystal defects, thereby resulting in a low-cost, high-quality light-emitting device.

[0093] Furthermore, since the two-dimensional material layer 30 such as graphene has high charge mobility, the presence of the two-dimensional material layer 30 between the first material layer 20 and the second material layer 40 is expected to promote electron diffusion in the in-plane direction of the two-dimensional material layer 30. This makes it possible to reduce the operating voltage of the semiconductor device.

[0094] 17 to 21 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a tenth embodiment. Fig. 21 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a tenth embodiment.

[0095] In the tenth embodiment, a plurality of light-emitting elements are formed on the semiconductor substrate 1 according to the first embodiment. The configuration of each light-emitting element may be the same as that of the light-emitting element according to the ninth embodiment. However, the tenth embodiment differs in its manufacturing method from that of the ninth embodiment and from part of the manufacturing method of the semiconductor substrate 1 according to the first embodiment.

[0096] First, a first material layer (e.g., GaP) 20 and a two-dimensional material layer (e.g., graphene) 30 are formed on a group IV semiconductor substrate (e.g., Si) 10, and then a mask material 150 is formed on the two-dimensional material layer 30. The mask material 150 may be, for example, an insulating film such as a silicon oxide film or a silicon nitride film.

[0097] Next, the mask material 150 is processed using lithography and etching techniques so as to remove the mask material 150 from the region where the second material layer 40 is to be formed.

[0098] Next, the material of the second material layer 40 (for example, n-type GaAs) is heteroepitaxially grown on the first material layer 20 via the two-dimensional material layer 30. This results in the semiconductor substrate structure shown in FIG.

[0099] 18 , the materials for the first reflecting mirror 70, the active layer 80, the conductive layer 90, the second reflecting mirror 100, and the electrode layer 110 are epitaxially grown on the second material layer 40. The materials for the first reflecting mirror 70, the active layer 80, the conductive layer 90, the second reflecting mirror 100, and the electrode layer 110 may be the same as those in the first embodiment.

[0100] 19, the electrode layer 110, the second reflecting mirror 100, the conductive layer 90, the active layer 80, and the first reflecting mirror 70 are processed using lithography and etching techniques, thereby exposing a portion of the upper surface of the second material layer 40.

[0101] Next, as shown in FIG. 20, the mask material 150, the two-dimensional material layer 30 and the first material layer 20 are processed using the second material layer 40 as a mask.

[0102] Next, as shown in FIG. 21 , a protective film 120 is formed to cover the side surfaces of the active layer 80, the first and second reflectors 70 and 100, the electrode layer 110, the oxide film 91, the first material layer 20, the two-dimensional material layer 30, and the second material layer 40.

[0103] Next, using lithography and etching techniques, portions of the electrode layer 110 and the second material layer 40 are exposed from the protective film 120 .

[0104] Next, materials for the lower electrode 130 and the upper electrode 140 are formed on the electrode layer 110 and the second material layer 40 .

[0105] Next, the materials of the lower electrode 130 and the upper electrode 140 are processed using lithography and etching techniques.

[0106] Thereafter, although not shown, an interlayer insulating film, a multilayer wiring layer, and the like are formed to complete the light emitting element (for example, a VCSEL) according to this embodiment.

[0107] In this way, according to the tenth embodiment, it is possible to form a plurality of light emitting elements on the semiconductor substrate 1. Furthermore, it is possible to control the positions of the plurality of light emitting elements and suppress film peeling due to stress.

[0108] 22 to 26 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an eleventh embodiment. Fig. 26 is a cross-sectional view showing an example of the configuration of a semiconductor device according to an eleventh embodiment. The eleventh embodiment is a light-emitting element (VCSEL) using InP as an electrode.

[0109] 22 , the following materials are epitaxially grown in this order on a group IV semiconductor substrate (e.g., Ge): a first material layer (e.g., n-type GaAs) 20, a first reflecting mirror (e.g., a stacked structure of GaAs and AlGaAs) 70, a two-dimensional material layer (e.g., graphene) 30, a second material layer (e.g., n-type InP) 40, an active layer (e.g., AlGaInAs) 80, a conductive layer (p-type InP) 90, a TJ (Tunnel Junction) layer 95, and an electrode layer (e.g., n-type InP) 110. The material of the TJ layer 95 is, for example, p+-type InAlGaAs / n+-type InP or p+-type InAlGaAs / n+-type InAlGaAs. The TJ layer 95 is provided between the first reflecting mirror 70 and the second reflecting mirror 100, and forms a pn junction with an n-type semiconductor layer and a p-type semiconductor layer.

[0110] 23, the electrode layer 110 and the TJ layer 95 are processed using lithography and etching techniques, thereby forming the electrode layer 110 and the TJ layer 95 in the region of the current confinement portion.

[0111] Next, as shown in FIG. 24, the material of the electrode layer 110 is further deposited on the electrode layer 110 and the TJ layer 95 .

[0112] 25 , lithography and etching techniques are used to process the electrode layer 110, the conductive layer 90, the active layer 80, the second material layer 40, the two-dimensional material layer 30, the first reflecting mirror 70, and the first material layer 20. At this time, a portion of the top surface of the second material layer 40 is exposed.

[0113] Next, as shown in FIG. 26, a protective film 120 is formed to cover the side surfaces of the electrode layer 110, the conductive layer 90, the active layer 80, the first reflecting mirror 70, the second material layer 40, the two-dimensional material layer 30 and the first material layer 20.

[0114] Next, using lithography and etching techniques, portions of the electrode layer 110 and the second material layer 40 are exposed from the protective film 120 .

[0115] Next, materials for the lower electrode 130 and the upper electrode 140 are formed on the electrode layer 110 and the second material layer 40 .

[0116] Next, the materials of the lower electrode 130 and the upper electrode 140 are processed using lithography and etching techniques, so that the electrode layer 110 in the region where the second reflecting mirror 100 is to be formed is exposed.

[0117] Next, the second reflecting mirror 100 is epitaxially grown on the electrode layer 110. The material of the second reflecting mirror 100 is the same as that of the first embodiment, that is, a laminated structure of multiple dielectric materials (e.g., SiO ２ and TiO ２ In this way, the light emitting device according to the eleventh embodiment is completed.

[0118] As described above, according to the eleventh embodiment, a light emitting element using InP (for example, an InP-VCSEL) can be formed on the germanium substrate 10 .

[0119] 27 to 30 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a twelfth embodiment. Fig. 30 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a twelfth embodiment. The twelfth embodiment is a light-emitting element (quantum dot laser device) using InAs as an active layer 80.

[0120] First, as shown in FIG. 27 , a first material layer (e.g., GaP) 20, a two-dimensional material layer (e.g., graphene) 30, a second material layer (e.g., n-type GaAs) 40, a first waveguide (e.g., GaAs) 71, an active layer 80, a second waveguide (e.g., GaAs) 101, and an electrode layer (e.g., p-type GaAs) 110 are epitaxially grown on a group IV semiconductor substrate (e.g., a Si substrate) 10. The active layer 80 includes, for example, quantum dots 81 provided on the first waveguide 71 and a burying layer 82 provided on the quantum dots 81. The quantum dots 81 are, for example, InAs epitaxially grown on the first waveguide 71. The burying layer 82 is, for example, AlGaInAs. The active layer 80 can emit light even when configured with the quantum dots 81 in this manner.

[0121] Next, as shown in FIG. 28, the electrode layer 110 and the upper portion of the second waveguide 101 are processed using lithography and etching techniques.

[0122] 29, the lower part of the second waveguide 101, the active layer 80, and the first waveguide 71 are processed using lithography and etching techniques, leaving part of the upper surface of the second material layer 40 exposed.

[0123] Next, as shown in FIG. 30, the second material layer 40, the two-dimensional material layer 30 and the first material layer 20 are processed using lithography and etching techniques.

[0124] Next, a protective film 120 is formed to cover the side surfaces of the electrode layer 110 , the second waveguide 101 , the active layer 80 , the first waveguide 71 , the second material layer 40 , the two-dimensional material layer 30 and the first material layer 20 .

[0125] Next, using lithography and etching techniques, portions of the electrode layer 110 and the second material layer 40 are exposed from the protective film 120 .

[0126] Next, materials for the lower electrode 130 and the upper electrode 140 are formed on the electrode layer 110 and the second material layer 40. As a result, the lower electrode 130 electrically connects between the second material layer 40 and the semiconductor element formed on the group IV semiconductor substrate 10. The upper electrode 140 electrically connects between the electrode layer 110 and the semiconductor element formed on the group IV semiconductor substrate 10.

[0127] Next, the materials of the lower electrode 130 and the upper electrode 140 are processed using lithography and etching techniques, thereby electrically isolating the lower electrode 130 from the upper electrode 140. This completes the light-emitting device according to the twelfth embodiment.

[0128] As described above, according to the twelfth embodiment, a light emitting device having an active layer 80 made up of quantum dots 81 can be formed.

[0129] 31 to 35 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a thirteenth embodiment. Fig. 35 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a thirteenth embodiment. The thirteenth embodiment is a light receiving element (SWIR (Short-Wavelength InfraRed) image sensor) using InGaAs as a light absorption layer 160.

[0130] First, as shown in Fig. 31 , using the semiconductor substrate 1 shown in Fig. 7 , a light absorbing layer 160 and a fifth material layer 170 are epitaxially grown on a second material layer (e.g., n-type GaAs) 40. The second material layer 40 is made of, for example, n-type InP. The light absorbing layer 160 is made of, for example, InGaAs. The fifth material layer 170 is made of, for example, n-type InP.

[0131] 32 , a support substrate 180 is attached onto the fifth material layer 170. The support substrate 180 may be, for example, a silicon substrate or other substrate. Next, the second material layer 40, the light absorbing layer 160, the fifth material layer 170, and the support substrate 180 are peeled off from the third material layer 50, the two-dimensional material layer 30, the first material layer 20, and the group IV semiconductor substrate 10, with the two-dimensional material layer 31 as the boundary. This results in a device structure having the fifth material layer 170, the light absorbing layer 160, and the second material layer 40 on the support substrate 180. Note that the group IV semiconductor substrate 10, the first material layer 20, the two-dimensional material layer 30, and the third material layer 50 may be discarded or reused.

[0132] 33, p-type impurities are introduced into a portion of the second material layer 40 using lithography and implantation techniques to form a contact region 41 in the second material layer 40. The contact region 41 is, for example, high-concentration p+-type InP.

[0133] Next, a material for the contact electrode 190 is deposited on the contact region 41, and the material for the contact electrode 190 is processed using lithography and etching techniques. As a result, the contact electrode 190 is formed on the contact region 41. The contact electrode 190 is made of a conductive metal material such as copper or tungsten.

[0134] Next, as shown in Fig. 34, another substrate 500 is prepared that includes a logic circuit (not shown) such as a signal processing circuit. The substrate 500 is provided with a contact electrode 510 that is electrically connected to the logic circuit. The contact electrode 190 is connected to the contact electrode 510 with the contact region 41 facing the substrate 500 (Cu-Cu bonding). As a result, the light receiving element is electrically connected to the logic circuit such as the signal processing circuit, as shown in Fig. 35.

[0135] Next, the transparent electrode film 200 is formed on the fifth material layer 170. For example, indium tin oxide (ITO) is used for the transparent electrode film 200. In this way, the light-receiving element according to the thirteenth embodiment is completed.

[0136] The semiconductor device according to the thirteenth embodiment shown in FIG. 35 includes a group IV semiconductor substrate (e.g., a silicon substrate) 500, a second material layer 40, a contact region 41, a light absorption layer 160, a fifth material layer (e.g., n-type InP) 170, and a transparent electrode film (e.g., ITO) 200.

[0137] The group IV semiconductor substrate 500 is, for example, a silicon substrate, and has a logic circuit such as a signal processing circuit formed thereon. The second material layer 40 is provided on the group IV semiconductor substrate 500 and contains an n-type III-V material (n-type InP). The contact region 41 is a high-concentration p+ type III-V material (p+ type InP) formed in the second material layer 40, and electrically connects the light absorption layer 160 and the logic circuit.

[0138] The light absorbing layer 160 is provided between the second material layer 40 and the fifth material layer 170, and generates charges in response to incident light when power is applied. That is, the light absorbing layer 160 converts incident light into electricity. The light absorbing layer 160 may be made of, for example, intrinsic InGaAs. The fifth material layer 170 is provided on the light absorbing layer 160 and includes, for example, n-type InP. The transparent electrode film 200 is provided on the fifth material layer 170 and includes, for example, ITO.

[0139] This allows the semiconductor device according to the thirteenth embodiment to function as a light receiving element (for example, a SWIR image sensor).

[0140] 36 and 37 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a fourteenth embodiment. The configuration of the semiconductor device according to the fourteenth embodiment may be the same as that of the thirteenth embodiment. That is, the semiconductor device according to the fourteenth embodiment is a light receiving element (SWIR image sensor) using InGaAs as the light absorption layer 160. The fourteenth embodiment differs from the thirteenth embodiment in the manufacturing method.

[0141] 36, a first material layer (e.g., GaAs) 20 is epitaxially grown on a germanium substrate 10, and a two-dimensional material layer 30 is formed on the first material layer 20. Furthermore, a second material layer (e.g., n-type InP) 40 is heteroepitaxially grown on the two-dimensional material layer 30. A semiconductor substrate 1 including such a second material layer (e.g., n-type InP) 40 is formed.

[0142] Next, similarly to the thirteenth embodiment, a light absorbing layer 160 and a fifth material layer 170 are epitaxially grown on the second material layer 40. Next, a support substrate 180 is attached onto the fifth material layer 170.

[0143] Next, the second material layer 40, the light absorbing layer 160, the fifth material layer 170, and the support substrate 180 are peeled off from the first material layer 20, with the two-dimensional material layer 30 as the boundary. This results in a structure having the fifth material layer 170, the light absorbing layer 160, and the second material layer 40 on the support substrate 180. The group IV semiconductor substrate 10 and the first material layer 20 may be discarded or reused.

[0144] Thereafter, the steps described with reference to FIGS. 33 to 35 are carried out to complete the light-receiving element according to the fourteenth embodiment.

[0145] 38 to 41 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a fifteenth embodiment. Fig. 41 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a fifteenth embodiment. The fifteenth embodiment is a light-receiving element (SPAD (Single Photon Avalanche Diode)) using InGaAs as a light absorption layer 160.

[0146] First, as shown in FIG. 38, using the semiconductor substrate 1 shown in FIG. 7, an amplification layer 42, material layers 43 and 44, a light absorption layer 160, and a fifth material layer 170 are epitaxially grown on a second material layer (e.g., n-type GaAs) 40.

[0147] The second material layer 40 is made of, for example, high-concentration p+ type InP. The amplification layer 42 is made of, for example, a III-V group material such as intrinsic InP. The material layer 43 is made of, for example, a III-V group material such as n-type InP. The material layer 44 is made of, for example, n-type InGaAsP. The light absorption layers 160 may be the same as those in the thirteenth embodiment. The fifth material layer 170 is made of, for example, high-concentration n+ type InP.

[0148] 39 , a support substrate 180 is attached onto the fifth material layer 170. Next, the second material layer 40, the amplification layer 42, the material layers 43 and 44, the light absorption layer 160, the fifth material layer 170, and the support substrate 180 are peeled off from the third material layer 50, the two-dimensional material layer 30, the first material layer 20, and the group IV semiconductor substrate 10, with the two-dimensional material layer 31 as the boundary. This results in a device structure having the second material layer 40 to the fifth material layer 170 on the support substrate 180. Note that the group IV semiconductor substrate 10, the first material layer 20, the two-dimensional material layer 30, and the third material layer 50 may be discarded or reused.

[0149] Next, similarly to the thirteenth embodiment, the material of the contact electrode 190 is deposited on the second material layer 40, and the material of the contact electrode 190 is processed using lithography and etching techniques. As a result, the contact electrode 190 is formed on the second material layer 40.

[0150] Next, as shown in Fig. 40, another substrate 500 equipped with a logic circuit (not shown) such as a signal processing circuit is prepared. The second material layer 40 is oriented toward the substrate 500, and the contact electrode 190 is connected to the contact electrode 510 (Cu-Cu bonding). As a result, the light receiving element is electrically connected to the logic circuit such as the signal processing circuit, as shown in Fig. 41.

[0151] Next, the transparent electrode film 200 is formed on the fifth material layer 170. For example, indium tin oxide (ITO) is used for the transparent electrode film 200. In this way, the light-receiving element according to the fifteenth embodiment is completed.

[0152] The semiconductor device according to the fifteenth embodiment shown in FIG. 41 includes a group IV semiconductor substrate (e.g., a silicon substrate) 500, a second material layer (e.g., p+ type InP) 40, an amplification layer (e.g., intrinsic InP) 42, a material layer (e.g., n type InP) 43, a material layer (e.g., n type InGaAsP) 44, a light absorption layer (intrinsic InGaAs) 160, a fifth material layer (e.g., n+ type InP) 170, and a transparent electrode layer (e.g., ITO) 200.

[0153] The group IV semiconductor substrate 500 is, for example, a silicon substrate, and has a logic circuit such as a signal processing circuit formed thereon. The second material layer 40 is provided on the group IV semiconductor substrate 500, contains an n-type III-V material (n+-type InP), and electrically connects the light absorption layer 160 and the logic circuit.

[0154] The light absorbing layer 160 is provided between the second material layer 40 and the fifth material layer 170, and generates charges when one photon is incident thereon. The amplification layer 42 avalanche amplifies the charges generated in the light absorbing layer 160. This allows the semiconductor device according to the fifteenth embodiment to function as a light receiving element (for example, a SPAD).

[0155] 42 and 43 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a sixteenth embodiment. The configuration of the semiconductor device according to the sixteenth embodiment may be the same as that of the fifteenth embodiment. The sixteenth embodiment differs from the fifteenth embodiment in the manufacturing method.

[0156] 42, a first material layer (e.g., GaAs) 20 is epitaxially grown on a germanium substrate 10, and a two-dimensional material layer 30 is formed on the first material layer 20. Furthermore, a second material layer (e.g., p+ type InP) 40 is heteroepitaxially grown on the two-dimensional material layer 30. A semiconductor substrate 1 including such a second material layer (e.g., p+ type InP) 40 is formed.

[0157] Next, similarly to the fifteenth embodiment, the amplification layer 42, the material layers 43 and 44, the light absorption layer 160, and the fifth material layer 170 are epitaxially grown on the second material layer 40. Next, a support substrate 180 is attached onto the fifth material layer 170.

[0158] Next, the second material layer 40 to the fifth material layer 170 and the support substrate 180 are peeled off from the first material layer 20, with the two-dimensional material layer 30 as the boundary. This results in a structure having the second material layer 40 to the fifth material layer 170 on the support substrate 180. The group IV semiconductor substrate 10 and the first material layer 20 may be discarded or reused.

[0159] Thereafter, the steps described with reference to FIGS. 40 and 41 are carried out to complete the light-receiving element (SPAD) according to the sixteenth embodiment.

[0160] 44 to 47 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a seventeenth embodiment. Fig. 47 is a cross-sectional view showing an example of the configuration of a semiconductor device according to the seventeenth embodiment. The configuration of the semiconductor device according to the seventeenth embodiment is almost the same as the structure shown in Fig. 26.

[0161] First, as shown in FIG. 44 , using the semiconductor substrate 1 shown in FIG. 7 , the following materials are epitaxially grown in this order on the second material layer (e.g., n-type GaAs) 40: an active layer (e.g., AlGaInAs) 80, a conductive layer (p-type InP) 90, a TJ layer (e.g., p+-type InAlGaAs / n+-type InP or p+-type InAlGaAs / n+-type InAlGaAs) 95, and an electrode layer (e.g., n-type InP) 110.

[0162] 45 , a support substrate 180 is attached onto the electrode layer 110. Next, the second material layer 40, the active layer 80, the conductive layer 90, the TJ layer 95, and the electrode layer 110 are peeled off from the third material layer 50, with the two-dimensional material layer 31 as the boundary. This results in a structure having the second material layer 40, the active layer 80, the conductive layer 90, the TJ layer 95, and the electrode layer 110 on the support substrate 180. Note that the group IV semiconductor substrate 10, the first material layer 20, the two-dimensional material layer 30, and the third material layer 50 may be discarded or reused.

[0163] Next, as shown in FIG. 46 , a GaAs substrate 500 is prepared on which a first material layer (e.g., n-type GaAs) and a first reflecting mirror (e.g., a stack of GaAs and AlGaAs or AlAs) 70 are formed. Next, a structure including a second material layer 40, an active layer 80, a conductive layer 90, a TJ layer 95, and an electrode layer 110 is bonded to the first reflecting mirror 70 by heterogeneous junction. This results in a structure substantially identical to that shown in FIG. 22 . The seventeenth embodiment differs from the eleventh embodiment in that a GaAs substrate 500 is used and that a two-dimensional material layer 30 is not provided between the first reflecting mirror 70 and the second material layer 40.

[0164] 22 to 26, the light emitting device shown in Fig. 47 is obtained. The light emitting device shown in Fig. 47 differs from the configuration of the 11th embodiment shown in Fig. 26 in that the material of the substrate 500 is different and the two-dimensional material layer 30 is omitted. The other configurations of the 17th embodiment may be the same as those of the 11th embodiment.

[0165] 48 and 49 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an eighteenth embodiment. The configuration of the semiconductor device according to the eighteenth embodiment may be the same as that of the seventeenth embodiment. The eighteenth embodiment differs from the seventeenth embodiment in the manufacturing method.

[0166] 48, a first material layer (e.g., GaAs) 20 is epitaxially grown on a germanium substrate 10, and a two-dimensional material layer 30 is formed on the first material layer 20. Furthermore, a second material layer (e.g., n-type InP) 40 is heteroepitaxially grown on the two-dimensional material layer 30. A semiconductor substrate 1 including such a second material layer (e.g., n-type InP) 40 is formed.

[0167] Next, similarly to the seventeenth embodiment, the active layer 80 , the conductive layer 90 , the TJ layer 95 , and the electrode layer 110 are epitaxially grown on the second material layer 40 .

[0168] 49, a support substrate 180 is attached onto the electrode layer 110. Next, the second material layer 40 to the electrode layer 110 and the support substrate 180 are peeled off from the first material layer 20, with the two-dimensional material layer 30 as the boundary. This results in a structure having the second material layer 40 to the electrode layer 110 on the support substrate 180. The group IV semiconductor substrate 10 and the first material layer 20 may be discarded or reused.

[0169] Thereafter, the light emitting device according to the eighteenth embodiment is completed through the steps described with reference to FIGS.

[0170] 50 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to a 19th embodiment. In the 19th embodiment, a device structure D is formed on the semiconductor substrate 1 shown in FIG. 3. In the two-dimensional material layer 30, the group IV semiconductor substrate (e.g., a silicon substrate) 10 and the first material layer 20 are peeled off from the second material layer 40 and the device structure D. The two-dimensional material layer 30 is made of a material that has weak chemical bonds with the first material layer 20 and the second material layer 40. Therefore, the second material layer 40 is easily peeled off from the first material layer 20 in the two-dimensional material layer 30.

[0171] Therefore, after forming the device structure D, as shown in Fig. 50, a support substrate 180 can be attached to the device structure D, and the second material layer 40 can be easily peeled off from the first material layer 20. The device structure D may have the structure of any semiconductor device (e.g., a light-emitting element or a light-receiving element such as a VCSEL, a semiconductor laser, an image sensor, or a SPAD). For example, the device structure D may have the structure from the first reflecting mirror 70 to the electrode layer 110 shown in Fig. 13.

[0172] The first material layer 20 and / or the two-dimensional material layer 30 are removed from the group IV semiconductor substrate 10 by an ashing process or the like. Thereafter, the group IV semiconductor substrate 10 and the first material layer 20 can be reused. Alternatively, the group IV semiconductor substrate 10 can be reused. This reduces the manufacturing cost of the semiconductor device.

[0173] 51 and 52 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to a twentieth embodiment. In the twentieth embodiment, in the two-dimensional material layer 30, the device structure D, the second sacrificial layer 220, and the second material layer 40 are peeled off from a group IV semiconductor substrate (e.g., a germanium substrate) 10. The device structure D is a part of a light-receiving element including a light absorption layer 160, a material layer 43, and a fifth material layer 170. The device structure D may be the structure of any semiconductor device (e.g., a light-emitting element or a light-receiving element such as a VCSEL, a semiconductor laser, an image sensor, or a SPAD).

[0174] The semiconductor substrate 1 includes a group IV semiconductor substrate (e.g., germanium substrate) 10, a first material layer (e.g., GaAs) 20, a first sacrificial layer (e.g., InGaP) 210, a two-dimensional material layer 30, and a second material layer (e.g., n-type InP) 40.

[0175] The first material layer 20 includes, for example, GaAs epitaxially grown on the group IV semiconductor substrate 10. The first sacrificial layer 210 includes, for example, InGaP epitaxially grown on the first material layer 20. The two-dimensional material layer 30 is, for example, graphene formed on the first sacrificial layer 210. The second material layer 40 includes n-type InP heteroepitaxially grown on the first sacrificial layer 210 via the two-dimensional material layer 30. The second sacrificial layer 220 includes, for example, InGaAs epitaxially grown on the second material layer 40. The material layer 43 includes n-type InP epitaxially grown on the second sacrificial layer 220. The light absorption layer 160 includes intrinsic InGaAs epitaxially grown on the material layer 43. The fifth material layer 170 includes n-type InP epitaxially grown on the light absorption layer 160.

[0176] After forming the device structure D, a support substrate 180 is attached to the device structure D, and the second material layer 40 is peeled off from the first material layer 20 at the boundary of the two-dimensional material layer 30. In the twentieth embodiment, the device structure D is a part of a light-receiving element including the light absorption layer 160, the material layer 43, and the fifth material layer 170 of the light-receiving element.

[0177] Next, on the device structure D side, the second material layer 40 is removed by removing the second sacrificial layer 220. On the group IV semiconductor substrate 10 side, the two-dimensional material layer 30 is removed by removing the first sacrificial layer 210.

[0178] Next, the device structure D is used to form a light-receiving element according to the twentieth embodiment through the steps described with reference to Figures 33 to 35. The light-receiving element according to the twentieth embodiment may have the same configuration as that of the thirteenth embodiment.

[0179] 53 to 55 are cross-sectional views showing an example of a reclaiming process for the semiconductor substrate 1. FIG.

[0180] The group IV semiconductor substrate 10, the first material layer 20, the first sacrificial layer 210 and the two-dimensional material layer 30 are peeled off and then recycled.

[0181] First, as shown in FIG. 53, the two-dimensional material layer 30 is removed by ashing or the like.

[0182] 54, the first sacrificial layer 210 is removed by wet etching or the like. At this time, the two-dimensional material layer 30 remaining on the first sacrificial layer 210 is also removed.

[0183] 55, a first sacrificial layer 210 is epitaxially grown again on the first material layer 20, and a two-dimensional material layer 30 is formed on the first sacrificial layer 210. Furthermore, a second material layer 40 is heteroepitaxially grown on the first sacrificial layer 210 via the two-dimensional material layer 30. In this way, the semiconductor substrate 1 is reproduced.

[0184] The semiconductor substrate 1 is then reused to form semiconductor devices, thereby reducing the manufacturing costs of the semiconductor devices.

[0185] (Application Example to a Mobile Body) The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0186] FIG. 56 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0187] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 56, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0188] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0189] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0190] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0191] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0192] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0193] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0194] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0195] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0196] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 56, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0197] FIG. 57 is a diagram showing an example of the installation position of the imaging unit 12031.

[0198] In FIG. 57, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0199] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0200] 57 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0201] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0202] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0203] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0204] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0205] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration.

[0206] The present technology can be configured as follows.

[0207] (1) A semiconductor substrate comprising: a group IV semiconductor substrate; a first material layer including a group III-V material or a group II-VI material provided on the group IV semiconductor substrate; a first two-dimensional material layer provided on the first material layer; and a second material layer including a group III-V material provided above the first two-dimensional material layer.

[0208] (2) The semiconductor substrate according to (1), wherein the group IV semiconductor substrate is a silicon substrate or a germanium substrate, and the first material layer includes any one of GaP, AlGaAs, ZnSSe, MgSSe, and CdSSe.

[0209] (3) The semiconductor substrate according to (1), wherein the first two-dimensional material layer is any one of graphene, a single layer of hexagonal boron nitride (h-BN), amorphous graphene, and amorphous hexagonal boron nitride.

[0210] (4) The semiconductor substrate according to (1) or (2), wherein the second material layer is any one of AlGaInAs, InP, AlGaInSb, and GaAs.

[0211] (5) The semiconductor substrate according to (1) or (2), further comprising: a third material layer including a III-V material provided between the first two-dimensional material layer and the second material layer; and a second two-dimensional material layer provided between the third material layer and the second material layer.

[0212] (6) The semiconductor substrate according to (5), wherein, when the group IV semiconductor substrate is a silicon substrate, the first material layer includes GaP, the second material layer includes GaAs, InP or GaSb, and the third material layer includes GaAs or GaAsP.

[0213] (7) The semiconductor substrate according to (5), further comprising: a fourth material layer including a III-V material provided between the second two-dimensional material layer and the second material layer; and a third two-dimensional material layer provided between the fourth material layer and the second material layer.

[0214] (8) The semiconductor substrate according to (7), wherein, when the group IV semiconductor substrate is a silicon substrate, the first material layer includes GaP, the second material layer includes GaSb, the third material layer includes GaAs, and the fourth material layer includes InP.

[0215] (9) The semiconductor substrate according to (1), wherein, when the group IV semiconductor substrate is a germanium substrate and the second material layer includes GaAs, the first material layer includes MgS; and when the group IV semiconductor substrate is a germanium substrate and the second material layer includes InP, the first material layer includes MgSe or CdS.

[0216] (10) A semiconductor device comprising: a semiconductor substrate including: a group IV semiconductor substrate; a first material layer including a group III-V material or a group II-VI material provided on the group IV semiconductor substrate; a first two-dimensional material layer provided on the first material layer; and a second material layer including a group III-V material provided on the first two-dimensional material layer; a first reflecting mirror or a first waveguide provided on the second material layer; a second reflecting mirror or a second waveguide provided above the first reflecting mirror; and an active layer provided between the first reflecting mirror and the second reflecting mirror or between the first waveguide and the second waveguide, which emits light when electric power is applied.

[0217] (11) The semiconductor device according to (10), further comprising a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type that are provided between the first reflecting mirror and the second reflecting mirror and that form a pn junction.

[0218] (12) The semiconductor device according to (10), wherein the active layer includes quantum dots.

[0219] (13) A semiconductor device comprising: a group IV semiconductor substrate; a second material layer including an n-type group III-V material provided on the group IV semiconductor substrate; a fifth material layer including a p-type group III-V material provided above the second material layer; and a light absorption layer provided between the second material layer and the fifth material layer, which generates charges in response to incident light when electric power is applied.

[0220] (14) The semiconductor device according to (13), wherein the second material layer includes n-type InP, the fifth material layer includes n-type InP, and the light absorption layer includes InGaAs.

[0221] (15) The semiconductor device according to (13), further comprising an amplification layer containing a III-V group material provided between the second material layer and the light absorption layer.

[0222] (16) The semiconductor device according to (15), wherein the second material layer includes p+ type InP, the fifth material layer includes n+ type InP, the light absorption layer includes InGaAs, and the amplification layer includes intrinsic InP.

[0223] (17) A method for manufacturing a semiconductor device, comprising: forming a first material layer including a III-V material or a II-VI material on a group IV semiconductor substrate; forming a first two-dimensional material layer above the first material layer; forming a second material layer including a III-V material on the first two-dimensional material layer; forming a device structure above the second material layer; and peeling the second material layer and the device structure from the group IV semiconductor substrate and the first material layer in the first two-dimensional material layer.

[0224] (18) The manufacturing method according to (17), further comprising forming a first sacrificial layer on the first material layer after forming the first material layer and before forming the first two-dimensional material layer; and removing the first sacrificial layer and the first two-dimensional material layer from the first material layer and the Group IV semiconductor substrate after peeling the second material layer and the device structure from the Group IV semiconductor substrate and the first material layer in the first two-dimensional material layer.

[0225] (19) The manufacturing method according to (17) or (18), further comprising forming a second sacrificial layer on the second material layer after forming the second material layer and before forming the device structure; and removing the second sacrificial layer and the second material layer from the device structure after peeling the second material layer and the device structure from the Group IV semiconductor substrate and the first material layer in the first two-dimensional material layer.

[0226] (20) A method for manufacturing a semiconductor device, comprising: forming a first material layer including a III-V material or a II-VI material on a group IV semiconductor substrate; forming a first two-dimensional material layer on the first material layer; forming a third material layer including a III-V material on the first two-dimensional material layer; forming a second two-dimensional material layer on the third material layer; forming a second material layer including a III-V material on the second two-dimensional material layer; forming a device structure on the second material layer; and peeling the group IV semiconductor substrate, the first material layer, the first two-dimensional material layer, and the third material layer from the second material layer and the device structure in the second two-dimensional material layer.

[0227] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0228] REFERENCE SIGNS LIST 10 Group IV semiconductor substrate 20 First material layer 30, 31, 32 Two-dimensional material layer 40 Second material layer 50 Third material layer 60 Fourth material layer 70 First reflector 80 Active layer 90 Conductive layer 91 Oxide film 95 TJ layer 100 Second reflector 110 Electrode layer 120 Protective film 130 Lower electrode 140 Upper electrode

Claims

1. A semiconductor substrate comprising: a group IV semiconductor substrate; a first material layer comprising a group III-V material or a group II-VI material disposed on the group IV semiconductor substrate; a first two-dimensional material layer disposed on the first material layer; and a second material layer comprising a group III-V material disposed above the first two-dimensional material layer.

2. The semiconductor substrate according to claim 1, wherein the group IV semiconductor substrate is a silicon substrate or a germanium substrate, and the first material layer includes any one of GaP, AlGaAs, ZnSSe, MgSSe, and CdSSe.

3. The semiconductor substrate of claim 1, wherein the first two-dimensional material layer is one of graphene, a single layer of hexagonal boron nitride (h-BN), amorphous graphene, and amorphous hexagonal boron nitride.

4. The semiconductor substrate of claim 1, wherein the second material layer is one of AlGaInAs, InP, AlGaInSb, and GaAs.

5. The semiconductor substrate of claim 1, further comprising: a third material layer including a III-V material disposed between the first two-dimensional material layer and the second material layer; and a second two-dimensional material layer disposed between the third material layer and the second material layer.

6. The semiconductor substrate according to claim 5, wherein when the group IV semiconductor substrate is a silicon substrate, the first material layer includes GaP, the second material layer includes GaAs, InP or GaSb, and the third material layer includes GaAs or GaAsP.

7. The semiconductor substrate of claim 5, further comprising: a fourth material layer including a III-V material disposed between the second two-dimensional material layer and the second material layer; and a third two-dimensional material layer disposed between the fourth material layer and the second material layer.

8. The semiconductor substrate according to claim 7, wherein when the group IV semiconductor substrate is a silicon substrate, the first material layer comprises GaP, the second material layer comprises GaSb, the third material layer comprises GaAs, and the fourth material layer comprises InP.

9. The semiconductor substrate of claim 1, wherein when the group IV semiconductor substrate is a germanium substrate and the second material layer includes GaAs, the first material layer includes MgS; and when the group IV semiconductor substrate is a germanium substrate and the second material layer includes InP, the first material layer includes MgSe, GaAs, or CdS.

10. A semiconductor device comprising: a semiconductor substrate including a group IV semiconductor substrate; a first material layer including a group III-V material or a group II-VI material provided on the group IV semiconductor substrate; a first two-dimensional material layer provided on the first material layer; and a second material layer including a group III-V material provided on the first two-dimensional material layer; a first reflecting mirror or a first waveguide provided on the second material layer; a second reflecting mirror or a second waveguide provided above the first reflecting mirror; and an active layer provided between the first reflecting mirror and the second reflecting mirror or between the first waveguide and the second waveguide, which emits light when electric power is applied.

11. The semiconductor device according to claim 10, further comprising a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, which are provided between the first reflector and the second reflector and form a pn junction.

12. The semiconductor device according to claim 10, wherein the active layer includes quantum dots.

13. A semiconductor device comprising: a group IV semiconductor substrate; a second material layer including an n-type group III-V material provided on the group IV semiconductor substrate; a fifth material layer including a p-type group III-V material provided above the second material layer; and a light absorption layer provided between the second material layer and the fifth material layer, which generates charges in response to incident light when electric power is applied.

14. The semiconductor device according to claim 13, wherein the second material layer includes n-type InP, the fifth material layer includes n-type InP, and the light absorption layer includes InGaAs.

15. The semiconductor device according to claim 13, further comprising an amplification layer including a III-V material provided between said second material layer and said light absorption layer.

16. The semiconductor device according to claim 15, wherein the second material layer includes p+ type InP, the fifth material layer includes n+ type InP, the light absorption layer includes InGaAs, and the amplification layer includes intrinsic InP.

17. A method for manufacturing a semiconductor device, comprising: forming a first material layer on a group IV semiconductor substrate, the first material layer comprising a group III-V material or a group II-VI material; forming a first two-dimensional material layer above the first material layer; forming a second material layer on the first two-dimensional material layer, the second material layer comprising a group III-V material; forming a device structure above the second material layer; and peeling the second material layer and the device structure from the group IV semiconductor substrate and the first material layer in the first two-dimensional material layer.

18. The method of claim 17, further comprising, after forming the first material layer and before forming the first two-dimensional material layer, forming a first sacrificial layer on the first material layer; and, after peeling the second material layer and the device structure from the group IV semiconductor substrate and the first material layer in the first two-dimensional material layer, removing the first sacrificial layer and the first two-dimensional material layer from the first material layer and the group IV semiconductor substrate.

19. The method of claim 17, further comprising, after forming the second material layer and before forming the device structure, forming a second sacrificial layer on the second material layer, and after peeling the second material layer and the device structure from the Group IV semiconductor substrate and the first material layer in the first layer of two-dimensional material, removing the second sacrificial layer and the second material layer from the device structure.

20. A method for manufacturing a semiconductor device, comprising: forming a first material layer comprising a III-V material or a II-VI material on a group IV semiconductor substrate; forming a first two-dimensional material layer on the first material layer; forming a third material layer comprising a III-V material on the first two-dimensional material layer; forming a second two-dimensional material layer on the third material layer; forming a second material layer comprising a III-V material on the second two-dimensional material layer; forming a device structure on the second material layer; and peeling the group IV semiconductor substrate, the first material layer, the first two-dimensional material layer, and the third material layer from the second material layer and the device structure in the second two-dimensional material layer.

Images