Capacitor

Abstract

A capacitor, according to one embodiment of the present invention, comprises: a base; a first electrode layer disposed on the base; a first dielectric layer disposed on the first electrode layer; and a second electrode layer disposed on the first dielectric layer, wherein the first electrode layer includes a ruthenium (Ru) layer and a ruthenium oxide layer disposed on the ruthenium layer, the first dielectric layer includes aluminum (Al)-doped titanium oxide, and the thickness of the first dielectric layer is 18 nm to 22 nm.

Description

capacitor

[0001] An embodiment of the present invention relates to a capacitor.

[0002] Semiconductor packages are used in a variety of fields, including automobiles, communications, and computers. They typically include printed circuit boards (PCBs), semiconductor chips positioned on the PCBs, and passive components positioned on the PCBs. Passive components may include, for example, resistors, inductors, and capacitors.

[0003] As semiconductor packaging becomes more sophisticated, demand for high-performance, highly reliable, and ultra-small capacitors is increasing. To improve capacitor performance, increasing their capacitance is crucial. Methods for increasing capacitance include maximizing the electrode area and reducing the thickness of the dielectric layer. However, active research is being conducted on dielectrics with high permittivity to ensure stable capacitance in confined spaces.

[0004] Ternary dielectrics such as BaTiO3, SrTiO3, and (Ba, Sr)TiO3 have higher permittivity than binary dielectrics, but their deposition conditions are complex, it is difficult to match the stoichiometry, and they require high post-treatment temperatures of over 600°C, which causes deformation of the electrode material.

[0005] The technical problem to be achieved by the present invention is to provide an ultra-small and high-capacity capacitor.

[0006] A capacitor according to one embodiment of the present invention includes a base, a first electrode layer disposed on the base, a first dielectric layer disposed on the first electrode layer, and a second electrode layer disposed on the first dielectric layer, wherein the first electrode layer includes a ruthenium (Ru) layer and a ruthenium oxide layer disposed on the ruthenium layer, the first dielectric layer includes titanium oxide doped with aluminum (Al), and the thickness of the first dielectric layer is 18 nm to 22 nm.

[0007] The thickness of the first electrode layer may be 5 nm to 50 nm.

[0008] The first dielectric layer includes a plurality of sublayers sequentially stacked in a direction from the first electrode layer toward the second electrode layer, and there may be a section in each sublayer in which the aluminum doping concentration changes in a direction from the first electrode layer toward the second electrode layer.

[0009] There may be a section in which the aluminum doping concentration decreases and then increases in the direction from the first electrode layer to the second electrode layer within each sublayer.

[0010] The aluminum doping concentration in the first dielectric layer may be 0.1 at% to 2 at%.

[0011] The base includes a first surface and a second surface opposite the first surface, and includes a plurality of structures protruding from the first surface in a direction toward the second surface, and the first electrode layer, the first dielectric layer, and the second electrode layer can be sequentially laminated between the plurality of structures and the plurality of structures.

[0012] The base includes a first surface and a second surface opposite the first surface, and includes a plurality of through holes formed along a direction from the first surface toward the second surface, and the first electrode layer, the first dielectric layer, and the second electrode layer can be sequentially laminated on the first surface, the second surface, and the inner wall surfaces of the plurality of through holes.

[0013] A second dielectric layer disposed on the second electrode layer, and a third electrode layer disposed on the second dielectric layer, wherein the second electrode layer includes a ruthenium (Ru) layer and a ruthenium oxide layer, and the second dielectric layer includes titanium oxide doped with aluminum (Al), and the thickness of the second dielectric layer may be 18 nm to 22 nm.

[0014] It further includes a passivation layer disposed on the second electrode layer, a first electrode pad connected to the first electrode layer through a first opening extending from the upper surface of the passivation layer to the first electrode layer, and a second electrode pad connected to the second electrode layer through a second opening extending from the upper surface of the passivation layer to the upper surface of the second electrode layer, wherein the passivation layer may be further disposed along the side surfaces of the first dielectric layer and the second electrode layer in the first opening.

[0015] The first opening extends to the upper surface of the ruthenium layer of the first electrode layer, and the first electrode pad can be connected to the ruthenium layer.

[0016] The thickness of the ruthenium oxide layer of the first electrode layer in the first opening may be different from the thickness of the ruthenium oxide layer of the first electrode layer in the second opening.

[0017] The first electrode pad may be exposed above the upper surface of the passivation layer, and the width of the first electrode pad exposed above the upper surface of the passivation layer may be greater than the width of the first electrode pad in the first opening.

[0018] According to embodiments of the present invention, an ultra-small, high-capacity capacitor can be provided. Furthermore, according to embodiments of the present invention, a dielectric layer having a simple structure and high dielectric constant, capable of low-temperature processing, and having an appropriate band gap to block leakage current, and a capacitor including the dielectric layer can be provided.

[0019] Figure 1 is a capacitor according to one embodiment of the present invention.

[0020] Figure 2 shows the doping concentration according to the height of the dielectric layer in a capacitor according to one embodiment of the present invention.

[0021] Figures 3 and 4 show examples in which a capacitor according to an embodiment of the present invention is applied.

[0022] Figures 5 to 8 are cross-sectional views of capacitors according to other embodiments of the present invention.

[0023] Figure 9 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0024] Figure 10 is an IV graph according to the thickness of the dielectric layer according to an embodiment of the present invention.

[0025] Figure 11 is a CV graph according to the thickness of the dielectric layer according to an embodiment of the present invention.

[0026] Figure 12 shows a manufacturing process of a capacitor according to an embodiment of the present invention.

[0027] FIG. 13(a) is a cross-section of a capacitor in which a first electrode pad and a second electrode pad are connected according to one embodiment of the present invention, and FIGS. 13(b) to 13(e) are enlarged views of the R region of FIG. 13(a).

[0028] FIG. 14 is a cross-section of a capacitor in which a first electrode pad and a second electrode pad are connected according to another embodiment of the present invention.

[0029] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

[0030] However, the technical idea of ​​the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of ​​the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

[0031] In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

[0032] Additionally, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention.

[0033] In this specification, the singular may also include the plural unless specifically stated otherwise in the phrase, and when it is described as “A and / or at least one (or more) of B, C”, it may include one or more of all combinations that can be combined with A, B, C.

[0034] Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

[0035] These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

[0036] And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

[0037] Additionally, when described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Furthermore, when expressed as "above" or "below", it can include the meaning of a downward direction as well as an upward direction based on one component.

[0038] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0039] FIG. 1 is a capacitor according to one embodiment of the present invention, and FIG. 2 shows the doping concentration according to the height of a dielectric layer in the capacitor according to one embodiment of the present invention.

[0040] Referring to FIG. 1, the capacitor (100) includes a base (110), a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140).

[0041] The base (110) includes a first surface (111), a second surface (112) opposite the first surface (111), and a third surface (113) disposed between the first surface (111) and the second surface (112). The first surface (111), the second surface (112), and the third surface (113) may be referred to as a lower surface, an upper surface, and a side surface, respectively.

[0042] The base (110) may include a semiconductor material or an insulator material. For example, the base (110) may be a silicon (Si) substrate. For example, the base (110) may be a doped silicon substrate. For example, the base (110) may be an n-type doped silicon substrate or a p-type doped silicon substrate. Alternatively, the base (110) may include anodic aluminum oxide (AAO).

[0043] According to an embodiment of the present invention, a first electrode layer (120) is disposed on a base (110), a first dielectric layer (130) is disposed on the first electrode layer (120), and a second electrode layer (140) is disposed on the first dielectric layer (130). Although not shown in FIG. 1, the first electrode layer (120) may be connected to a first electrode pad, and the second electrode layer (140) may be connected to a second electrode pad.

[0044] The capacitance of a capacitor can be calculated according to the following mathematical formula 1.

[0045]

[0046] Here, C is the capacitance, ε is the permittivity, S is the area of ​​the electrode layers, and d is the distance between the electrode layers. According to this, it can be seen that the larger the area of ​​the electrode layers, the higher the capacitance, and the shorter the distance between the electrode layers, the higher the capacitance. However, in order to obtain a stable capacitance within a limited space, it is necessary to increase the permittivity of the dielectric layer.

[0047] According to an embodiment of the present invention, a capacitor is provided that includes a dielectric layer having a high dielectric constant and capable of blocking leakage current.

[0048] To this end, the first electrode layer (120) includes a ruthenium (Ru) layer (121) and a ruthenium oxide layer (122) disposed on the ruthenium layer (121). The ruthenium oxide layer (122) can be formed by oxidizing the surface of the ruthenium layer (121) or by heat treating or plasma treating the surface of the ruthenium layer (121). According to an embodiment of the present invention, the thickness of the first electrode layer (120) is 5 nm to 50 nm, preferably 10 nm to 50 nm, and more preferably 10 nm to 30 nm, and the thickness of the ruthenium oxide layer (122) can be 5 nm or less, preferably 0.1 nm to 5 nm, more preferably 0.1 nm to 3 nm, and more preferably 0.1 nm to 1 nm. When the thickness of the first electrode layer (120) and the ruthenium oxide layer (122) satisfies this numerical range, the first dielectric layer (130) can have a high dielectric constant without lowering the electrical conductivity of the ruthenium layer (121).

[0049] According to an embodiment of the present invention, the first dielectric layer (130) includes titanium oxide. For example, the titanium oxide may be TiO2. The titanium oxide may have an anatase crystal structure with a permittivity of 30 to 40 or a rutile crystal structure with a permittivity of 70 to 100. In general, titanium oxide deposited on a ruthenium layer at low temperature or room temperature may have an anatase crystal structure, and titanium oxide deposited on a ruthenium layer at high temperature may have a rutile crystal structure. However, according to an embodiment of the present invention, when titanium oxide is deposited on the ruthenium oxide layer (122), the titanium oxide may be deposited in a rutile crystal structure even at low temperature depending on the ruthenium oxide layer (122) rutile crystal structure.

[0050] Titanium oxide having a rutile crystal structure like this can have a high permittivity. However, titanium oxide having a rutile crystal structure has a small band gap, which can cause leakage current. According to an embodiment of the present invention, the first dielectric layer (130) includes titanium oxide doped with aluminum (Al). Accordingly, a first dielectric layer (130) having a high permittivity and improved leakage current characteristics can be obtained.

[0051] According to an embodiment of the present invention, the thickness of the first dielectric layer (130) including aluminum-doped titanium oxide is 18 nm to 22 nm. When the thickness of the first dielectric layer (130) satisfies this numerical range, a capacitor having a large electrostatic capacitance and a small leakage current can be obtained.

[0052] According to an embodiment of the present invention, the aluminum doping concentration in the first dielectric layer (130) may be 0.1 at% to 2 at%, preferably 0.5 at% to 1.5 at%, and more preferably 0.75 at% to 1.25 at%. When the aluminum doping concentration in the first dielectric layer (130) satisfies this numerical range, a capacitor having a large electrostatic capacity and a small leakage current can be obtained. In order to deposit the first dielectric layer (130) on the first electrode layer (120), a Ti precursor and an Al precursor may be introduced into the reactor together with an oxidizer and a purge gas. The aluminum doping concentration in the first dielectric layer (130) may vary depending on the introduction ratio of the Ti precursor and the Al precursor. For example, the Ti precursor may be Star-Ti(Ti(CpMe5)(OMe)3, the Al precursor may be trimethylaluminum(TMA), the oxidizer may be O3, and the purge gas may be argon, but is not limited thereto.

[0053] Depending on the order and time of introduction of the Ti precursor and Al precursor, the first dielectric layer (130) can be divided into multiple sublayers.

[0054] Referring to FIG. 2, the first dielectric layer (130) includes a plurality of sublayers sequentially stacked in a direction from the first electrode layer (120) toward the second electrode layer (140), for example, in the height direction of the first dielectric layer (130), and there may be a section in which the aluminum doping concentration varies in the height direction of the first dielectric layer (130) within each sublayer. For example, there may be a section in which the aluminum doping concentration decreases and then increases in the height direction of the first dielectric layer (130) within each sublayer. In this way, when there is a section in which the aluminum doping concentration varies in the height direction of the first dielectric layer (130) within each sublayer, the effect of preventing leakage current may be greater than when the aluminum doping concentration is uniform within the first dielectric layer (130).

[0055] A capacitor (100) according to an embodiment of the present invention can be applied to a server CPU (control processing unit), a mobile AP (access point), an FC-BGA (filp chip-ball grid array) substrate, etc.

[0056] Figures 3 and 4 show examples in which a capacitor according to an embodiment of the present invention is applied.

[0057] Referring to FIGS. 3 and 4, a capacitor according to an embodiment of the present invention may include a plurality of dielectric layers. For example, as illustrated in FIG. 3(a), electrode 1 (E1), dielectric layer 1 (D1), electrode 2 (E2), dielectric layer 2 (D2), and electrode 3 (E3) may be sequentially arranged. Here, the description regarding the first electrode layer (120) referring to FIG. 1 may be applied to at least one of electrode 1 (E1), electrode 2 (E2), and electrode 3 (E3). That is, at least one of electrode 1 (E1), electrode 2 (E2), and electrode 3 (E3) may be implemented as the first electrode layer (120) according to the embodiment illustrated in FIG. 1. In addition, the description regarding the first dielectric layer (130) referring to FIG. 1 may be applied to at least one of dielectric layer 1 (D1) and dielectric layer 2 (D2). That is, at least one of the dielectric layer 1 (D1) and the dielectric layer 2 (D2) can be implemented as the first dielectric layer (130) according to the embodiment illustrated in FIG. 1. Accordingly, as illustrated in FIG. 3(b), capacitor 1 (C1) and capacitor 2 (C2) can be connected in parallel to obtain high electrostatic capacitance. Alternatively, as illustrated in FIG. 4(a), electrode 1 (E1), dielectric layer 1 (D1), electrode 2 (E2), dielectric layer 2 (D2), electrode 3 (E3), dielectric layer 3 (D3), and electrode 4 (E4) can be sequentially arranged. Here, the description regarding the first electrode layer (120) referring to FIG. 1 can be applied to at least one of the electrode 1 (E1), electrode 2 (E2), electrode 3 (E3), and electrode 4 (E4). That is, at least one of electrode 1 (E1), electrode 2 (E2), electrode 3 (E3), and electrode 4 (E4) can be implemented as a first electrode layer (120) according to the embodiment illustrated in FIG. 1. In addition, the description regarding the first dielectric layer (130) referring to FIG. 1 can be applied to at least one of dielectric layer 1 (D1), dielectric layer 2 (D2), and dielectric layer 3 (D3).That is, at least one of the dielectric layer 1 (D1), the dielectric layer 2 (D2), and the dielectric layer 3 (D3) can be implemented as the first dielectric layer (130) according to the embodiment illustrated in FIG. 1. Accordingly, as illustrated in FIG. 4(b), the capacitor 1 (C1), the capacitor 2 (C2), and the capacitor 3 (C3) can be connected in parallel to obtain a high electrostatic capacitance.

[0058] Referring back to FIG. 1, according to an embodiment of the present invention, the second electrode layer (140) may include ruthenium (Ru). That is, the second electrode layer (140) may have the same material as the ruthenium layer (121) of the first electrode layer (120). Alternatively, the second electrode layer (140) may have a different material from the ruthenium layer (121) of the first electrode layer (120). For example, the second electrode layer (140) may include at least one of titanium (Ti), molybdenum (Mo), tungsten (W), indium-tin, copper (Cu), and aluminum (Al). For example, the second electrode layer (140) may include TiN, TiO2, MoO x , WO x , may include at least one of ITO, ITGO, Cu and Al, wherein x is a positive integer.

[0059] Figures 5 to 8 are cross-sectional views of capacitors according to other embodiments of the present invention.

[0060] Referring to FIGS. 5 to 8, the capacitor (100) includes a base (110), a first electrode layer (120) disposed on the base (110), a first dielectric layer (130) disposed on the first electrode layer (120), and a second electrode layer (140) disposed on the first dielectric layer (120).

[0061] According to an embodiment of the present invention, the base (110) includes a plurality of structures (115) protruding in a direction from the first surface (111) toward the second surface (112), and the plurality of structures (115) may be arranged to be spaced apart from each other. At this time, the plurality of structures (115) include silicon and may be formed integrally with the base (110). The plurality of structures (115) may be formed by a method of etching a silicon substrate. In order to form the plurality of structures (115), the silicon substrate may be etched in a negative shape or a positive shape. The plurality of structures (115) may have the same shape or a regular shape, and the spacing between the plurality of structures (115) may be the same, or may have a pattern that increases regularly or decreases regularly. According to an embodiment of the present invention, a trench structure may be formed between two adjacent structures (115).

[0062] As illustrated in FIGS. 5 and 6, at least some of the plurality of structures (115) may have a columnar shape. For example, at least some of the plurality of structures (115) may have a polygonal columnar shape or a cylindrical shape. For example, at least some of the plurality of structures (115) may have a triangular prism shape. As illustrated in FIG. 5, the bottom surface of the trench structure may have a concave shape. Alternatively, as illustrated in FIG. 6, the bottom surface of the trench structure may have a flat shape. Alternatively, as illustrated in FIG. 7, at least some of the plurality of structures (115) may have a cone shape. For example, at least some of the plurality of structures (115) may have a polygonal pyramidal shape or a cone shape. For example, at least some of the plurality of structures (115) may have a triangular pyramidal shape. In this specification, when the ratio (TA / BA) of the area of ​​the top surface to the area of ​​the bottom surface (BA) of each structure (115) is 1 or less, it can be referred to as a horn shape. That is, when the angle (θ) formed by the bottom surface and the side surface of each structure (115) is less than 90 degrees, it can be referred to as a horn shape. In this specification, when the ratio of the area of ​​the top surface to the area of ​​the bottom surface of each structure (115) is 1, it can be referred to as a pillar shape. That is, when the angle (θ) formed by the bottom surface and the side surface of each structure (115) is 90 degrees, it can be referred to as a pillar shape.

[0063] According to an embodiment of the present invention, the first electrode layer (120) is disposed on the surface of the base (110), i.e., the surface of the plurality of structures (115), and the first dielectric layer (130) and the second electrode layer (140) are disposed according to the shape of the first electrode layer (120).

[0064] To this end, the first electrode layer (120) includes a ruthenium (Ru) layer (121) and a ruthenium oxide layer (122) disposed on the ruthenium layer (121). At this time, the thickness of the first electrode layer (120) is 5 nm to 50 nm, preferably 5 nm to 50 nm, and more preferably 10 nm to 30 nm, and the thickness of the ruthenium oxide layer (122) may be 5 nm or less, preferably 0.1 nm to 5 nm, more preferably 0.1 nm to 3 nm, and more preferably 0.1 nm to 1 nm. When the thicknesses of the first electrode layer (120) and the ruthenium oxide layer (122) satisfy these numerical ranges, the first dielectric layer (130) can have a high dielectric constant without lowering the electrical conductivity of the ruthenium layer (121).

[0065] The first dielectric layer (130) disposed on the first electrode layer (120) includes aluminum-doped titanium oxide. Here, the thickness of the first dielectric layer (130) including aluminum-doped titanium oxide is 18 nm to 22 nm. If the thickness of the first dielectric layer (130) satisfies this numerical range, a capacitor having a large electrostatic capacitance and a small leakage current can be obtained.

[0066] Here, the aluminum doping concentration in the first dielectric layer (130) may be 0.1 at% to 2 at%, preferably 0.5 at% to 1.5 at%, and more preferably 0.75 at% to 1.25 at%. If the aluminum doping concentration in the first dielectric layer (130) satisfies this numerical range, a capacitor having a large electrostatic capacitance and a small leakage current can be obtained. At this time, the first dielectric layer (130) includes a plurality of sublayers sequentially stacked in the direction from the first electrode layer (120) toward the second electrode layer (140), that is, in the height direction of the first dielectric layer (130), and a section in which the aluminum doping concentration changes in the height direction of the first dielectric layer (130) in each sublayer may exist. For example, a section in which the aluminum doping concentration decreases and then increases in the height direction of the first dielectric layer (130) in each sublayer may exist. In this way, when there is a section in which the aluminum doping concentration varies in the height direction of the first dielectric layer (130) within each sublayer, the effect of preventing leakage current can be greater than when the aluminum doping concentration is uniform within the first dielectric layer (130).

[0067] According to an embodiment of the present invention, since the ratio of the area of ​​the first electrode layer (120) and the second electrode layer (140) to the thickness of the first dielectric layer (130) can be maximized, a capacitor having a high electrostatic capacitance can be obtained. In addition, if the thickness of the first dielectric layer (130) is 18 nm to 22 nm, it is possible to uniformly deposit the thickness of the second electrode layer (140) even in a trench structure, so a highly reliable capacitor can be obtained.

[0068] Meanwhile, referring to FIG. 8, the capacitor (100) may further include a second dielectric layer (180) disposed on a second electrode layer (140) and a third electrode layer (190) disposed on the second dielectric layer (180). The second dielectric layer (180) and the third electrode layer (190) may be disposed according to the shapes of the first dielectric layer (130) and the second electrode layer (140).

[0069] At this time, the second electrode layer (140) may include a ruthenium (Ru) layer (141) and a ruthenium oxide layer (142) disposed on the ruthenium layer (141). At this time, the thickness of the second electrode layer (140) is 5 nm to 50 nm, preferably 5 nm to 50 nm, and more preferably 10 nm to 30 nm, and the thickness of the ruthenium oxide layer may be 5 nm or less, preferably 0.1 nm to 5 nm, more preferably 0.1 nm to 3 nm, and more preferably 0.1 nm to 1 nm. When the thicknesses of the second electrode layer (140) and the ruthenium oxide layer (142) satisfy these numerical ranges, the second dielectric layer (180) can have a high dielectric constant without lowering the electrical conductivity of the ruthenium layer (141).

[0070] The second dielectric layer (180) disposed on the second electrode layer (140) may include aluminum-doped titanium oxide. Here, the thickness of the second dielectric layer (180) including aluminum-doped titanium oxide may be 18 nm to 22 nm. If the thickness of the second dielectric layer (180) satisfies this numerical range, a capacitor having a large electrostatic capacitance and a small leakage current can be obtained.

[0071] Here, the aluminum doping concentration in the second dielectric layer (180) may be 0.1 at% to 2 at%, preferably 0.5 at% to 1.5 at%, and more preferably 0.75 at% to 1.25 at%. If the aluminum doping concentration in the second dielectric layer (180) satisfies this numerical range, a capacitor having a large electrostatic capacity and a small leakage current can be obtained. At this time, the second dielectric layer (180) includes a plurality of sublayers sequentially stacked in a direction from the second electrode layer (140) to the third electrode layer (190), and a section in which the aluminum doping concentration in each sublayer changes may exist. For example, a section in which the aluminum doping concentration decreases and then increases in the direction from the second electrode layer (140) to the third electrode layer (190) in each sublayer may exist. In this way, when there is a section in which the aluminum doping concentration within each sublayer is different, the effect of preventing leakage current can be greater than when the aluminum doping concentration is uniform within the second dielectric layer (180).

[0072] As in the embodiment of Fig. 8, when the capacitor (100) includes a plurality of sequentially stacked dielectric layers (130, 180), parallel connection of the capacitors is possible, so that a high electrostatic capacitance can be obtained.

[0073] Figure 9 is a cross-sectional view of a capacitor according to another embodiment of the present invention.

[0074] Referring to FIG. 9, the base (110) may include a plurality of through holes (TH) penetrating from the first surface (111) to the second surface (112). That is, the plurality of through holes (TH) may extend from the first surface (111) of the base (110) to the second surface (112). At this time, at least some of the plurality of through holes (TH) may be parallel to each other. For example, a virtual line connecting the center of the first surface (111) of one of the plurality of through holes (TH) to the center of the second surface (112) may be parallel to a virtual line connecting the center of the first surface (111) of another of the plurality of through holes (TH) to the center of the second surface (112). Accordingly, since an electrode layer may be deposited with a uniform thickness on the inner wall surfaces of the plurality of through holes (TH), a highly reliable capacitor may be obtained.

[0075] According to an embodiment of the present invention, the first electrode layer (120) may be disposed on the first surface (111), the second surface (112) of the base (110) and the inner wall surfaces of the plurality of through holes (TH), the first dielectric layer (130) may be disposed on the first electrode layer (120), and the second electrode layer (140) may be disposed on the first dielectric layer (130).

[0076] To this end, the first electrode layer (120) includes a ruthenium (Ru) layer (121) and a ruthenium oxide layer (122) disposed on the ruthenium layer (121). At this time, the thickness of the first electrode layer (120) is 5 nm to 50 nm, preferably 5 nm to 50 nm, and more preferably 10 nm to 30 nm, and the thickness of the ruthenium oxide layer (122) may be 5 nm or less, preferably 0.1 nm to 5 nm, more preferably 0.1 nm to 3 nm, and more preferably 0.1 nm to 1 nm. When the thicknesses of the first electrode layer (120) and the ruthenium oxide layer (122) satisfy these numerical ranges, the first dielectric layer (130) can have a high dielectric constant without lowering the electrical conductivity of the ruthenium layer (121).

[0077] The first dielectric layer (130) disposed on the first electrode layer (120) includes aluminum-doped titanium oxide. Here, the thickness of the first dielectric layer (130) including aluminum-doped titanium oxide is 18 nm to 22 nm. If the thickness of the first dielectric layer (130) satisfies this numerical range, a capacitor having a large electrostatic capacitance and a small leakage current can be obtained.

[0078] Here, the aluminum doping concentration in the first dielectric layer (130) may be 0.1 at% to 2 at%, preferably 0.5 at% to 1.5 at%, and more preferably 0.75 at% to 1.25 at%. If the aluminum doping concentration in the first dielectric layer (130) satisfies this numerical range, a capacitor having a large electrostatic capacitance and a small leakage current can be obtained. At this time, the first dielectric layer (130) includes a plurality of sublayers sequentially stacked in the direction from the first electrode layer (120) toward the second electrode layer (140), that is, in the height direction of the first dielectric layer (130), and a section in which the aluminum doping concentration changes in the height direction of the first dielectric layer (130) in each sublayer may exist. For example, a section in which the aluminum doping concentration decreases and then increases in the height direction of the first dielectric layer (130) in each sublayer may exist. In this way, when there is a section in which the aluminum doping concentration varies in the height direction of the first dielectric layer (130) within each sublayer, the effect of preventing leakage current can be greater than when the aluminum doping concentration is uniform within the first dielectric layer (130).

[0079] According to an embodiment of the present invention, since the ratio of the area of ​​the first electrode layer (120) and the second electrode layer (140) to the thickness of the first dielectric layer (130) can be maximized, a capacitor having a high electrostatic capacitance can be obtained. In addition, if the thickness of the first dielectric layer (130) is 18 nm to 22 nm, it is possible to uniformly deposit the thickness of the second electrode layer (140) even in a trench structure, so a highly reliable capacitor can be obtained.

[0080] FIG. 10 is an IV graph according to the thickness of a dielectric layer according to an embodiment of the present invention, FIG. 11 is a CV graph according to the thickness of a dielectric layer according to an embodiment of the present invention, Table 1 shows the leakage current according to the thickness of a dielectric layer, and Table 2 shows the electrostatic capacitance according to the thickness of a dielectric layer.

[0081] Referring to Fig. 10 and Table 1, it can be seen that when the thickness of the dielectric layer is 15 nm, the leakage current is 949 pA, but when the thickness is 18 nm or more, the leakage current can be significantly reduced to 248 pA.

[0082] Dielectric layer thickness [nm] 15182125 Leakage current [pA] @ 1.1 V 949248187139

[0083] Referring to Fig. 11 and Table 2, when the thickness of the dielectric layer is 25 nm, the capacitance is 18.9 nF / mm 2 However, when the thickness of the dielectric layer is less than 21 nm, the capacitance is 27.2 F / mm 2 You can see that it is abnormal.

[0084] Dielectric layer thickness [nm] 15182125 Capacitance [nF / mm 2 ]39.932.527.218.9

[0085] In this way, if the thickness of the dielectric layer satisfies the numerical range according to the embodiment of the present invention, a capacitor satisfying both leakage current characteristics and capacitance characteristics can be obtained.

[0086] Figure 12 shows a manufacturing process of a capacitor according to an embodiment of the present invention.

[0087] Referring to Fig. 12(a), a first electrode layer (120), a first dielectric layer (130), and a second electrode layer (140) are sequentially laminated on a base (110). The lamination of the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) can be performed by ALD (atomic layer deposition). Using the ALD process, the materials of the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) can be conformally deposited at atomic levels.

[0088] Referring to Fig. 12(b), the first dielectric layer (130) and the second electrode layer (140) are etched. To this end, photoresist (PR) may be coated on the second electrode layer (140), then exposed and developed to etch the second electrode layer (140) and the first dielectric layer (130). Thereafter, the PR may be removed.

[0089] Referring to Fig. 12(c), a passivation layer is deposited. The passivation layer may include SiO2. The passivation layer is disposed on the second electrode layer (140) and may fill the etched area in Fig. 12(b).

[0090] Referring to Fig. 12(d), a photomask for the first opening and the second opening is formed on the passivation layer. To this end, photoresist (PR) may be coated on the passivation layer, followed by exposure and development.

[0091] Referring to Fig. 12(e), the passivation layer is etched. Accordingly, a first opening extending from the upper surface of the passivation layer to the first electrode layer (120) can be formed, and a second opening extending from the upper surface of the passivation layer to the upper surface of the second electrode layer (140) can be formed.

[0092] Referring to Fig. 12(f), the PR on the passivation layer is removed.

[0093] Referring to Fig. 12(g), a material constituting an electrode pad is deposited, and a photomask for the electrode pad is formed. The material constituting the electrode pad may be, for example, aluminum. That is, the aluminum is disposed on the passivation layer and can fill the first opening and the second opening.

[0094] Referring to Fig. 12(h), aluminum is etched to form a first electrode pad (150) and a second electrode pad (160), and PR on the first electrode pad (150) and the second electrode pad (160) is removed.

[0095] FIG. 13(a) is a cross-section of a capacitor in which a first electrode pad and a second electrode pad are connected according to one embodiment of the present invention, and FIGS. 13(b) to 13(e) are enlarged views of the R region of FIG. 13(a).

[0096] Referring to Fig. 13(a), a first electrode layer (120), a first dielectric layer (130), a second electrode layer (140), and a passivation layer are sequentially arranged on a base (110). A first electrode pad (150) may be connected to the first electrode layer (120) through a first opening extending from the upper surface of the passivation layer to the first electrode layer (120), and a second electrode pad (160) may be connected to the second electrode layer (140) through a second opening extending from the upper surface of the passivation layer to the upper surface of the second electrode layer (140). At this time, the passivation layer may be further arranged along the side surfaces of the first dielectric layer (130) and the second electrode layer (140) in the first opening. According to this, the passivation layer can electrically insulate between the first electrode pad (150) connected to the first electrode layer (120) and the second electrode layer (140).

[0097] At this time, the first electrode pad (150) is protruded above the upper surface of the passivation layer, and the width of the first electrode pad (150) exposed above the upper surface of the passivation layer may be greater than the width of the first electrode pad (150) in the first opening. For example, the width of the first electrode pad (150) in the first opening may be 45 to 55 μm, and the width of the first electrode pad (150) exposed above the upper surface of the passivation layer may be 65 to 75 μm. Similarly, the second electrode pad (160) is protruded above the upper surface of the passivation layer, and the width of the second electrode pad (160) exposed above the upper surface of the passivation layer may be greater than the width of the second electrode pad (160) in the second opening. For example, the width of the second electrode pad (160) in the second opening may be 45 to 55 μm, and the width of the second electrode pad (160) exposed above the upper surface of the passivation layer may be 65 to 75 μm. When the widths of the first electrode pad (150) and the second electrode pad (160) satisfy these numerical ranges, not only is it easy to deposit the first electrode pad (150) and the second electrode pad (160) in the first opening and the second opening, but it is also easy to stably connect the first electrode pad (150) and the second electrode pad (160) to an external electrode or an external wire.

[0098] Meanwhile, referring to FIG. 13(b), the first opening extends to the upper surface of the ruthenium oxide layer (122) of the first electrode layer (120), and the first electrode pad (150) can be connected to the ruthenium oxide layer (122) of the first electrode layer (120). Accordingly, the first electrode pad (150) can be easily deposited on the ruthenium oxide layer (122) of the first electrode layer (120), and the bonding strength between the first electrode pad (150) and the first electrode layer (120) can be increased.

[0099] Alternatively, referring to FIG. 13(c), the first opening may extend to the upper surface of the ruthenium layer (121) of the first electrode layer (120), and the first electrode pad (150) may be connected to the ruthenium layer (121) of the first electrode layer (120). Accordingly, the electrical conductivity between the first electrode pad (150) and the first electrode layer (120) may be increased.

[0100] Meanwhile, referring to FIG. 13(d), the first opening may extend to a portion of the ruthenium oxide layer (122) of the first electrode layer (120), and the first electrode pad (150) may be connected to the ruthenium oxide layer (122) of the first electrode layer (120). Accordingly, the thickness of the ruthenium oxide layer (122) of the first electrode layer (120) in the first opening may be different from the thickness of the ruthenium oxide layer (122) of the first electrode layer (120) in the second opening. That is, the thickness of the ruthenium oxide layer (122) of the first electrode layer (120) in the first opening may be thinner than the thickness of the ruthenium oxide layer (122) of the first electrode layer (120) in the second opening. According to this, the first electrode pad (150) can be easily deposited on the ruthenium oxide layer (122) of the first electrode layer (120), so that not only the bonding strength between the first electrode pad (150) and the first electrode layer (120) can be increased, but also the electrical conductivity between the first electrode pad (150) and the first electrode layer (120) can be increased.

[0101] Meanwhile, referring to FIG. 13(e), the first opening extends to a portion of the ruthenium layer (121) of the first electrode layer (120), and the first electrode pad (150) can be connected to the ruthenium layer (121) of the first electrode layer (120). Accordingly, the passivation layer extends to the side of the ruthenium layer (121) as well as the side of the ruthenium oxide layer (122), so that the overall resistance of the capacitor can be reduced, the passivation function against thermal expansion of the first electrode layer (120) and the first electrode pad (150) can be further increased, and the electrical conductivity between the first electrode pad (150) and the first electrode layer (120) can also be increased.

[0102] FIG. 14 is a cross-section of a capacitor in which a first electrode pad and a second electrode pad are connected according to another embodiment of the present invention.

[0103] Referring to FIG. 14, a first electrode layer (120), a first dielectric layer (130), a second electrode layer (140), and a passivation layer are sequentially arranged on a trench-shaped base (110), and a first electrode pad (150) can be connected to the first electrode layer (120) through a first opening, and a second electrode pad (160) can be connected to the second electrode layer (140). As illustrated, the first electrode pad (150) and the second electrode pad (160) can be arranged on the upper surfaces of a plurality of structures forming a trench shape.

[0104] Duplicate descriptions of the same contents as those described above regarding the first electrode layer (120), the first dielectric layer (130), and the second electrode layer (140) are omitted.

[0105] As described using FIGS. 13(b) to 13(e), in the embodiment of FIG. 14, the first opening extends to the upper surface of the ruthenium oxide layer (122) of the first electrode layer (120), and the first electrode pad (150) is connected to the ruthenium oxide layer (122) of the first electrode layer (120), or the first opening extends to the upper surface of the ruthenium layer (121) of the first electrode layer (120), and the first electrode pad (150) is connected to the ruthenium layer (121) of the first electrode layer (120), or the first opening extends to a part of the ruthenium oxide layer (122) of the first electrode layer (120), and the first electrode pad (150) is connected to the ruthenium oxide layer (122) of the first electrode layer (120), or the first opening extends to the It extends to a part of the ruthenium layer (121), and the first electrode pad (150) can be connected to the ruthenium layer (121) of the first electrode layer (120).

[0106] For convenience of explanation, only the embodiment of FIG. 5 with a concave bottom of the trench shape is illustrated, but the first electrode pad and the second electrode pad of the same structure can also be applied to the embodiments of FIGS. 6 to 9.

[0107] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims

1. Base, A first electrode layer disposed on the above base, A first dielectric layer disposed on the first electrode layer, and A second electrode layer is disposed on the first dielectric layer, The first electrode layer includes a ruthenium (Ru) layer and a ruthenium oxide layer disposed on the ruthenium layer, The first dielectric layer comprises aluminum (Al) doped titanium oxide, A capacitor wherein the thickness of the first dielectric layer is 18 nm to 22 nm.

2. In paragraph 1, A capacitor wherein the thickness of the first electrode layer is 5 nm to 50 nm.

3. In paragraph 1, The first dielectric layer includes a plurality of sublayers sequentially stacked in a direction from the first electrode layer toward the second electrode layer, A capacitor in which there is a section in which the aluminum doping concentration changes in the direction from the first electrode layer to the second electrode layer within each sublayer.

4. In paragraph 3, A capacitor in which there is a section in which the aluminum doping concentration decreases and then increases in the direction from the first electrode layer to the second electrode layer within each sublayer.

5. In paragraph 1, A capacitor having an aluminum doping concentration in the first dielectric layer of 0.1 at% to 2 at%.

6. In paragraph 1, The base includes a first surface and a second surface opposite to the first surface, and includes a plurality of structures protruding from the first surface in a direction toward the second surface, A capacitor in which the first electrode layer, the first dielectric layer, and the second electrode layer are sequentially stacked between the plurality of structures and the plurality of structures.

7. In paragraph 1, The base includes a first surface and a second surface opposite to the first surface, and includes a plurality of through holes formed along a direction from the first surface toward the second surface, A capacitor in which the first electrode layer, the first dielectric layer, and the second electrode layer are sequentially laminated on the first surface, the second surface, and the inner wall surfaces of the plurality of through holes.

8. In paragraph 1, A second dielectric layer disposed on the second electrode layer, and including a third electrode layer disposed on the second dielectric layer, The second electrode layer includes a ruthenium (Ru) layer and a ruthenium oxide layer, The second dielectric layer comprises aluminum (Al) doped titanium oxide, A capacitor wherein the thickness of the second dielectric layer is 18 nm to 22 nm.

9. In paragraph 1, A passivation layer disposed on the second electrode layer, A first electrode pad connected to the first electrode layer through a first opening extending from the upper surface of the passivation layer to the first electrode layer, and Further comprising a second electrode pad connected to the second electrode layer through a second opening extending from the upper surface of the passivation layer to the upper surface of the second electrode layer, A capacitor in which the passivation layer is further arranged along the side surfaces of the first dielectric layer and the second electrode layer in the first opening.

10. In paragraph 9, The first opening extends to the upper surface of the ruthenium layer of the first electrode layer, and the first electrode pad is a capacitor connected to the ruthenium layer.

Images