Systems and methods for achieving process rate uniformity by identifying one or more bins

Abstract

A method for achieving process rate uniformity by identifying one or more bins is described. The method includes receiving a voltage signal provided from an output of an impedance matching circuit. The method further includes dividing the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal, accessing a recipe set identifying one or more of the bins for achieving the process rate uniformity, and controlling delivered power to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity.

Description

SYSTEMS AND METHODS FOR ACHIEVING PROCESS RATE UNIFORMITY BY IDENTIFYING ONE OR MORE BINSFIELD

[0001] The embodiments described in the present disclosure relate to systems and methods for achieving process rate uniformity by identifying one or more bins.BACKGROUND

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In a plasma system, a radio frequency (RF) generator is coupled to a plasma chamber. A semiconductor wafer is placed within the plasma chamber for being processed. The RF generator generates an RF signal and provides the RF signal to the plasma chamber for processing the semiconductor wafer. When a gas is supplied to the plasma chamber in conjunction with the RF signal, plasma is stricken within the plasma chamber. However, when the plasma is generated, it is difficult to process the semiconductor wafer in a desirable manner.

[0004] It is in this context that embodiments described in the present disclosure arise.SUMMARY

[0005] Embodiments of the disclosure provide systems and methods for achieving process rate uniformity by identifying one or more bins. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Several embodiments are described below.

[0006] In one embodiment, a method for achieving process rate uniformity is described. The method includes receiving a voltage signal provided from an output of an impedance matching circuit. The method further includes dividing the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal, accessing a recipe set identifying one or more of the bins for achieving the process rate uniformity, and controlling delivered power to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity.

[0007] In an embodiment, a controller for achieving process rate uniformity by identifying one or more bins is described. The controller includes a processor and a memory device coupled to the processor. The processor receives a voltage signal provided from an outputof an impedance matching circuit, divides the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal, and accesses a recipe set identifying one or more of the bins for achieving the process rate uniformity. The processor controls delivered power to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity. The controller includes a memory device coupled to the processor.

[0008] In one embodiment, a system for achieving process rate uniformity is described. The system includes a first radio frequency (RF) generator that generates a first RF signal, a second RF generator that generates a second RF signal, and a match coupled to the first and second RF generators to receive the first and second RF signals to output a modified RF signal. The match has an output. The system includes a controller coupled to the first and second RF generators. The controller receives a voltage signal provided from the output of the match, divides the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal, and accesses a recipe set identifying one or more of the bins for achieving the process rate uniformity. The controller controls delivered power to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity.

[0009] Some advantages of the herein described systems and methods include achieving the process rate uniformity by identifying bins during which power delivered from a high frequency (HF) RF generator is controlled to be of a predetermined amount. By identifying the bins, the process rate uniformity is achieved.

[0010] Some other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments are understood by reference to the following description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a diagram of an embodiment of a system to identify bins during which delivered power is controlled to be at a predetermined amount to achieve a process benefit.

[0013] Figure 2A is an embodiment of a graph to illustrate cycles of a measurement voltage signal or of a low frequency radio frequency (RF) signal.

[0014] Figure 2B is an embodiment of a graph to illustrate a measurement voltage signal.

[0015] Figure 2C-1 is an embodiment of a graph to illustrate power that is delivered by a high frequency (HF) radio frequency (RF) generator at an output during each bin of each cycle of the measurement voltage signal.

[0016] Figure 2C-2 is an embodiment of a graph to illustrate power that is delivered by the HF RF generator at an output during each bin of each cycle of the measurement voltage signal.

[0017] Figure 3 is an embodiment of a graph to illustrate multiple states of pulsing of power of an HF multi state signal that is generated by the HF RF generator.

[0018] Figure 4 is a diagram of an embodiment of a system to illustrate details of an HF RF generator.

[0019] Figure 5A is an embodiment of a graph to illustrate etch amounts at which a substrate is etched.

[0020] Figure 5B is an embodiment of a graph to illustrate twenty bins.

[0021] Figure 5C is an embodiment of a graph to illustrate that split blanking is used to control etch rate uniformity.DETAILED DESCRIPTION

[0022] The following embodiments describe systems and methods for achieving process rate uniformity by identifying one or more bins. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0023] Figure 1 is a diagram of an embodiment of a system 100 to identify bins during which delivered power is controlled to be at a predetermined amount to achieve a process benefit, such as the process rate uniformity. As an example, a process rate, as used herein, is an etch rate or a deposition rate or a combination thereof. The system 100 includes a host computer 102, a low frequency (LF) radio frequency (RF) generator 104, a high frequency (HF) RF generator 106, a match 108, and a plasma chamber 110. The system 100 further includes a voltage sensor 112 and process rate measurement devices (PRMDs) 114, 116, and 118.

[0024] An example of the host computer 102 includes a desktop computer or a laptop computer or a smart phone or a tablet or a controller. An example of the LF RF generator 104 is an RF generator having a low frequency, such as a low operating frequency. The low operating frequency is sometimes referred to herein as a low frequency of operation. Examples of the low operating frequency include a frequency in kilohertz (kHz), such as 100 kHz or 400 kHz, and a frequency of 2 MHz. An example of the HF RF generator 106 is an RF generator having a high frequency, such as a high operating frequency. The high operating frequency is sometimes referred to herein as a high frequency of operation. An example of the high operating frequency includes a frequency of 60 MHz.

[0025] Examples of the match 108 include an impedance matching circuit, which is sometimes referred to herein as an impedance match or an impedance matching network. To illustrate, the match 108 includes a network of capacitors and inductors. The capacitors and inductors are sometimes referred to herein as network components. An example of the plasma chamber 110 includes a capacitively coupled plasma (CCP) chamber. An example of a process rate measurement device that includes an etch rate measurement device (ERMD). To illustrate, an ERMD includes a spectrophotometer that monitors the plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma generated within the plasma chamber 110.

[0026] The host computer 102 includes a processor 120 and a memory device 122. Examples of the processor 120 include a central processing unit (CPU), an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of the memory device 122 include a read-only memory and a random access memory. The HF RF generator 106 includes a power sensor 124 that is coupled to an output 126 of the HF RF generator 106.

[0027] The plasma chamber 110 includes an electrostatic chuck 101 and an upper electrode 103. The upper electrode 103 is situated above the electrostatic chuck 101 to face the electrostatic chuck 101 and form a gap 105 between the electrostatic chuck 101 and the upper electrode 103. A substrate S, such as a semiconductor wafer on which one or more integrated circuits are to be formed, is placed on a top surface of the electrostatic chuck 101 for being processed. The plasma chamber 110 further includes a window 107, another window 109, and another window 111. The window 107 is associated with, such as coupled to, a left wall 113 of the plasma chamber 110, and the windows 109 and 111 are associated with, such as coupled to, a right wall 115 of the plasma chamber 110.

[0028] The PRMD 114 is associated with the window 107, the PRMD 116 is associated with the window 109, and the PRMD 118 is associated with the window 111. For example, the PRMD 114 is attached to the window 107, the PRMD 116 is attached to the window 109, and the PRMD 118 is attached to the window 111. As another example, the PRMD 114 is placed proximate to the window 107, the PRMD 116 is placed proximate to the window 109, and the PRMD 118 is placed proximate to the window 111. As an example, each window 107, 109, and I l l is made of a transparent material, such as glass, that allows light emitted by the plasma to pass through. In various embodiments, each window 107, 109, and 111 is a translucent window.

[0029] The processor 120 is coupled to the memory device 122. The processor 120 is also coupled via a transfer cable 128 to an input of the LF RF generator 104 and via a transfer cable 130 to an input of the HF RF generator 106. An example of a transfer cable includes a universal serial bus (USB) cable or a cable that allows a parallel transfer of data or a cable thatenables a serial transfer data. An output 132 of the LF RF generator 104 is coupled via an RF cable 134 to an input 136 of the match 108. Also, the output 126 of the HF RF generator 106 is coupled via an RF cable 138 to an input 140 of the match 108. An output 142 of the match 108 is coupled via an RF transmission line 144 to a lower electrode embedded within the electrostatic chuck 101. An example of the output 142 is a connector that connects the RF transmission line 144 to the network components of match 108.

[0030] The PRMD 114 is coupled to the processor 120 via a transfer cable 146 and has a line of sight via the window 107 into the gap 105 within the plasma chamber 110. The line of sight of the PRMD 114 is directed into a space in which the plasma is generated within the plasma chamber 110. For example, the PRMD 114 includes a spectrophotometer that monitors plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma via the window 107. The intensity of radiation emitted by the plasma via the window 107 is directly proportional to a process rate at a left edge region 148 of the substrate S. As an example, the line of sight of the PRMD 114 is directed to the left edge region 148 of the substrate S.

[0031] Similarly, the PRMD 116 is coupled to the processor 120 via a transfer cable 150 and has a line of sight via the window 109 into the gap 105. The line of sight of the PRMD 116 is directed into the space in which the plasma is generated within the plasma chamber 110. For example, the PRMD 116 includes a spectrophotometer that monitors plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma via the window 109. The intensity of radiation emitted by the plasma via the window 109is directly proportional to a process rate at a central region 152 of the substrate S that is processed by the plasma within the plasma chamber 110. As an example, the line of sight of the PRMD 116 is directed to the central region 152 of the substrate S.

[0032] Also, the PRMD 118 is coupled to the processor 120 via a transfer cable 154 and has a line of sight via the window 111 into the gap 105. The line of sight of the PRMD 118 is directed into the space in which the plasma is generated within the plasma chamber 110. For example, the PRMD 118 includes a spectrophotometer that monitors plasma within the plasma chamber 110 to measure intensity of radiation emitted by the plasma via the window 111. The intensity of radiation emitted by the plasma via the window I l l is directly proportional to a process rate at a right edge region 156 of the substrate S that is processed by the plasma within the plasma chamber 110. As an example, the line of sight of the PRMD 118 is directed to the right edge region 156 of the substrate S. The central region 152 is surrounded by the edge regions 148 and 156. The voltage sensor 112 is coupled to the processor 120 via a transfer cable 115.

[0033] The processor 120 sends a recipe set 156A via the transfer cable 128 to the LF RF generator 104 to control the LF RF generator 104. Also, the processor 120 sends a recipe set 156B via the transfer cable 132 to the HF RF generator 106 to control the HF RF generator 106. For example, the recipe sets 156A and 156B are received from a user via an input device. Examples of the input device include a mouse, a keyboard, a keypad, a touch screen, and a stylus. The input device is coupled to the processor 120.

[0034] The recipe set 156A includes power and frequency information for generating an RF signal 158A and the recipe set 156B includes power and frequency information, such as a predetermined amount of delivered power level, for generating an RF signal 158B. The recipe set 156B includes identities of one or more of the bins during each cycle of a clock signal for which delivered power level output from the HF RF generator 106 is equal to the predetermined amount. The clock signal is further described below. An example of the frequency information for generating the RF signal 158A includes the low frequency of operation and an example of the frequency information for generating the RF signal 158B includes the high frequency of operation. As an example, the high frequency of operation is applied to generate the RF signal 158B during one or more cycles, such as a cycle n, of the RF signal 158A, where n is a positive integer. An example of the RF signal 158A is a continuous wave RF signal. Another example of the RF signal 158A is a mutistate RF signal. Similarly, an example of the RF signal 158B is a continuous wave RF signal and another example of the RF signal 158B is a mutistate RF signal. Each RF signal, as described herein, is a sinusoidal signal.

[0035] The processor 120 also sends a trigger signal via the transfer cables 128 and 132 to the RF generators 104 and 106 to control the RF generators 104 and 106. Upon receiving the trigger signal, the LF RF generator 104 generates the RF signal 158 A based on the power and frequency information received within the recipe set 156A, and sends the RF signal 158A via the output 132 and the RF cable 134 to the input 136. Moreover, upon receiving the trigger signal, the HF RF generator 106 generates the RF signal 158B based on the power and frequency information, and the identities of one or more of the bins received within the recipe set 156B, and sends the RF signal 158B via the output 126 and the RF cable 138 to the input 140.

[0036] When the RF signal 158A is generated, the voltage sensor 112 senses a voltage of the modified RF signal 160 at the output 142 to generate a measurement voltage signal 162, and sends the measurement voltage signal 162 via the transfer cable 115 to the processor 120. As an example, the measurement voltage signal 162 has a frequency that is substantially similar to a frequency of the RF signal 158A generated by the LF RF generator 104. For example, the frequency of the measurement voltage signal 162 is the same as, such as equal to, the frequency of the RF signal 158 A. To illustrate, the frequency of the measurement voltage signal 162 isequal to the frequency of the RF signal 158A. In the illustration, the frequency of the RF signal 158A is equal to the low frequency of operation. As another illustration, the frequency of the measurement voltage signal 162 is equal to the frequency of the RF signal 158 A slightly modified by the frequency of the RF signal 158B. Upon receiving the measurement voltage signal 162, the processor 120 divides each cycle of the measurement voltage signal 162 into multiple time intervals, such as multiple time periods, and each of the time intervals is sometimes referred to herein as a bin.

[0037] Upon receiving the RF signals 158A and 158B, the match 108 matches an impedance of a load coupled to the output 142 with an impedance of a source coupled to the inputs 136 and 140 and combines the RF signals 158A and 158B to generate a modified RF signal 160 at the output 142. An example of the load includes the RF transmission line 144 and the plasma chamber 110, and an example of the source, includes the RF generators 104 and 106 and the RF cables 134 and 138.

[0038] The modified RF signal 160 is sent from the output 142 via the RF transmission line 144 to the lower electrode. When one or more process gases, such as an oxygen-containing gas or a halogen-containing gas or a phosphorus-containing gas or a combination thereof, are supplied to the gap 105 with the modified RF signal 160, the substrate S is processed within the plasma chamber 110. For example, one or more materials are deposited on the substrate S or the substrate S is etched or the substrate S is cleaned or a combination thereof to process the substrate S.

[0039] Moreover, when the substrate S is being processed, the PRMD 114 generates intensity signals 164A and 164B based on the line of sight towards the left edge region 148 of the substrate S, and sends the intensity signals 164A and 164B via the transfer cable 146 to the processor 120. Similarly, the PRMD 116 generates intensity signals 164C and 164D based on the line of sight towards the central region 152 of the substrate S, and sends the intensity signals 164C and 164D via the transfer cable 150 to the processor 120. Also, the PRMD 118 generates intensity signals 164E and 164F based on the line of sight towards the right edge region 156 of the substrate S, and sends the intensity signals 164E and 164F via the transfer cable 154 to the processor 120. Based on the intensity signals 164A through 164F, the processor 120 determines a first process rate uniformity in a manner described below with reference to Figure 2C-2.

[0040] The processor 120 further accesses a modified recipe set 166 from the memory device 122, and sends the modified recipe set 166 to the HF RF generator 106. For example, the processor 120 receives the modified recipe set 166 from the user via the input device and stores the modified recipe set 166 in the memory device 122. As another example, the processor 120 generates the modified recipe set 166 from the recipe set 156B and stores the modified recipe set166 in the memory device 122. The processor 120 receives an indication from the user via the input device to access the modified recipe set 166. In the example, upon receiving the indication, the processor 120 accesses, such as reads, the modified recipe set 166 from the memory device 122 and sends the modified recipe set 166 to the HF RF generator 106. The modified recipe set 166 includes identities of one or more of the bins during each cycle of the clock signal for which delivered power level output from the HF RF generator 106 is equal to the predetermined amount. The modified recipe set 166 further includes power and frequency information, such as the predetermined amount of delivered power level, for generating an RF signal 168.

[0041] Upon receiving the modified recipe set 166 and the trigger signal from the processor 120, the HF RF generator 106 modifies the RF signal 158B to achieve the delivered power level of the predetermined amount during the one or more bins identified within the modified recipe set 166 to generate the RF signal 168 having the delivered power level during the one or more bins. For example, the modified recipe set 166 is sent to the HF RF generator 106 to apply the modified recipe set 166 during a following cycle, such as a next cycle, of the RF signal 158A that follows one or more cycles of the RF signal 158A during which the recipe set 158B is applied. To illustrate, the modified recipe set 166 is sent from the processor 120 to the HF RF generator 106 to generate the RF signal 168 during an (n+l)thcycle of the RF signal 158A and the recipe set 156B is sent from the processor 120 to the HF RF generator 106 to generate the RF signal 158B during the nthcycle of the RF signal 158 A. In the illustration, the (n+l)thcycle immediately follows the nthcycle. As another illustration, the modified recipe set 166 is sent from the processor 120 to the HF RF generator 106 to generate the RF signal 168 during an (n+t)thcycle of the RF signal 158A and the recipe set 156B is sent to generate the RF signal 158B during the nthcycle of the RF signal 158A, where t is a positive integer. In the illustration, the (n+t)thcycle follows the nthcycle. To further illustrate, the nthcycle occurs preceding to or occurs one or more cycles before an occurrence of the (n+t)thcycle.

[0042] The RF signal 168 is sent from the output 126 via the RF cable 138 to the input 140. Upon receiving the RF signals 158A and 168, the match 108 combines the RF signals 158A and 168, and matches an impedance of the load with the impedance of the source to generate a modified RF signal 170 at the output 142. The modified RF signal 170 is sent via the RF transmission line 144 to the lower electrode to process the substrate S. When the modified RF signal 170 is supplied to the lower electrode and the one or more process gases are supplied to the gap 105, first, second, third, fourth, fifth, and sixth intensity signals are generated by the PRMDs 114, 116, and 118 in a manner described below with reference to Figure 2C-1. Based on the first through sixth intensity signals, the processor 120 determines a second process rate uniformity in a manner described below with reference to Figure 2C-2.

[0043] When the modified RF signal 170 is applied to the lower electrode, the substrate S is processed at a uniform process rate, such as a uniform etch rate or a uniform deposition rate or a combination thereof. For example, although power delivered to the plasma chamber 110 decreases when the modified RF signal 170 is supplied to the plasma chamber 110 compared to when the modified RF signal 160 is supplied to the plasma chamber 110, uniformity in a rate of processing the substrate S is achieved, such as increased. To illustrate, the second process rate uniformity is greater than the first process rate uniformity. As an example, power delivered from the HF RF generator 106 is a difference between power that is supplied from the HF RF generator 106 and power that is reflected towards the HF RF generator 106 from the plasma chamber 110. The power is supplied from the output 126 of the HF RF generator 106 via the RF cable 138, the match 108, and the RF transmission line 148 to the lower electrode. The power is reflected from the plasma chamber 110 via the RF transmission line 144, the match 108, and the RF cable 138 to the HF RF generator 106.

[0044] In one embodiment, the RF signal 168 is generated for multiple instances, such as a first instance and a second instance. Before generating the RF signal 168 during the second instance and after processing the substrate S with the RF signal 158B and the RF signal 168 generated during the first instance, the substrate S is replaced with another substrate. An example of the other substrate is a semiconductor wafer on which one or more integrated circuits are to be fabricated. The other substrate is placed on the top surface of the electrostatic chuck 101 within the plasma chamber 110.

[0045] In one embodiment, the power sensor 124 is located outside the HF RF generator 106 instead of being located within an enclosure, such as a body or a container, of the HF RF generator 106.

[0046] In an embodiment, instead of substrate S, a dummy substrate, such as a substrate on which an integrated circuit is not to be formed or a substrate made from glass, is used.

[0047] In an embodiment, the processor 120 is coupled to the RF generators 104 and 106 via a single transfer cable.

[0048] In one embodiment, the voltage sensor 112 is coupled at any point on the RF transmission line 144.

[0049] In an embodiment, the terms recipe set and recipe signal are used herein interchangeably.

[0050] In one embodiment, the terms control and regulate are used herein interchangeably and the terms controlling and regulating are used herein interchangeably.

[0051] In one embodiment, instead of the process rate measurement devices 114, 116, and 118, another type of sensors, such as photodiodes or temperature sensors or B-dot probes,are used to generate the intensity signals 164A through 164F or the first through sixth intensity signals. For example, the temperature sensors measure temperature at the central region 152 and the edge regions 148 and 156 of the substrate S to generate the intensity signals 164A through 164F or the first through sixth intensity signals. As another example, the photodiodes measure intensities of light emitted from the plasma proximate to the regions 152, 140, and 156 to generate the intensity signals 164A through 164F or the first through sixth intensity signals. As yet another example, the B-dot probes measure magnitudes of magnetic fields affected by the plasma formed within the plasma chamber 110 to generate the intensity signals 164A through 164F or the first through sixth intensity signals.

[0052] Figure 2A is an embodiment of a graph 200 to illustrate cycles n and n+1 of the measurement voltage signal 162 or of the RF signal 158A (Figure 1). The graph 200 includes a plot 202 of a logic level on a y-axis versus time t on an x-axis. An example of the logic level is a voltage level. The plot 202 is an example of the clock signal. To illustrate, the clock signal is generated by the processor 120 (Figure 1) and sent via the transfer cables 128 and 130 (Figure 1) to the RF generators 104 and 106 (Figure 1) to synchronize operation of the RF generators 104 and 106. Also, functions, described herein, as being performed by the processor 120 are synchronized with the clock signal.

[0053] The plot 202 has a logic level of 5, such as 5 volts, from a time tO to a time tlO. It should be noted that times tl, t2, t3, t4, t5, t6, t7, t8, and t9 occur between the times tO and tlO. For example, the times tO through tlO occur in a progressively and consecutively increasing manner. The plot 202 transitions from the logic level 5 to a logic level 0, such as zero volts, at the time tlO. The plot 202 has the logic level of 0 from the time tlO to a time t20. It should be noted that times ti l, tl2, tl3, tl4, tl5, tl6, tl7, tl8, and tl9 occur between the times tlO and t20. For example, the times tlO through t20 occur in a progressively and consecutively increasing manner. The cycle n of the plot 202 occurs from the time tO to the time tlO.

[0054] The plot 202 repeats the cycle n for a second time to form the cycle n+1. For example, the plot 202 transitions from the logic level 0 back to the logic level 5 at the time t20. The plot 202 has the logic level of 5 from the time t20 to a time t30. It should be noted that times t21, t22, t23, t24, t25, t26, t27, t28, and t29 occur between the times t20 and t30. For example, the times t20 through t30 occur in a progressively and consecutively increasing manner. The plot 202 transitions from the logic level 5 to the logic level 0 at the time t30. The cycle n+1 of the plot 202 occurs from the time t20 to a time t40.

[0055] It should be noted that a time interval between any two consecutive times illustrated on the x-axis of the graph 200 is the same. For example, a first time interval betweenthe times tO and tl is equal to a second time interval between the times tl and t2, and the second time interval is equal to a third time interval between the times t2 and t3.

[0056] Figure 2B is an embodiment of a graph 220 to illustrate a measurement voltage signal 222. The measurement voltage signal 222 is a sinusoidal RF signal. The measurement voltage signal 222 is an example of the measurement voltage signal 162 (Figure 1). The graph 220 plots a voltage of the measurement voltage signal 222 on a y-axis and the time t on an x- axis. For example, the x-axis of the graph 220 is the same as the x-axis of the graph 200 (Figure 2A).

[0057] The processor 120 (Figure 1) receives the measurement voltage signal 222 and divides each cycle, such as any of the cycles n and n+1, of the measurement voltage signal 222 into a predetermined number of bins, such as m number of bins, where m is an integer greater than one. As an example, m is equal to 20. As another example, m is equal to 10 or 30. To illustrate, the processor 120 divides each cycle, such as the cycle n and the cycle n+1, of the measurement voltage signal 222 into ten bins 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10. The bin 1 is a time interval from the time tO to the time t2, the bin 2 is a time interval from the time t2 to the time t4, the bin 3 is a time interval from the time t4 to the time t6, the bin 4 is a time interval from the time t6 to the time t8, and the bin 5 is a time interval from the time t8 to the time tlO. The bin 5 is sometimes referred to herein as a bin 0. The bin 6 is a time interval from the time tlO to the time tl2, the bin 7 is a time interval from the time tl2 to the time tl4, the bin 8 is a time interval from the time tl4 to the time tl6, the bin 9 is a time interval from the time tl6 to the time tl 8, and the bin 10 is a time interval from the time tl 8 to the time t20.

[0058] It should be noted that the bins 1 through 10 that repeat during each cycle of the measurement voltage signal 222 are equally spaced time intervals. For example, the bin 1 has a time interval that is equal to a time interval of the bin 2 or the bin 3 or the bin 4 and so on until the bin 10.

[0059] It should also be noted that a first bin of a cycle of the LF RF signal 158A (Figure 1) or the voltage measurement signal 222 is adjacent to, such as contiguous with, a second bin of the cycle when there are no bins between the first and second bins. When there is at least one bin between the first and second bins, the first and second bins of the cycle are not contiguous. For example, the bin 1 of the cycle n is next to, such as adjacent to, the bin 2 of the cycle n and the bin 2 of the cycle n is next to, such as adjacent to, the bin 3 of the cycle n. To illustrate, the bin 2 of the cycle n is consecutive to the bin 1 of the cycle n and the bin 3 of the cycle n is consecutive to the bin 2 of the cycle n. Also, the bin 3 of the cycle n is not contiguous with the bin 1 of the cycle n when the bins 1 and 3 are separated by the bin 2 of the cycle n.

[0060] The measurement voltage signal 222 has positive voltage values from the time tO to the time t9 and transitions at the time t9 from the positive voltage values to negative voltage values. The time t9 is a time of occurrence of a negative zero crossing of the measurement voltage signal 222. The measurement voltage signal 222 has the negative voltage values from the time t9 to the time tl9 and transitions at the time tl9 from the negative voltage values to positive voltage values. The time tl9 is a time of occurrence of a positive zero crossing of the measurement voltage signal 222. In this manner, the measurement voltage signal 222 repeats the cycle n+1 from the time t20 to the time t40.

[0061] It should be noted that a bin occurs once during each cycle of the measurement voltage signal 222 or the clock signal. For example, the bin 1 occurs once during the cycle n, occurs once again during a cycle (n+t-q), and occurs once again during the cycle (n+t), where q is an integer, and the cycle (n+t-q) occurs after the cycle n but before the cycle (n+t). In the example, the occurrence of the bin 1 during the cycle n is a first occurrence of the bin 1, the occurrence of the bin 1 during the cycle (n+t-q) is a second occurrence of the bin 1, and the occurrence of the bin 1 during the cycle (n+t) is a third occurrence of the bin 1. As another example, the bin 2 occurs once during the cycle n, occurs once again during the cycle (n+t-q), and occurs once again during the cycle (n+t). In the example, the occurrence of the bin 2 during the cycle n is a first occurrence of the bin 1, the occurrence of the bin 2 during the cycle (n+t-q) is a second occurrence of the bin 2, and the occurrence of the bin 2 during the cycle (n+t) is a third occurrence of the bin 2.

[0062] Figure 2C-1 is an embodiment of a graph 230 to illustrate power that is delivered by the HF RF generator 106 (Figure 1) at the output 126 (Figure 1) during each bin of each cycle of the measurement voltage signal 222 (Figure 2B) or the clock signal or the RF signal 158A (Figure 1). The graph 230 includes a plot 232 of the delivered power of the RF signal 168 (Figure 1) output from the HF RF generator 106 on a y-axis and the time t on an x-axis. The x- axis of the graph 230 is the same as the x-axis of the graph 200 (Figure 2A).

[0063] The y-axis of the graph 230 plots power levels P0, Pl, P2, P3, and P4 in an increasing order. For example, the power level Pl is greater than the power level P0. Also, the power level P2 is greater than the power level Pl, the power level P3 is greater than the power level P2, and the power level P4 is greater than the power level P3. The power level P0 is a power level of the predetermined amount. To illustrate, the power level P0 is zero watts. As yet another illustration, the power level P0 is less than 0 watts. To further illustrate, the power level P0 is less than 0 W and greater than -4000 watts. As another further illustration, the power level P0 is a value less than 0 watts and greater than -5000 watts.

[0064] The delivered power of the RF signal 168 has the power level P4 during the bins 1 and 2 of the cycle n, and transitions from the power level P4 to the power level P0 at the time t4. A power level during a bin represents one or more values of delivered power during a time interval of the bin. For example, the power level P4 during the bin l is a statistical value, such as an average or median, of values of delivered power of the RF signal 168 during the bin 1.

[0065] The delivered power of the RF signal 168 has the power level P0 during the bins 3 and 4 of the cycle n, and transitions from the power level P0 to the power level P4 at the time t8. The delivered power of the RF signal 168 has the power level P4 during the bins 5 through 10 of the cycle n. In the same manner, the power levels P4 and P0 repeat during the bins of following cycles, such as the cycle n+1 or the cycle n+t, of the measurement voltage signal 222. When the power levels, P4 and P0, repeat during each cycle of the measurement voltage signal 222, the RF signal 168 is the continuous wave RF signal.

[0066] It should be noted that the power levels P0 and P4 are examples of the delivered power levels of the RF signal 168. Also, identities of the bins 1 through 10 during each cycle of the LF RF signal 158A (Figure 1) or the measurement voltage signal 222 or the clock signal during which the power levels P0 and P4 are to be maintained are provided as information within the modified recipe set 166 (Figure 1) from the processor 120 to the HF RF generator 106. To illustrate, an identity of a bin is a time interval within a duration of a cycle of the measurement voltage signal 222 or the LF RF signal 158A or the clock signal.

[0067] Figure 2C-2 is an embodiment of a graph 250 to illustrate power that is delivered by the HF RF generator 106 (Figure 1) at the output 126 (Figure 1) during each bin of each cycle of the measurement voltage signal 222 (Figure 2B) or the clock signal or the RF signal 158A (Figure 1). The graph 240 includes a plot 252 of the delivered power of the RF signal 158B (Figure 1) output from the HF RF generator 106 on a y-axis and the time t on an x-axis. The x- axis of the graph 250 is the same as the x-axis of the graph 200 (Figure 2A).

[0068] The y-axis of the graph 250 plots power levels P0, Pl, P2, P3, and P4 in the increasing order. The delivered power of the RF signal 158B has the power level P4 during the bins 1 through 5 of the cycle n, and transitions from the power level P4 to the power level P0 at the time tlO. The delivered power of the RF signal 158B has the power level P0 during the bins 6 and 7 of the cycle n, and transitions from the power level P0 to the power level P4 at the time tl4. The delivered power of the RF signal 158B has the power level P4 during the bins 8 through 10 of the cycle n. In the same manner, the power levels P4 and P0 repeat during the bins of following cycles, such as the cycle n+1 or the cycle n+t, of the measurement voltage signal 222. When the power levels, P4 and P0, repeat during each cycle of the measurement voltage signal 222, the RF signal 158B is the continuous wave RF signal.

[0069] It should be noted that the power levels P0 and P4 are examples of the delivered power levels of the RF signal 158B. Also, identities of the bins 1 through 10 during each cycle of the LF RF signal 158A (Figure 1) or the measurement voltage signal 222 or the clock signal during which the power levels P0 and P4 are to be maintained are provided as information within the recipe set 156B (Figure 1) from the processor 120 to the HF RF generator 106.

[0070] With reference to Figures 2C-1 and 2C-2, the power level of P0 during the bins 3 and 4 of each cycle of the LF RF signal 158 A or the measurement voltage signal 222 or the clock signal achieves the increase in the process rate uniformity compared that achieved with the power level of P0 during the bins 6 and 7 of the cycle. For example, with reference to Figure 2C- 2, the recipe set 156B (Figure 1) includes an indication that the power level P4 of the RF signal 158B be output during the bins 1 through 5 of each cycle of the LF RF signal 158 A, the power level P0 of the RF signal 158B be output during the bins 6 and 7 of each cycle of the LF RF signal 158 A, and the power level P4 of the RF signal 158B be output during the bins 8 through 10 of each cycle of the LF RF signal 158A. To illustrate, the recipe set 156B includes an indication that the power level P4 of the RF signal 158B be output during an occurrence of the bins 1 through 5 of a cycle of the LF RF signal 158A, the power level P0 of the RF signal 158B be output during an occurrence of the bins 6 and 7 of the cycle of the LF RF signal 158A, and the power level P4 of the RF signal 158B be output during an occurrence of the bins 8 through 10 of the cycle of the LF RF signal 158A. Also, identities of the bins 1 through 10 during each cycle of the LF RF signal 158A (Figure 1) or the measurement voltage signal 222 during which the power level P4 and the power level P0 are to be maintained are provided as information within the recipe set 156B from the processor 120 to the HF RF generator 106.

[0071] Continuing with the example, during a time period in which the RF signal 158B (Figure 1) generated based on the recipe set 156B is being supplied by the HF RF generator 106, the processor 120 receives the intensity signals 164A through 164F and determines the first process rate uniformity from the intensity signals 164A through 164F. To illustrate, the processor 120 receives the intensity signal 164A at a first primary time from the PRMD 114 (Figure 1) and the intensity signal 164B at a second primary time from the PRMD 114 and calculates a process rate at the left edge region 148 (Figure 1) from the intensity signals 164A and 164B and the first and second primary times. The second primary time occurs after the first primary time. The processor 120 calculates the process rate at the left edge region 148 to be a ratio of a first primary difference and a second primary difference. The processor 120 calculates the first primary difference to be a difference between an intensity value indicated within the intensity signal 164B and an intensity value indicated within the intensity signal 164A. Also, the processor 120 calculates the second primary difference to be a difference between the secondand first primary times. In the illustration, the second primary time occurs after the first primary time.

[0072] Continuing with the example, the processor 120 receives the intensity signal 164C at the first primary time from the PRMD 116 (Figure 1) and the intensity signal 164D at the second primary time from the PRMD 116 and calculates a process rate at the central region 152 (Figure 1) from the intensity signals 164C and 164D and the first and second primary times. To illustrate, the processor 120 calculates the process rate at the central region 152 to be a ratio of a third primary difference and the second primary difference. The processor 120 calculates the third primary difference to be a difference between an intensity value indicated within the intensity signal 164D and an intensity value indicated within the intensity signal 164C.

[0073] Moreover, in the example, the processor 120 receives the intensity signal 164E at the first primary time from the PRMD 118 (Figure 1) and the intensity signal 164F at the second primary time from the PRMD 118 and calculates a process rate at the right edge region 156 (Figure 1) from the intensity signals 164E and 164F and the first and second primary times. To illustrate, the processor 120 calculates the process rate at the right edge region 156 to be a ratio of a fourth primary difference and the second primary difference. The processor 120 calculates the fourth primary difference to be a difference between an intensity value indicated within the intensity signal 164F and an intensity value indicated within the intensity signal 164E.

[0074] In the example, the processor 120 determines the first process rate uniformity from the process rates at the left edge region 148, the central region 152, and the right edge region 156. To illustrate, the processor 120 determines that a combination of the process rate at the left edge region 148, the process rate at the central region 152, and the process rate at the right edge region 156 is the first process rate uniformity.

[0075] Continuing with the example, with reference to Figure 2C-1, the recipe set 166 (Figure 1) includes an indication that the power level P4 of the RF signal 168 be output during the bins 1 and 2 of each cycle of the LF RF signal 158 A, the power level P0 of the RF signal 168 be output during the bins 3 and 4 of each cycle of the LF RF signal 158A, and the power level P4 of the RF signal 168 be output during the bins 5 through 10 of each cycle of the LF RF signal 158A. To illustrate, the recipe set 166 includes an indication that the power level P4 of the RF signal 168 be output during an occurrence of the bins 1 and 2 of a cycle of the LF RF signal 158 A, the power level P0 of the RF signal 168 be output during an occurrence of the bins 3 and 4 of the cycle of the LF RF signal 158 A, and the power level P4 of the RF signal 168 be output during an occurrence of the bins 5 through 10 of the cycle of the LF RF signal 158 A.

[0076] Further, in the example, during a time period in which the RF signal 168 generated based on the recipe set 166 is being supplied by the HF RF generator 106, theprocessor 120 receives the first through sixth intensity signals from the PRMDs 114, 116, and 118 and determines a second process rate uniformity from the intensity signals. The processor 120 receives the first intensity signal at a first secondary time from the PRMD 114 and the second intensity signal at a second secondary time from the PRMD 114 and calculates a process rate at the left edge region 148 from the first and second intensity signals and the first and second secondary times. The second secondary time occurs after the first secondary time. To illustrate, the processor 120 calculates the process rate at the left edge region 148 to be a ratio of a first secondary difference and a second secondary difference. The processor 120 calculates the first secondary difference to be a difference between an intensity value indicated within the second intensity signal and an intensity value indicated within the first intensity signal. Also, the processor 120 calculates the second secondary difference to be a difference between the second and first secondary times. In the illustration, the second secondary time occurs after the first secondary time.

[0077] Continuing with the example, the processor 120 receives the third intensity signal at the first secondary time from the PRMD 116 and the fourth intensity signal at the second secondary time from the PRMD 116 and calculates a process rate at the central region 152 from the third and fourth intensity signals and the first and second primary times. To illustrate, the processor 120 calculates the process rate at the central region 152 to be a ratio of a third secondary difference and the second secondary difference. The processor 120 calculates the third secondary difference to be a difference between an intensity value indicated within the fourth intensity signal and an intensity value indicated within the third intensity signal.

[0078] Moreover, in the example, the processor 120 receives the fifth intensity signal at the first secondary time from the PRMD 118 and a sixth intensity signal at the second secondary time from the PRMD 118 and calculates a process rate at the right edge region 156 from the fifth and sixth intensity signals and the first and second secondary times. To illustrate, the processor 120 calculates the process rate at the right edge region 156 to be a ratio of a fourth secondary difference and the second secondary difference. The processor 120 calculates the fourth secondary difference to be a difference between an intensity value indicated within the sixth intensity signal and an intensity value indicated within the fifth intensity signal.

[0079] In the example, the processor 120 determines the second process rate uniformity from the process rates at the left edge region 148, the central region 152, and the right edge region 156. The process rates are determined based on the first through sixth intensity signals. To illustrate, the processor 120 determines that a combination of the process rate, at the left edge region 148, calculated based on the first and second intensity signals, the process rate, at the central region 152, calculated based on the third and fourth intensity signals, and the processrate, at the right edge region 156, calculated based on the fifth and sixth intensity signals is the second process rate uniformity.

[0080] The processor 120 further determines whether the second process rate uniformity is greater than the first process rate uniformity. To illustrate, the processor 120 determines whether a first difference between the process rate at the left edge region 148 used to calculate the second process rate uniformity and the process rate at the central region 152 used to calculate the second process rate uniformity is less than a second difference. The second difference is between the process rate at the left edge region 148 used to calculate the first process rate uniformity and the process rate at the central region 152 used to calculate the first process rate uniformity. The first and second differences are calculated by the processor 120. The processor 120 further determines whether a third difference between the process rate at the right edge region 156 used to calculate the second process rate uniformity and the process rate at the central region 152 used to calculate the second process rate uniformity is less than a fourth difference. The fourth difference is between the process rate at the right edge region 156 used to calculate the first process rate uniformity and the process rate at the central region 152 used to calculate the first process rate uniformity. The third and fourth differences are calculated by the processor 120. Upon determining that the first difference is less than the second difference and the third difference is less than the fourth difference, the processor 120 determines that the second process rate uniformity is greater than the first process rate uniformity.

[0081] In response to determining that the second process rate uniformity is greater than the first process rate uniformity, the processor 120 determines to control the HF RF generator 106 based on the modified recipe set 166 instead of the recipe set 156B. The HF RF generator 106 is controlled based on the modified recipe set 166 to apply the modified recipe set 166. For example, to process the substrate S, the processor 120 sends the modified recipe set 166 to the HF RF generator 106 for generating the RF signal 168. To illustrate, when the substrate S is processed, the recipe set 166 includes an indication that the power level P4 of the RF signal 168 be output during an occurrence of the bins 1 and 2 of a cycle of the LF RF signal 158A, the power level P0 of the RF signal 168 be output during an occurrence of the bins 3 and 4 of the cycle of the LF RF signal 158A, and the power level P4 of the RF signal 168 be output during an occurrence of the bins 5 through 10 of the cycle of the LF RF signal 158 A. As another illustration, when the substrate S is replaced with the other substrate in the plasma chamber 110, the processor 120 sends the modified recipe set 166 to the HF RF generator 106 for generating the RF signal 168. To further illustrate, when the substrate S is replaced with the other substrate, the recipe set 166 includes an indication that the power level P4 of the RF signal 168 be output during an occurrence of the bins 1 and 2 of a cycle of the LF RF signal 158A, the power level P0of the RF signal 168 be output during an occurrence of the bins 3 and 4 of the cycle of the LF RF signal 158 A, and the power level P4 of the RF signal 168 be output during an occurrence of the bins 5 through 10 of the cycle of the LF RF signal 158A. The RF signal 168 is supplied to process the other substrate.

[0082] It should be noted that when the modified recipe set 166 is provided to the HF RF generator 106, by the processor 120, based on the power levels P4, P0, and P4 during the bins 1 through 10 occurring in a time period of each cycle, such as the cycle (n+t), of the RF signal 158 A, there is a decrease in power that is delivered from the HF RF generator 106 to the plasma chamber 110. The power that is delivered decreases compared to an amount of power that is delivered when the recipe set 156B is provided to the HF RF generator 106 by the processor 120. The modified recipe set 166 includes the power information indicating to apply the power levels P4 and P0 during the bins 1 through 10, as illustrated, in Figure 2C-1, within each cycle, such as the cycle n, of the RF signal 158A. The recipe set 156B includes the power information indicating to apply the power levels P4 and P0 during the bins 1 through 10, as illustrated, in Figure 2C-2, within each cycle, such as the cycle n, of the RF signal 158A. Although during the application of the modified recipe set 166, there is a decrease in the delivered power at the output 126, there is an increase in process rate uniformity from the first process rate uniformity to the second process rate uniformity. As such, a process benefit of the increase in the process rate uniformity is achieved.

[0083] In one embodiment, the processor 120 indicates within the recipe set 166 that the power level P0 is to be achieved during one or more bins of each cycle of the LF RF signal 158A. For example, the processor 120 indicates that the power level P0 be achieved during the bins 5 and 6 instead of during the bins 3 and 4. As another example, the processor 120 indicates that the power level P0 be achieved during the bins 1 and 3 instead of during the bins 3 and 4. As yet another example, the processor 120 indicates that the power level P0 be achieved during the bin 4 only instead of during the bins 3 and 4.

[0084] In an embodiment, with reference to Figure 2C-1, instead of controlling the HF RF generator 106 to achieve the power level of P0 during the bins 3 and 4, the processor 120 controls the HF RF generator 106 to achieve the power level P0 during the bin 3 or the bin 4. For example, the processor 120 controls the HF RF generator 106 to achieve the power level P0 during the bin 3 and the power level P4 during the bin 4. To illustrate, the processor 120 includes, within the recipe set 166, an indication that the RF signal 158B have the power level P0 during the bin 3 and have the power level P4 during the bin 4. As another example, the processor 120 controls the HF RF generator 106 to maintain the power level P4 during the bin 3 and achieve the power level P0 during the bin 4. The second process rate uniformity isdetermined in the same manner as that described above even when the RF generator 106 is controlled to achieve the power level P0 during the bin 3 or the bin 4.

[0085] In an embodiment, with reference to Figure 2C-2, instead of controlling the HF RF generator 106 to achieve the power level of P0 during the bins 6 and 7, the processor 120 controls the HF RF generator 106 to achieve the power level P0 during the bin 6 or the bin 7. For example, the processor 120 controls the HF RF generator 106 to achieve the power level P0 during the bin 6 and the power level P4 during the bin 7. To illustrate, the processor 120 includes, within the recipe set 166, an indication that the RF signal 158B have the power level P0 during the bin 6 and have the power level P4 during the bin 7. As another example, the processor 120 controls the HF RF generator 106 to maintain the power level P4 during the bin 6 and achieve the power level P0 during the bin 7. The first process rate uniformity is determined in the same manner as that described above even when the RF generator 106 is controlled to achieve the power level P0 during the bin 6 or the bin 7.

[0086] In an embodiment, the first process rate uniformity is achieved when power delivered by the HF RF generator 106 is controlled to have the value P0 during one or more of the bins 1 through 10. The second process rate uniformity is achieved when power delivered by the HF RF generator 106 is controlled to have the value P0 during one or more of the bins 1 through 10. The one or more bins from the bins 1 through 10 for which the first process rate uniformity is achieved is different from the one or more bins from the bins 1 through 10 for which the second process rate uniformity is achieved. For example, the first process rate uniformity is achieved when power delivered by the HF RF generator 106 is controlled to have the value P0 during the bins 1 and 2 or the bins 8 and 9. The second process rate uniformity is achieved when power delivered by the HF RF generator 106 is controlled to have the value P0 during the bins 6 and 7.

[0087] Figure 3 is an embodiment of a graph 300 to illustrate multiple states of pulsing of power of an HF multistate signal, which is an example of the RF signal 168, that is generated by the HF RF generator 106 (Figure 1). The graph 300 includes a plot 302 of power levels, such as power levels P0, Pl, P2, P3, and P4, of delivered power of the HF multistate signal on a y- axis and the time t on an x-axis. To illustrate, each of the power levels Pl and P4 can be a zero- to-peak power value of the HF multistate signal. The x-axis of the graph 300 is the same as the x-axis of the graph 200 (Figure 2A).

[0088] The HF multistate signal has the same power levels as those illustrated in the plot 232 (Figure 2C-1) from the time tO to the time t20. The power levels P4 and P0 of the HF multistate signal from the time tO to the time t20 represent a state SI of the delivered power of the HF multistate signal. At the time t20, the HF multistate signal transitions from the state SI toa state S2. For example, at the time t20, the HF multistate signal transitions from the power level P4 to the power level Pl. During the state S2 of the HF multistate signal, the HF multistate signal has the power level Pl from the time t20 to the time t30. A time period from the time t20 to the time t30 is of an occurrence of the bins 1 through 5. At the time t30, the HF multi state signal transitions from the power level Pl to the power level P0 and remains at the power level P0 from the time t30 to the time t34. A time period from the time t30 to the time t34 is of an occurrence of the bins 6 and 7. At the time t34, the HF multi state signal transitions from the power level P0 to the power level Pl. The HF multistate signal remains of the power level Pl from the time t34 to the time t40. A time period from the time t34 to the time t40 is of an occurrence of the bins 8 through 10. The power levels Pl and P0 of the HF multistate signal from the time t20 to the time t40 represent the state S2 of the delivered power of the HF multi state signal.

[0089] It should be noted that for a majority of time interval from the time tO to the time t20, the HF multistate signal has the power level P4 of the state SI. Moreover, during a majority of a time interval from the time t20 to the time t40, the HF multistate signal has the power level Pl of the state S2. Because the power level P4 of the state SI is greater than the power level Pl of the state S2, the state SI is sometimes referred to herein as a high state and the state S2 is sometimes referred to herein as a low state.

[0090] It should further be noted that when the state of the delivered power of the HF multistate signal is SI, the power level is P0 during a first set of one or more bins within a cycle of the measurement voltage signal 222 (Figure 2A). When the state of the delivered power of the HF multistate signal is S2, the power level is P0 during a second set of one or more bins within a cycle of the measurement voltage signal 222. As an example, one or more bins of the first set are different than the one or more bins of the second set. To illustrate, when the state of the delivered power of the HF multistate signal is SI, the power level is P0 during an occurrence of the bins 3 and 4. Also in the example, when the state of the delivered power of the HF multistate signal is S2, the power level is P0 during an occurrence of the bins 6 and 7. As another example, the one or more bins of the first set are the same as the one or more bins of the second set. To illustrate, when the state of the delivered power of the HF multistate signal is SI, the power level is P0 during an occurrence of the bins 3 and 4. Also in the example, when the state of the delivered power of the HF multistate signal is S2, the power level is P0 during an occurrence of the bins 3 and 4.

[0091] It should be noted that the bins 6 and 7 of the state S2 during which the power level P0 is to be achieved are determined in the same manner in which the bins 3 and 4 of the state SI during which the power level P0 is to be achieved are determined. For example, duringthe bins 6 and 7 of the state S2 occurring within a cycle (n+t+1) of the RF signal 158 A, the power level PO is applied in response to a determination, by the processor 120, that a process rate uniformity is achieved, such as increased. The process rate uniformity is increased compared to a process rate uniformity that is achieved when the power level PO is applied by the HF RF generator 106 during the bins 8 and 9 of the state S2 occurring within the cycle (n+1) of the RF signal 158A, The cycle (n+1) of the RF signal 158A occurs before the cycle (n+t+1) of the RF signal 158 A.

[0092] In one embodiment, instead of having the two states SI and S2, the delivered power of the HF multistate signal has more than two states. For example, the delivered power of the HF multistate signal has three states or four states or five states or any other number of states, such as ten.

[0093] In an embodiment, an LF multistate signal, which is an example of the RF signal 158A (Figure 1), is synchronized in conjunction with the HF multistate signal. For example, when the HF multi state signal has the state SI, such as the high state, the LF multi state signal has a high state. On the other hand, when the HF multi state signal has the state S2, such as the low state, the LF multistate signal has a low state. Moreover, at a time at which the LF multistate signal transitions from the high state to the low state, the HF multistate signal transitions from the high state to the low state to synchronize the transition of the LF multistate signal with the transition of the HF multistate signal. Also, at a time at which the LF multistate signal transitions from the low state to the high state, the HF multistate signal transitions from the low state to the high state to synchronize the transition of the LF multistate signal with the transition of the HF multi state signal. The high state of the LF multi state signal has a power value, such as a zero-to- peak power value, that is greater than a power value, such as a zero-to-peak power value, of the low state of the LF multistate signal.

[0094] Figure 4 is a diagram of an embodiment of a system 400 to illustrate details of an HF RF generator 402. The HF RF generator 402 is an example of the HF RF generator 106 (Figure 1). The system 400 includes the host computer 102 and the HF RF generator 402. The HF RF generator 402 includes a digital signal processor (DSP) 404, the driver and amplifier circuit 406, an RF power supply 401, and multiple delivered power controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml, where p is a number of states of delivered power of an RF signal 408 that is output from the HF RF generator 402, and ml is the predetermined number of bins. It should be noted that a number of delivered power controllers for each state is equal to the predetermined number bins. For example, there are ml controllers for ml bins. As an example, a controller includes a processor and a memory device. The processor of the controller is coupled to the memory device of the controller. An example of the RF powersupply 401 is an RF oscillator that produces periodic oscillating signals, such as sinusoidal waveforms.

[0095] The processor 120 is coupled via the transfer cable 130 to the DSP 404. The driver and amplifier circuit 406 is coupled to the RF power supply 401. The DSP 404 is coupled to the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml. The controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml are coupled to the driver and amplifier circuit 406. The RF power supply 401 is coupled at the output 126 to the RF cable 138. The power sensor 124 is coupled to the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml.

[0096] The processor 120 receives the measurement voltage signal 162 via the transfer cable 115 from the voltage sensor 112 and identifies each cycle of the measurement voltage signal 162. For example, the processor 120 identifies a first positive zero crossing of the measurement voltage signal 162 and a second positive zero crossing of the measurement voltage signal 162. The first positive zero crossing precedes the second positive zero crossing. The processor 120 determines a time interval, such as a time period, between the first and second positive zero crossings to be a cycle of the measurement voltage signal 162.

[0097] The processor 120 divides each cycle of the measurement voltage signal 162 into the predetermined number, such as the m or ml, of bins. For each bin of the predetermined number, the processor 120 assigns a delivered power value to the bin to generate a recipe set 410. For example, the processor 120 assigns a first delivered power level of the recipe set 156B (Figure 1) to a first bin of the predetermined number of bins of each cycle and assigns a second delivered power level of the recipe set 156B to a second bin of the predetermined number of bins of each cycle. As an instance, the power levels P4 and P0 are assigned to the bins 1 through 10 according to identities of the bins 1 through 10 received within the recipe set 156B from the user via the input device. As another illustration, with reference to Figure 2C-2 and 3, the processor 120 assigns the power level P4 to the bins 1 through 5, the power level P0 to the bins 6 and 7, and the power level P4 to the bins 8 through 10, and designates the power levels P4 and the power level P0 as power levels of the state SI, and the bins of the state SI to generate the recipe set 156B. The processor 120 further indicates, within the recipe set 156B, that the state SI of the RF signal 408 is to be generated during a first cycle of the measurement voltage signal 162. In the illustration, with reference to Figure 3, the processor 120 assigns the power level Pl to the bins 1 through 7, the power level P0 to the bin 8, and the power level Pl to the bins 9 and 10, and designates the power levels Pl and the power level P0 as power levels of the state Sp, and the bins of the state Sp to generate the recipe set 156B. In the illustration, the processor 120 further indicates, within the recipe set 156B, that the state Sp of the RF signal 408 is to begenerated during a second cycle of the measurement voltage signal 162. The first cycle precedes the second cycle. As another illustration, the processor 120 assigns the power level P4 or the power level P0 to each bin of each cycle of the measurement voltage signal 162 without assigning the power levels of the state Sp when the RF signal 408 to be generated is the continuous wave RF signal. In the illustration, the power level P4 or the power level P0 is assigned to each bin of each cycle of the measurement voltage signal 162 to generate the recipe set 156B.

[0098] As another instance, the power levels P4 and P0 are assigned to the bins 1 through 10 according to identities of the bins 1 through 10 received within the recipe set 166 from the user via the input device. As yet another illustration, with reference to Figures 2C-1 and 3, the processor 120 assigns the power level P4 to the bins 1 and 2, the power level P0 to the bins 3 and 4, and the power level P4 to the bins 5 through 10, and designates the power levels P4 and the power level P0 as power levels of the state SI, and the bins of the state SI to generate the recipe set 166 (Figure 1). The processor 120 further indicates, within the recipe set 166, that the state SI of the RF signal 408 is to be generated during a first cycle of the measurement voltage signal 162. In the illustration, with reference to Figure 3, the processor 120 assigns the power level Pl to the bins 1 through 5, the power level P0 to the bins 6 and 7, and the power level Pl to the bins 8 through 10, and designates the power levels Pl and the power level P0 as power levels of the state Sp, and the bins of the state Sp to generate the recipe set 166. In the illustration, the processor 120 further indicates, within the recipe set 166, that the state Sp of the RF signal 408 is to be generated during a second cycle of the measurement voltage signal 162. The first cycle precedes the second cycle. As still another illustration, the processor 120 assigns the power level P4 or the power level P0 to each bin of each cycle of the measurement voltage signal 162 without assigning the power levels of the state Sp when the RF signal 408 to be generated is the continuous wave RF signal. In the illustration, the power level P4 or the power level P0 is assigned to each bin of each cycle of the measurement voltage signal 162 to generate the recipe set 166.

[0099] An example of the recipe set 410 is the recipe set 156B. Another example of the recipe set 410 is the recipe set 166. Also, an example of the RF signal 408 is the RF signal 158B (Figure 1) and another example of the RF signal 408 is the RF signal 168 (Figure 1).

[0100] The processor 120 generates the recipe set 410, and sends the recipe set 410 via the transfer cable 130 to the DSP 404 to control the HF RF generator 402 to generate the RF signal 408 having the power levels for the bins identified within the recipe set 410. Upon receiving the recipe set 410, the DSP 404 identifies each state of the RF signal 408 to be generated. For example, the DSP 404 identifies, from the recipe set 410, the states SI and Sp orthat the RF signal 408 to be generated is the continuous wave signal. Moreover, for each state or for the continuous wave signal, the DSP 404 identifies a time interval of each bin based on the identity of the bin and identifies a power level of delivered power for the bin.

[0101] For the state SI, the DSP 404 provides the power level for each bin to a corresponding one of the controllers DPCSlbinl and DPCSlbinml . Similarly, for the state Sp, the DSP 404 provides the power level for each bin to a corresponding one of the controllers DPCSpbinl and DPCSpbinml. For example, the DSP 404 provides the power level for the bin 1 and for the state SI to the controller DPCSlbinl. Also, in the example, the DSP 404 provides the power level for the bin ml and for the state SI to the controller DPCSlbinml. As another example, the DSP 404 provides the power level for the bin 1 and for the state Sp to the controller DPCSpbinl. Also, in the example, the DSP 404 provides the power level for the bin ml and for the state Sp to the controller DPCSpbinml.

[0102] Each controller DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml stores a corresponding one of the power levels that is received from the DSP 404 within a memory device of the controller. For example, the controller DPCSlbinl stores the power level P4 of the state SI that is to be generated during the bin 1 and the controller DPCSlbinml stores a power level of the state SI that is to be generated during the bin 3.

[0103] Upon receiving the trigger signal from the processor 120 via the transfer cable 130, the DSP 404 controls the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml to generate the RF signal 408 according to the recipe set 410. For example, in response to receiving the trigger signal, the DSP 404 generates and sends an on control signal to the controller DPCSlbinl. In response receiving the on control signal, the controller DPCSlbinl accesses the power level for the bin 1 and for the state SI from the memory device of the controller DPCSlbinl, and generates a control signal indicating an amount of the power level. The controller DPCSlbinl sends the control signal to the driver and amplifier circuit 406. Upon receiving the control signal from the controller DPCSlbinl, the driver and amplifier circuit 406 generates a current signal based on the power level for the bin 1 and the state SI, and sends the current signal to the RF power supply 401. The RF power supply 404 converts the current signal for the bin 1 and the state SI into RF oscillations having the power level of the state SI during the bin 1 to generate the RF signal 408 having the power level of the state SI for the time period of the bin 1.

[0104] Continuing with the example, the DSP 404 determines that the time period of the bin 1 has ended, and upon determining so, generates and sends an off control signal to the controller DPCSlbinl. In response receiving the off control signal, the controller DPCSlbinl stop generating the control signal indicating the power level for the bin 1 and for the state SI.When the control signal indicating the power level for the bin 1 and for the state SI is not received from the controller DPCSlbinl, the driver and amplifier circuit 406 stops generating the current signal based on the power level for the bin 1 and the state SI, and stops sending the current signal to the RF power supply 401. When the current signal for the bin 1 and the state SI is not received from the driver and amplifier circuit 406, the RF power supply 404 stops generating the power level of the state SI during the bin 1 to start transitioning to a power level of the state SI for the time period of the bin ml .

[0105] Further, in the example, at the same time at which it is determined that the time period of the bin 1 has ended, the DSP 404 generates and sends an on control signal to the controller DPCSlbinml. In response receiving the on control signal, the controller DPCSlbinl accesses the power level for the bin ml and for the state SI from the memory device of the controller DPCSlbinl, and generates a control signal indicating an amount of the power level. The controller DPCSlbinml sends the control signal to the driver and amplifier circuit 406. Upon receiving the control signal from the controller DPCSlbinml, the driver and amplifier circuit 406 generates a current signal based on the power level for the bin ml and the state SI, and sends the current signal to the RF power supply 401. The RF power supply 404 converts the current signal for the bin ml and the state SI into RF oscillations having the power level of the state SI during the bin ml to generate the RF signal 408 having the power level of the state SI for the time period of the bin ml .

[0106] In the example, the DSP 404 determines that the time period of the bin ml has ended, and upon determining so, generates and sends an off control signal to the controller DPCSlbinml. In response receiving the off control signal, the controller DPCSlbinml stops generating the control signal indicating the power level for the bin ml and for the state SI. When the control signal indicating the power level for the bin ml and for the state SI is not received from the controller DPCSlbinml, the driver and amplifier circuit 406 stops generating the current signal based on the power level for the bin ml and the state SI, and stops sending the current signal to the RF power supply 401. When the current signal for the bin ml and the state SI is not received from the driver and amplifier circuit 406, the RF power supply 404 stops generating the power level of the state SI during the bin ml to start transitioning to a power level of the state Sp.

[0107] Also, in the example, at the same time at which it is determined that the time period of the bin ml and the time period of the state SI has ended, the DSP 404 generates and sends an on control signal to the controller DPCSpbinl. In response receiving the on control signal, the controller DPCSpbinl accesses the power level for the bin 1 and for the state Sp from the memory device of the controller DPCSpbinl, and generates a control signal indicating anamount of the power level. The controller DPCSpbinl sends the control signal to the driver and amplifier circuit 406. Upon receiving the control signal from the controller DPCSpbinl, the driver and amplifier circuit 406 generates a current signal based on the power level for the bin 1 and the state Sp, and sends the current signal to the RF power supply 401. The RF power supply 404 converts the current signal for the bin 1 and the state Sp into RF oscillations having the power level of the state Sp during the bin 1 to generate the RF signal 408 having the power level of the state Sp for the time period of the bin 1.

[0108] Continuing with the example, the DSP 404 determines that the time period of the bin 1 has ended, and upon determining so, generates and sends an off control signal to the controller DPCSpbinl. In response receiving the off control signal, the controller DPCSpbinl stops generating the control signal indicating the power level for the bin 1 and for the state Sp. When the control signal indicating the power level for the bin 1 and for the state Sp is not received from the controller DPCSpbinl, the driver and amplifier circuit 406 stops generating the current signal based on the power level for the bin 1 and the state Sp, and stops sending the current signal to the RF power supply 401. When the current signal for the bin 1 and the state Sp is not received from the driver and amplifier circuit 406, the RF power supply 404 stops generating the power level of the state Sp during the bin 1 to start transitioning to a power level of the state Sp for the time period of the bin ml .

[0109] Moreover, in the example, at the same time at which it is determined that the time period of the bin 1 has ended, the DSP 404 generates and sends an on control signal to the controller DPCSpbinml. In response receiving the on control signal, the controller DPCSpbinml accesses the power level for the bin ml and for the state Sp from the memory device of the controller DPCSpbinml, and generates a control signal indicating an amount of the power level. The controller DPCSpbinml sends the control signal to the driver and amplifier circuit 406. Upon receiving the control signal from the controller DPCSpbinml, the driver and amplifier circuit 406 generates a current signal based on the power level for the bin ml and the state Sp, and sends the current signal to the RF power supply 401. The RF power supply 404 converts the current signal for the bin ml and the state Sp into RF oscillations having the power level of the state Sp during the bin ml to generate the RF signal 408 having the power level of the state Sp for the time period of the bin ml .

[0110] In the example, the DSP 404 determines that the time period of the bin ml has ended, and upon determining so, generates and sends an off control signal to the controller DPCSpbinml. In response receiving the off control signal, the controller DPCSpbinml stops generating the control signal indicating the power level for the bin ml and for the state Sp. When the control signal indicating the power level for the bin ml and for the state Sp is not receivedfrom the controller DPCSpbinml, the driver and amplifier circuit 406 stops generating the current signal based on the power level for the bin ml and the state Sp, and stops sending the current signal to the RF power supply 401. When the current signal for the bin ml and the state Sp is not received from the driver and amplifier circuit 406, the RF power supply 404 stops generating the power level of the state Sp during the bin ml to start transitioning to another power level.

[0111] It should be noted that in an embodiment, when the power level P0 of the RF signal 408 is to be generated, the driver and amplifier circuit 406 is turned off. For example, after the power level P4 for the bin 2 is generated, the DSP 404 sends the off control signal to the controller DPCSpbinml. In response receiving the off control signal, the controller DPCSpbinml accesses the power level for the bin ml and for the state Sp from the memory device of the controller DPCSpbinml, and generates a control signal indicating an amount of the power level P0. The controller DPCSpbinml sends the control signal to the driver and amplifier circuit 406. Upon receiving the control signal from the controller DPCSpbinml, the driver and amplifier circuit 406 is turned off and does not generate the current signal to achieve the power level P0 for the bin ml and the state Sp, and the current signal is not sent to the RF power supply 401. When the current signal is not received, the RF power supply 404 does not produce RF oscillations for the bin ml and the state Sp to output the power level P0 of the state Sp during the bin ml to generate the RF signal 408.

[0112] It should be further be noted that in an embodiment, for each bin, the power sensor 124 measures an amount of delivered power, such as a power level, at the output 126 to output a power measurement signal and provides the power measurement signal to the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml. Each of the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml determines whether the power measurement signal indicates the amount of delivered power for a bin for which the delivered power is controlled by the controller. For example, the controller DCPSpbinml determines whether the amount of delivered power received within the power measurement signal is received during a time interval of the bin ml. Upon determining so, the controller DCPSpbinml determines that the amount of power delivered is for the bin ml for which the delivered power is controlled by the controller DCPSpbinml. Upon receiving the amount of power delivered for the bin ml, the controller DCPSpbinml compares the amount of power delivered with a preset amount, such as the power level P0 or P4 or Pl, received within the recipe set 410 to be delivered during the bin ml to determine whether to modify the preset amount. In response to determining that the amount of power delivered received within the power measurement signal is within a predetermined range from, such as is equal to, the preset amount, the controllerDCPSpbinml does not control the driver and amplifier circuit 406 to modify the preset amount. On the other hand, in response to determining that the amount of power delivered received within the power measurement signal is outside the predetermined range from the preset amount, the controller DCPSpbinml controls the driver and amplifier circuit 406 to modify the preset amount. For example, the controller DCPSpbinml increases or decreases an amount of current within the on control signal generated by the controller DCPSpbinml to modify the preset amount.

[0113] In one embodiment, any number of delivered power controllers is used. For example, instead of ml number of delivered power controllers for the two or more states of the RF signal 408, a single controller is used.

[0114] In an embodiment, functionality, described herein as being performed by the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml, and the DSP 404 is performed by the DSP 404. In the embodiment, functionality of the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml and the DSP 404 is incorporated within the DSP 404, which is coupled to the driver and amplifier circuit 406. There is no need for the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml.

[0115] In an embodiment, functionality, described herein as being performed by the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml, and the DSP 404 is performed by one of the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml. In the embodiment, functionality of the controllers DPCSlbinl, DPCSlbinml, DPCSpbinl, and DPCSpbinml and the DSP 404 is incorporated within the one of the controllers DPCSlbinl, DPC S 1 binm 1 , DPC Spbin 1 , and DPC Spbinm 1. There i s no need for the D SP 404.

[0116] Figure 5 A is an embodiment of a graph 500 to illustrate etch amounts at which a substrate, such as the substrate S or the other substrate, is etched. The graph 500 plots the etch amounts on a y-axis and a radius of the substrate on an x-axis. The graph 500 includes a plot 502, another plot 504, and yet another plot 506. The plot 502 is generated when there is no selective blanking performed. For example, the plot 502 is generated by the processor 120 (Figure 1) when power delivered from the HF RF generator 106 (Figure 1) is not controlled to have the value P0 during any bin, such as the bins 1 through 10 or bins 0 through 20, of each cycle of the measurement voltage signal 222 (Figure 2B). The bins 1 through 20 are illustrated below with reference to Figure 5B.

[0117] The plot 504 is generated when selective blanking is performed during the bins 1, 2, and 3 from the bins zero through 20. As an example, the plot 504 is generated by the processor 120 when power delivered from the HF RF generator 106 (Figure 1) is controlled to have the value P0 during the bins 1, 2, and 3 of each cycle of the measurement voltage signal222. Moreover, the plot 506 is generated when selective blanking is performed during the bins 8, 9, and 10 from the bins zero through 20. As an example, the plot 506 is generated by the processor 120 when power delivered from the HF RF generator 106 (Figure 1) is controlled to have the value P0 during the bins 8, 9, and 10 of each cycle of the measurement voltage signal 222.

[0118] As illustrated from the plots 504 and 506, the substrate is etched less at a central region, such as the central region 152 (Figure 1) when power delivered from the HF RF generator is blanked during the bins 8 through 10 from the bins zero through 20 compared to when power delivered from the HF RF generator is blanked during the bins 1, 2, and 3 from the bins zero through 20. Also, the substrate is etched less at an edge region, such as the edge region 148 or 152 (Figure 1) when power delivered from the HF RF generator is blanked during the bins 8 through 10 from the bins zero through 20 compared to when power delivered from the HF RF generator is blanked during the bins 1, 2, and 3 from the bins zero through 20. As such, by modifying bins during which the power delivered from the HF RF generator 106 is controlled to have the value P0, uniformity in etching the substrate is controlled.

[0119] Figure 5B is an embodiment of a graph 520 to illustrate the 20 bins. The graph 520 plots voltage on a y-axis and the time t on an x-axis. The graph 520 includes a plot 522 of a measurement voltage signal that is received from the voltage sensor 112 (Figure 1). The processor 120 receives the measurement voltage signal from the voltage sensor 112 and divides the measurement voltage signal into the 20 bins.

[0120] Figure 5C is an embodiment of a graph 530 to illustrate that split blanking is used to control etch rate uniformity. The graph 530 plots etch amounts at which the substrate is etched on a y-axis and the radius of the substrate on an x-axis. The graph 530 includes a plot 532, a plot 534, and a plot 536. The plot 534 is generated when selective blanking is performed during the bins 8, 9, and 15 from the bins zero through 20. As an example, the plot 534 is generated by the processor 120 (Figure 1) when power delivered from the HF RF generator 106 (Figure 1) is controlled to have the value P0 during the bins 8, 9, and 15 of each cycle of the measurement voltage signal 222 (Figure 2B). The bins 9 and 15 are nonadj acent to each other to achieve the split blanking. To illustrate, there is at least one bin between the bins 9 and 15. Moreover, the plot 536 is generated when selective blanking is performed during the bins 9, 14, and 15 from the bins zero through 20. As an example, the plot 536 is generated by the processor 120 when power delivered from the HF RF generator 106 is controlled to have the value P0 during the bins 9, 14, and 15 of each cycle of the measurement voltage signal 222. The bins 9 and 14 are nonadjacent to each other to achieve the split blanking. To illustrate, there is at least one bins between the bins 9 and 14.

[0121] The plot 532 is generated when selective blanking is performed during the bins 8, 9, 14 and 15 from the bins zero through 20. The selective blanking is performed during the occurrence of the state SI. As an example, the plot 532 is generated by the processor 120 when power delivered from the HF RF generator 106 is controlled to have the value P0 during the bins8, 9, 14 and 15 of the state SI that occurs within a time period of a cycle of the measurement voltage signal 222. Also, the plot 532 is generated when selective blanking is performed during the bins 8 and 9 from the bins zero through 20. The selective blanking is performed during the occurrence of the state Sp. As an example, the plot 532 is generated by the processor 120 when power delivered from the HF RF generator 106 is controlled to have the value P0 during the bins 8 and 9 of the state Sp that occurs within a time period of a cycle of the measurement voltage signal 222.

[0122] As illustrated from the plots 534 and 536, the substrate is etched is a more uniform manner at the central region when power delivered from the HF RF generator is blanked during the bins 8, 9, and 15 from the bins zero through 20 compared to when power delivered from the HF RF generator is blanked during the bins 9, 14, and 15 from the bins zero through 20. Also, the substrate is etched in a similar manner at an edge region, such as the edge region 148 or 152 (Figure 1) when power delivered from the HF RF generator is blanked during the bins 8, 9, and 15 from the bins zero through 20 compared to when power delivered from the HF RF generator is blanked during the bins 9, 14, and 15 from the bins zero through 20. As such, by modifying bins during which the power delivered from the HF RF generator 106 is controlled to have the value P0, uniformity in etching the substrate is controlled.

[0123] Also, as illustrated from the plots 532 and 534, the substrate is etched more in the central region when power delivered from the HF RF generator is blanked during the bins 8,9, 14 and 15 that occur within a time period of the state SI and during the bins 8 and 9 that occur within a time period of the state Sp compared to when power delivered from the HF RF generator is blanked during the bins 8, 9, and 15 from the bins zero through 20. As such, by modifying the HF RF signal 168 (Figure 1) to have the multiple states SI through Sp and selectively blanking the bins during one or more of the states SI through Sp, etch rate uniformity across the substrate is controlled.

[0124] Embodiments, described herein, may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments, described herein, can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a computer network.

[0125] In some embodiments, a controller is part of a system, which may be part of the above-described examples. The system includes semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). The system is integrated with electronics for controlling its operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system. The controller, depending on processing requirements and / or a type of the system, is programmed to control any process disclosed herein, including a delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks connected to or interfaced with the system.

[0126] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as ASICs, PLDs, one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a process on or for a semiconductor wafer. The operational parameters are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0127] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer system, which allows for remote access for wafer processing. The controller enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[0128] In some embodiments, a remote computer (e.g. a server) provides process recipes to the system over a computer network, which includes a local network or the Internet.The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of settings for processing a wafer. It should be understood that the settings are specific to a type of process to be performed on a wafer and a type of tool that the controller interfaces with or controls. Thus as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the fulfilling processes described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at a platform level or as part of a remote computer) that combine to control a process in a chamber.

[0129] Without limitation, in various embodiments, a plasma system, described herein, includes a plasma etch chamber, a deposition chamber, a spin-rinse chamber, a metal plating chamber, a clean chamber, a bevel edge etch chamber, a physical vapor deposition (PVD) chamber, a chemical vapor deposition (CVD) chamber, an atomic layer deposition (ALD) chamber, an atomic layer etch (ALE) chamber, an ion implantation chamber, a track chamber, or any other semiconductor processing chamber that is associated or used in fabrication and / or manufacturing of semiconductor wafers.

[0130] It is further noted that although the above-described operations are described with reference to a parallel plate plasma chamber, e.g., a capacitively-coupled plasma (CCP) chamber, etc., in some embodiments, the above-described operations apply to other types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a transformer coupled plasma (TCP) reactor, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, an X MHz RF generator, a Y MHz RF generator, and a Z MHz RF generator are coupled to an inductor within the ICP plasma chamber.

[0131] As noted above, depending on a process operation to be performed by the tool, the controller communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0132] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored incomputer systems. These computer-implemented operations are those that manipulate physical quantities.

[0133] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[0134] In some embodiments, the operations, described herein, are performed by a computer selectively activated, or are configured by one or more computer programs stored in a computer memory, or are obtained over a computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0135] One or more embodiments, described herein, can also be fabricated as computer- readable code on a non-transitory computer-readable medium. The non-transitory computer- readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter read by a computer system. Examples of the non-transitory computer- readable medium include hard drives, network attached storage (NAS), ROM, RAM, compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non- transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer-readable code is stored and executed in a distributed fashion.

[0136] Although some method operations, described above, were presented in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between the method operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[0137] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[0138] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodimentsare to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims

CLAIMS1. A method for achieving process rate uniformity by identifying one or more bins, comprising: receiving a voltage signal provided from an output of an impedance matching circuit; dividing the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal; accessing a recipe set identifying one or more of the bins for achieving the process rate uniformity; and controlling delivered power output from a radio frequency (RF) generator to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity.

2. The method of claim 1, wherein the process rate uniformity is a first process rate uniformity, wherein the bins include a first bin and a second bin, the method further comprising: regulating the delivered power to have the predetermined amount during the first bin; determining the first process rate uniformity when the delivered power is of the predetermined amount during the first bin; regulating the delivered power to have the predetermined amount during the second bin; determining a second process rate uniformity when the delivered power is of the predetermined amount during the second bin; determining that the first process rate uniformity is greater than the second process rate uniformity, wherein said controlling the delivered power to be of the predetermined amount during the one or more of the bins includes controlling the delivered power to be of the predetermined amount during the first bin.

3. The method of claim 2, wherein the second bin occurs after the first bin.

4. The method of claim 2, wherein the second bin occurs before the first bin.

5. The method of claim 1, wherein the output of the impedance matching circuit is coupled via an RF transmission line to a plasma chamber.

6. The method of claim 1, wherein the one or more bins include a first bin and a second bin, wherein the second bin occurs next to the first bin.

7. The method of claim 1, wherein the one or more bins include a first bin and a second bin, wherein the second bin occurs one or more bins after an occurrence of the first bin.

8. The method of claim 1, wherein the predetermined amount is equal to zero.

9. A controller for achieving process rate uniformity by identifying one or more bins, comprising: a processor configured to:receive a voltage signal provided from an output of an impedance matching circuit; divide the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal; access a recipe set identifying one or more of the bins for achieving the process rate uniformity; and control delivered power output from a radio frequency (RF) generator to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity; and a memory device coupled to the processor.

10. The controller of claim 9, wherein the process rate uniformity is a first process rate uniformity, wherein the bins include a first bin and a second bin, wherein the processor is configured to: regulate the delivered power to have the predetermined amount during the first bin; determine the first process rate uniformity when the delivered power is of the predetermined amount during the first bin; regulate the delivered power to have the predetermined amount during the second bin; determine a second process rate uniformity when the delivered power is of the predetermined amount during the second bin; determine that the first process rate uniformity is greater than the second process rate uniformity, wherein to control the delivered power to be of the predetermined amount during the one or more of the bins, the processor is configured to control the delivered power to be of the predetermined amount during the first bin.

10. The controller of claim 10, wherein the second bin occurs after the first bin.

11. The controller of claim 10, wherein the second bin occurs before the first bin.

13. The controller of claim 9, wherein the output of the impedance matching circuit is coupled via an RF transmission line to a plasma chamber.

14. The controller of claim 9, wherein the one or more bins include a first bin and a second bin, wherein the second bin occurs next to the first bin.

15. The controller of claim 9, wherein the one or more bins include a first bin and a second bin, wherein the second bin occurs one or more bins after an occurrence of the first bin.

16. The controller of claim 9, wherein the predetermined amount is equal to zero.

17. A system for achieving process rate uniformity, comprising: a first radio frequency (RF) generator configured to generate a first RF signal;a second RF generator configured to generate a second RF signal; a match coupled to the first and second RF generators to receive the first and second RF signals to output a modified RF signal, wherein the match has an output; and a controller coupled to the first and second RF generators, wherein the controller is configured to: receive a voltage signal provided from the output of the match; divide the voltage signal into a predetermined number of bins during each of a plurality of cycles of a clock signal; access a recipe set identifying one or more of the bins for achieving the process rate uniformity; and control delivered power output from the second RF generator to be of a predetermined amount during the one or more of the bins to achieve the process rate uniformity.

18. The system of claim 17, wherein the process rate uniformity is a first process rate uniformity, wherein the bins include a first bin and a second bin, wherein the controller is configured to: regulate the delivered power to have the predetermined amount during the first bin; determine the first process rate uniformity when the delivered power is of the predetermined amount during the first bin; regulate the delivered power to have the predetermined amount during the second bin; determine a second process rate uniformity when the delivered power is of the predetermined amount during the second bin; determine that the first process rate uniformity is greater than the second process rate uniformity, wherein to control the delivered power to be of the predetermined amount during the one or more of the bins, the controller is configured to control the delivered power to be of the predetermined amount during the first bin.

19. The system of claim 18, wherein the second bin occurs after the first bin.

20. The system of claim 18, wherein the second bin occurs before the first bin.

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