Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display, and provides a display panel and a display apparatus. The display panel of the present disclosure has a display area and a peripheral area surrounding the display area. The display panel comprises: a base substrate; a plurality of gate lines and a plurality of data lines arranged on the base substrate and extending from the display area to the peripheral area; a connection structure located in the peripheral area and used for electrically connecting the gate lines to a shift register and arranged on the side of the shift register close to the display area; and a first electrostatic protection structure located in the peripheral area, wherein the first electrostatic protection structure comprises first lead-out portions, second lead-out portions and first electrostatic lines; the first lead-out portions are connected to the side of the connection structure facing away from the display area, the second lead-out portions are arranged corresponding to the first lead-out portions, each second lead-out portion is located on the side of the corresponding first lead-out portion away from the display area, and the second lead-out portions are electrically connected to the first electrostatic lines.

Description

Display panel and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a display device. Background Art

[0002] Tip discharge is a type of discharge that occurs at the sharp end of an object under the influence of a strong electric field. On a conductor, the point with greater curvature is the tip compared to the less curvature. The sharper the tip, the greater the curvature, the higher the surface charge density, and the stronger the field strength near it. Therefore, the ends of a metal trace relative to the middle, and thinner wires relative to thicker wires, can both be considered tips and are susceptible to the tip effect. Due to electrostatic induction, opposite charges are induced at the tip of a grounded object, and discharge can easily occur between the tip and the charged object. The high discharge current can burn through the film layer, damaging the display circuitry.

[0003] During the display panel manufacturing process, the stacking of metal film layers accumulates static electricity. Consequently, electrostatic discharge (ESD), also known as tip discharge, often occurs at the ends of metal traces, causing metal trace shorts and severely impacting product yield. During panel operation, ESD can be triggered by external static electricity, leading to sudden high current flow within the panel, causing irreversible damage such as metal trace shorts, device burnout, and progressive failures.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display panel and a display device.

[0006] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a display panel having a display area and a peripheral area surrounding the display area; the display panel includes a base substrate;

[0007] A plurality of gate lines and a plurality of data lines are provided on the base substrate and extend from the display area to the peripheral area;

[0008] a connecting structure, located in the peripheral area, for electrically connecting the gate line to the shift register, and disposed on a side of the shift register close to the display area;

[0009] A first electrostatic protection structure is located in the peripheral area; wherein the first electrostatic protection structure includes: a first lead-out portion, a second lead-out portion and a first electrostatic line; the first lead-out portion is connected to a side of the connection structure away from the display area, the second lead-out portion is arranged corresponding to the first lead-out portion, and the second lead-out portion is located on a side of the corresponding first lead-out portion away from the display area, and the second lead-out portion is electrically connected to the first electrostatic line.

[0010] In some embodiments, the first lead-out portion includes a plurality of first lead-out portions; the plurality of first lead-out portions are arranged side by side along the extension direction of the connection structure.

[0011] In some embodiments, the display panel further comprises a plurality of pixel units arranged in an array on the base substrate, and a plurality of gate lines are provided between two adjacent rows of the pixel units;

[0012] The gate line is electrically connected to the shift register through at least one connection structure, and the connection structure closest to the shift register on the transmission path of the gate driving signal is connected to the first lead-out portion.

[0013] In some embodiments, the gate line is electrically connected to the shift register through at least two of the connection structures; and on the transmission path of the gate drive signal, two adjacent connection structures are electrically connected through a transfer line, and the transfer line is located on the side of the first lead-out portion close to the display area.

[0014] In some embodiments, the connection structure having the first lead-out portion includes: a first end portion, a second end portion, and an intermediate portion located between the first end portion and the second end portion;

[0015] The first end portion is electrically connected to the gate line, the second end portion is electrically connected to the adapter line, and the middle portion is electrically connected to the signal output line of the shift register through a connecting via;

[0016] The distance between the first lead-out portion and the first connection position of the connection structure and the side of the first end away from the second end is a first distance; the distance between the second connection position of the gate line and the first end and the side of the first end away from the second end is a second distance; the first distance is greater than the second distance.

[0017] In some embodiments, the shift register is electrically connected to the connection structure via a signal output line; the signal output line extends along an extension direction of the gate line, and the first electrostatic line extends along an extension direction of the data line;

[0018] The first electrostatic line includes a plurality of electrostatic line segments, and the electrostatic line segments are defined in a region between two adjacent signal output lines.

[0019] In some embodiments, the plurality of second lead-out portions connected to the electrostatic line segment include second lead-out portions located at both ends of the electrostatic line segment;

[0020] The first electrostatic protection structure further includes: a third lead-out portion connected to both ends of the electrostatic line segment, and an extending direction of the third lead-out portion is the same as an extending direction of the electrostatic line segment.

[0021] In some embodiments, the electrostatic line segments are arranged corresponding to a plurality of gate lines located between two adjacent rows of pixel units.

[0022] In some embodiments, at least part of the first lead-out portions on a plurality of different connection structures correspond to the same electrostatic line segment.

[0023] In some embodiments, the first electrostatic protection structure further includes: a second electrostatic line disposed on a side of the first electrostatic line away from the second lead-out portion, the second electrostatic line being connected to the first electrostatic line.

[0024] In some embodiments, the width of the first electrostatic line is smaller than the width of the second electrostatic line.

[0025] In some embodiments, the first electrostatic line includes a plurality of electrostatic line segments, and the plurality of electrostatic line segments are arranged at intervals;

[0026] The second lead portion connected to the end of the electrostatic line segment extends from the electrostatic line segment to the second electrostatic line and is connected to the second electrostatic line.

[0027] In some embodiments, the display panel further includes a common electrode line located in the peripheral area and a first electrostatic ring unit located in the peripheral area; one end of the second electrostatic line is electrically connected to the common electrode line through the first electrostatic ring unit.

[0028] In some embodiments, the n first lead portions connected to the connection structure are sequentially recorded as the first first lead portion, the second first lead portion, ..., the nth first lead portion in a direction from the first end portion to the second end portion of the connection structure; wherein the spacing between the first first lead portion and the corresponding second lead portion is the first spacing; the spacing between the i-th first lead portion and the corresponding second lead portion is the second spacing; and the spacing between the n-th first lead portion and the corresponding second lead portion is the third spacing; n is a positive integer greater than or equal to 2, and i is a positive integer between 2 and (n-1);

[0029] The first spacing is smaller than or equal to the second spacing; and the third spacing is smaller than or equal to the second spacing.

[0030] In some embodiments, the display panel further includes a second electrostatic protection structure located in the peripheral area;

[0031] The second electrostatic protection structure includes: a fourth lead-out portion and a third electrostatic line. The fourth lead-out portion is provided corresponding to the end portion corresponding to the data line, and the fourth lead-out portion is electrically connected to the third electrostatic line.

[0032] In some embodiments, the second electrostatic protection structure further includes: at least one short middle line segment provided corresponding to the data line, the at least one short middle line segment being located between the data line and the corresponding fourth lead-out portion;

[0033] The data line and the fourth lead-out portion are respectively spaced apart from the corresponding middle short line, and when the middle short line corresponding to the data line includes multiple segments, the multiple segments of the middle short line are spaced apart.

[0034] In some embodiments, the plurality of fourth lead-out portions connected to the third electrostatic line include fourth lead-out portions located at both ends of the third electrostatic line;

[0035] The second electrostatic protection structure further includes: a fifth lead-out portion connected to both ends of the third electrostatic line, and an extending direction of the fifth lead-out portion is the same as an extending direction of the third electrostatic line.

[0036] In some embodiments, the display panel also includes a signal repair line; the signal repair line includes a first sub-line segment, a second sub-line segment and a third sub-line segment; the first sub-line segment is located on the side of the second electrostatic protection structure away from the display area; the third sub-line segment is located on the side of the second electrostatic protection structure close to the display area; one end of the second sub-line segment is electrically connected to the first sub-line segment, and the other end is electrically connected to the third sub-line segment; the orthographic projection of each of the multiple data lines on the substrate overlaps with the orthographic projection of the third sub-line segment on the substrate, and the overlapping area is closer to the display area relative to the end of the data line.

[0037] In some embodiments, the orthographic projection of the second sub-segment on the substrate overlaps with the orthographic projection of the third electrostatic line on the substrate, and the line width of the second electrostatic line in the overlapping area is smaller than the line width of the second electrostatic line in the non-overlapping area.

[0038] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes a display panel as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0040] FIG2 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0041] FIG3 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0042] FIG4 is an enlarged view of the M region in FIG3 ;

[0043] FIG5 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0044] FIG6 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0045] FIG7 is a schematic diagram of an exemplary second electrostatic protection structure provided by an embodiment of the present disclosure;

[0046] FIG8 is a schematic diagram of another display panel provided by an embodiment of the present disclosure;

[0047] FIG9 is a circuit diagram of a third electrostatic protection structure provided by an embodiment of the present disclosure;

[0048] FIG10 is a circuit diagram of another third electrostatic protection structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0050] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0051] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0052] In the embodiment of the present disclosure, the first direction X, the second direction Y, and the third direction Z intersect in pairs. In the present disclosure, the first direction X and the second direction Y are perpendicular to each other in the plane where the substrate is located. The first direction X is a horizontal direction (or an extension direction of the gate line Gate), the second direction Y is a vertical direction (or an extension direction of the data line Data), and the third direction Z is a vertical direction, which is perpendicular to the plane where the substrate is located. This is described as an example, but does not constitute a limitation to the present disclosure.

[0053] In the disclosed embodiments, "the same layer" refers to a layer structure formed by using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, the sequential patterning process may include multiple exposure, development, or etching processes, and the specific patterns formed in the same layer may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0054] The structure of a display panel provided by an embodiment of the present disclosure is described in detail below.

[0055] FIG1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. As shown in FIG1 , the display panel has a display area AA and a peripheral area BB surrounding the display area. A pixel unit 01 is provided in the display area AA, a gate integrated drive circuit (Gate On Array, GOA), including a plurality of cascaded shift registers 02, and a source driver chip (Chip, IC) are provided in the peripheral area BB. The shift register 02 can provide a gate drive signal to each row of pixel units 01 via a gate line Gate, and the source driver chip IC can provide a data signal to each column of pixel units 01 via a data line Data. The pixel unit 01 includes a pixel drive circuit and a light-emitting device electrically connected thereto. The pixel drive circuit is used to drive the light-emitting device to emit light.

[0056] The display panel includes a base substrate, a plurality of gate lines Gate and a plurality of data lines Data arranged on the base substrate, a connection structure 1, and a first electrostatic protection structure 2. The plurality of gate lines Gate and the plurality of data lines Data extend from the display area AA to the peripheral area BB. The connection structure 1 is located in the peripheral area BB and is used to electrically connect the gate line Gate to the shift register 02. It is specifically arranged on the side of the shift register 02 close to the display area AA to achieve a cross-layer connection between the gate line Gate and the signal output line Gout of the shift register 02. To ensure a more stable cross-layer connection, the width of the connection structure 1 is wider than the width of the gate line Gate.

[0057] The first electrostatic protection structure 2 is located in the peripheral area BB. Specifically, the first electrostatic protection structure 2 is located in the area between the shift register 02 and the connection structure 1, which is recorded as the first electrostatic release area CC1.

[0058] The first electrostatic protection structure 2 includes: a first lead-out portion 21, a second lead-out portion 22 and a first electrostatic line 23; the first lead-out portion 21 is connected to the side of the connection structure 1 away from the display area AA, the second lead-out portion 22 is arranged corresponding to the first lead-out portion 21, and the second lead-out portion 22 is located on the side of the corresponding first lead-out portion 21 away from the display area AA, the second lead-out portion 22 is electrically connected to the first electrostatic line 23, and the first electrostatic line 23 has no electrical signal and is in a floating state. In this way, when static electricity accumulates on the gate line Gate, the correspondingly arranged first lead-out portion 21 and second lead-out portion 22, as well as the first electrostatic line 23, can induce electrostatic charge to generate ESD in the first electrostatic release area CC1. In this way, when ESD occurs at the end of the gate line Gate, the influence of the short circuit between the gate line Gate and other metal wiring is eliminated, or damage to the devices in the shift register 02 is avoided.

[0059] Exemplarily, the first lead-out portion 21 is provided on the same layer as the connection structure 1 and is an integrated structure.

[0060] Exemplarily, the connection structure 1 and the gate line Gate are provided in the same layer and are an integrated structure.

[0061] Exemplarily, the first lead-out portion 21 , the connection structure 1 and the gate line Gate are provided in the same layer and form an integrated structure.

[0062] Exemplarily, the second lead-out portion 22 and the first electrostatic line 23 are provided on the same layer and are an integrated structure.

[0063] Exemplarily, the first lead-out portion 21 and the second lead-out portion 22 are provided in a one-to-one correspondence.

[0064] Exemplarily, the gate line Gate, the connection structure 1, the first lead portion 21, the second lead portion 22, and the first electrostatic line 23 are arranged on the same layer and can be formed through a single patterning process.

[0065] In the embodiment of the present disclosure, the first electrostatic protection structure 2 is disposed on the side of the connection structure 1 away from the display area AA. Since the metal traces in the display area AA are relatively thin and the trace spacing is relatively narrow, the present disclosure provides the above-mentioned technical solution to induce the static electricity generated on the gate line Gate to be discharged in a safe area away from the display area AA (i.e., the first electrostatic discharge area CC1), thereby protecting the pixel driving circuit in the display area AA. In addition, the first lead-out portion 21 is connected to the side of the connection structure 1 away from the display area AA. Before the gate line Gate is cross-connected with the signal output line Gout on the shift register 02, the gate line Gate is subjected to electrostatic discharge (ESD) to eliminate the impact on the shift register 02.

[0066] In some embodiments, as shown in FIG1 , the first lead portion 21 includes a plurality of first lead portions 21, which are arranged side by side along the extension direction of the connection structure 1 (i.e., the second direction Y). In this embodiment, by connecting the plurality of first lead portions 21 to the connection structure 1, static charge is dispersed, reducing the degree of static discharge at various locations on the connection structure 1, thereby weakening the impact of static discharge on the connection structure 1 and preventing irreversible damage such as structural short circuits and burning.

[0067] In some embodiments, FIG2 is a schematic diagram of another display panel provided by an embodiment of the present disclosure, which differs from the structure shown in FIG1 in that a plurality of gate lines Gate are provided between adjacent rows of pixel units 01 .

[0068] As shown in Figure 2, the display panel also includes a plurality of pixel units 01 arranged in an array on a base substrate, and a plurality of gate lines Gate are arranged between two adjacent rows of pixel units 01; the gate line Gate is electrically connected to the shift register 02 through at least one connection structure 1, and the connection structure 1 closest to the shift register 02 on the transmission path of the gate drive signal is connected to the first lead-out portion 21.

[0069] Exemplarily, a plurality of gate lines Gate are respectively used to control pixel units 01 in different rows.

[0070] Exemplarily, multiple gate lines Gate are used to control the same row of pixel units 01. Taking one pixel unit 01 in the same row of pixel units 01 as an example, the pixel driving circuit in the pixel unit 01 includes multiple switching transistors, and the multiple gate lines Gate respectively control different switching transistors.

[0071] Exemplarily, as shown in FIG2 , two gate lines Gate are provided between two adjacent rows of pixel units 01, which are respectively denoted as the first gate line Gate1 and the second gate line Gate2. The first gate line Gate1 and the second gate line Gate2 are electrically connected to the respective pixel drive circuits in the same row of pixel units 01. The first gate line Gate1 is electrically connected to the shift register 02 through two connection structures 1, and the two connection structures 1 are respectively denoted as the first connection structure 11 and the second connection structure 12. In the transmission path of the gate drive signal, the first connection structure 11 is closer to the shift register 02 than the second connection structure 12. The difference between the first connection structure 11 and the second connection structure 12 is that a plurality of first lead-out portions 21 are connected to the first connection structure 11. The second gate line Gate2 is electrically connected to the shift register 02 through a connection structure 1 (i.e., the first connection structure 11).

[0072] In this embodiment, the first lead-out portion 21 is connected to the first connection structure 1, that is, the first electrostatic protection structure 2 is provided on the side of the first connection structure 1 away from the second connection structure 1, away from the display area AA. Once electrostatic discharge occurs, it is beneficial to protect the structure in the display area AA.

[0073] In some embodiments, as shown in Figure 2, there is a gate line Gate electrically connected to the shift register 02 through at least two connection structures 1; and on the transmission path of the gate drive signal, two adjacent connection structures 1 are electrically connected through a transfer line 3, and the transfer line 3 is located on the side of the first lead-out portion 21 close to the display area AA.

[0074] For example, on the transmission path of the gate drive signal, the number of connection structures 1 electrically connected to the gate line Gate depends on the number of gate lines Gate between two adjacent rows of pixel units 01. For example, the number of connection structures 1 electrically connected to the gate line Gate is equal to the number of gate lines Gate between two adjacent rows of pixel units 01. Of course, for any gate line Gate, cross-line switching can also be achieved by only two connection structures 1. The number of actual connection structures 1 can be set according to specific circumstances and is not limited in the embodiments of the present disclosure.

[0075] Multiple connection structures 1 are arranged on the same layer and belong to different layers from the adapter lines 3. The adapter lines 3 are connected to the connection structures 1 through connecting vias, thereby achieving electrical connection between different connection structures 1, and further achieving electrical connection between the gate line Gate and the shift register 02.

[0076] In this embodiment, the first electrostatic protection structure 2 is further disposed on a side of the plurality of adapter lines 3 away from the display area AA, which is beneficial for protecting the structure in the display area AA.

[0077] In some embodiments, as shown in Figure 2, the connection structure 1 having a first lead-out portion 21 (i.e., a first connection structure 11) includes: a first end portion 1a, a second end portion 1b, and a middle portion 1c located between the first end portion 1a and the second end portion 1b; the first end portion 1a is electrically connected to the gate line Gate, the second end portion 1b is electrically connected to the adapter line 3, and the middle portion 1c is electrically connected to the signal output line Gout of the shift register 02 through a connecting via.

[0078] A plurality of first lead portions 21 are provided on the first connecting structure 1. Among them, the distance from the first connection position of any first lead portion 21 to the connecting structure 1 to the side of the first end away from the second end is the first distance; the distance from the second connection position of the gate line Gate to the first end to the side of the first end away from the second end is the second distance; the first distance is greater than the second distance. Taking the first lead portion 21 closest to the first end 1a (that is, the first lead portion 21A in Figure 2) as an example, the distance from the first connection position of the first lead portion 21A to the connecting structure 1 to the side S1 of the first end 1a away from the second end 1b is the first distance L1; the distance from the second connection position of the gate line Gate to the first end 1a to the side S1 of the first end 1a away from the second end 1b is the second distance L2; the first distance L1 is greater than the second distance L2.

[0079] As shown in Figure 2, the gate line Gate is connected to the side of the first end 1a away from the second end 1b. The first lead portion 21 is connected to the middle portion 1c near the first end 1a. In this case, the first distance L1 is greater than the second distance L2. The design of the first lead portion 21 away from the overlapping area DD of the gate line Gate and the adapter cable 3 prevents the influence of electrostatic discharge on the transmission of the gate drive signal by the adapter cable 3.

[0080] Exemplarily, the signal output line Gout is electrically connected to the middle portion through two rows of connection vias, thereby ensuring the connection stability between the connection structure 1 and the signal output line Gout.

[0081] In some embodiments, the display panel further includes a common electrode line (not shown in the figure) located in the peripheral area BB and a first electrostatic ring unit (not shown in the figure) located in the peripheral area BB; one end of the second electrostatic line 24 is electrically connected to the common electrode line through the first electrostatic ring unit. The first electrostatic line 23 has no additional electrical signal, and at least one end thereof is connected to the first electrostatic ring unit, and the other end of the first electrostatic ring unit is connected to the common electrode line to maintain floating. In this way, when static electricity accumulates on the gate line Gate, electrostatic charge can be induced to realize ESD through the first electrostatic ring unit, thereby avoiding a short circuit with the adjacent gate line Gate when ESD occurs at the end of the gate line Gate, or causing damage to the devices in the connected shift register 02.

[0082] The circuit structure of the first electrostatic ring unit can be found in the following description of the second electrostatic ring unit 61 , as shown in FIG7 , and will not be described in detail here.

[0083] In some embodiments, Figure 3 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. As shown in Figure 3, the shift register 02 is electrically connected to the connection structure 1 through the signal output line Gout; the signal output line Gout extends along the extension direction of the gate line Gate (that is, the first direction X), and the first electrostatic line 23 extends along the extension direction of the data line Data (that is, the second direction Y); the first electrostatic line 23 includes multiple electrostatic line segments 23a, and the electrostatic line segments 23a are confined to the area between two adjacent signal output lines Gout.

[0084] Specifically, the electrostatic line segment 23 a extends along the second direction Y, and its orthographic projection on the base substrate does not overlap with the orthographic projection of the signal output line Gout on the base substrate.

[0085] Compared to the first electrostatic line 23 shown in Figure 2 , the first electrostatic line 23 shown in Figure 3 differs in that it includes multiple electrostatic line segments 23a spaced apart, with the signal output line Gout routed through the spaced apart areas. Compared to the first electrostatic line 23 shown in Figure 2 , this embodiment, on the one hand, disperses the overall electrostatic charge through the multiple electrostatic line segments 23a; on the other hand, it avoids the signal output line Gout, reducing the number of overlaps and ramps of the signal output line Gout, lowering the capacitance of the signal output line Gout and the risk of breakage (opening), thereby improving product yield.

[0086] Exemplarily, the line width of the first electrostatic line 23 is smaller than the line width of the signal output line Gout.

[0087] In some embodiments, as shown in FIG3 , a plurality of second lead portions 22 are connected to the electrostatic segment 23a. The plurality of second lead portions 22 connected to the electrostatic segment 23a include second lead portions 22 located at both ends of the electrostatic segment 23a, respectively referred to as second lead portions 221 and second lead portions 222. The first electrostatic protection structure 2 further includes a third lead portion 25 connected to both ends of the electrostatic segment 23a, and the extension direction of the third lead portion 25 is the same as the extension direction of the electrostatic segment 23a. The third lead portion 25 has a different extension direction from the second lead portion 22. The extension direction of the second lead portion 22 is the relative direction of the second lead portion 22 and the corresponding first lead portion 21 (i.e., the first direction X). The extension direction of the third lead portion 25 is the second direction Y.

[0088] Exemplarily, the third lead-out portion 25 and the electrostatic line segment 23 a are an integrated structure.

[0089] In this embodiment, third lead-out portions 25 are added at both ends of the electrostatic line segment 23 a , which is beneficial for further dispersing the electrostatic charge and improving the efficiency of electrostatic charge extraction.

[0090] In some embodiments, as shown in FIG3 , the electrostatic line segment 23 a is provided corresponding to a plurality of gate lines Gate located between two adjacent rows of pixel units 01. For example, the electrostatic line segment 23 a can correspond to two rows of gate lines Gate, or more rows of gate lines Gate, according to different product requirements. This disclosure takes the case of corresponding to two rows of gate lines Gate as an example, and other cases are not listed one by one.

[0091] In some embodiments, as shown in FIG. 3 , the electrostatic line segment 23 a is staggered with a row of pixel units 01 .

[0092] In some embodiments, as shown in Figure 3, the electrostatic line segment 23a is connected to multiple second lead-out portions 22. At least some of the first lead-out portions 21 on multiple different connection structures 1 correspond to the same electrostatic line segment 23a, which is conducive to the centralized extraction of electrostatic charges.

[0093] In some embodiments, the structure shown in FIG3 differs from the structure shown in FIG2 in that a second electrostatic line 24 is added. As shown in FIG3 , the first electrostatic protection structure 2 further includes a second electrostatic line 24 disposed on a side of the first electrostatic line 23 away from the second lead-out portion 22. The second electrostatic line 24 is connected to the first electrostatic line 23 and is used to further conduct away static electricity introduced into the first electrostatic line 23.

[0094] In some embodiments, as shown in Figure 3, the distance from the second electrostatic line 24 to the area where the shift register 02 is located is relatively short. In order to avoid the influence of electrostatic discharge on the internal devices and signals of the shift register 02, the width of the first electrostatic line 23 is smaller than the width of the second electrostatic line 24. The resistance of the second electrostatic line 24 is smaller than that of the first electrostatic line 23, which is conducive to the extraction of static electricity.

[0095] In some embodiments, as shown in Figure 3, the first electrostatic line 23 includes multiple electrostatic line segments 23a, and the multiple electrostatic line segments 23a are arranged at intervals; for the second lead-out portion 22 (that is, the second lead-out portion 221 and the second lead-out portion 222) connected to the end of the electrostatic line segment 23a, it extends from the electrostatic line segment 23a to the second electrostatic line 24 and is connected to the second electrostatic line 24. On the one hand, it is beneficial to disperse the charge. On the other hand, the static electricity introduced from the first lead-out portion 21 into the second lead-out portion 22 can be introduced into the second electrostatic line 24 from the shortest path, further improving the electrostatic lead-out efficiency and facilitating electrostatic protection.

[0096] In some embodiments, the display panel further includes a common electrode line (not shown in the figure) located in the peripheral area BB and a first electrostatic ring unit (not shown in the figure) located in the peripheral area BB; one end of the second electrostatic line 24 is electrically connected to the common electrode line through the first electrostatic ring unit. The first electrostatic protection structure 2 has no additional electrical signal, and at least one end thereof is connected to the first electrostatic ring unit, and the other end of the first electrostatic ring unit is connected to the common electrode line to maintain floating. In this way, when static electricity accumulates on the gate line Gate, electrostatic charge can be induced to realize ESD through the first electrostatic ring unit, thereby avoiding a short circuit with the adjacent gate line Gate when ESD occurs at the end of the gate line Gate, or causing damage to the devices in the connected shift register 02.

[0097] In some embodiments, Figure 4 is an enlarged view of the M area in Figure 3. As shown in Figure 4, the n first lead-out portions 21 connected to the connection structure 1 are sequentially recorded as the first first lead-out portion 21, the second first lead-out portion 21, ..., the nth first lead-out portion 21 in the direction from the first end 1a of the connection structure 1 to the second end; wherein, the spacing between the first first lead-out portion 21 and the corresponding second lead-out portion 22 is the first spacing H1; the spacing between the i-th first lead-out portion 21 and the corresponding second lead-out portion 22 is the second spacing H2; the spacing between the n-th first lead-out portion 21 and the corresponding second lead-out portion 22 is the third spacing H3; n is a positive integer greater than or equal to 2, and i is a positive integer between 2 and (n-1); wherein, the first spacing H1 is less than or equal to the second spacing H2; the third spacing H3 is less than or equal to the second spacing H2, so that ESD can be ensured to the greatest extent possible to occur at the end of the gate line Gate routing, reducing the impact on the structure of the connection via corresponding to the middle part of the connection structure 1.

[0098] Here, it can be understood that the distance between the first lead-out portion 21 and the corresponding second lead-out portion 22 is: in the first direction X, the shortest distance between the first lead-out portion 21 and the corresponding second lead-out portion 22 .

[0099] Exemplarily, the first interval H1 may be equal to the third interval H3.

[0100] In some embodiments, FIG5 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Compared to the above embodiment, a second electrostatic protection structure 4 is further added to provide electrostatic protection for the data line Data. As shown in FIG5 , the display panel also includes a second electrostatic protection structure 4 located in the peripheral area BB. The second electrostatic protection structure 4 includes a fourth lead portion 41 and a third electrostatic line 42. The fourth lead portion 41 is disposed corresponding to the end of the data line Data, and the fourth lead portion 41 is electrically connected to the third electrostatic line 42.

[0101] This embodiment can dissipate static electricity when ESD occurs at the end of the data line Data by providing a fourth lead-out portion 41 at the corresponding end of the data line Data and a third electrostatic line 42 connected to the fourth lead-out portion 41. The second electrostatic protection structure 4 is signal-free and in a floating state, meaning it does not require connection to an actual circuit. This facilitates stable ESD protection of the data line Data in the second electrostatic discharge zone CC2, preventing product failure caused by short circuits between the data line Data and other metal traces during electrostatic discharge.

[0102] Exemplarily, the fourth lead-out portion 41 is provided on the same layer as the third electrostatic line 42. Exemplarily, the fourth lead-out portion 41, the third electrostatic line 42 and the data line Data are provided on the same layer.

[0103] Exemplarily, the fourth lead-out portion 41 and the third electrostatic line 42 are an integrated structure and can be formed through a single patterning process.

[0104] Exemplarily, the fourth lead-out portion 41 , the third electrostatic line 42 , and the data line Data may be formed through a single patterning process.

[0105] In some embodiments, FIG6 is a schematic diagram of another display panel provided by embodiments of the present disclosure. Compared to the structure shown in FIG5 , FIG6 differs in that the second electrostatic protection structure 4 is a step-by-step discharge structure. As shown in FIG6 , the second electrostatic protection structure 4 further includes: at least one intermediate short line 43 corresponding to the data line Data, with at least one intermediate short line 43 located between the data line Data and the corresponding fourth lead portion 41; the data line Data and the fourth lead portion 41 are spaced apart from the corresponding intermediate short line 43, and if the intermediate short line 43 corresponding to the data line Data includes multiple segments, the multiple intermediate short lines 43 are spaced apart.

[0106] In some embodiments, as shown in FIG. 6 , the length of the middle short line 43 in the extending direction of the data line Data (the second direction Y) is between 25 μm and 35 μm.

[0107] In some embodiments, as shown in FIG. 6 , the distance between the middle short line 43 and the corresponding data line Data is between 5 μm and 15 μm.

[0108] In some embodiments, as shown in FIG6 , the fourth lead-out portion 41 , the third electrostatic line 42 and the middle short line 43 are disposed on the same layer.

[0109] In conjunction with the embodiment related to the structure of FIG6 , the greater the number of intermediate short lines 43 corresponding to the data lines, the better the step-by-step static discharge effect. The present disclosure can specifically design the number of intermediate short lines 43 corresponding to each data line based on the actual accommodation space of the peripheral area BB to achieve a stable static discharge effect.

[0110] It should be noted that the “corresponding arrangement” between the two structures disclosed herein can be understood as the end portions of the structures being aligned.

[0111] Exemplarily, the second electrostatic protection structure 4 also includes: a short middle line 43 arranged corresponding to the data line Data, the short middle line 43 is located between the data line Data and the corresponding fourth lead-out portion 41; the data line Data and the fourth lead-out portion 41 are respectively spaced apart from the corresponding short middle line 43.

[0112] FIG7 is a schematic diagram of an exemplary second electrostatic protection structure provided by an embodiment of the present disclosure. As shown in FIG7 , the second electrostatic protection structure 4 further includes two intermediate short lines 43 corresponding to the data line Data, designated as a first intermediate short line 43a and a second intermediate short line 43b. The first intermediate short line 43a and the second intermediate short line 43b are arranged in correspondence with each other. The first intermediate short line 43a is located between the corresponding data line Data and the corresponding second intermediate short line 43b; the second intermediate short line 43b is located between the corresponding first intermediate short line 43a and the corresponding fourth lead portion 41. The data line Data and the corresponding first intermediate short line 43a are spaced apart, the first intermediate short line 43a and the corresponding second intermediate short line 43b are spaced apart, and the second intermediate short line 43b and the corresponding fourth lead portion 41 are spaced apart. When ESD occurs at the end of the data line Data, static electricity is discharged step by step from the first intermediate short line 43a to the second intermediate short line 43b to the fourth lead portion 41 and finally to the third electrostatic line 42, facilitating the stable discharge of static electricity in the second electrostatic discharge area CC2.

[0113] In some embodiments, FIG8 is a schematic diagram of another display panel provided by an embodiment of the present disclosure. Compared with the structure shown in FIG6 , FIG8 differs in that fifth lead-out portions 44 are additionally provided at both ends of the third electrostatic line 42 .

[0114] As shown in Figure 8, a plurality of fourth lead portions 41 are connected to the third electrostatic line 42. The plurality of fourth lead portions 41 connected to the third electrostatic line 42 include fourth lead portions 41 located at both ends of the third electrostatic line 42, respectively denoted as 41a and 41b; the second electrostatic protection structure 4 also includes: a fifth lead portion 44 connected to both ends of the third electrostatic line 42, and the extension direction of the fifth lead portion 44 is the same as the extension direction of the third electrostatic line 42. The extension direction of the fifth lead portion 44 is different from that of the fourth lead portion 41. The extension direction of the fourth lead portion 41 is the extension direction of the data line Data (that is, the second direction Y). The extension direction of the third electrostatic line 42 is the first direction X. The extension direction of the fifth lead portion 44 is the first direction X.

[0115] Exemplarily, the fifth lead-out portion 44 and the third electrostatic line 42 are an integrated structure.

[0116] In this embodiment, fourth lead-out portions 41 are additionally provided at both ends of the third electrostatic line 42 , which is beneficial for further dispersing the electrostatic charge and improving the efficiency of electrostatic charge extraction.

[0117] In some embodiments, as shown in FIG6 or FIG8 , the display panel further includes a signal repair line 5. If the data lines Data are intact, there is no electrical connection between the signal repair line 5 and the data lines Data. The signal repair line 5 is used when data signal repair is required, such as when a data line Data is broken. In this case, the signal repair line 5 can be used to connect (short) the data line Data to be repaired to achieve normal data signal transmission.

[0118] As shown in Figure 6 or Figure 8, the signal repair line 5 includes a first sub-segment 51, a second sub-segment 52 and a third sub-segment 53; the first sub-segment 51 is located on the side of the second electrostatic protection structure 4 away from the display area AA; the third sub-segment 53 is located on the side of the second electrostatic protection structure 4 close to the display area AA; one end of the second sub-segment 52 is electrically connected to the first sub-segment 51, and the other end is electrically connected to the third sub-segment 53; the positive projection of each of the multiple data lines Data on the substrate overlaps with the positive projection of the third sub-segment 53 on the substrate, and the overlapping area is closer to the display area AA than the end of the data line Data, so that the tip discharge end Q of the data line Data is reserved to avoid a short circuit at the overlapping position of the third sub-segment 53 and the data line Data when ESD occurs.

[0119] In some embodiments, as shown in Figure 6 or Figure 8, the orthographic projection of the second sub-segment 52 on the substrate overlaps with the orthographic projection of the third electrostatic line 42 on the substrate, and the line width of the third electrostatic line 42 in the overlapping area W1 is smaller than the line width of the third electrostatic line 42 in the non-overlapping area W1, thereby reducing the capacitance of the signal repair line 5 and the risk of breakage (open), thereby improving product yield.

[0120] 3 and 6 , in the manufacturing process of the Panel, the electrostatic discharge (ESD) of the gate line Gate and the data line Data is effectively reduced, which is beneficial to the overall electrostatic protection of the Panel.

[0121] In some embodiments, FIG9 is a circuit diagram of a third electrostatic protection structure provided by an embodiment of the present disclosure. Compared to the structures of FIG1 to FIG4 above, the structure of FIG9 further adds a third electrostatic protection structure 6 for implementing electrostatic protection for the data line Data. As shown in FIG9 , the display panel also includes a third electrostatic protection structure 6 located in the peripheral area BB. The third electrostatic protection structure 6 includes a second electrostatic ring unit 61. One end of the second electrostatic ring unit 61 is electrically connected to the data line Data, and the other end is electrically connected to the external floating line 62. When a large current is suddenly generated on the data line Data due to ESD, the thin film transistor in the second electrostatic ring unit 61 will be broken down and turned on, and then the electrostatic charge will be quickly introduced into the external floating line 62, thereby protecting the device connected to the data line Data from damage.

[0122] In the embodiments of the present disclosure, the thin film transistor can be either an N-type thin film transistor or a P-type thin film transistor. An N-type thin film transistor refers to a thin film transistor in which an N-type ion is doped in its active layer; a P-type thin film transistor refers to a thin film transistor in which a P-type ion is doped in its active layer. The operating level signal of an N-type thin film transistor is a high-level signal; the operating level signal of a P-type thin film transistor is a low-level signal. The following embodiments are described using an N-type thin film transistor as an example, but the present disclosure is not limited to N-type thin film transistors.

[0123] For example, as shown in FIG9 , the second electrostatic ring unit 61 includes four thin film transistors, namely a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and a fourth thin film transistor T4. The first thin film transistor T1 includes a first control stage T11, a first source electrode T12, and a first drain electrode T13; the second thin film transistor T2 includes a second control stage T21, a second source electrode T22, and a second drain electrode T23; the third thin film transistor T3 includes a third control stage T31, a third source electrode T32, and a third drain electrode T33; and the fourth thin film transistor T4 includes a fourth control stage T41, a fourth source electrode T42, and a fourth drain electrode T43. The first control stage T11 is electrically connected to the first source electrode T12; the second control stage T21 is electrically connected to the second source electrode T22; the first source electrode T12 and the second drain electrode T23 are electrically connected and are both electrically connected to the data line Data; the first drain electrode T13 is electrically connected to the second source electrode T22 and are both electrically connected to the third source electrode T32. The third control stage T31 is electrically connected to the third source T32; the fourth control stage T41 is electrically connected to the fourth source T42; the third source T32 is electrically connected to the fourth drain T43; the third drain T33 is electrically connected to the fourth source T42, and both are connected to the external floating line 62. Here, the external floating line 62 is in a floating state, that is, no electrical signal is connected to it.

[0124] Exemplarily, the third electrostatic protection structures 6 are arranged in a one-to-one correspondence with the data lines Data.

[0125] In some embodiments, FIG10 is a circuit diagram of another third electrostatic protection structure provided in an embodiment of the present disclosure. Compared with FIG9 , FIG10 further adds a short-circuit ring structure 63. As shown in FIG10 , the display panel further includes a third electrostatic protection structure 6 located in the peripheral area BB. The third electrostatic protection structure 6 includes an electrically connected second electrostatic ring unit 61 and at least one short-circuit ring structure 63. One end of the second electrostatic ring unit 61 is electrically connected to the data line Data, and the other end is electrically connected to the short-circuit ring structure 63. When a large current is suddenly generated on the data line Data due to ESD, the thin film transistor in the second electrostatic ring unit 61 will be broken down and turned on, and then the electrostatic charge will be quickly introduced into the short-circuit ring structure 63, thereby protecting the device connected to the data line Data from damage.

[0126] Exemplarily, the short-circuit ring structure 63 includes short wires forming a ring-shaped structure.

[0127] Illustratively, the short-circuit ring structure 63 includes a plurality of short-circuit ring structures 63 , and two adjacent short-circuit ring structures 63 are connected in series.

[0128] Exemplarily, the third electrostatic protection structures 6 are arranged in a one-to-one correspondence with the data lines Data.

[0129] In some embodiments, the short lines forming a ring structure in the short-circuit ring structure 63 are arranged in the same layer, and the material of the short lines may include but is not limited to one of indium tin oxide (ITO), polysilicon, copper (Cu), aluminum (Al), etc.

[0130] In some embodiments, the short-circuit ring structure 63 is provided in the same layer as the gate of the thin film transistor in the second electrostatic ring unit 61. Exemplarily, the short-circuit ring structure 63 and the gate of the thin film transistor in the second electrostatic ring unit 61 are formed by a single patterning process.

[0131] For example, the material of the short lines forming the ring structure in the short-circuit ring structure 63 may be the material of the gate of a thin film transistor.

[0132] In some embodiments, the display panel is a liquid crystal display (LCD) panel.

[0133] In addition, embodiments of the present disclosure further provide a display device comprising the display panel described in any of the above embodiments. The display device may be, for example, a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, vehicle-mounted device, or any other product with a display function. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0134] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel comprising a display area and a peripheral area surrounding the display area; the display panel comprising a base substrate; A plurality of gate lines and a plurality of data lines are provided on the base substrate and extend from the display area to the peripheral area; a connecting structure, located in the peripheral area, for electrically connecting the gate line to the shift register, and disposed on a side of the shift register close to the display area; A first electrostatic protection structure is located in the peripheral area; wherein the first electrostatic protection structure includes: a first lead-out portion, a second lead-out portion and a first electrostatic line; the first lead-out portion is connected to a side of the connection structure away from the display area, the second lead-out portion is arranged corresponding to the first lead-out portion, and the second lead-out portion is located on a side of the corresponding first lead-out portion away from the display area, and the second lead-out portion is electrically connected to the first electrostatic line.

2. The display panel according to claim 1, wherein The first lead-out portions include a plurality of first lead-out portions, and the plurality of first lead-out portions are arranged side by side along the extending direction of the connecting structure.

3. The display panel according to claim 1, wherein: The display panel further comprises a plurality of pixel units arranged in an array on the base substrate, and a plurality of gate lines are arranged between two adjacent rows of the pixel units; The gate line is electrically connected to the shift register through at least one connection structure, and the connection structure closest to the shift register on the transmission path of the gate driving signal is connected to the first lead-out portion.

4. The display panel according to claim 3, wherein: The gate line is electrically connected to the shift register through at least two of the connection structures; and on the transmission path of the gate drive signal, two adjacent connection structures are electrically connected through a switching line, and the switching line is located on the side of the first lead-out portion close to the display area.

5. The display panel according to claim 4, wherein: The connection structure having the first lead-out portion includes: a first end portion, a second end portion, and an intermediate portion located between the first end portion and the second end portion; The first end portion is electrically connected to the gate line, the second end portion is electrically connected to the adapter line, and the middle portion is electrically connected to the signal output line of the shift register through a connecting via; The distance between the first lead-out portion and the first connection position of the connection structure and the side of the first end away from the second end is a first distance; the distance between the second connection position of the gate line and the first end and the side of the first end away from the second end is a second distance; the first distance is greater than the second distance.

6. The display panel according to any one of claims 1 to 5, wherein: The shift register is electrically connected to the connection structure via a signal output line; the signal output line extends along an extension direction of the gate line, and the first electrostatic line extends along an extension direction of the data line; The first electrostatic line includes a plurality of electrostatic line segments, and the electrostatic line segments are defined in a region between two adjacent signal output lines.

7. The display panel according to claim 6, wherein: a plurality of second lead-out portions connected to the electrostatic line segment, including second lead-out portions located at both ends of the electrostatic line segment; The first electrostatic protection structure further includes: a third lead-out portion connected to both ends of the electrostatic line segment, and an extending direction of the third lead-out portion is the same as an extending direction of the electrostatic line segment.

8. The display panel according to claim 6, wherein: The electrostatic line segments are arranged corresponding to a plurality of gate lines located between two adjacent rows of pixel units.

9. The display panel according to claim 6, wherein: At least part of the first lead-out portions on a plurality of different connection structures corresponds to the same electrostatic line segment.

10. The display panel according to any one of claims 1 to 5, wherein: The first electrostatic protection structure further includes: a second electrostatic line arranged on a side of the first electrostatic line away from the second lead-out portion, and the second electrostatic line is connected to the first electrostatic line.

11. The display panel according to claim 10, wherein: The width of the first electrostatic line is smaller than the width of the second electrostatic line.

12. The display panel according to claim 10, wherein: The first electrostatic line includes a plurality of electrostatic line segments, and the plurality of electrostatic line segments are arranged at intervals; The second lead portion connected to the end of the electrostatic line segment extends from the electrostatic line segment to the second electrostatic line and is connected to the second electrostatic line.

13. The display panel according to claim 10, wherein: The display panel further includes a common electrode line located in the peripheral area and a first electrostatic ring unit located in the peripheral area; one end of the second electrostatic line is electrically connected to the common electrode line through the first electrostatic ring unit.

14. The display panel according to any one of claims 1 to 5, wherein: The n first lead portions connected to the connection structure are sequentially designated as the first first lead portion, the second first lead portion, ..., the nth first lead portion, in a direction from the first end portion to the second end portion of the connection structure; wherein the spacing between the first first lead portion and the corresponding second lead portion is a first spacing; the spacing between the i-th first lead portion and the corresponding second lead portion is a second spacing; and the spacing between the n-th first lead portion and the corresponding second lead portion is a third spacing; n is a positive integer greater than or equal to 2, and i is a positive integer between 2 and (n-1); The first spacing is smaller than or equal to the second spacing; and the third spacing is smaller than or equal to the second spacing.

15. The display panel according to any one of claims 1 to 5, wherein The display panel further includes a second electrostatic protection structure located in the peripheral area; The second electrostatic protection structure includes: a fourth lead-out portion and a third electrostatic line. The fourth lead-out portion is provided corresponding to the end portion corresponding to the data line, and the fourth lead-out portion is electrically connected to the third electrostatic line.

16. The display panel according to claim 15, wherein: The second electrostatic protection structure further includes: at least one short middle line section provided corresponding to the data line, wherein the at least one short middle line section is located between the data line and the corresponding fourth lead-out portion; The data line and the fourth lead-out portion are respectively spaced apart from the corresponding middle short line, and when the middle short line corresponding to the data line includes multiple segments, the multiple segments of the middle short line are spaced apart.

17. The display panel according to claim 16, wherein: a plurality of fourth lead-out portions connected to the third electrostatic line, including fourth lead-out portions located at both ends of the third electrostatic line; The second electrostatic protection structure further includes: a fifth lead-out portion connected to both ends of the third electrostatic line, and an extending direction of the fifth lead-out portion is the same as an extending direction of the third electrostatic line.

18. The display panel according to claim 16, wherein: The display panel also includes a signal repair line; the signal repair line includes a first sub-line segment, a second sub-line segment and a third sub-line segment; the first sub-line segment is located on the side of the second electrostatic protection structure away from the display area; the third sub-line segment is located on the side of the second electrostatic protection structure close to the display area; one end of the second sub-line segment is electrically connected to the first sub-line segment, and the other end is electrically connected to the third sub-line segment; the orthographic projection of each of the multiple data lines on the base substrate overlaps with the orthographic projection of the third sub-line segment on the base substrate, and the overlapping area is closer to the display area than the end of the data line.

19. The display panel according to claim 18, wherein: The orthographic projection of the second sub-segment on the base substrate overlaps with the orthographic projection of the third electrostatic line on the base substrate, and the line width of the second electrostatic line in the overlapping area is smaller than the line width of the second electrostatic line in the non-overlapping area.

20. A display device comprising the display panel according to any one of claims 1 to 19.

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