Display panel and display apparatus

Abstract

A display panel and a display apparatus, relating to the technical field of display. A display substrate (PNL) of the display panel comprises a plurality of light-emitting devices (LD) located in a display area (AA) and blocking dams (DAM) located in a peripheral area (WA); the display substrate (PNL) is provided with a partition recess (SH) located in the peripheral area (WA); the part of the display substrate (PNL) located on the side of the partition recess (SH) away from the display area (AA) is an edge part (EP); the blocking dams (DAM) are arranged in the partition recess (SH), there being a gap (SHH) between the outermost blocking dam (DAM) and the edge part (EP). An encapsulation layer (TFE) comprises a first inorganic layer (CVD1), a second inorganic layer (CVD2) and an organic layer (IJP) provided between the first inorganic layer (CVD1) and the second inorganic layer (CVD2); the first inorganic layer (CVD1) and the second inorganic layer (CVD2) cover the blocking dams (DAM), and at least extend into the gap (SHH); the organic layer (IJP) is located on the sides of the blocking dams (DAM) close to the light-emitting devices (LD); signal lines (SL) of the display panel are arranged on the side of the encapsulation layer (TFE) away from the display substrate (PNL); at least partial regions of some of the signal lines (SL) are located in the gap (SHH); at least partial regions of at most some of the signal lines (SL) overlap the edge part (EP), the number of the signal lines (SL) overlapping the edge part (EP) being less than the number of the signal lines (SL) located in the gap (SHH).

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Currently, display panels that use independent light-emitting devices to achieve direct display are widely used. The light-emitting devices can be organic light-emitting diodes (OLEDs), etc. Existing display panels may have display anomalies, and display panels with touch functions may also have touch anomalies.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] The present disclosure provides a display panel and a display device.

[0006] According to one aspect of the present disclosure, a display panel is provided, comprising a display area and a peripheral area outside the display area; the display panel comprises:

[0007] A display substrate comprising a plurality of light-emitting devices located in the display area and a barrier dam located in the peripheral area; the display substrate is provided with a separation groove located in the peripheral area and surrounding the display area; a portion of the display substrate located on a side of the separation groove away from the display area is an edge portion; the barrier dam is provided in the separation groove and surrounds the display area, with a gap between the outermost barrier dam and the edge portion;

[0008] an encapsulation layer covering each of the light-emitting devices; the encapsulation layer comprising a first inorganic layer and a second inorganic layer distributed in a direction away from the display substrate, and an organic layer disposed between the first inorganic layer and the second inorganic layer; the first inorganic layer and the second inorganic layer covering the barrier dam and extending at least into the gap; the organic layer being located on a side of the barrier dam close to the light-emitting device;

[0009] A plurality of signal lines are arranged on a side of the packaging layer away from the display substrate; each of the signal lines extends to the peripheral area, and at least part of the areas of some of the signal lines are located in the gap; at most at least part of the areas of some of the signal lines overlap with the edge portion, and the number of the signal lines overlapping with the edge portion is less than the number of the signal lines located in the gap.

[0010] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0011] A touch layer is provided on a side of the packaging layer away from the display substrate; the touch layer includes a plurality of touch electrodes located in the display area;

[0012] Each of the signal lines includes a plurality of touch leads located in the touch layer, the touch leads are connected to the touch electrodes; and at least part of the areas of some of the touch leads are located in the gap; at most at least part of the areas of some of the touch leads overlap with the edge portion, and the number of the touch leads overlapping with the edge portion is less than the number of the touch leads located in the gap.

[0013] In an exemplary embodiment of the present disclosure, the first inorganic layer and the second inorganic layer extend onto the edge portion, and the touch wire overlapping the edge portion is located on a surface of the second inorganic layer away from the edge portion.

[0014] In an exemplary embodiment of the present disclosure, a boundary between the first inorganic layer and the second inorganic layer is located within the gap.

[0015] In an exemplary embodiment of the present disclosure, at least a portion of the touch wire located in the gap is located between a boundary between the first inorganic layer and the second inorganic layer and the edge portion.

[0016] In an exemplary embodiment of the present disclosure, the number of the signal lines overlapping the edge portion is at most two.

[0017] In an exemplary embodiment of the present disclosure, each of the signal lines further includes a plurality of test lines located in the peripheral area, the test lines are located outside the touch leads, and at least a portion of the test lines overlaps with the edge portion.

[0018] In an exemplary embodiment of the present disclosure, the number of the signal lines overlapping the edge portion is two, and a distance between the two signal lines overlapping the edge portion is greater than a distance between two adjacent signal lines in the gap.

[0019] In an exemplary embodiment of the present disclosure, at least partial areas of the two test lines are located in different layers.

[0020] In an exemplary embodiment of the present disclosure, the touch layer further includes dummy leads, at least a portion of the dummy leads overlaps with the barrier dam and is located between the touch leads.

[0021] In an exemplary embodiment of the present disclosure, the peripheral area is surrounded by a fan-out area and a peripheral area, and the separation groove and the barrier dam both pass through the fan-out area and the peripheral area; one end of any of the touch leads is connected to the touch electrode, and the other end extends to the fan-out area;

[0022] Parts of the touch leads located in the fan-out area are located in the gap, and at most parts of the touch leads located in the fan-out area overlap with the edge portion.

[0023] According to one aspect of the present disclosure, a display panel is provided, comprising a display area and a peripheral area outside the display area; the display panel comprises:

[0024] A display substrate comprising a plurality of light-emitting devices located in the display area and a barrier dam located in the peripheral area; the display substrate is provided with a separation groove located in the peripheral area, the separation groove being arranged around the display area, and a portion of the display substrate located on a side of the separation groove away from the display area being an edge portion; the barrier dam is provided in the separation groove and is arranged around the display area, with a gap between the outermost barrier dam and the edge portion;

[0025] an encapsulation layer covering each of the light-emitting devices; the encapsulation layer comprising a first inorganic layer and a second inorganic layer distributed in a direction away from the display substrate, and an organic layer disposed between the first inorganic layer and the second inorganic layer; the first inorganic layer and the second inorganic layer covering the barrier dam and extending at least into the gap; the organic layer being located on a side of the barrier dam close to the light-emitting device;

[0026] a flat covering layer, provided on a side of the encapsulation layer away from the display substrate and covering the edge portion;

[0027] A plurality of signal lines are arranged on a side of the packaging layer away from the display substrate; each of the signal lines extends to the peripheral area, and at least part of the signal lines is stacked on a surface of the flat cover layer away from the display substrate.

[0028] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0029] A touch layer is provided on a side of the packaging layer away from the display substrate; the touch layer includes a plurality of touch electrodes located in the display area;

[0030] Each of the signal lines includes a plurality of touch leads located in the touch layer, the touch leads are connected to the touch electrodes, and at least a portion of the touch leads is stacked on a surface of the flat cover layer away from the display substrate.

[0031] In an exemplary embodiment of the present disclosure, the first inorganic layer and the second inorganic layer extend onto the edge portion; and the flat cover layer covers the second inorganic layer on the edge portion and the edge portion.

[0032] In an exemplary embodiment of the present disclosure, a boundary of the flat cover layer is located within a boundary of the edge portion.

[0033] In an exemplary embodiment of the present disclosure, the flat cover layer has an inner boundary close to the display area and an outer boundary away from the display area, wherein the inner boundary is located within the separation groove and the outer boundary is located within the boundary of the edge portion.

[0034] In an exemplary embodiment of the present disclosure, the flat cover layer has an inner boundary close to the display area and an outer boundary away from the display area, wherein the inner boundary is located between the separation groove and the display area, and the outer boundary is located within the boundary of the edge portion.

[0035] In an exemplary embodiment of the present disclosure, a surface of the flat cover layer away from the display substrate is not higher than a surface of a region of the encapsulation layer located in the display area away from the display substrate.

[0036] In an exemplary embodiment of the present disclosure, the distance between the flat cover layer and the display area is not less than 20 μm.

[0037] According to one aspect of the present disclosure, a display panel is provided, comprising a display area and a peripheral area outside the display area; the display panel comprises:

[0038] A display substrate comprising a plurality of light-emitting devices located in the display area and a barrier dam located in the peripheral area; the display substrate is provided with a separation groove located in the peripheral area, the separation groove being arranged around the display area, and a portion of the display substrate located on a side of the separation groove away from the display area being an edge portion; the barrier dam is provided in the separation groove and is arranged around the display area, with a gap between the outermost barrier dam and the edge portion;

[0039] a supporting layer, stacked on the edge portion and not completely covering the edge portion;

[0040] an encapsulation layer covering each of the light-emitting devices and a portion of the support layer; the encapsulation layer comprising a first inorganic layer and a second inorganic layer distributed in a direction away from the display substrate, and an organic layer disposed between the first inorganic layer and the second inorganic layer; the first inorganic layer and the second inorganic layer covering the barrier dam and extending at least into the gap; the organic layer being located on a side of the barrier dam close to the light-emitting device;

[0041] A plurality of signal lines are arranged on a side of the packaging layer away from the display substrate; each of the signal lines extends to the peripheral area, and at least a portion of the signal lines is stacked in an area of ​​the edge portion not covered by the support layer.

[0042] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0043] A touch layer is provided on a side of the packaging layer away from the display substrate; the touch layer includes a plurality of touch electrodes located in the display area;

[0044] Each of the signal lines includes a plurality of touch leads located in the touch layer, and the touch leads are connected to the touch electrodes; each of the touch leads extends to the peripheral area, and at least part of some of the touch leads is stacked in the area of ​​the edge portion not covered by the supporting layer.

[0045] In an exemplary embodiment of the present disclosure, the supporting layer is located within the boundary of the edge portion close to and away from the boundary of the display area; the supporting layer has a groove that exposes the edge portion and surrounds the display area; and at least a portion of the touch lead is located within the groove.

[0046] In an exemplary embodiment of the present disclosure, the first inorganic layer and the second inorganic layer extend to a surface of the support layer away from the display substrate, and are located on a side of the groove close to the display area.

[0047] In an exemplary embodiment of the present disclosure, the touch layer includes a first conductive layer and a second conductive layer distributed in a direction away from the display substrate;

[0048] The touch lead is located in at least one of the first conductive layer and the second conductive layer.

[0049] In an exemplary embodiment of the present disclosure, the depth of the separation groove is less than the thickness of the display substrate; the edge portion includes a plurality of stacked sub-layers, and at least part of the sub-layers are made of organic material.

[0050] According to one aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above.

[0051] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0053] FIG1 is a schematic diagram of various regions of an embodiment of a display panel according to the present disclosure.

[0054] FIG2 is a schematic cross-sectional view of an embodiment of a display panel according to the present disclosure.

[0055] FIG3 is a schematic cross-sectional view of a display substrate of an embodiment of a display panel disclosed herein.

[0056] FIG4 is a schematic diagram showing the distribution of a touch layer and signal lines of an embodiment of a display panel disclosed herein.

[0057] FIG5 is a schematic cross-sectional view of a first embodiment of the first conception of the present disclosure.

[0058] FIG6 is a partially enlarged view of a fan-out area of ​​a first embodiment under the first concept of the present disclosure.

[0059] FIG7 is a schematic cross-sectional view of a second embodiment of the first concept of the present disclosure.

[0060] FIG8 is a partially enlarged view of a fan-out area of ​​a second embodiment under the first conception of the present disclosure.

[0061] FIG9 is a schematic cross-sectional view of a first embodiment of the second concept of the present disclosure.

[0062] FIG10 is a schematic cross-sectional view of a second embodiment of the second concept of the present disclosure.

[0063] FIG11 is a schematic cross-sectional view of a third embodiment of the second conception of the present disclosure.

[0064] FIG12 is a schematic cross-sectional view of an embodiment of the third concept of the present disclosure. DETAILED DESCRIPTION

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0066] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0067] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0068] The row direction X and column direction Y herein are two intersecting directions. In the drawings of this disclosure, the row direction X is horizontal and the column direction Y is vertical, and the two are perpendicular to each other. However, this is not limiting. The row direction X and the column direction Y may also be non-perpendicular. Furthermore, those skilled in the art will appreciate that, as the display panel rotates, the actual orientations of the row direction X and the column direction Y may change, but their relative positions remain unchanged.

[0069] In this article, the "overlap" of feature A and feature B means that the orthographic projection of feature A on a plane and the orthographic projection of feature B on the same plane at least partially overlap; the plane can be the surface of the substrate, the surface of the backlight side of the display substrate, or other plane parallel to the substrate.

[0070] In this article, A and B are "set in the same layer" means that A and B belong to different continuous or disconnected regions in the same film layer, and each region can be formed at the same time; A and B are located in "different layers" means that A and B belong to different film layers, and different film layers refer to film layers that are not formed at the same time.

[0071] Embodiments of the present disclosure provide a display panel, as shown in FIG1 . The display panel includes a display area AA and a peripheral area WA located outside the display area AA. The peripheral area WA can be a continuous annular area surrounding the display area AA, or it can be a discontinuous area surrounding the display area AA. For example, the peripheral area WA can be located on both sides of the display area AA. The display area AA can be configured to emit light to display images, while the peripheral area WA does not emit light.

[0072] In some embodiments of the present disclosure, the peripheral area WA is a continuous annular area surrounding the display area AA, which can be surrounded by the fan-out area FA and the peripheral area. The fan-out area FA has a binding portion PA, and the binding portion PA can have multiple conductive contacts, which can be bound to the driving chip through the conductive contacts. At the same time, at least part of the conductive contacts of the binding portion PA can be connected to a flexible circuit board, and the flexible circuit board can be connected to a control circuit board, thereby realizing the connection between the display panel and the control circuit board. The display panel can be controlled to display images through the control circuit board and the driving chip.

[0073] In some embodiments, the display area AA may have a rectangular outline, and the peripheral area WA is a rectangular ring structure surrounded by two end areas and two side areas EA. The two side areas EA are distributed on both sides of the display area AA along the row direction X, and the two end areas DA are distributed at both ends of the display area AA along the column direction Y. One end area DA is the aforementioned fan-out area FA, that is, the fan-out area FA and the display area AA are distributed along the column direction Y. The two side areas EA and the end area DA constitute the peripheral area.

[0074] Furthermore, in some embodiments, the fan-out area FA may include a bending area BA extending along the row direction X. The bending area BA is a flexible, bendable structure, and the binding portion PA is located on the side of the bending area BA away from the display area AA. By bending the bending area BA, the fan-out area FA can be bent toward the backlight side of the display panel, i.e., the side opposite the light-emitting direction; thus, the flexible printed circuit board can be connected to the control circuit board on the backlight side of the display panel.

[0075] Of course, in other embodiments of the present disclosure, the fan-out area FA may not be provided with the bending area BA, and the flexible circuit board may be bent to connect the flexible circuit board to the control circuit board on the backlight side of the display panel.

[0076] The display panel includes a display substrate PNL and an encapsulation layer TFE, wherein:

[0077] As shown in FIG1 to FIG3 , the display substrate PNL includes a driving backplane BP and a plurality of light-emitting devices LD provided on one side of the driving backplane BP, wherein:

[0078] The driving backplane BP includes a driving circuit that drives the light-emitting devices LD to emit light, thereby displaying images. In some embodiments of the present disclosure, the driving backplane BP may include a substrate SU and a circuit layer CL located on one side of the substrate SU. The substrate SU may be a flat plate made of either a rigid material such as glass or a flexible material such as polyimide. Furthermore, the substrate SU may have a single-layer or multi-layer structure.

[0079] The circuit layer CL includes the aforementioned drive circuit. For example, the drive circuit may include a pixel circuit located in the display area AA and a peripheral circuit located in the peripheral area WA. The pixel circuit may have a 7T1C, 8T1C, or other structure, as long as it can drive the light-emitting device LD to emit light. There is no specific limitation on its structure. Here, nTmC indicates that a pixel circuit includes n thin-film transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). The number of pixel circuits may be the same as the number of light-emitting devices LD, and each light-emitting device LD is connected in a one-to-one correspondence. Of course, the same pixel circuit may also be connected to multiple light-emitting devices LD, and this is not specifically limited here.

[0080] The peripheral circuit is connected to the pixel circuit and is used to input drive signals to the pixel circuit to control the light-emitting device LD to emit light. The peripheral circuit may include a gate drive circuit and a light-emission control circuit. Of course, it may also include other circuits. The specific structure of the peripheral circuit is not particularly limited here. The gate drive circuit and the light-emission control circuit may be located in the side area.

[0081] The aforementioned driving circuit may include multiple thin-film transistors and capacitors. The thin-film transistors may be top-gate or bottom-gate thin-film transistors. Each thin-film transistor may include an overlapping active layer and a gate electrode. The active layers of each thin-film transistor may be disposed in the same semiconductor layer. Alternatively, the active layers may be disposed in multiple semiconductor layers, with the active layers of different thin-film transistors located in different semiconductor layers. The semiconductor layer may be made of polycrystalline silicon or a metal oxide, without particular limitation.

[0082] The circuit layer CL may also include wiring for transmitting signals connected to the pixel circuits and peripheral circuits. For example, a column of pixel circuits may be connected to a data line extending along the column direction Y, and a data signal may be transmitted through the data line. The data line may extend to the fan-out area FA and be connected to the binding part PA. The gate drive circuit and the light-emitting control circuit may be connected to multiple wirings such as the clock signal line SL. These wirings may also extend to the fan-out area FA and be connected to the binding part PA.

[0083] As shown in Figure 2, taking the top-gate thin film transistor as an example, in some embodiments, the circuit layer CL may include a semiconductor layer SE, a first gate insulation layer GI1, a first gate layer GA1, a second gate insulation layer GI2, a second gate layer GA2, an interlayer dielectric layer ILD, a first source and drain layer SD1, a passivation layer, a first flat layer PLN1, a second source and drain layer SD2, and a second flat layer PLN2, which are stacked in sequence along a direction away from the substrate SU. The active layer of the thin film transistor is located in the semiconductor layer SE, the gate is located in the first gate layer GA1, and the two plates of the capacitor are located in the first gate layer GA1 and the second gate layer GA2. The first source and drain layer SD1 and the second source and drain layer SD2 are used to achieve connection between at least part of the thin film transistors and between the thin film transistors and the capacitors, and are used to transmit driving signals. The type of driving signal and the specific pattern of each film layer depend on the specific composition of the driving circuit and are not specifically limited here.

[0084] In other embodiments, based on the above embodiments, the circuit layer CL may further include a third source and drain layer and a third flat layer. The third source and drain layer is arranged on the surface of the second flat layer away from the substrate, and the third flat layer covers the third source and drain layer. The third source and drain layer is also used to achieve connection between at least part of the thin film transistors and between the thin film transistors and capacitors. The specific pattern depends on the specific structure of the driving circuit.

[0085] In other embodiments, the circuit layer CL may not include the aforementioned second source / drain layer, second planarization layer, third source / drain layer, and third planarization layer, but may instead include only a semiconductor layer, a first gate insulation layer, a first gate layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, a first source / drain layer, a passivation layer, and a first planarization layer stacked in sequence in a direction away from the substrate SU. In other words, the circuit layer CL may include at least one source / drain layer and one planarization layer.

[0086] The light-emitting device LD can be an OLED (organic light-emitting diode) using organic light-emitting materials, or a Mini LED (sub-millimeter light-emitting diode, 100μm-200μm in size), a Micro LED (micro light-emitting diode, 100μm or less in size), or an LED (light-emitting diode, 200μm or greater in size) using inorganic light-emitting materials, without any particular limitation herein, as long as it can emit light. The light-emitting device LD is located within the display area AA. Of course, some light-emitting devices LD may also be located in the peripheral area WA, but the light-emitting devices LD located in the peripheral area WA may be floating and thus not emit light.

[0087] As shown in Figures 3 and 5, taking the light-emitting device LD as an example of an OLED, the light-emitting device LD may include a first electrode ANO, a light-emitting layer EL, and a second electrode CAT stacked in sequence in a direction away from the driving backplane BP. By applying an electrical signal to the first electrode ANO and the second electrode CAT, the light-emitting layer EL can be stimulated to emit light. The specific light-emitting principle will not be described in detail here. The first electrode ANO can be used as an anode, and the second electrode CAT can be used as a cathode. The materials of the two include conductive materials such as metals and metal oxides. The light-emitting layer EL may include a hole injection layer, a hole transport layer, a light-emitting material layer, an electron transport layer, and an electron injection layer stacked in sequence in a direction away from the driving backplane BP. Of course, other structures can also be used as long as they can cooperate with the first electrode ANO and the second electrode CAT to emit light.

[0088] As shown in Figures 3 and 5 , the display substrate may further include a pixel definition layer PDL that separates the light-emitting devices LD. The pixel definition layer PDL and the light-emitting devices LD may be disposed on the same surface of the driving backplane BP. For example, the pixel definition layer PDL and the first electrodes ANO may be disposed on a surface of the third planar layer away from the substrate SU. The pixel definition layer PDL is thicker than the first electrodes ANO and covers a portion of each first electrode ANO. The pixel definition layer PDL has pixel openings that expose each first electrode ANO, with each pixel opening exposing one first electrode ANO.

[0089] As shown in Figures 3 and 5, the light-emitting layer EL and the second electrode CAT are sequentially stacked on the first electrode ANO within the pixel opening. In some embodiments, the light-emitting layer EL has a discontinuous structure, with the light-emitting layer EL of each light-emitting device LD independently spaced apart. This allows different light-emitting devices LD to emit different colors. The second electrode CAT has a continuous, single-layer structure, with the portion of the second electrode CAT located within the pixel opening covering the light-emitting layer EL. The portion of the second electrode CAT located outside the pixel opening may also cover the pixel definition layer PDL. The combined thickness of the light-emitting layer EL and the second electrode CAT is less than the thickness of the pixel definition layer PDL, resulting in the second electrode CAT being recessed within the pixel opening.

[0090] As shown in Figures 3 and 5, each light-emitting device LD is defined by the pixel definition layer PDL. The extent of the pixel opening corresponds to the extent of the light-emitting device LD. In other words, the shape and size of the orthographic projection of the pixel opening on the substrate SU correspond to the shape and size of the orthographic projection of the light-emitting device LD on the substrate SU. Furthermore, the shape of the pixel opening corresponds to the shape of its orthographic projection on the driver backplane BP and substrate SU, and can be a polygon such as a rectangle, or a circle.

[0091] As shown in FIG. 2 , FIG. 3 and FIG. 5 , the display substrate PNL may further include a barrier dam DAM and an encapsulation layer TFE, wherein:

[0092] The blocking dam DAM is located in the peripheral area WA, which can be an annular ridge structure surrounding the display area AA. The number of blocking dams DAM can be one, two or more, and they are distributed in sequence in the direction away from the display area AA, and the outer blocking dam DAM is larger than the inner blocking dam DAM.

[0093] The barrier dam DAM can be directly formed on the surface of the driving backplane BP, or it can be formed using a portion of the display substrate's film layer to simplify the process. For example, the display substrate can be provided with a separation trench SH located in the peripheral area WA. The separation trench SH can be an annular groove surrounding the display area AA, and the barrier dam DAM is disposed within and extends along the separation trench SH. The depth of the separation trench SH is less than the thickness of the display substrate, so that the separation trench SH only partially interrupts the display substrate's film layer, rather than completely terminating the display substrate. Alternatively, it can be understood that the separation trench SH is formed by partially disconnecting the display substrate's film layer.

[0094] As shown in Figures 2, 3, and 5, the separation groove SH is divided into two parts on the display substrate. The inner portion of the separation groove SH can be defined as the center portion, and the outer portion of the separation groove SH (i.e., the side away from the display area AA) can be defined as the edge portion EP. In some embodiments, the edge portion EP may include multiple stacked sublayers, at least some of which are made of organic materials. The organic material can be a resin such as optical adhesive, which is not particularly limited here.

[0095] As shown in Figures 2, 3, and 5, a gap SHH is defined between the barrier dam DAM and the edge portion EP. For example, if there is only one barrier dam DAM, a gap SHH is defined between the barrier dam DAM and the edge portion EP. If there are two or more barrier dams DAM, a gap SHH is defined between the outermost barrier dam DAM and the edge portion EP. The width of the gap SHH, i.e., the distance between the barrier dam DAM closest to the edge portion EP and the edge portion EP, can be defined as the distance between the barrier dam DAM and the edge portion EP. If there are two or more barrier dams DAM, this distance can be greater than the distance between two adjacent barrier dams DAM; the thickness of the outer barrier dam DAM is greater than the thickness of the inner barrier dam DAM.

[0096] As shown in FIG5 , in some embodiments of the present disclosure, there are two barrier dams DAM, namely a first barrier dam DAM1 and a second barrier dam DAM2. The first barrier dam DAM1 is located inside the second barrier dam DAM2, and the second barrier dam DAM2 is thicker than the first barrier dam DAM1. Furthermore, the distance between the second barrier dam DAM2 and the edge portion EP is greater than the distance between the first barrier dam DAM1 and the second barrier dam DAM2.

[0097] In some embodiments of the present disclosure, the barrier dam DAM and the edge portion EP may be formed simultaneously when forming a portion of the film layer in the center portion. The barrier dam DAM may be a multi-layer structure and may be formed simultaneously with the planar layer of the driving backplane BP and the pixel definition layer PDL. For example:

[0098] In some embodiments, the blocking dam DAM includes the first blocking dam DAM1 and the second blocking dam DAM2 mentioned above; the flat layer of the driving backplane has two layers, namely the first flat layer and the second flat layer mentioned above, then the edge portion EP may include at least two sub-layers, and the two sub-layers are respectively arranged on the same layer with the first flat layer PLN1 and the second flat layer PLN2; the first blocking dam DAM1 may be a single-layer structure, which may be arranged on the same layer with the second flat layer PLN2 so as to be formed at the same time; the second blocking dam DAM2 may be a multi-layer structure, in which there is a layer that can be arranged on the same layer with the second flat layer PLN2, and there is another layer that can be arranged on the same layer with the pixel definition layer PDL so as to be formed at the same time, and the thickness of the second blocking dam DAM2 can be greater than the thickness of the first blocking dam DAM1.

[0099] In some embodiments, the barrier dam DAM includes the first barrier dam DAM1 and the second barrier dam DAM2 mentioned above. The driving backplane has three planar layers, namely the first to third planar layers mentioned above. The edge portion EP may include at least three sublayers, each of which is disposed co-located with the first to third planar layers. The first barrier dam DAM1 may be a single-layer structure, co-located with the third planar layer for simultaneous formation. The second barrier dam DAM2 may be a multi-layer structure, with one layer co-located with the third planar layer and another layer co-located with the pixel definition layer (PDL) for simultaneous formation. Furthermore, the thickness of the second barrier dam DAM2 may be greater than that of the first barrier dam DAM1.

[0100] Of course, in other embodiments, based on the above embodiments, the edge portion EP may further include a sublayer provided in the same layer as the pixel definition layer PDL.

[0101] As shown in Figures 2, 3, and 5, the encapsulation layer TFE can cover each light-emitting device LD to block external moisture and oxygen and prevent the light-emitting device LD from being corroded. The encapsulation layer TFE can be a thin film encapsulation method, which may include a first inorganic layer CVD1, an organic layer IJP, and a second inorganic layer CVD2, wherein:

[0102] The first inorganic layer CVD1 can cover each light-emitting device LD, that is, the first inorganic layer CVD1 can cover the surface of the second electrode CAT away from the driving backplane BP. For the second electrode CAT with an interrupted structure, the first inorganic layer CVD1 can also cover the area of ​​the pixel definition layer PDL not covered by the second electrode CAT. The thickness of the first inorganic layer CVD1 is less than the thickness of the pixel definition layer PDL and can be recessed at the pixel opening. The material of the first inorganic layer CVD1 can include inorganic insulating materials such as silicon nitride and silicon oxide. The thickness of the first inorganic layer CVD1 is less than the thickness of the blocking dam DAM, covers the blocking dam DAM, and extends at least into the above-mentioned gap SHH. In other words, the boundary of the first inorganic layer CVD1 can be located within the gap SHH, or the first inorganic layer CVD1 can extend to the edge portion EP away from the surface of the driving backplane BP, so that the boundary of the first inorganic layer CVD1 is located outside the gap SHH.

[0103] The organic layer IJP can be disposed on the surface of the first inorganic layer CVD1 away from the driving backplane BP. With the barrier dam DAM blocking the organic layer IJP, its boundary is located inside the barrier dam DAM, i.e., on the side closer to the display area. The boundary of the orthographic projection of the organic layer IJP on the driving backplane BP can be located in the peripheral area WA, ensuring that the organic layer IJP covers all light-emitting devices LD. It should be noted that due to factors such as process tolerances, in the presence of multiple barrier dams DAM, the organic layer IJP may extend over some of the barrier dams DAM, at least not over the outermost barrier dams DAM.

[0104] The second inorganic layer CVD2 can cover the organic layer IJP and the first inorganic layer CVD1 not covered by the organic layer IJP. The second inorganic layer CVD2 can block the intrusion of water and oxygen, and achieve flattening through the organic layer IJP that has fluidity before solidification. The material of the second inorganic layer CVD2 may include inorganic insulating materials such as silicon nitride and silicon oxide. The thickness of the second inorganic layer CVD2 is less than the thickness of the blocking dam DAM, and covers the blocking dam DAM, and at least extends to the above-mentioned gap SHH, that is, the boundary of the second inorganic layer CVD2 can be located within the gap SHH; or, the second inorganic layer CVD2 can extend to the edge portion EP away from the surface of the driving backplane BP, so that the boundary of the second inorganic layer CVD2 is located outside the gap SHH. Furthermore, the boundary of the second inorganic layer CVD2 can be aligned with the boundary of the first inorganic layer CVD1.

[0105] The display substrate PNL may further include a plurality of support pillars stacked on the pixel definition layer PDL, and at least a portion of the support pillars is located in the display area AA for supporting a mask for forming the light emitting layer EL.

[0106] As shown in Figures 2-4 , in some embodiments of the present disclosure, the display panel may further include a touch layer TPS, which may be disposed on a side of the encapsulation layer TFE away from the driver backplane BP. The touch layer TPS may include multiple touch electrodes located in the display area AA for sensing touch operations. Furthermore, to transmit touch signals, the display panel may further include multiple touch leads HL. Each touch lead HL is at least partially located in the peripheral area WA, with one end connected to a touch electrode and the other end connected to the binding portion PA for transmitting touch signals. The driver chip bound to the binding portion PA processes the touch signals to implement touch functionality.

[0107] As shown in Figures 2 and 4 , taking the mutual capacitance touch structure of the touch layer TPS as an example, the touch electrodes of the touch layer TPS may include multiple first touch electrodes Tx and multiple second touch electrodes Rx. Each first touch electrode Tx may be spaced apart along the row direction X. A first touch electrode Tx includes multiple first electrode blocks Txc connected in series along the column direction Y. A second touch electrode Rx may include multiple second electrode blocks Rxc spaced apart along the row direction X and a transfer bridge Rxb connecting two adjacent second electrode blocks Rxc. Each second touch electrode Rx may be spaced apart along the column direction Y. A transfer bridge Rxb intersects with a first touch electrode Tx and is insulated from the first touch electrode Tx. One of the first touch electrode Tx and the second touch electrode Rx may function as a transmitting electrode, and the other as a receiving electrode. Both are connected to the touch drive circuit in the peripheral area WA.

[0108] As shown in Figure 4 , each touch electrode can be connected to two touch leads HL simultaneously. For example, the two ends of a first touch electrode Tx are connected to two touch leads HL respectively. One touch lead HL can extend from an end area DA away from the fan-out area FA through the side area EA to the fan-out area FA, while the other touch lead HL can extend directly to the fan-out area FA. The two ends of a second touch electrode Rx are also connected to two touch leads HL respectively, extending from the two side areas EA to the fan-out area FA, and can be arranged symmetrically.

[0109] As shown in FIG2 , taking a mutual capacitance touch structure as an example, the touch layer TSP may include a buffer layer TLD, a first conductive layer TMA, an isolation layer SEP, and a second conductive layer TMB distributed in a direction away from the driving backplane BP, wherein:

[0110] The buffer layer TLD may be disposed on a surface of the encapsulation layer TFE away from the driving backplane BP. The material of the buffer layer TLD may be insulating materials such as silicon nitride and silicon oxide, and is not particularly limited here.

[0111] The first conductive layer TMA may include the transfer bridge Rxb, and the specific pattern is not particularly limited herein. The isolation layer SEP may at least cover the transfer bridge Rxb of the first conductive layer TMA, and the isolation layer SEP may be made of inorganic insulating materials such as silicon nitride and silicon oxide.

[0112] The second conductive layer TMB may include the aforementioned second electrode blocks Rxc and first touch electrodes Tx. That is, the second electrode blocks Rxc and first touch electrodes Tx are arranged on the same layer and can be formed simultaneously using the same process. Furthermore, the second conductive layer TMB has a mesh structure with multiple meshes, with each mesh overlapping a light-emitting device LD, allowing light emitted by the light-emitting device LD to be emitted through the meshes. The meshes and light-emitting devices LD can have a one-to-one correspondence; alternatively, a single mesh may overlap with multiple light-emitting devices LD simultaneously, meaning that the orthographic projections of the multiple light-emitting devices LD on the driver backplane BP are within the orthographic projection of the same mesh on the driver backplane BP, as long as light emitted by the light-emitting device LD can be emitted.

[0113] Both the first conductive layer TMA and the second conductive layer TMB may be made of conductive materials such as metals and metal oxides, and both may be single-layer or multi-layer structures. Taking the second conductive layer TMB of the multi-layer structure as an example, it may include a first conductive material layer, a second conductive material layer, and a third conductive material layer stacked in sequence in a direction away from the driving backplane BP. The material of the second conductive material layer is different from that of the first conductive material layer and the third conductive material layer, and the resistivity of the second conductive material layer is lower than that of the first conductive material layer and the third conductive material layer. The chemical stability of the first conductive material layer and the third conductive material layer is higher than that of the second conductive material layer. For example, the material of the second conductive material layer is aluminum, silver, etc., and the material of the first conductive material layer and the third conductive material layer is titanium, titanium oxide, indium tin oxide (ITO), etc. For example, the material of the first conductive material layer and the third conductive material layer is titanium, and the material of the second conductive material layer is aluminum; or the material of the first conductive material layer and the third conductive material layer is indium tin oxide, and the material of the second conductive material layer is silver.

[0114] In some other embodiments of the present disclosure, the first electrode block Txc and the second electrode block Rxc may also be located in the first conductive layer TMA, and the transfer bridge Rxb may be located in the second conductive layer TMB.

[0115] In addition, as shown in FIG. 2 , in some embodiments of the present disclosure, the display panel may further include a protection layer TOC covering the second conductive layer TMB, which may be made of an organic material such as resin to achieve planarization.

[0116] In other embodiments of the present disclosure, a self-capacitive touch structure may also be used, and the touch layer may include a plurality of electrode blocks arranged in an array on the same layer, and the touch operation is sensed separately by each electrode block.

[0117] The touch leads HL can have a single-layer structure. For example, they can be located in the first conductive layer TMA or the second conductive layer TMB. Different touch leads HL can be located in different layers. For example, one of adjacent touch leads HL can be located in the first conductive layer TMA, while the other can be located in the second conductive layer TMB. This reduces the risk of short circuits between adjacent touch leads HL. Of course, portions of two adjacent touch leads HL can also be located in different layers.

[0118] As shown in Figures 1 and 4 , the display panel has multiple signal lines SL. At least some of the signal lines SL are located on the side of the encapsulation layer TFE away from the display substrate. Each signal line SL extends to the peripheral area WA and is connected to the binding portion PA. These signal lines SL may include at least some of the touch leads HL, data lines, and traces connecting to peripheral circuits mentioned above.

[0119] The signal lines SL may further include multiple test lines PCL located in the peripheral area WA. The test lines PCL are located outside the touch leads HL and the touch lines, i.e., away from the display area AA. They may be connected to the binding portion PA and the data lines. When the test lines PCL are disconnected and connected, the display area AA may display different images. This allows the test lines PCL to detect cracks on the edge of the display panel. There may be multiple test lines PCL, distributed away from the display area AA.

[0120] Furthermore, if there are two test lines PCL outside the touch lead HL, at least part of the two test lines PCL can be located in different layers. For example, the test line PCL can be formed using the first conductive layer TMA and the second conductive layer TMB. Both test lines PCL are partially located in the first conductive layer TMA and partially located in the second conductive layer TMB; thereby reducing the risk of short circuit and achieving an anti-ESD effect.

[0121] In the fan-out area FA, the touch lead HL connected to the first touch electrode Tx is located inside the touch lead HL connected to the second touch electrode Rx, and the test line PCL is located outside the touch lead HL connected to the second touch electrode Rx.

[0122] In addition, as shown in FIG4 , the display panel may further include a shielding line GNL and an isolation line GUL, wherein:

[0123] There can be one or more shielding lines GNL, and they can be located outside the test lines PCL, away from the display area AA. They can also be located between the test lines PCL and the touch lines, or between adjacent touch lines. The shielding lines GNL can be connected to the binding portion PA and connected to the ground signal, thereby providing signal shielding and providing ESD protection.

[0124] The isolation line GUL can be used to isolate the touch lead HL connected to the first touch electrode Tx from the touch lead HL connected to the second touch electrode Rx. It can be located between the touch lead HL connected to the first touch electrode Tx and the touch lead HL connected to the second touch electrode Rx, which are the closest. It can transmit a signal synchronized with the transmitting electrode (the touch electrode that receives the signal from the binding portion PA, i.e., the first touch electrode Tx or the second touch electrode Rx) to the isolation line GUL, thereby reducing damage to the touch lead HL caused by electron migration due to the voltage difference between the two touch leads HL. Of course, the isolation line GUL can also be provided between other signal lines SL that have a voltage difference and are relatively close to each other.

[0125] The inventors discovered that display panels in related technologies sometimes exhibit display anomalies or touch failures. After experiments and analysis, the inventors concluded that because some signal lines SL are formed on the edge portion EP, when a mask is used to form the light-emitting layer EL, the second electrode CAT, the first inorganic layer CVD1, etc., the mask will scratch the surface of the edge portion EP, making the surface uneven. When forming the signal lines SL thereon through a photolithography process, it is difficult to ensure that the area between adjacent signal lines SL is completely removed, resulting in a short circuit between adjacent signal lines SL, affecting the display and touch functions. Therefore, the inventors have proposed various concepts to reduce the risk of short circuits in the signal lines SL, which are exemplified below:

[0126] The first concept

[0127] As shown in Figures 5 to 8, the number of signal lines SL on the edge portion EP can be reduced by setting more signal lines SL in the gap SHH, thereby reducing the risk of short circuit. In some embodiments of the present disclosure, at least part of the area of ​​at most some of the signal lines SL can overlap with the edge portion, for example, be set on the surface of the edge portion EP away from the substrate SU. At least part of the area of ​​some of the signal lines SL is located in the gap SHH, for example, be set on the bottom surface of the separation groove SH, and the film layer on which the bottom surface is located depends on the depth of the separation groove SH, which is not specifically limited here. Among them, the number of signal lines SL overlapping with the edge portion EP is less than the number of signal lines SL located in the gap SHH, thereby reducing the risk of short circuit of the signal lines SL on the edge portion EP due to scratches by the mask.

[0128] In some embodiments of the present concept, no signal line SL may overlap the edge portion EP. The number of signal lines SL overlapping the edge portion EP may be one or two, and at most two. Furthermore, the number of signal lines SL overlapping the edge portion is two. To further reduce the risk of short circuits, the spacing between the two signal lines SL overlapping the edge portion may be greater than the spacing between two adjacent signal lines SL within the gap SHH.

[0129] Furthermore, the portion of the touch lead HL located in the fan-out area FA is located in the gap SHH, and at most the portion of the touch lead HL located in the fan-out area FA overlaps with the edge portion EP.

[0130] In some embodiments of the present concept, the test lines PCL are located outside the touch leads HL, and at least a portion of one or more test lines PCL may overlap with the edge portion EP. For example, there may be two test lines PCL, and at most one test line PCL may overlap with the edge portion. That is, at least a portion of the test lines PCL is located within the gap SHH. Accordingly, the touch leads HL do not overlap with the edge portion, with the outermost touch leads HL located within the gap SHH. Of course, in some embodiments, each test line PCL may overlap with the edge portion EP, while the touch leads HL located inside the test lines PL do not overlap with the edge portion EP. The step created by the edge portion EP can be used to separate the two, reducing the risk of short circuits. Furthermore, because the circuits used to detect cracks via the test lines PCL are different from the circuits connected to the touch leads HL, the test lines PCL can receive the same signals. Therefore, even if a short circuit occurs, the test function is not affected. Furthermore, the touch leads HL do not overlap with the edge portion EP, leaving a larger space at the edge portion EP. This can reduce the risk of short circuits by increasing the spacing between the test lines PCL. For example, the pitch of the test lines PCL is made larger than the pitch of the touch leads HL.

[0131] As shown in Figures 5 and 6, in a first embodiment of the present concept, the first inorganic layer CVD1 and the second inorganic layer CVD2 extend onto the edge portion EP but do not completely cover it. If any signal lines SL overlap with the edge portion EP, each signal line SL overlapping with the edge portion EP is located on the surface of the second inorganic layer CVD2 away from the edge portion EP. Of course, if there are multiple signal lines SL overlapping with the edge portion EP, only some of the signal lines SL may be located on the surface of the second inorganic layer CVD2 away from the edge portion EP. For example, if there are two signal lines SL overlapping with the edge portion EP, one may be located on the surface of the second inorganic layer CVD2 away from the edge portion EP, while the other may be located on the surface of the edge portion EP. This also helps prevent short circuits.

[0132] The signal lines SL overlapping the edge portion EP may include only the test lines PCL or both the test lines PCL and the touch leads HL. Alternatively, if the test lines PCL are not provided, the signal lines SL may include only the touch leads HL. Furthermore, the signal lines SL within the gap SHH must include the touch leads HL.

[0133] As shown in Figures 7 and 8, in a second embodiment of the present concept, if the number of signal lines SL is large, the width of the edge portion EP is reduced, thereby increasing the width of the gap SHH and accommodating more signal lines SL within the gap SHH. Since the distance between the boundary between the first and second inorganic layers CVD1 and CVD2 and the display area AA remains constant, and can be between 90 μm and 120 μm, reducing the width of the edge portion EP allows the boundary between the first and second inorganic layers CVD1 and CVD2 to be located within the gap SHH, at a distance from the edge portion EP, without overlapping the edge portion EP. In this case, no signal lines SL overlap the edge portion EP. Furthermore, at least portions of at least some of the signal lines SL located within the gap SHH are located between the boundary between the first and second inorganic layers CVD1 and CVD2 and the edge portion EP. For example, the outermost one or two signal lines SL are located between the boundary between the first and second inorganic layers CVD1 and CVD2 and the edge portion EP, and not on the second inorganic layer CVD2.

[0134] Of course, the boundary and edge portion EP of the first inorganic layer CVD1 and the second inorganic layer CVD2 may also be in contact without exposing the bottom surface of the separation groove SH, so that the signal lines SL in the gap SHH are all located on the second inorganic layer CVD2.

[0135] The signal lines SL between the boundary of the first and second inorganic layers CVD1 and CVD2 and the edge portion EP may include only the test lines PCL or both the test lines PCL and the touch lines HL. Alternatively, if the test lines PCL are not provided, the signal lines SL may include only the touch lines HL. Furthermore, the signal lines SL within the gaps SHH must include the touch lines HL.

[0136] Furthermore, as shown in FIG6 , the spacing between adjacent touch leads HL can vary. In this case, the touch layer TSP further includes dummy leads DUL, with at least some of these dummy leads located between adjacent touch leads HL and arranged in the same layer. One or more dummy leads DUL can be positioned between two adjacent touch leads HL. The distance between a dummy lead DUL and its adjacent touch lead HL can be equal to the distance between other adjacent touch leads HL or dummy leads DUL, thereby improving the uniformity of the film layer. Furthermore, at least some of the dummy leads DUL overlap with the barrier dam DAM, thereby preventing reflections from the bottom surface.

[0137] In the above-mentioned FIG. 6 and FIG. 8 , TFE is used to illustrate the boundary between the first inorganic layer CVD1 and the second inorganic layer CVD2 .

[0138] The second concept

[0139] As shown in Figures 9-11, after forming the encapsulation layer TFE, the edge portion EP can be covered with a flat cover layer PL to conceal surface defects caused by scratches on the mask. A portion of the signal lines SL can be formed on the surface of the flat cover layer PL away from the edge portion EP, thereby preventing short circuits in the signal lines SL caused by surface defects. Specifically, the flat cover layer PL can be positioned on the side of the encapsulation layer TFE away from the display substrate, covering the edge portion. At least portions of at least some of the signal lines SL are stacked on the surface of the flat cover layer PL away from the edge portion EP, and at least portions of at least some of the touch leads HL are stacked on the surface of the flat cover layer PL away from the edge portion EP, meaning that at least some of the touch leads HL overlap with the edge portion EP. Since the surface of the flat cover layer PL is flat, the number of these touch leads HL is not limited and can be one, two, or more. Of course, the test lines PCL can also be located on the surface of the flat cover layer PL away from the edge portion EP.

[0140] Furthermore, the intervals between adjacent signal lines SL on the surface of the flat cover layer PL away from the edge portion EP may be the same.

[0141] The surface of the flat cover layer PL away from the display substrate is no higher than the surface of the encapsulation layer TFE located in the display area AA. In other words, the flat cover layer PL does not protrude beyond the area of ​​the encapsulation layer TFE located in the display area AA. The flat cover layer PL can be formed using an organic material such as resin through printing or photolithography. Furthermore, a certain distance between the flat cover layer PL and the display area AA is maintained to prevent the flat cover layer PL from extending into the display area AA due to processing requirements. This distance can be set to be greater than or equal to 20 μm.

[0142] In some embodiments of the present invention, the first and second inorganic layers CVD1 and CVD2 extend onto the edge portion EP but do not completely cover the edge portion EP. The flat cover layer PL covers the second inorganic layer CVD2 on the edge portion EP and the area of ​​the edge portion EP not covered by the second inorganic layer CVD2.

[0143] As shown in FIG. 9 , in the first embodiment of the present concept, the boundary of the flat cover layer PL is located within the boundary of the edge portion EP. That is, the flat cover layer PL does not extend into the separation groove SH but only covers the edge portion EP.

[0144] As shown in Figure 10 , in a second embodiment of the present concept, the flat cover layer PL has an inner boundary close to the display area AA and an outer boundary away from the display area AA. The inner boundary is located within the separation groove SH, and the outer boundary is located within the boundary of the edge portion EP. The inner boundary can be located within the gap SHH, on the barrier dam DAM, or between adjacent barrier dams DAM, without particular limitation.

[0145] As shown in Figure 11 , in a third embodiment of this concept, the flat cover layer PL has an inner boundary close to the display area AA and an outer boundary away from the display area AA. The inner boundary is located between the separation trench SH and the display area AA, so that the flat cover layer PL covers the barrier dam DAM, and the outer boundary is located within the boundary of the edge portion EP. Consequently, the flat cover layer PL can be used to fill the separation trench SH, allowing at least some of the signal lines SL in the peripheral area WA to be located on the same surface, reducing the step difference between the signal lines SL and mitigating the risk of line breakage.

[0146] The third concept

[0147] As shown in Figure 12, before forming the encapsulation layer TFE, a support layer ZL that does not completely cover the edge portion EP can be stacked on the edge portion EP. This support layer ZL supports the mask, preventing the mask from scratching the edge portion EP and ensuring the surface flatness of the edge portion EP. In this case, at least a portion of some signal lines SL can be stacked in the area of ​​the edge portion EP not covered by the support layer ZL. Because this area is flat and not scratched, the risk of short circuits between adjacent signal lines SL can be reduced. The number of signal lines SL stacked in the area of ​​the edge portion EP not covered by the support layer ZL is not specifically limited herein and may include touch leads HL, i.e., at least a portion of some touch leads HL stacked in the area of ​​the edge portion not covered by the support layer ZL. If test lines PCL are present, they can be stacked in the area of ​​the edge portion not covered by the support layer ZL.

[0148] The support layer ZL can be made of materials such as resin, and in order to simplify the structure and process, it can be set on the same layer as other film layers of the display panel. For example, the support layer ZL can be set on the same layer as the pixel definition layer PDL. Of course, the edge portion EP in this case does not include the pixel definition layer PDL; or, the support layer ZL can also be set on the same layer as the support column on the pixel definition layer PDL. In this case, the edge portion EP can include the pixel definition layer PDL.

[0149] In a first embodiment of this concept, the support layer ZL's boundaries near and away from the display area AA are located within the periphery EP. Specifically, the support layer ZL is located within the periphery EP and does not extend beyond the periphery EP. Furthermore, the support layer ZL has a groove ZH that exposes the periphery EP and surrounds the display area AA. The signal line SL, which overlaps the periphery EP, is located within the groove ZH and includes a portion of the touch lead HL. In other words, at least a portion of the touch lead HL is located within the groove ZH.

[0150] Furthermore, in some embodiments, the first inorganic layer CVD1 and the second inorganic layer CVD2 extend to the surface of the support layer ZL away from the display substrate, that is, the support layer ZL is formed before the first inorganic layer CVD1. At the same time, the boundary between the first inorganic layer CVD1 and the second inorganic layer CVD2 is located on the side of the groove ZH closer to the display area AA, that is, the first inorganic layer CVD1 and the second inorganic layer CVD2 do not extend into the groove ZH.

[0151] Of course, the first inorganic layer CVD1 and the second inorganic layer CVD2 can also extend into the groove ZH, or even completely cover the support layer ZL, but are recessed at the groove ZH, and part of the signal line SL is located in the area where the second inorganic layer CVD2 is recessed, that is, the area where the groove ZH is located.

[0152] The present disclosure also provides a display device, which may include a display panel. The display panel may be any of the display panels described above, and its specific structure and beneficial effects are not further described here. The display device may be a mobile phone, a television, a tablet computer, or a wearable device such as a VR (Virtual Reality) device or a smartwatch, and the details are not listed here.

[0153] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel comprising a display area and a peripheral area located outside the display area; the display panel comprising: A display substrate comprising a plurality of light emitting devices located in the display area and a barrier dam located in the peripheral area; The display substrate is provided with a separation groove located in the peripheral area and surrounding the display area; a portion of the display substrate located on a side of the separation groove away from the display area is an edge portion; the barrier dam is provided in the separation groove and surrounding the display area, with a gap between the outermost barrier dam and the edge portion; an encapsulation layer covering each of the light-emitting devices; the encapsulation layer comprising a first inorganic layer and a second inorganic layer distributed in a direction away from the display substrate, and an organic layer disposed between the first inorganic layer and the second inorganic layer; the first inorganic layer and the second inorganic layer covering the barrier dam and extending at least into the gap; the organic layer being located on a side of the barrier dam close to the light-emitting device; A plurality of signal lines are arranged on a side of the packaging layer away from the display substrate; each of the signal lines extends to the peripheral area, and at least part of the areas of some of the signal lines are located in the gap; at most at least part of the areas of some of the signal lines overlap with the edge portion, and the number of the signal lines overlapping with the edge portion is less than the number of the signal lines located in the gap.

2. The display panel according to claim 1, wherein The display panel further includes: A touch layer is provided on a side of the packaging layer away from the display substrate; the touch layer includes a plurality of touch electrodes located in the display area; Each of the signal lines includes a plurality of touch leads located in the touch layer, the touch leads are connected to the touch electrodes; and at least part of the areas of some of the touch leads are located in the gap; at most at least part of the areas of some of the touch leads overlap with the edge portion, and the number of the touch leads overlapping with the edge portion is less than the number of the touch leads located in the gap.

3. The display panel according to claim 2, wherein: The first inorganic layer and the second inorganic layer extend onto the edge portion, and the touch lead overlapping the edge portion is located on a surface of the second inorganic layer away from the edge portion.

4. The display panel according to claim 2, wherein: A boundary between the first inorganic layer and the second inorganic layer is located within the gap.

5. The display panel according to claim 4, wherein: At least a portion of the touch wire located in the gap is located between the boundary between the first inorganic layer and the second inorganic layer and the edge portion. The display panel according to claim 2 , wherein: The number of the signal lines overlapping the edge portion is at most two.

7. The display panel according to claim 6, wherein: Each of the signal lines further includes a plurality of test lines located in the peripheral area. The test lines are located outside the touch leads, and at least a portion of the test lines overlaps with the edge portion.

8. The display panel according to claim 6, wherein: The number of the signal lines overlapping the edge portion is two, and a distance between the two signal lines overlapping the edge portion is greater than a distance between two adjacent signal lines in the gap.

9. The display panel according to claim 7, wherein: At least partial areas of the two test lines are located in different layers.

10. The display panel according to claim 2, wherein: The touch layer further includes dummy leads, at least a portion of which overlaps with the barrier dam and is located between the touch leads.

11. The display panel according to claim 2, wherein: The peripheral area is surrounded by a fan-out area and a peripheral area, and the separation groove and the blocking dam both pass through the fan-out area and the peripheral area; one end of any touch lead is connected to the touch electrode, and the other end extends to the fan-out area; Parts of the touch leads located in the fan-out area are located in the gap, and at most parts of the touch leads located in the fan-out area overlap with the edge portion.

12. A display panel comprising a display area and a peripheral area outside the display area; the display panel comprising: A display substrate comprising a plurality of light emitting devices located in the display area and a barrier dam located in the peripheral area; The display substrate is provided with a separation groove located in the peripheral area, the separation groove is provided around the display area, and a portion of the display substrate located on a side of the separation groove away from the display area is an edge portion; the barrier dam is provided in the separation groove and is provided around the display area, with a gap between the outermost barrier dam and the edge portion; an encapsulation layer covering each of the light-emitting devices; the encapsulation layer comprising a first inorganic layer and a second inorganic layer distributed in a direction away from the display substrate, and an organic layer disposed between the first inorganic layer and the second inorganic layer; the first inorganic layer and the second inorganic layer covering the barrier dam and extending at least into the gap; the organic layer being located on a side of the barrier dam close to the light-emitting device; a flat covering layer, provided on a side of the encapsulation layer away from the display substrate and covering the edge portion; A plurality of signal lines are arranged on a side of the packaging layer away from the display substrate; each of the signal lines extends to the peripheral area, and at least part of the signal lines is stacked on a surface of the flat cover layer away from the display substrate.

13. The display panel according to claim 12, wherein: The display panel further includes: A touch layer is provided on a side of the packaging layer away from the display substrate; the touch layer includes a plurality of touch electrodes located in the display area; Each of the signal lines includes a plurality of touch leads located in the touch layer, the touch leads are connected to the touch electrodes, and at least a portion of the touch leads is stacked on a surface of the flat cover layer away from the display substrate.

14. The display panel according to claim 12, wherein: The first inorganic layer and the second inorganic layer extend onto the edge portion; and the flat cover layer covers the second inorganic layer on the edge portion and the edge portion.

15. The display panel according to claim 12, wherein: The boundary of the flat cover layer is located inside the boundary of the edge portion.

16. The display panel according to claim 12, wherein: The flat cover layer has an inner boundary close to the display area and an outer boundary away from the display area, wherein the inner boundary is located in the separation groove, and the outer boundary is located within the boundary of the edge portion.

17. The display panel according to claim 12, wherein: The flat cover layer has an inner boundary close to the display area and an outer boundary away from the display area, wherein the inner boundary is located between the separation groove and the display area, and the outer boundary is located within the boundary of the edge portion.

18. The display panel according to any one of claims 12 to 17, wherein: A surface of the flat cover layer away from the display substrate is no higher than a surface of a region of the encapsulation layer located in the display area away from the display substrate.

19. The display panel according to claim 12, wherein: The distance between the flat cover layer and the display area is not less than 20 μm.

20. A display panel comprising a display area and a peripheral area outside the display area; the display panel comprising: A display substrate comprising a plurality of light emitting devices located in the display area and a barrier dam located in the peripheral area; The display substrate is provided with a separation groove located in the peripheral area, the separation groove is provided around the display area, and a portion of the display substrate located on a side of the separation groove away from the display area is an edge portion; the barrier dam is provided in the separation groove and is provided around the display area, with a gap between the outermost barrier dam and the edge portion; a supporting layer, stacked on the edge portion and not completely covering the edge portion; an encapsulation layer covering each of the light-emitting devices and a portion of the support layer; the encapsulation layer comprising a first inorganic layer and a second inorganic layer distributed in a direction away from the display substrate, and an organic layer disposed between the first inorganic layer and the second inorganic layer; the first inorganic layer and the second inorganic layer covering the barrier dam and extending at least into the gap; the organic layer being located on a side of the barrier dam close to the light-emitting device; A plurality of signal lines are arranged on a side of the packaging layer away from the display substrate; each of the signal lines extends to the peripheral area, and at least a portion of the signal lines is stacked in an area of ​​the edge portion not covered by the support layer.

21. The display panel according to claim 20, wherein: The display panel further includes: A touch layer is provided on a side of the packaging layer away from the display substrate; the touch layer includes a plurality of touch electrodes located in the display area; Each of the signal lines includes a plurality of touch leads located in the touch layer, and the touch leads are connected to the touch electrodes; each of the touch leads extends to the peripheral area, and at least part of some of the touch leads is stacked in the area of ​​the edge portion not covered by the supporting layer.

22. The display panel according to claim 21, wherein: The support layer is located within the boundary of the edge portion close to and away from the boundary of the display area; the support layer has a groove that exposes the edge portion and surrounds the display area; at least part of the area of ​​some of the touch leads is located in the groove.

23. The display panel according to claim 22, wherein: The first inorganic layer and the second inorganic layer extend to a surface of the support layer away from the display substrate and are located on a side of the groove close to the display area.

24. The display panel according to any one of claims 2-11, 13, and 21-23, wherein: The touch layer includes a first conductive layer and a second conductive layer distributed in a direction away from the display substrate; The touch lead is located in at least one of the first conductive layer and the second conductive layer.

25. The display panel according to any one of claims 1 to 23, wherein: The depth of the separation groove is less than the thickness of the display substrate; the edge portion includes a plurality of stacked sub-layers, and at least part of the sub-layers are made of organic material.

26. A display device comprising the display panel according to any one of claims 1 to 25.

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