Channel bus arbitration circuit, acceleration device, method, system, device and medium

Abstract

The present application relates to the field of data processing, and discloses a channel bus arbitration circuit, an acceleration device, a method, a system, a device and a medium, for use in solving the problem of waste of time cycles when a plurality of channel buses access a memory to be accessed. According to the solution, priorities are set for channel buses; a control circuit stores, according to the sequence of the preset channel priorities, access requests transmitted by the channel buses into a first memory circuit by means of a first multiplexer; and the memory to be accessed sequentially processes the access requests according to the storage sequence. Access requests sent by a plurality of channel buses are effectively coordinated and managed, thereby ensuring that all access requests are processed, avoiding access disorder and conflicts, avoiding the problem of waste of clock cycles caused during channel switching, reducing the waiting time of a memory to be accessed, and effectively utilizing the bandwidth of the memory to be accessed. In addition, the use of a hardware circuit can also reduce the delay of signal transmission compared with software logic.

Description

Channel bus arbitration circuit, acceleration device, method, system, device and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on February 29, 2024, with application number 202410230114.9, and application name “Channel bus arbitration circuit, acceleration device, method, system, device and medium”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of data processing, and in particular to a channel bus arbitration circuit, acceleration device, method, system, device and medium. Background Art

[0004] With the rapid development of technologies such as cloud computing and artificial intelligence, the demand for high computing power continues to grow. Heterogeneous accelerated computing units (Central Processing Units) combined with FPGA (Field-Programmable Gate Array) accelerator cards have become the mainstream computing units in data centers. As shown in Figure 1, when an FPGA is used as an accelerated computing unit, the FPGA's internal Accelerated Processing Unit (AFU) reads and writes data to external memory via a data bus. Due to the parallel computing advantages of FPGAs, in some scenarios, multiple AFUs may need to read and write data to external memory simultaneously. This requires an arbitration module that combines multiple channels to coordinate access between different channels.

[0005] However, existing arbitration modules present several issues. First, they lack channel-by-channel priority, resulting in inefficient channel switching. This wastes many clock cycles during channel switching, impacting overall FPGA computing performance. Second, as the number of channels to be merged increases, the wasted clock cycles also increase, leading to inefficient utilization of external memory bandwidth and reduced overall FPGA computing performance.

[0006] Summary of the Invention

[0007] The purpose of the present application is to provide a channel bus arbitration circuit, acceleration device, method, system, device and medium to effectively coordinate and manage access requests sent by multiple channel buses, ensure that each access request is processed, avoid access confusion and conflicts, avoid the problem of clock cycle waste caused by switching channels, reduce the waiting time of the memory to be accessed, and effectively utilize the bandwidth of the memory to be accessed. In addition, the use of hardware circuits can also reduce the delay of signal transmission compared to software logic.

[0008] In a first aspect, the present application provides a channel bus arbitration circuit, comprising a control circuit, a first multiplexer, and a first memory circuit;

[0009] A plurality of channel buses are connected to a plurality of input terminals of the first multiplexer in a one-to-one correspondence, a plurality of the channel buses are connected to a plurality of acceleration function units in a one-to-one correspondence, an output terminal of the first multiplexer is connected to one terminal of the first memory circuit, another terminal of the first memory circuit is connected to a memory to be accessed, and the control circuit is connected to a control terminal of the first multiplexer;

[0010] The control circuit is used to monitor the access requests sent by each of the channel buses and adjust the channels that are turned on in the first multiplexer according to the order of preset channel priorities, so as to store each of the access requests in the first memory circuit in sequence, so that the memory to be accessed can process the multiple access requests in the first memory circuit in sequence according to the order of storage.

[0011] In some implementations, the channel bus arbitration circuit further includes a second memory circuit and a second multiplexer; one end of the second memory circuit is connected to the first memory circuit, the other end of the second memory circuit is connected to a control end of the second multiplexer, an input end of the second multiplexer is connected to the memory to be accessed, and multiple output ends of the second multiplexer are connected to the multiple channel buses in a one-to-one correspondence;

[0012] The first memory circuit is specifically configured to, when the access request is a write request, store a first message corresponding to the write request in its own storage space; and, when the access request is a read request, store a request type and an address to be read in a second message corresponding to the read request in its own storage space, and store a channel bus identifier in the second message in the second memory circuit, wherein the first message includes the request type, the address to be written, and the data to be written.

[0013] The second memory circuit is used to store the identifier of the channel bus corresponding to the read request, and when the data to be read corresponding to the second message is read from the memory to be accessed, control the channel corresponding to the channel bus corresponding to the channel bus identifier in the second multiplexer to be turned on, so as to transmit the data to be read corresponding to the second message to the channel bus corresponding to the channel bus identifier.

[0014] In some implementations, the first message further includes a first burst length of the data to be written, and the channel bus arbitration circuit further includes a first counter, one end of the first counter is connected to the output end of the first multiplexer, the other end of the first counter is connected to the first memory circuit, and the output end of the first counter is connected to the control circuit;

[0015] The first counter is configured to increase its first count value by one when the write request sent by the channel bus is valid, and output a channel switching signal to the control circuit when the first count value reaches the first burst length;

[0016] The control circuit is specifically configured to, when controlling the channels of the first multiplexer to be turned on for the first time, select, based on the preset channel priority, the channels corresponding to the channel bus with the highest priority for turning on; and, when controlling the channels of the first multiplexer to be turned on for a non-initial time, adjust the channels turned on in the first multiplexer based on the channel switching signal and the preset channel priority, so as to sequentially store the access requests in the first memory circuit, so that the memory to be accessed sequentially processes the multiple access requests in the first memory circuit in the order in which they are stored.

[0017] In some implementations, the second message further includes a second burst length of the data to be read, the first memory circuit is further configured to store the second burst length in the second memory circuit when the access request is a read request, and the second memory is further configured to store the second burst length;

[0018] The channel bus arbitration circuit further includes a second counter, a first terminal of the second counter is connected to the input terminal of the second multiplexer, and a second terminal of the second counter is connected to the second memory circuit;

[0019] The second counter is configured to increase its second count value by one when the data flag of the data to be read inputted at the input end of the second multiplexer is valid, and to clear the second count value to zero when the second count value reaches the second burst length.

[0020] In the second aspect, the present application also provides an acceleration device, including multiple acceleration functional units and multiple channel buses, and also including the channel bus arbitration circuit mentioned above. The multiple acceleration functional units are connected to the control circuit in the channel bus arbitration circuit through channel buses corresponding to themselves one by one.

[0021] In a third aspect, the present application further provides a channel bus arbitration method, which is applied to the control circuit in the channel bus arbitration circuit described above. The channel bus arbitration method includes:

[0022] monitoring access requests sent by the plurality of channel buses;

[0023] Adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities;

[0024] The access requests are stored in the first memory circuit through the first multiplexer, so that the memory to be accessed sequentially processes the multiple access requests in the first memory circuit according to the order of storage.

[0025] In some implementations, the channel bus arbitration circuit further includes a second memory circuit and a second multiplexer; one end of the second memory circuit is connected to the first memory circuit, the other end of the second memory circuit is connected to a control end of the second multiplexer, an input end of the second multiplexer is connected to a memory to be accessed, and multiple output ends of the second multiplexer are connected to the multiple channel buses in a one-to-one correspondence;

[0026] Storing the access request in a first memory circuit via the first multiplexer includes:

[0027] When the access request is a write request, storing a first message corresponding to the write request in the first memory circuit through the first multiplexer, the first message including a request type, an address to be written, and data to be written;

[0028] When the access request is a read request, storing the request type and the to-be-read address in the second message corresponding to the read request in the first memory circuit through the first multiplexer, and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit;

[0029] When the data to be read is read from the memory to be accessed, triggering the second memory circuit to control the channel corresponding to the channel bus corresponding to the channel bus identifier in the second multiplexer to be turned on;

[0030] The to-be-read data is transmitted to the channel bus corresponding to the channel bus identifier through the conductive channel in the first multiplexer.

[0031] In some implementations, the first message further includes a first burst length of the data to be written, and the channel bus arbitration method further includes:

[0032] When the access request is a write request, determining whether the first burst length is one;

[0033] If the value is one, the first message corresponding to the write request is stored in the first memory circuit through the first multiplexer, and after the writing of the data to be written is completed, the step of monitoring the access requests sent by the multiple channel buses is entered;

[0034] If the first burst length is not one, the first message corresponding to the write request is stored in the first memory circuit through the first multiplexer, and the valid write requests transmitted by the first multiplexer are counted. When the first count value of the valid write requests reaches the first burst length, a channel switching signal is output, and the first count value is cleared to zero, and the step of monitoring the access requests sent by the multiple channel buses is entered.

[0035] In some implementations, the channel bus arbitration circuit further includes a first counter, one end of the first counter being connected to the output end of the first multiplexer, the other end of the first counter being connected to the first memory circuit, and the output end of the first counter being connected to the control circuit; counting valid write requests transmitted by the first multiplexer, outputting a channel switching signal when a first count value of the valid write requests reaches the first burst length, clearing the first count value, and entering the step of monitoring access requests sent by the multiple channel buses, including:

[0036] triggering the first counter to increase its own first count value by one when detecting that the write request transmitted by the first multiplexer is valid;

[0037] When the first count value reaches the first burst length, a channel switching signal is output and the first count value is cleared to zero, so as to enter the step of monitoring access requests sent by the plurality of channel buses.

[0038] In some implementations, the second message further includes a second burst length of the data to be read, and the channel bus arbitration method further includes:

[0039] When the data to be read is read from the memory to be accessed, the valid number of data flag bits of the data to be read inputted from the input end of the second multiplexer is counted to obtain a second count value;

[0040] When the second count value reaches the second burst length, the second count value is cleared to zero.

[0041] In some implementations, the channel bus arbitration circuit further includes a second counter, wherein a first terminal of the second counter is connected to an input terminal of the second multiplexer, and a second terminal of the second counter is connected to the second memory circuit; when the data to be read is read from the memory to be accessed, the second counter counts the valid number of data flag bits of the data to be read inputted from the input terminal of the second multiplexer to obtain a second count value, including:

[0042] When the data to be read is read from the memory to be accessed, determining whether a data flag bit of the data to be read inputted from the input end of the second multiplexer is valid;

[0043] If valid, triggering the second count value of the second counter to increase by one;

[0044] When the second count value reaches the second burst length, clearing the second count value to zero includes:

[0045] When the second count value reaches the second burst length, the second counter is triggered to clear the second count value to zero.

[0046] In some implementations, before storing the first message corresponding to the write request in the first memory circuit through the first multiplexer, the method further includes:

[0047] determining whether an amount of first data stored in the first memory circuit is less than a first threshold, where the first threshold is less than a capacity value of the first memory circuit;

[0048] If the first data amount is less than the first threshold, entering the step of storing the first message corresponding to the write request in the first memory circuit through the first multiplexer;

[0049] If the first data amount is not less than the first threshold, the system enters a waiting state until the first data amount stored in the first memory circuit is less than the first threshold.

[0050] In some implementations, when the first burst length is not one, determining whether the amount of the first data stored in the first memory circuit is less than a first threshold includes:

[0051] each time the write request is received and the first count value does not reach the first burst length, determining whether the amount of first data stored in the first memory circuit is less than a first threshold;

[0052] If the first count value does not reach the first burst length and the amount of the first data stored in the first memory circuit is not less than the first threshold, a waiting state is entered until the amount of the first data stored in the first memory circuit is less than the first threshold.

[0053] In some implementations, when the access request is a read request, before storing the request type and the to-be-read address in the second message corresponding to the read request in the first memory circuit via the first multiplexer and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit, the method further includes:

[0054] determining whether an amount of first data stored in the first memory circuit is less than a first threshold and whether an amount of second data stored in the second memory circuit is less than a second threshold, wherein the first threshold is less than a capacity value of the first memory circuit and the second threshold is less than a capacity value of the second memory circuit;

[0055] If the first data amount is less than the first threshold and the second data amount is less than the second threshold, then, when the access request is a read request, the step of storing the request type and the to-be-read address in the second message corresponding to the read request in the first memory circuit through the first multiplexer, and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit;

[0056] If the first data amount is not less than the first threshold or the second data amount is not less than the second threshold, the system enters a waiting state until the first data amount is less than the first threshold and the second data amount is less than the second threshold.

[0057] In some implementations, adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities includes:

[0058] Determine, according to the sequence numbers of the channel buses and the preset channel priorities, the target channel bus with the highest priority among the channel buses currently transmitting the access request;

[0059] controlling the target channel corresponding to the target channel bus in the first multiplexer to be turned on according to a first preset channel priority;

[0060] The sequence number of each channel bus is positively correlated or negatively correlated with its own priority.

[0061] In some implementations, adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities includes:

[0062] When the access request is received for the first time according to the second preset channel priority, determining the channel bus with the smallest sequence number among the channel buses currently transmitting the access request as the target channel bus;

[0063] controlling a first target channel corresponding to the target channel bus in the first multiplexer to be turned on;

[0064] After storing the access request corresponding to the target channel bus in the first memory circuit, polling a previous channel bus or a next channel bus of the target channel bus in sequence, and determining whether the previous channel bus or the next channel bus transmits the access request;

[0065] If the previous channel bus or the next channel bus transmits the access request, the second target channel corresponding to the previous channel bus or the next channel bus in the first multiplexer is turned on.

[0066] In some implementations, the method further includes:

[0067] Receive priority setting instructions issued by the central processing unit;

[0068] The preset channel priority is set to the first preset channel priority or the second preset channel priority according to the priority setting instruction.

[0069] In some implementations, receiving a priority setting instruction issued by a central processing unit includes:

[0070] Obtaining the value written into the preset register by the central processing unit;

[0071] Setting the preset channel priority to the first preset channel priority or the second preset channel priority according to the priority setting instruction includes:

[0072] If the value in the preset register is a first value, setting the preset channel priority to a first preset channel priority;

[0073] If the value in the preset register is a second value, the preset channel priority is set to a second preset channel priority.

[0074] In a fourth aspect, the present application further provides a channel bus arbitration system, which is applied to the control circuit of the channel bus arbitration circuit as described above, and the channel bus arbitration system includes:

[0075] a monitoring unit, configured to monitor access requests sent by the plurality of channel buses;

[0076] a channel adjustment unit, configured to adjust the channels turned on in the first multiplexer according to an order of preset channel priorities;

[0077] The request processing unit is configured to store the access request in the first memory circuit through the first multiplexer, so that the memory to be accessed sequentially processes the multiple access requests in the first memory circuit according to the order in which they are stored.

[0078] In a fifth aspect, the present application further provides a channel bus arbitration device, comprising:

[0079] Memory for storing computer programs;

[0080] The processor is used to implement the steps of the channel bus arbitration method as described above when storing a computer program.

[0081] In a sixth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the channel bus arbitration method as described above are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0083] FIG1 is a schematic diagram of an existing channel bus arbitration solution;

[0084] FIG2 is a schematic diagram of a channel bus arbitration circuit provided by the present application;

[0085] FIG3 is a flow chart of a channel bus arbitration method provided by the present application;

[0086] FIG4 is a specific flow chart of a channel bus arbitration method provided by the present application;

[0087] FIG5 is a schematic diagram of an application scenario of a channel bus arbitration circuit provided by the present application;

[0088] FIG6 is a schematic diagram of processing an access request provided by this application. DETAILED DESCRIPTION

[0089] The core of this application is to provide a channel bus arbitration circuit, acceleration device, method, system, device and medium, which relates to the field of data processing and is used to solve the problem of wasting time cycles when multiple channel buses access the memory to be accessed. The solution sets a priority for each channel bus, and the control circuit stores the access requests transmitted by each channel bus to the first memory circuit through a first multiplexer in the order of preset channel priorities. The memory to be accessed processes the access requests in sequence according to the storage order, and effectively coordinates and manages the access requests sent by multiple channel buses, ensuring that each access request is processed, avoiding access confusion and conflicts, avoiding the problem of clock cycle waste caused by switching channels, reducing the waiting time of the memory to be accessed, and effectively utilizing the bandwidth of the memory to be accessed. In addition, using hardware circuits to implement it can also reduce the delay of signal transmission compared to software logic.

[0090] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0091] In a first aspect, as shown in FIG2 , the present application provides a channel bus arbitration circuit, comprising a control circuit 11 , a first multiplexer 12 , and a first memory circuit 13 ;

[0092] The plurality of channel buses are connected to the plurality of input terminals of the first multiplexer 12 in a one-to-one correspondence, and the plurality of channel buses are connected to the plurality of acceleration functional units in a one-to-one correspondence. The output terminal of the first multiplexer 12 is connected to one terminal of a first memory circuit 13, the other terminal of the first memory circuit 13 is connected to a to-be-accessed memory 14, and the control circuit 11 is connected to the control terminal of the first multiplexer 12.

[0093] The control circuit 11 is used to monitor the access requests sent by each channel bus and adjust the channels turned on in the first multiplexer 12 according to the order of preset channel priorities, so as to store each access request in the first memory circuit 13 in sequence, so that the memory to be accessed 14 can process the multiple access requests in the first memory circuit 13 in sequence according to the order of storage.

[0094] This embodiment describes a channel bus arbitration circuit, including a control circuit 11, a first multiplexer 12, and a first memory circuit 13. This arbitration circuit is applicable to FPGAs with multiple acceleration functional units, each corresponding to a channel bus (which may be an Avalon-MM bus). The multiple channel buses are connected to the first memory circuit 13 via the first multiplexer 12. The other end of the first memory circuit 13 is connected to the memory to be accessed 14. The control circuit 11 is connected to the control end of the first multiplexer 12.

[0095] In this arbitration circuit, control circuit 11 monitors access requests sent from each channel bus (e.g., channel bus 0 access request, channel bus 1 access request, and channel bus 2 access request in Figure 1) and adjusts the channels enabled in first multiplexer 12 according to the order of preset channel priorities. Thus, each access request is sequentially stored in first memory circuit 13, to be processed by access memory 14 in the order in which it was stored.

[0096] By setting a preset channel priority order, the arbitration circuit can quickly switch the conductive channel, so that each access request is stored in the memory circuit in sequence, improving the channel access efficiency. Since each access request is stored in the memory circuit according to the preset channel priority order, the clock cycle waste caused by switching channels can be reduced, and the overall FPGA computing performance can be improved. By storing the access requests in the memory circuit in sequence, the memory 14 to be accessed can process these requests in sequence, maximizing the utilization of the external memory bandwidth. In summary, the channel bus arbitration circuit provided by the present application can effectively improve the FPGA computing performance, improve the memory access efficiency, reduce the clock cycle waste, and maximize the utilization of the external memory bandwidth.

[0097] In some implementations, the channel bus arbitration circuit further includes a second memory circuit 15 and a second multiplexer 16; one end of the second memory circuit 15 is connected to the first memory circuit 13, the other end of the second memory circuit 15 is connected to the control end of the second multiplexer 16, an input end of the second multiplexer 16 is connected to the to-be-accessed memory 14, and multiple output ends of the second multiplexer 16 are connected one-to-one to the multiple channel buses;

[0098] The first memory circuit 13 is specifically configured to, when the access request is a write request, store a first message corresponding to the write request in its own storage space; when the access request is a read request, store a request type and an address to be read in a second message corresponding to the read request in its own storage space, and store a channel bus identifier in the second message in the second memory circuit 15, wherein the first message includes the request type, the address to be written, and the data to be written;

[0099] The second memory circuit 15 is used to store the identifier of the channel bus corresponding to the read request, and when the data to be read corresponding to the second message is read from the memory to be accessed 14, it controls the channel corresponding to the channel bus corresponding to the channel bus identifier in the second multiplexer 16 to be turned on, so as to transmit the data to be read corresponding to the second message to the channel bus corresponding to the channel bus identifier.

[0100] Furthermore, this embodiment also includes a second memory circuit 15 and a second multiplexer 16. The first memory circuit 13 is used to store message information corresponding to write requests and read requests, and the second memory circuit 15 is used to store the identifier of the channel bus corresponding to the read request, and when the data to be read is read from the memory to be accessed 14, the channel bus corresponding to the channel bus identifier in the second multiplexer 16 is controlled to be turned on, and the data to be read is transmitted to the corresponding channel bus.

[0101] Specifically, in the case of a multi-channel bus merge, if there is a need for multiple acceleration functional units to read data from the external memory at the same time, the second memory circuit 15 stores and manages the channel bus identifier corresponding to the read request, which can effectively realize the control and scheduling of access between different channels without relying on the storage of the first memory circuit 13. This can improve the utilization efficiency of the channel bus resources and avoid the inefficiency when switching channels, thereby improving the computing performance of the entire FPGA. Secondly, the existence of the second memory circuit 15 makes it possible to control the corresponding channel in the second multiplexer 16 to be turned on according to the stored channel bus identifier when reading the data to be read from the memory to be accessed 14, and transmit the data to be read to the corresponding channel bus. In this way, the read data can be distributed in a timely and effective manner, avoiding data transmission confusion and delay when the multi-channel buses are merged. This improves the bandwidth utilization efficiency of the external memory and further improves the computing performance of the entire FPGA.

[0102] In some implementations, the first message further includes a first burst length of data to be written, and the channel bus arbitration circuit further includes a first counter 17, one end of the first counter 17 is connected to the output end of the first multiplexer 12, the other end of the first counter 17 is connected to the first memory circuit 13, and the output end of the first counter 17 is connected to the control circuit 11 (the connection relationship between one end and the other end of the first counter 17 is not shown in FIG. 2 ; in addition, it should be noted that the one end, the other end, and the output end of the first counter 17 are three different ends).

[0103] The first counter 17 is configured to increase its own first count value by one when the write request sent by the channel bus is valid, and output a channel switching signal to the control circuit 11 when the first count value reaches the first burst length;

[0104] The control circuit 11 is specifically configured to, when controlling the channel conduction of the first multiplexer 12 for the first time, select the channel corresponding to the channel bus with the highest priority to be turned on according to the preset channel priority; when controlling the channel conduction of the first multiplexer 12 for the non-first time, adjust the channel turned on in the first multiplexer 12 according to the channel switching signal and the preset channel priority, so as to store each access request in the first memory circuit 13 in sequence, so that the memory to be accessed 14 can process the multiple access requests in the first memory circuit 13 in sequence according to the order of storage.

[0105] In this embodiment, when the content of the first message includes the first burst length of the data to be written, the channel bus arbitration circuit further introduces a first counter 17, which is connected to the channel bus, the first memory circuit 13, and the control circuit 11. The function of the first counter 17 is to increase its own count value by one when the write request sent by the channel bus is valid. When the count value reaches the preset first burst length, the counter will output a channel switching signal to the control circuit 11. The control circuit 11 controls the channels that are turned on in the first multiplexer 12 based on the channel switching signal and the preset channel priority. When the channels of the first multiplexer 12 are turned on for the first time, the control circuit 11 selects the channel corresponding to the channel with the highest priority to turn on. When the channels of the first multiplexer 12 are not turned on for the first time, the control circuit 11 adjusts the channels that are turned on in the first multiplexer 12 based on the channel switching signal and the preset channel priority. In this way, through the cooperation of the first counter 17 and the control circuit 11, channel selection and switching according to the preset channel priority can be achieved. When the counter reaches the first burst length, the control circuit 11 triggers channel switching and selects the next higher priority channel for access.

[0106] The use of the first counter 17 can improve the access efficiency of the channel. When the first burst length of the data to be written is large, multiple data can be continuously transmitted in one communication through the accumulation of the counter, reducing the number of channel switching times, thereby improving the efficiency of data transmission; in addition, by adjusting the channel priority, it can also ensure that high-priority channels are selected and accessed first, further improving the response speed and overall performance of the system.

[0107] In some implementations, the second message further includes a second burst length of the data to be read, and the first memory circuit 13 is further configured to store the second burst length in the second memory circuit 15 when the access request is a read request, and the second memory is further configured to store the second burst length;

[0108] The channel bus arbitration circuit further includes a second counter 18 , a first terminal of the second counter 18 is connected to the input terminal of the second multiplexer 16 , and a second terminal of the second counter 18 is connected to the second memory circuit 15 ;

[0109] The second counter 18 is used to increase its second count value by one when the data flag of the data to be read inputted at the input end of the second multiplexer 16 is valid, and to clear the second count value to zero when the second count value reaches the second burst length.

[0110] In this embodiment, when the second message includes the request type of the data to be read, the address to be read, and the second burst length of the data to be read, a second counter 18 is further introduced into the channel bus arbitration circuit. The second counter 18 is connected to the input end of the second multiplexer 16 and is used to calculate the burst length of the data to be read. When the data flag bit at the input end is valid, the second counter 18 increases its count value by one. When the count value reaches the same as the second burst length, it indicates that the data of the entire burst length has been transmitted, and the second counter 18 clears the count value.

[0111] Using the second counter 18 to record and control the length of the burst data can ensure that only the required amount of data is transmitted when reading data, avoiding unnecessary data transmission and improving transmission efficiency. At the same time, it can ensure that the data to be read can be processed completely and accurately during the transmission process, while avoiding confusion or errors in the data transmission process.

[0112] In a second aspect, the present application also provides an acceleration device comprising multiple acceleration functional units and multiple channel buses, and also comprising the aforementioned channel bus arbitration circuit. The multiple acceleration functional units are connected to the control circuit in the channel bus arbitration circuit via their corresponding channel buses. The acceleration device provided by the present application comprises multiple acceleration functional units and multiple channel buses, and also comprises a channel bus arbitration circuit. Each acceleration functional unit is connected to the channel bus arbitration circuit via an independent channel bus. The channel bus arbitration circuit effectively manages access requests from multiple acceleration functional units to a memory to be accessed 14 through a control circuit 11 and a first multiplexer 12. The control circuit 11 monitors the access requests sent by each channel bus and adjusts the channels enabled in the first multiplexer 12 according to a preset channel priority order so that each access request is sequentially stored in the memory circuit. The memory to be accessed 14 can process these access requests sequentially in the order in which they were stored. Therefore, through the effective management of the channel bus arbitration circuit, the acceleration device enables multiple acceleration functional units to efficiently communicate with and process data in the memory to be accessed 14, thereby improving the performance and efficiency of the entire system.

[0113] In a third aspect, as shown in FIG3 , the present application further provides a channel bus arbitration method, which is applied to the control circuit in the above-mentioned channel bus arbitration circuit. The channel bus arbitration method includes:

[0114] S11: monitoring access requests sent by multiple channel buses;

[0115] In the channel bus arbitration method, it is first necessary to monitor access requests from multiple channel buses. That is, the system needs to be able to detect and identify the type and priority of access requests sent by each channel bus in real time. By monitoring these requests, the system can make corresponding adjustments and processing in the next steps to ensure that each access request is processed effectively and orderly.

[0116] S12: adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities;

[0117] In this step, it is necessary to determine the priority order between different channels. When multiple channel buses are detected sending access requests, the control circuit will adjust the conductive channels in the first multiplexer according to the pre-set channel priority order so that the access requests can be stored in the first memory circuit in sequence. The purpose of this step is to ensure that when multiple channel buses send access requests at the same time, these requests can be processed in order of priority so that the memory to be accessed can process these access requests in order of storage. This can effectively perform channel bus arbitration, avoid conflicts between access requests from different channels, and ensure that access requests are processed in accordance with the preset priority order.

[0118] S13: storing the access request in the first memory circuit through the first multiplexer, so that the memory to be accessed sequentially processes the multiple access requests in the first memory circuit according to the order of storage.

[0119] In the channel bus arbitration method, this step is used to sequentially store access requests sent by each channel bus into a first memory circuit. This step is achieved by directing the access requests from each channel bus to the first memory circuit via a first multiplexer. Specifically, after the control circuit adjusts the channels that are turned on in the first multiplexer based on preset channel priorities, the access requests sent by each channel bus are directed to the first memory circuit. At this point, the first memory circuit processes the multiple stored access requests sequentially in the order in which they were stored. This order is determined by the control circuit adjusting the channels that are turned on in the first multiplexer. In this way, the memory to be accessed can be ensured to sequentially process the multiple access requests in the first memory circuit in the order in which they were stored, thereby improving access efficiency and system performance.

[0120] Based on the above embodiment, as shown in FIG4 :

[0121] In some implementations, the channel bus arbitration circuit further includes a second memory circuit and a second multiplexer; one end of the second memory circuit is connected to the first memory circuit, the other end of the second memory circuit is connected to a control end of a second multiplexer, an input end of the second multiplexer is connected to a memory to be accessed, and multiple output ends of the second multiplexer are connected to the multiple channel buses in a one-to-one correspondence;

[0122] Storing the access request in the first memory circuit through the first multiplexer includes: when the access request is a write request, storing a first message corresponding to the write request in the first memory circuit through the first multiplexer, the first message including a request type, an address to be written, and data to be written; when the access request is a read request, storing the request type and the address to be read in a second message corresponding to the read request in the first memory circuit through the first multiplexer, and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit.

[0123] This embodiment describes the structure of a channel bus arbitration circuit, which includes, in addition to a control circuit, a first multiplexer, and a first memory circuit, a second memory circuit and a second multiplexer. In this channel bus arbitration method, a processing portion of the second memory circuit and the second multiplexer is also introduced. Specifically, when the access request is a write request, the control circuit will store the first message corresponding to the write request, including the request type, the address to be written, and the data to be written, in the first memory circuit through the first multiplexer. When the access request is a read request, the control circuit will store the request type and the address to be read in the second message corresponding to the read request in the first memory circuit through the first multiplexer, and trigger the first memory circuit to store the channel bus identifier in the second message in the second memory circuit. By introducing the second memory circuit and the second multiplexer, this channel bus arbitration circuit can implement more complex access request processing, can more effectively manage and schedule multiple access requests, and improve the transmission efficiency and overall performance of the channel bus.

[0124] In some implementations, the channel bus arbitration method further includes: when the data to be read corresponding to the second message is read from the memory to be accessed, triggering the second memory circuit to control the channel corresponding to the channel bus corresponding to the channel bus identifier in the second multiplexer to be turned on; and transmitting the data to be read corresponding to the second message to the channel bus corresponding to the channel bus identifier through the turned-on channel in the first multiplexer.

[0125] In this embodiment, when the first memory circuit stores data to be read from the accessed memory, the second memory circuit is triggered to operate and read the data from the accessed memory. Once the data is retrieved, the second memory circuit triggers the control of the channel corresponding to the channel bus identifier in the second multiplexer to conduct. The data is transmitted to the channel bus corresponding to the channel bus identifier through the conducted channel in the first multiplexer, ensuring that the data can be smoothly transmitted to the target channel bus. This implementation of the channel bus arbitration method ensures that the data can be transmitted to the target channel bus in a timely manner when processing a read request, thereby achieving the effectiveness and efficiency of channel bus arbitration.

[0126] In some implementations, the first message also includes a first burst length of the data to be written, and the channel bus arbitration method also includes: when the access request is a write request, determining whether the first burst length is one; if it is one, storing the first message corresponding to the write request in the first memory circuit through the first multiplexer, and after completing the writing of the data to be written, entering the step of monitoring access requests sent by multiple channel buses.

[0127] This embodiment mentions a specific implementation method, in which the first message includes the first burst length of the data to be written. In the channel bus arbitration method, when a write request is received, it is first determined whether the first burst length of the data to be written is one; if the first burst length is one, it indicates that the length of the data to be written is only one data burst length, that is, only one data needs to be written. If the first burst length is one, the first message corresponding to the write request will be stored in the first memory circuit through the first multiplexer, and after the writing of the data to be written is completed, the step of monitoring the access requests sent by multiple channel buses is entered. This means that if the length of the data to be written is only one data burst length, the write request will be directly stored in the memory circuit, and the next step will be performed after the writing is completed. This design method can more effectively handle write requests with short data burst lengths, thereby improving the efficiency and flexibility of the channel bus arbitration method.

[0128] In some implementations, when the access request is a write request, after determining whether the first burst length is one, the channel bus arbitration method further includes: if the first burst length is not one, storing the first message corresponding to the write request in the first memory circuit through the first multiplexer, and counting the valid write requests transmitted by the first multiplexer, outputting a channel switching signal when the first count value of the valid write request reaches the first burst length, clearing the first count value to zero, and entering the step of monitoring the access requests sent by multiple channel buses.

[0129] In this embodiment, when the access request is a write request, after determining whether the first burst length is one, if the first burst length is not one, the first message corresponding to the write request is stored in the first memory circuit through the first multiplexer, and the valid write requests transmitted by the first multiplexer are counted. When the first count value of the valid write requests reaches the first burst length, a channel switching signal is output, and the first count value is cleared to zero, and the step of monitoring the access requests sent by multiple channel buses is entered. Simply put, this implementation method is to solve the problem of low transmission efficiency when only one data is transmitted at a time during data transmission on the channel bus. Therefore, when the first burst length is not one, it is necessary to count the valid write requests transmitted and output a channel switching signal when the first burst length is reached to enable the next round of data transmission. At the same time, it is also necessary to clear the first count value to prepare for the next round of counting, so that efficient data transmission can be achieved and the transmission efficiency of the channel bus can be improved.

[0130] In some implementations, the channel bus arbitration circuit further includes a first counter, one end of the first counter is connected to the first multiplexer, the other end of the first counter is connected to the first memory circuit, and the output end of the first counter is connected to the control circuit; counting valid write requests transmitted by the first multiplexer, outputting a channel switching signal when a first count value of the valid write request reaches a first burst length, and clearing the first count value to enter the step of monitoring access requests sent by multiple channel buses, including: triggering the first counter to increase its own first count value by one when monitoring that the write request transmitted by the first multiplexer is valid; outputting a channel switching signal and clearing the first count value to zero when the first count value reaches the first burst length, and entering the step of monitoring access requests sent by multiple channel buses.

[0131] In this embodiment, when the channel bus arbitration circuit further includes a first counter, one end of the first counter is connected to the channel bus, the other end is connected to the first memory circuit, and the output end is connected to the control circuit (the output end is not the same end as the two ends connecting the channel bus and the first memory circuit). In this implementation, the function of the first counter is to count valid write requests transmitted by the first multiplexer. Whenever a valid write request transmitted by the first multiplexer is detected, the first counter increments its own count value by one. When the count value of valid write requests reaches a preset first burst length, the first counter outputs a channel switching signal and clears the count value to zero. This channel switching signal triggers the control circuit to enter the step of monitoring access requests sent by multiple channel buses to ensure that the channel buses can efficiently process access requests.

[0132] In some implementations, the second message also includes a second burst length of the data to be read, and the channel bus arbitration method also includes: when the data to be read is read from the memory to be accessed, counting the valid number of data flag bits of the data to be read input at the input end of the second multiplexer to obtain a second count value; when the second count value reaches the second burst length, clearing the second count value to zero.

[0133] In this embodiment, when the second message includes the second burst length of the data to be read, when the data to be read is read from the memory to be accessed, the valid number of data flag bits of the data to be read inputted at the input end of the second multiplexer is counted to obtain a second count value. When the second count value reaches the second burst length, the second count value is cleared to zero. In layman's terms, when a read operation is performed, a certain amount of data (i.e., the second burst length) needs to be read from the memory and transmitted to the corresponding acceleration functional unit via the channel bus. During the data transmission process, the transmitted data needs to be marked so that the data can be correctly transmitted to the corresponding acceleration functional unit after the transmission is completed. Therefore, the channel bus arbitration circuit needs to count the transmitted data to ensure that the amount of transmitted data is correct, and clear the counter after the transmission is completed to facilitate the next data transmission.

[0134] In some implementations, the channel bus arbitration circuit further includes a second counter, wherein a first terminal of the second counter is connected to an input terminal of the second multiplexer, and a second terminal of the second counter is connected to the second memory circuit; when the data to be read is read from the memory to be accessed, the second counter counts the valid number of data flag bits of the data to be read inputted from the input terminal of the second multiplexer to obtain a second count value, including:

[0135] When the data to be read is read from the memory to be accessed, determining whether the data flag bit of the data to be read inputted from the input end of the second multiplexer is valid;

[0136] If valid, trigger the second count value of the second counter to increase by one;

[0137] When the second count value reaches the second burst length, clearing the second count value to zero includes:

[0138] When the second count value reaches the second burst length, the second counter is triggered to clear the second count value to zero.

[0139] This embodiment describes an implementation method of a channel bus arbitration circuit, including the function and workflow of a second counter. The channel bus arbitration circuit is used to process access requests sent by multiple channel buses, wherein the second counter is associated with a second multiplexer and a second memory circuit. Its workflow is as follows: First, when the data to be read is read from the memory to be accessed, it is determined whether the data flag bit of the data to be read inputted from the input end of the second multiplexer is valid. If valid, the second count value of the second counter is triggered to increase by one. This process ensures that each valid data to be read is counted; then, when the second count value reaches the second burst length, the second count value is cleared to zero. This step is to reset the counter when a specific burst length is reached to prepare for the next round of counting. In summary, this embodiment describes the function and workflow of the second counter in the channel bus arbitration circuit, which is used to effectively process and control access requests from multiple channel buses, thereby improving the efficiency and stability of the bus.

[0140] In some implementations, before storing the first message corresponding to the write request in the first memory circuit through the first multiplexer, the method further includes: determining whether the amount of first data stored in the first memory circuit is less than a first threshold, where the first threshold is less than the capacity value of the first memory circuit; if the amount of first data is less than the first threshold, entering the step of storing the first message corresponding to the write request in the first memory circuit through the first multiplexer; if the amount of first data is not less than the first threshold, entering a waiting state until the amount of first data stored in the first memory circuit is less than the first threshold.

[0141] In this embodiment, in order to optimize the data flow management of the channel bus and the processing efficiency of the memory. First, determining whether the amount of first data stored in the first memory circuit is less than the first threshold can help control data flow. By setting the first threshold, it is possible to avoid storing too much data in the memory circuit, thereby reducing the pressure on the channel bus and the memory; when the amount of first data is less than the threshold, the first message corresponding to the write request is stored in the memory circuit, which can effectively control the load of the channel bus and avoid data congestion and delay. Secondly, this step can also improve the processing efficiency of the memory; when the amount of stored data is less than the threshold, it means that the memory still has sufficient processing capacity to receive and process new write requests, which can ensure that the memory can process requests more promptly and efficiently, avoiding the problem of performance degradation and increased delay caused by excessive load. In summary, by determining whether the amount of data stored in the first memory circuit is less than the preset threshold, data flow can be effectively managed, the load on the channel bus and memory can be reduced, and the processing efficiency and performance stability of the entire system can be improved, which enables the channel bus arbitration circuit to operate more stably and efficiently under high load conditions.

[0142] In some implementations, when the first burst length is not one, determining whether the amount of first data stored in the first memory circuit is greater than a first threshold includes: each time a write request is received and the first count value does not reach the first burst length, determining whether the amount of first data stored in the first memory circuit is less than the first threshold; if the first count value does not reach the first burst length and the amount of first data stored in the first memory circuit is not less than the first threshold, entering a waiting state until the amount of first data stored in the first memory circuit is less than the first threshold.

[0143] This embodiment provides a detailed description of an implementation of a channel bus arbitration method. In this implementation, when the first burst length is not one, a determination is first made as to whether the amount of first data stored in the first memory circuit is less than a first threshold. This step ensures that the amount of data in the first memory circuit does not exceed its capacity, thereby ensuring system stability and reliability. Each time a write request is received and the first count value does not reach the first burst length, a determination is made as to whether the amount of first data stored in the first memory circuit is greater than the first threshold. If the amount of first data stored in the first memory circuit is not less than the first threshold, the system enters a wait state until the amount of first data stored in the first memory circuit is less than the first threshold. This step is intended to prevent excessive data volume from causing system performance degradation or data loss. By limiting and controlling the amount of data stored in the first memory circuit, system stability and data integrity can be effectively protected, avoiding the problem of system performance degradation caused by excessive data storage, reducing the risk of data loss, and improving system reliability and stability.

[0144] In some implementations, when the access request is a read request, the request type and the address to be read in the second message corresponding to the read request are stored in the first memory circuit through the first multiplexer, and before the first memory circuit is triggered to store the channel bus identifier in the second message in the second memory circuit, it also includes: judging whether the amount of first data stored in the first memory circuit is less than a first threshold and whether the amount of second data in the second memory circuit is less than a second threshold, the first threshold is less than the capacity value of the first memory circuit, and the second threshold is less than the capacity value of the second memory circuit; if the amount of first data is less than the first threshold and the amount of second data is less than the second threshold, then entering the step of storing the request type and the address to be read in the second message corresponding to the read request in the first memory circuit through the first multiplexer, and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit when the access request is a read request; if the amount of first data is not less than the first threshold or the amount of second data is not less than the second threshold, then entering a waiting state until the amount of first data is less than the first threshold and the amount of second data is less than the second threshold.

[0145] In this embodiment, when processing a read request, it is necessary to determine whether the first data amount stored in the first memory circuit is less than a first threshold value and whether the second data amount in the second memory circuit is less than a second threshold value. The first data amount refers to the amount of data stored in the first memory circuit, and the second data amount refers to the amount of data stored in the second memory circuit. Determining whether these two data amounts are less than the preset threshold value is to ensure that when processing a read request, there is enough space in the memory circuit to store new request information to ensure the normal operation of the system. By determining whether the amount of stored data in the first memory circuit and the second memory circuit is less than the threshold value, the load of the memory circuit can be effectively controlled to avoid memory overflow or system freeze caused by excessive data volume; when the data volume is close to the threshold value, the system can enter a waiting state until the data volume drops to a safe range before continuing to process the request, thereby ensuring the stability and reliability of the system; this processing method can effectively avoid failures of the memory circuit due to excessive load, thereby improving the stability and reliability of the system.

[0146] The specific process in Figure 4 is: when the control circuit is in an idle state (specifically, the control circuit is in a non-idle state when the channel corresponding to a channel bus currently controlled by the control circuit is turned on); determine whether the first data volume reaches the first threshold and whether the second data volume reaches the second threshold. If so, enter the idle state of the control circuit; if not, receive an access request (write request or read request); select the channel in the first multiplexer to turn on according to the preset channel high priority. Determine whether it is a write request; if it is a write request, determine whether the first burst length is 1; if not, determine whether the first burst length is equal to the count value of the first counter; if not, determine whether the first data amount of the first memory circuit reaches a first threshold; if so, the control circuit enters a waiting state, that is, the control circuit is in an idle state; if not, enter the step of determining whether the first burst length is equal to the count value of the first counter; if it is not a write request, or the first burst length is 1, or the first burst length is equal to the count value of the first counter, determine whether the first data amount reaches the first threshold and whether the second data amount reaches the second threshold; if so, the control circuit enters an idle state, that is, waiting; otherwise, write the access request into the first memory circuit and the second memory circuit accordingly, and re-enter the step of receiving the access request.

[0147] In some implementations, adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities includes:

[0148] Determine, according to the second preset channel priority, the target channel bus with the highest priority among the channel buses currently transmitting the access request based on the sequence numbers of the channel buses and the preset channel priority;

[0149] Controlling the target channel corresponding to the target channel bus in the first multiplexer to be turned on;

[0150] The sequence number of each channel bus is positively or negatively correlated with its own priority.

[0151] In this implementation, the specific implementation method of adjusting the channels that are turned on in the first multiplexer according to the order of preset channel priorities is as follows: by comparing the sequence numbers of each channel bus with the preset channel priority, the channel with the highest priority in the channel bus that currently needs to transmit the access request is determined; once the target channel bus is determined, the target channel corresponding to the target channel bus in the first multiplexer is controlled to be turned on to ensure that the access request can be smoothly transmitted to the memory circuit. In the above steps, the sequence number of each channel bus is positively or negatively correlated with its own priority, which means that the priority of the channel can be determined according to the size of its sequence number, or it can be determined in the opposite way. This design can flexibly adjust the priority of the channel according to actual needs and system architecture to achieve a more efficient channel bus arbitration method.

[0152] In some implementations, adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities includes:

[0153] When an access request is received for the first time according to the second preset channel priority, determining the channel bus with the smallest sequence number among the channel buses currently transmitting the access request as the target channel bus;

[0154] Controlling a first target channel corresponding to the target channel bus in the first multiplexer to be turned on;

[0155] After storing the access request corresponding to the target channel bus in the first memory circuit, polling a previous channel bus or a next channel bus of the target channel bus in sequence, and determining whether the previous channel bus or the next channel bus transmits the access request;

[0156] If the previous channel bus or the next channel bus transmits an access request, the second target channel corresponding to the previous channel bus or the next channel bus in the first multiplexer is turned on.

[0157] This embodiment mainly involves adjusting the channels that are turned on in the first multiplexer according to the order of preset channel priorities. Specifically, when an access request is first received, the channel bus with the smallest sequence number among the channel buses currently transmitting the access request is determined as the target channel bus, and then the first target channel corresponding to the target channel bus in the first multiplexer is controlled to be turned on. Next, after the access request corresponding to the target channel bus is stored in the first memory circuit, the previous channel bus or the next channel bus of the target channel bus is polled in sequence according to the sequence number, and it is determined whether the previous channel bus or the next channel bus transmits the access request. If the previous channel bus or the next channel bus transmits the access request, the second target channel corresponding to the previous channel bus or the next channel bus in the first multiplexer is turned on.

[0158] Compared to determining priority based on the sequence number of each channel bus (sequence number is positively or negatively correlated with priority), this embodiment more flexibly processes access requests from multiple channel buses by polling the previous or next channel bus of the target channel bus in sequence and determining whether the previous or next channel bus has transmitted an access request. This method ensures that access requests are processed sequentially in sequence after being stored in the first memory circuit, thereby improving channel bus utilization and efficiency. For example, there are four channels, channel bus 0, channel bus 1, channel bus 2, and channel bus 3. If the channel corresponding to channel bus 0 in the first multiplexer is initially turned on, then after the access request corresponding to channel bus 0 is written to the first memory circuit, if the remaining three channel buses and channel bus 0 all have access requests, channel bus 1 is polled next, followed by channel bus 2, and so on, so that the priorities of each channel bus are relatively equal. However, according to the previous embodiment of setting priorities, if the sequence number of the channel bus is inversely proportional to the priority, then the priority of channel bus 0 is greater than the priority of channel bus 1, and the priority of channel bus 2 is greater than the priority of channel bus 3. If channel bus 0 always transmits access requests, the channel in the first multiplexer corresponding to channel bus 0 is always controlled to be turned on, and the channels corresponding to the other channel buses are not controlled to be turned on.

[0159] Specifically, as shown in Figure 5, one application scenario is: the channel bus arbitration circuit is a circuit in a field programmable gate array, the central processing unit sets a preset channel priority for it through PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), and the field programmable gate array is connected to two memories to be accessed.

[0160] In Figure 6, if channel bus 0 transmits a write request with a burst length of 3 for data to be written and a read request with a burst length of 4 for data to be read, channel bus 1 transmits a read request with a burst length of 1 for data to be read, and channel bus 2 transmits a write request with a burst length of 1 for data to be written, then the request processing order is shown in the upper left half of Figure 6, and the processing order is from top to bottom. The order of the read data is shown in the upper right half of Figure 6, and the order of the read data is from bottom to top.

[0161] In some implementations, the method further includes:

[0162] Receive priority setting instructions issued by the central processing unit;

[0163] The preset channel priority is set to the first preset channel priority or the second preset channel priority according to the priority setting instruction.

[0164] In some implementations, receiving a priority setting instruction issued by a central processing unit includes:

[0165] Obtaining the value written into the preset register by the central processing unit;

[0166] Setting the preset channel priority to the first preset channel priority or the second preset channel priority according to the priority setting instruction includes:

[0167] If the value in the preset register is a first value, setting the preset channel priority to a first preset channel priority;

[0168] If the value in the preset register is a second value, the preset channel priority is set to a second preset channel priority.

[0169] In a fourth aspect, a channel bus arbitration system is provided, which is applied to the channel bus arbitration circuit described above. The channel bus arbitration system includes:

[0170] A monitoring unit, configured to monitor access requests sent by multiple channel buses;

[0171] a channel adjustment unit, configured to adjust the channels turned on in the first multiplexer according to an order of preset channel priorities;

[0172] The request processing unit is used to store the access request in the first memory circuit through the first multiplexer, so that the memory to be accessed sequentially processes multiple access requests in the first memory circuit according to the order of storage.

[0173] For an introduction to the channel bus arbitration system, please refer to the above embodiment. The present application will not elaborate on the fifth aspect here. The present application further provides a channel bus arbitration device, including:

[0174] Memory for storing computer programs;

[0175] The processor is configured to implement the steps of the channel bus arbitration method described above when storing a computer program.

[0176] For the introduction of the channel bus arbitration device, please refer to the above embodiment. This application will not repeat the sixth aspect here. This application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by the processor, the steps of the channel bus arbitration method as described above are implemented.

[0177] For an introduction to computer-readable storage media, please refer to the above embodiments, and this application will not go into details here.

[0178] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0179] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A channel bus arbitration circuit, characterized in that: comprising a control circuit, a first multiplexer, and a first memory circuit; A channel bus is connected to an input terminal of the first multiplexer, the channel bus is connected to an acceleration function unit, an output terminal of the first multiplexer is connected to one terminal of the first memory circuit, the other terminal of the first memory circuit is connected to a memory to be accessed, and the control circuit is connected to a control terminal of the first multiplexer; The control circuit is used to monitor the access requests sent by each of the channel buses and adjust the channels that are turned on in the first multiplexer according to the order of preset channel priorities, so as to store each of the access requests in the first memory circuit in sequence, so that the memory to be accessed processes the access requests in the first memory circuit in sequence according to the order in which they are stored.

2. The channel bus arbitration circuit according to claim 1, wherein: The channel bus arbitration circuit further includes a second memory circuit and a second multiplexer; one end of the second memory circuit is connected to the first memory circuit, the other end of the second memory circuit is connected to the control end of the second multiplexer, an input end of the second multiplexer is connected to the memory to be accessed, and multiple output ends of the second multiplexer are respectively connected to the channel bus; The first memory circuit is specifically configured to store the first message corresponding to the write request into its own storage space when the access request is a write request; When the access request is a read request, storing the request type and the address to be read in the second message corresponding to the read request into its own storage space, and storing the channel bus identifier in the second message into the second memory circuit, wherein the first message includes the request type, the address to be written, and the data to be written; The second memory circuit is used to store the identifier of the channel bus corresponding to the read request, and when the data to be read corresponding to the second message is read from the memory to be accessed, control the channel corresponding to the channel bus corresponding to the channel bus identifier in the second multiplexer to be turned on, so as to transmit the data to be read corresponding to the second message to the channel bus corresponding to the channel bus identifier.

3. The channel bus arbitration circuit according to claim 2, wherein: The first message further includes a first burst length of the data to be written, the channel bus arbitration circuit further includes a first counter, one end of the first counter is connected to the output end of the first multiplexer, the other end of the first counter is connected to the first memory circuit, and the output end of the first counter is connected to the control circuit; The first counter is configured to increase its first count value by one when the write request sent by the channel bus is valid, and output a channel switching signal to the control circuit when the first count value reaches the first burst length; The control circuit is specifically configured to, when controlling the channels of the first multiplexer to be turned on for the first time, select, based on the preset channel priority, the channels corresponding to the channel bus with the highest priority for turning on; and, when controlling the channels of the first multiplexer to be turned on for a non-initial time, adjust the channels turned on in the first multiplexer based on the channel switching signal and the preset channel priority, so as to sequentially store the access requests in the first memory circuit, so that the memory to be accessed sequentially processes the access requests in the first memory circuit in the order in which they are stored.

4. The channel bus arbitration circuit according to claim 2, wherein: The second message also includes a second burst length of the data to be read, the first memory circuit is further used to store the second burst length in the second memory circuit when the access request is a read request, and the second memory is further used to store the second burst length; The channel bus arbitration circuit further includes a second counter, a first terminal of the second counter and an input terminal of the second multiplexer. An input end is connected to the second counter, and a second end of the second counter is connected to the second memory circuit; The second counter is configured to increase its second count value by one when the data flag of the data to be read inputted at the input end of the second multiplexer is valid, and to clear the second count value to zero when the second count value reaches the second burst length.

5. An acceleration device, characterized in that: It includes multiple acceleration function units and multiple channel buses, and also includes the channel bus arbitration circuit as described in any one of claims 1 to 4, and the multiple acceleration function units are connected to the control circuit of the channel bus arbitration circuit through the channel buses corresponding to themselves one by one.

6. A channel bus arbitration method, characterized in that: A control circuit applied to a channel bus arbitration circuit according to any one of claims 1 to 4, wherein the channel bus arbitration method comprises: Monitor access requests sent by multiple channel buses; Adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities; The access requests are stored in the first memory circuit through the first multiplexer, so that the memory to be accessed sequentially processes the multiple access requests in the first memory circuit according to the order of storage.

7. The channel bus arbitration method according to claim 6, wherein: The channel bus arbitration circuit further includes a second memory circuit and a second multiplexer; one end of the second memory circuit is connected to the first memory circuit, the other end of the second memory circuit is connected to the control end of the second multiplexer, an input end of the second multiplexer is connected to the memory to be accessed, and multiple output ends of the second multiplexer are respectively connected to the multiple channel buses in a one-to-one correspondence; Storing the access request in a first memory circuit via the first multiplexer includes: When the access request is a write request, storing a first message corresponding to the write request in the first memory circuit through the first multiplexer, the first message including a request type, an address to be written, and data to be written; When the access request is a read request, storing the request type and the to-be-read address in the second message corresponding to the read request in the first memory circuit through the first multiplexer, and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit; When the data to be read is read from the memory to be accessed, triggering the second memory circuit to control the channel corresponding to the channel bus corresponding to the channel bus identifier in the second multiplexer to be turned on; The to-be-read data is transmitted to the channel bus corresponding to the channel bus identifier through the conductive channel in the first multiplexer.

8. The channel bus arbitration method according to claim 7, wherein: The first message also includes a first burst length of the data to be written, and the channel bus arbitration method further includes: When the access request is a write request, determining whether the first burst length is one; In response to the first burst length being one, storing the first message corresponding to the write request in the first memory circuit through the first multiplexer, and after completing writing the data to be written, entering the step of monitoring access requests sent by the multiple channel buses; In response to the first burst length not being one, the first message corresponding to the write request is stored in the first memory circuit through the first multiplexer, and the valid write requests transmitted by the first multiplexer are counted, and when the first count value of the valid write requests reaches the first burst length, a channel switching signal is output, and the first count value is cleared to zero, and the monitoring state is entered. Describe the steps of sending access requests to multiple channel buses.

9. The channel bus arbitration method according to claim 8, wherein: The channel bus arbitration circuit further includes a first counter, one end of the first counter is connected to the output end of the first multiplexer, the other end of the first counter is connected to the first memory circuit, and the output end of the first counter is connected to the control circuit; The step of counting valid write requests transmitted by the first multiplexer, outputting a channel switching signal when a first count value of the valid write requests reaches the first burst length, clearing the first count value, and entering the step of monitoring access requests sent by the multiple channel buses includes: triggering the first counter to increase its own first count value by one when detecting that the write request transmitted by the first multiplexer is valid; When the first count value reaches the first burst length, a channel switching signal is output and the first count value is cleared to zero, so as to enter the step of monitoring access requests sent by the plurality of channel buses.

10. The channel bus arbitration method according to claim 7, wherein: The second message also includes a second burst length of the data to be read, and the channel bus arbitration method further includes: When the data to be read is read from the memory to be accessed, the valid number of data flag bits of the data to be read inputted from the input end of the second multiplexer is counted to obtain a second count value; When the second count value reaches the second burst length, the second count value is cleared to zero.

11. The channel bus arbitration method according to claim 10, wherein: The channel bus arbitration circuit further includes a second counter, wherein a first end of the second counter is connected to an input end of the second multiplexer, and a second end of the second counter is connected to the second memory circuit; when the data to be read is read from the memory to be accessed, the second counter counts the valid number of data flag bits of the data to be read inputted from the input end of the second multiplexer to obtain a second count value, including: When the data to be read is read from the memory to be accessed, determining whether a data flag bit of the data to be read inputted from the input end of the second multiplexer is valid; In response to the data flag being valid, triggering the second count value of the second counter to be incremented by one; When the second count value reaches the second burst length, clearing the second count value to zero includes: When the second count value reaches the second burst length, the second counter is triggered to clear the second count value to zero.

12. The channel bus arbitration method according to claim 8, wherein: Before storing the first message corresponding to the write request in the first memory circuit through the first multiplexer, the method further includes: determining whether an amount of first data stored in the first memory circuit is less than a first threshold, where the first threshold is less than a capacity value of the first memory circuit; In response to the first data amount being less than the first threshold, entering a step of storing the first message corresponding to the write request in the first memory circuit through the first multiplexer; In response to the first data amount being not less than the first threshold, entering a waiting state until the first data amount stored in the first memory circuit is less than the first threshold.

13. The channel bus arbitration method according to claim 12, wherein: When the first burst length is not one, determining whether the amount of first data stored in the first memory circuit is less than a first threshold includes: Each time the write request is received and the first count value does not reach the first burst length, the first memory circuit is determined whether the amount of first data stored in is less than a first threshold; In response to the first count value not reaching the first burst length and the first data amount stored in the first memory circuit being not less than the first threshold, entering a waiting state until the first data amount stored in the first memory circuit is less than the first threshold.

14. The channel bus arbitration method according to claim 8, wherein: When the access request is a read request, before storing the request type and the to-be-read address in the second message corresponding to the read request in the first memory circuit through the first multiplexer and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit, the method further includes: determining whether an amount of first data stored in the first memory circuit is less than a first threshold and whether an amount of second data stored in the second memory circuit is less than a second threshold, wherein the first threshold is less than a capacity value of the first memory circuit and the second threshold is less than a capacity value of the second memory circuit; In response to the first data amount being less than the first threshold and the second data amount being less than the second threshold, when the access request is a read request, the step of storing the request type and the to-be-read address in the second message corresponding to the read request in the first memory circuit via the first multiplexer, and triggering the first memory circuit to store the channel bus identifier in the second message in the second memory circuit; In response to the first data amount being not less than the first threshold or the second data amount being not less than the second threshold, entering a waiting state until the first data amount is less than the first threshold and the second data amount is less than the second threshold.

15. The channel bus arbitration method according to any one of claims 6 to 14, characterized in that: Adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities, including: Determine, according to the first preset channel priority, a target channel bus with the highest priority among the channel buses currently transmitting the access request based on the sequence numbers of the channel buses and the preset channel priorities; controlling the target channel corresponding to the target channel bus in the first multiplexer to be turned on; The sequence number of each channel bus is positively correlated or negatively correlated with its own priority.

16. The channel bus arbitration method according to claim 15, wherein: Adjusting the channels turned on in the first multiplexer according to the order of preset channel priorities, including: When the access request is received for the first time according to the second preset channel priority, determining the channel bus with the smallest sequence number among the channel buses currently transmitting the access request as the target channel bus; controlling a first target channel corresponding to the target channel bus in the first multiplexer to be turned on; After storing the access request corresponding to the target channel bus in the first memory circuit, polling a previous channel bus or a next channel bus of the target channel bus in sequence, and determining whether the previous channel bus or the next channel bus transmits the access request; In response to the previous channel bus or the next channel bus transmitting the access request, the second target channel corresponding to the previous channel bus or the next channel bus in the first multiplexer is turned on.

17. The channel bus arbitration method according to claim 16, wherein: Also includes: Receive priority setting instructions issued by the central processing unit; The preset channel priority is set to the first preset channel priority or the second preset channel priority according to the priority setting instruction.

18. The channel bus arbitration method according to claim 17, wherein: Receive priority setting instructions from the central processing unit, including: Obtaining the value written into the preset register by the central processing unit; Setting the preset channel priority to the first preset channel priority or the second preset channel priority according to the priority setting instruction includes: In response to the value in the preset register being a first value, setting the preset channel priority to a first preset channel priority; In response to the value in the preset register being a second value, the preset channel priority is set to a second preset channel priority.

19. A channel bus arbitration system, characterized in that: A control circuit applied to a channel bus arbitration circuit according to any one of claims 1 to 4, wherein the channel bus arbitration system comprises: a monitoring unit, configured to monitor access requests sent by the plurality of channel buses; a channel adjustment unit, configured to adjust the channels turned on in the first multiplexer according to an order of preset channel priorities; The request processing unit is configured to store the access request in the first memory circuit through the first multiplexer, so that the memory to be accessed sequentially processes the multiple access requests in the first memory circuit according to the order in which they are stored.

20. A channel bus arbitration device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the channel bus arbitration method according to any one of claims 6 to 18 when storing a computer program.

21. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the channel bus arbitration method according to any one of claims 6 to 18 are implemented.

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