Back-contact cell and manufacturing method therefor

Abstract

The present application relates to the technical field of photovoltaics. Disclosed are a back-contact cell and a manufacturing method therefor, which are used for reducing the risk of electric leakage between a first doped semiconductor layer and a second doped semiconductor layer which have opposite conductivity types in the back-contact cell. The back-contact cell comprises: a semiconductor substrate, a first doped semiconductor layer, a second doped semiconductor layer, a first dielectric layer, and a second dielectric layer, wherein at least part of the first dielectric layer and at least part of the second dielectric layer are stacked between the first doped semiconductor layer and the second doped semiconductor layer in the arrangement direction of a first region and a second region, the at least part of the first dielectric layer is in contact with the first doped semiconductor layer, and the at least part of the second dielectric layer is in contact with the second doped semiconductor layer; the first dielectric layer and the second dielectric layer are made of different materials; and a structure formed by the first dielectric layer and the second dielectric layer is used for electrically isolating at least part of the region of the first doped semiconductor layer from at least part of the region of the second doped semiconductor layer.

Description

Back contact battery and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and benefits of Chinese patent application No. 202410216919.8, filed on February 27, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a method for manufacturing the same. Background Art

[0004] Back-contact cells are solar cells with both the positive and negative electrodes on the back of the cell, with no metal electrodes blocking the front. Compared to solar cells with obstructed front surfaces, back-contact cells offer higher short-circuit current and photoelectric conversion efficiency, and are currently one of the technological advancements in achieving high-efficiency crystalline silicon cells.

[0005] However, in existing back-contact cells, the risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer, which have opposite conductivity types and are alternately distributed on the backlight side, is high, which is not conducive to improving the working performance of the back-contact cell. Summary of the Invention

[0006] The purpose of this application is to provide a back-contact battery and a manufacturing method thereof, which are used to reduce the leakage risk between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types in the back-contact battery, thereby improving the working performance of the back-contact battery.

[0007] To achieve the above objectives, in a first aspect, the present application provides a back-contact cell, comprising: a semiconductor substrate, a first doped semiconductor layer, a second doped semiconductor layer, a first dielectric layer, and a second dielectric layer. The backlight surface of the semiconductor substrate comprises alternating first and second regions, as well as a spacing region between each first region and its adjacent second region. The first doped semiconductor layer is formed on the first region of the backlight surface. The second doped semiconductor layer is formed at least on the second region of the backlight surface; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. The first dielectric layer and the second dielectric layer are formed at least on the spacing region of the backlight surface. At least a portion of the first dielectric layer and at least a portion of the second dielectric layer are stacked and disposed between the first doped semiconductor layer and the second doped semiconductor layer along the arrangement direction of the first and second regions, with at least a portion of the first dielectric layer in contact with the first doped semiconductor layer and at least a portion of the second dielectric layer in contact with the second doped semiconductor layer. The first and second dielectric layers are made of different materials; and the structure formed by the first and second dielectric layers serves to electrically isolate at least a portion of the first doped semiconductor layer from at least a portion of the second doped semiconductor layer.

[0008] When the above-mentioned technical solution is adopted, in the back-contact battery provided by the present application, the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types are both located on the backlight side of the semiconductor substrate. The area between the first doped semiconductor layer and the second doped semiconductor layer corresponding to the backlight side of the semiconductor substrate is a spacing area. The existence of the spacing area can spatially separate the first doped semiconductor layer and the second doped semiconductor layer in a direction parallel to the backlight side. In addition, the back-contact battery provided by the present application also includes a first dielectric layer and a second dielectric layer formed at least on the spacing area on the backlight side. At least part of the first dielectric layer and at least part of the second dielectric layer are stacked between the first doped semiconductor layer and the second doped semiconductor layer along the arrangement direction of the first area and the second area. It can be seen that along the arrangement direction of the first region and the second region, there are two dielectric layers, a first dielectric layer and a second dielectric layer, between at least part of the first doped semiconductor layer and at least part of the second doped semiconductor layer for achieving electrical isolation. Compared with the existing back-contact battery in which the first doped semiconductor layer and the second doped semiconductor are only isolated by a single dielectric layer with poor insulation (such as a surface passivation layer), the structure formed by the first dielectric layer and the second dielectric layer in the present application has a higher electrical isolation effect, reduces the leakage risk between at least part of the first doped semiconductor layer and at least part of the second doped semiconductor layer, and is conducive to improving the working performance of the back-contact battery.

[0009] In addition, at least a portion of the first dielectric layer contacts the first doped semiconductor layer, and at least a portion of the second dielectric layer contacts the second doped semiconductor layer. Furthermore, the first dielectric layer and the second dielectric layer are made of different materials, which facilitates determining the materials of the first dielectric layer and the second dielectric layer based on the different distribution locations of the first and second dielectric layers, different contact objects, and different practical needs, thereby improving the applicability of the back-contact battery provided by this application in different application scenarios.

[0010] As a possible implementation solution, the material of the first dielectric layer contains oxygen.

[0011] When the above technical solution is adopted, the dielectric layer containing oxygen elements in the material has a higher dielectric property, which can improve the electrical isolation effect of the first dielectric layer and further reduce the leakage risk between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer.

[0012] As a possible implementation solution, the material of the first dielectric layer contains silicon.

[0013] When adopting the above technical solution, the content of silicon in nature is abundant, and there are many types of dielectric materials containing silicon, such as silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide, etc., which makes it easy to select suitable types according to different actual needs, and is beneficial to improving the applicability of the back contact battery provided in this application in different application scenarios.

[0014] As a possible implementation solution, the first dielectric layer includes a tunneling oxide layer.

[0015] When adopting the above technical solution, the first dielectric layer can include not only a thick insulating dielectric layer but also a thin tunnel oxide layer, providing an alternative structure for the first dielectric layer. In addition, the manufacturing process of the tunnel oxide layer is relatively mature. Therefore, when the first dielectric layer includes a tunnel oxide layer, the compatibility of the back-contact battery provided by this application with existing back-contact battery manufacturing processes can be improved, and the manufacturing difficulty of the first dielectric layer can be reduced.

[0016] As a possible implementation solution, the material of the first dielectric layer includes at least one of silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and zinc oxide.

[0017] When employing the above-described technical solution, a variety of materials are available for the first dielectric layer, making it easy to select the appropriate material based on different practical needs, thereby improving the applicability of the back-contact battery provided herein in various application scenarios. Furthermore, silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and zinc oxide all exhibit excellent electrical isolation properties, further reducing the risk of leakage between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer.

[0018] As a possible implementation solution, the second dielectric layer includes a crystalline silicon layer, and the doping type of the crystalline silicon layer includes at least one of an intrinsic type and a lightly doped type.

[0019] When employing the above technical solution, the second dielectric layer may include a crystalline silicon layer, and the doping type of the crystalline silicon layer may include at least one of an intrinsic type and a lightly doped type. Intrinsic crystalline silicon material has a relatively poor conductivity. Therefore, when the doping type of the crystalline silicon layer is intrinsic, the second dielectric layer provides excellent electrical isolation, ensuring that the structure formed by the first and second dielectric layers can reduce the risk of leakage between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer. In the actual manufacturing process, when at least the second doped semiconductor layer is doped with impurities, the impurities therein may diffuse into the contacting portion of the second dielectric layer, thereby causing the doping type of at least a portion of the second dielectric layer to become lightly doped. Therefore, when the doping type of the crystalline silicon layer is lightly doped, there is no need to strictly control the manufacturing conditions to ensure that the conductivity type of the crystalline silicon layer is intrinsic, which helps reduce the manufacturing difficulty of back-contact cells.

[0020] As a possible implementation solution, when the doping type of the crystalline silicon layer includes a lightly doped type, the doping concentration of the impurities in the crystalline silicon layer is greater than or equal to 1E15 / cm 3 , and less than or equal to 5E21 / cm 3 .

[0021] When employing the above technical solution, it can be understood that, within a certain range, the greater the impurity doping concentration within the crystalline silicon layer, the better its conductivity. Based on this, when the doping type of the crystalline silicon layer includes a lightly doped type, the impurity doping concentration within the crystalline silicon layer is within the above range. This can prevent the dielectric properties of the second dielectric layer from being lowered due to the high impurity doping concentration within the crystalline silicon layer, thereby ensuring a high degree of electrical isolation between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer.

[0022] As a possible implementation scheme, when the doping types of the crystalline silicon layer include intrinsic type and lightly doped type, the portion of the crystalline silicon layer with intrinsic doping type and the portion of the crystalline silicon layer with lightly doped type are distributed along the direction of the second dielectric layer close to the second doped semiconductor layer, and the lightly doped portion is in contact with the second doped semiconductor layer.

[0023] When the above technical solution is employed, at least a portion of the second dielectric layer contacts the second doped semiconductor layer. Furthermore, when the doping types of the crystalline silicon layer included in the second dielectric layer include both intrinsic and lightly doped types, the intrinsic and lightly doped portions of the crystalline silicon layer are distributed along the second dielectric layer in a direction close to the second doped semiconductor layer, and the lightly doped portions are in contact with the second doped semiconductor layer. In this case, as described above, during the actual manufacturing process, when at least the second doped semiconductor layer is doped with impurities, the impurities therein may diffuse into the contacting portion of the second dielectric layer, thereby changing the doping type of at least a portion of the second dielectric layer to a lightly doped type. This allows for the manufacture of the above crystalline silicon layer without requiring additional doping treatments to form the crystalline silicon layer, thereby simplifying the manufacturing process and manufacturing difficulty of the second dielectric layer.

[0024] As a possible implementation solution, the crystal phase of the first dielectric layer is amorphous, and the crystal phase of the second dielectric layer includes at least one of microcrystalline, nanocrystalline, polycrystalline or single crystal.

[0025] When employing the above technical solution, the different materials of the first and second dielectric layers may also refer to different crystalline phases of the first and second dielectric layers, providing a screening direction for selecting materials for the first and second dielectric layers. Furthermore, there are multiple options for the crystalline phase of the second dielectric layer, and second dielectric layers with different crystalline phases may have different physical properties, thereby improving the applicability of the back-contact battery provided herein in different application scenarios.

[0026] As a possible implementation solution, along the arrangement direction of the first region and the second region, the width of a portion of the first dielectric layer corresponding to the spacing region is greater than or equal to 1 nm and less than or equal to 3 nm.

[0027] When employing the above technical solution, the width of the portion of the first dielectric layer corresponding to the spacing region is within the above range. This prevents the first dielectric layer from having poor dielectric properties along the arrangement direction of the first and second regions due to the smaller width of the portion corresponding to the spacing region, thereby ensuring that at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer can be electrically isolated by the structure formed by the first and second dielectric layers. Furthermore, this prevents the first doped semiconductor layer and / or the second doped semiconductor layer from having low carrier collection efficiency due to the larger width of the portion of the first dielectric layer corresponding to the spacing region, thereby increasing the width of the spacing region between the first and second doped semiconductor layers. Furthermore, when the first dielectric layer is integrally continuous with the second passivation layer located between the second doped semiconductor layer and the semiconductor substrate, the width of the portion of the first dielectric layer corresponding to the spacing region is within the above range. This prevents the second passivation layer from having a larger thickness due to the larger width, thereby ensuring high operating performance of the back-contact battery.

[0028] As a possible implementation solution, along the arrangement direction of the first region and the second region, the width of a portion of the second dielectric layer corresponding to the spacing region is greater than or equal to 80 nm and less than or equal to 300 nm.

[0029] When the above technical solution is adopted, the width of the portion of the second dielectric layer corresponding to the spacing region is within the above range, thereby preventing the first doped semiconductor layer and / or the second doped semiconductor layer from having a low carrier collection efficiency due to the width of the portion of the second dielectric layer corresponding to the spacing region being larger, which results in a larger width of the spacing region between the first doped semiconductor layer and the second doped semiconductor layer. Secondly, it can also prevent the use of a large amount of consumables in manufacturing the second dielectric layer due to the large width of the portion of the second dielectric layer corresponding to the spacing region, which is beneficial to controlling the manufacturing cost of the back contact battery. In addition, when the second dielectric layer and the second doped semiconductor layer are continuous and integral, the width of the portion of the second dielectric layer corresponding to the spacing region is within the above range, which can also prevent the second doped semiconductor layer from having a low carrier collection efficiency due to the small width of the portion of the second dielectric layer corresponding to the spacing region, which results in a small thickness of the second doped semiconductor layer, thereby ensuring that the back contact battery has high operating performance.

[0030] As a possible implementation, the first dielectric layer includes a first dielectric portion and a second dielectric portion that are continuous and integral. Along the arrangement of the first and second regions, the first dielectric portion is located between the second dielectric layer and the first doped semiconductor layer. The second dielectric portion is located between the second dielectric layer and the semiconductor substrate.

[0031] When using the above technical solution, the first dielectric layer is located not only on the side of the second dielectric layer closest to the first doped semiconductor layer, but also on the side of the second dielectric layer closest to the semiconductor substrate. Therefore, in the actual manufacturing process, after depositing a layer of material that is disposed entirely on the backlight side and used to form the first dielectric layer, there is no need to perform an additional etching operation before forming the second dielectric layer to remove the portion of the material layer located between the second dielectric layer and the semiconductor substrate, thereby simplifying the manufacturing process for the first dielectric layer.

[0032] As one possible implementation, the first dielectric layer includes a first dielectric portion and a third dielectric portion that are integrally connected. Along the arrangement of the first and second regions, the first dielectric portion is located between the second dielectric layer and the first doped semiconductor layer. The third dielectric portion is located on a side of the first doped semiconductor layer facing away from the semiconductor substrate, and a first conductive window is defined through the third dielectric portion.

[0033] When the above technical solution is adopted, the first dielectric layer is not only located between the second dielectric layer and the first doped semiconductor layer along the arrangement direction of the first region and the second region, but also located on the side of the first doped semiconductor layer facing away from the semiconductor substrate. This can increase the formation range of the first dielectric layer and reduce the selective etching range of the material layer formed by deposition on the backlight side and used to manufacture the first dielectric layer during the actual manufacturing process, which is conducive to improving etching efficiency and production capacity. Secondly, the presence of the third dielectric portion is also conducive to passivating the surface of the first doped semiconductor layer facing away from the semiconductor substrate, which is conducive to reducing the number of defects on the side of the first doped semiconductor layer facing away from the semiconductor substrate. In addition, a first conductive window is provided through the second dielectric portion, which is conducive to direct contact between the first doped semiconductor layer and the corresponding electrode, reducing the contact resistance between the two, and ensuring that the back-contact battery has high operating performance.

[0034] As one possible implementation, the second dielectric layer extends onto the third dielectric portion of the first dielectric layer, and the first conductive window penetrates the portion of the second dielectric layer corresponding to the first region. This increases the range over which the second dielectric layer is formed, reduces the selective etching range of the material layer deposited as a whole and disposed on the backlight side during actual manufacturing, and improves etching efficiency and production capacity. Furthermore, the first conductive window penetrates the portion of the second dielectric layer corresponding to the first region, enabling direct contact between the first doped semiconductor layer and the corresponding electrode, thereby reducing contact resistance between the two.

[0035] As a possible implementation scheme, the above-mentioned second doped semiconductor layer includes a first doped portion and a second doped portion that are electrically connected. The first doped portion is located on the second region. The second doped portion is located on the side of the second dielectric layer away from the first dielectric layer, and the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion. In this case, it is beneficial to increase the formation range of the second doped semiconductor layer, reduce the selective etching range of the intrinsic semiconductor layer that is formed by deposition and other processes in the actual manufacturing process, and is arranged on the side of the backlight surface and used to manufacture the second doped semiconductor layer, which is beneficial to improve etching efficiency and production capacity. In addition, the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion, which is beneficial to prevent short circuits caused by electrical connection between the first doped semiconductor layer and the first doped portion through the second doped portion, thereby ensuring that the back contact battery has high electrical reliability.

[0036] As a possible implementation, the second doped semiconductor layer includes a first doped portion and a second doped portion that are electrically connected. The first doped portion is located on the second region. The second doped portion is disposed in the spacing region and extends into the first region. The portion of the second doped portion corresponding to the spacing region is located on a side of the second dielectric layer facing away from the first dielectric layer, and the portion of the second doped portion corresponding to the first region is located above the third dielectric portion facing away from the first doped semiconductor layer. The doping concentration of impurities in the second doped portion is lower than the doping concentration of impurities in the first doped portion.

[0037] When the above technical solution is adopted, the above second doped portion can not only be located in the spacing area, but can also extend to the first area, which can further increase the formation range of the second doped semiconductor layer and further improve the etching efficiency and etching capacity of the selective etching of the second doped semiconductor layer.

[0038] As a possible implementation, when the second doped semiconductor layer includes a first doped portion and a second doped portion that are electrically connected, the second dielectric layer extends onto the third dielectric portion included in the first dielectric layer, and a portion of the second doped portion corresponding to the first region is located above a portion of the second dielectric layer corresponding to the first region. The first conductive window extends through the second dielectric layer and the portion of the second doped portion corresponding to the first region.

[0039] When the above technical solution is used, when the second doped portion of the second doped semiconductor layer is not only located within the spacing region but also extends into the first region, the second dielectric layer also extends onto the third dielectric portion of the first dielectric layer. In this case, the second doped portion of opposite conductivity and the first doped semiconductor layer are separated not only by the third dielectric portion but also by the portion of the second dielectric layer corresponding to the first region, ensuring a high degree of electrical isolation between the portion of the second doped portion corresponding to the first region and the first doped semiconductor layer.

[0040] As a possible implementation, when the second doped semiconductor layer includes an electrically connected first doped portion and a second doped portion, the back-contact cell further includes a third dielectric layer located between the third dielectric portion and the first doped semiconductor layer. The first conductive window extends through the third dielectric layer. In this case, the third dielectric portion and the third dielectric layer are located between the second doped portion of opposite conductivity type and the first doped semiconductor layer, ensuring high electrical isolation between the portion of the second doped portion corresponding to the first region and the first doped semiconductor layer.

[0041] As a possible implementation solution, the thickness of the second doping portion is greater than or equal to 40 nm and less than or equal to 150 nm.

[0042] When employing the above technical solution, if the thickness of the second doped portion is within the above range, this can prevent the need for high precision control of doping conditions during manufacturing due to the smaller thickness of the second doped portion, thereby reducing the difficulty of manufacturing the second doped portion. Furthermore, when the second dielectric layer and the second doped semiconductor layer are integrally continuous, if the thickness of the second doped portion is within the above range, this can also prevent the risk of leakage from at least portions of the first doped semiconductor layer and at least portions of the second doped semiconductor layer being reduced by the first and second dielectric layers due to the larger thickness of the second doped portion, thereby ensuring high operating performance of the back-contact cell.

[0043] As a possible implementation solution, the doping concentration of impurities in the second doping portion is greater than 0 and less than or equal to 1E20 cm-3.

[0044] When the above technical solution is adopted, the doping concentration of impurities in the second doping part is within the above range, which can prevent the degree of leakage risk reduced by the first dielectric layer and the second dielectric layer in at least part of the first doped semiconductor layer and at least part of the second doped semiconductor layer due to the high conductivity of the second doped part due to the high doping concentration of impurities in the second doping part, thereby ensuring that the back contact battery has high working performance.

[0045] As a possible implementation scheme, when the second doped semiconductor layer includes a first doped portion and a second doped portion that are electrically connected, along the arrangement direction of the first region and the second region, the width of the portion of the second dielectric layer corresponding to the spacing region is greater than or equal to 40 nm and less than or equal to 150 nm.

[0046] When employing the above technical solution, the width of the portion of the second dielectric layer corresponding to the spacing region is within the above-mentioned range. This prevents the second dielectric layer from having poor dielectric properties along the arrangement direction of the first and second regions due to the smaller width of the portion of the second dielectric layer corresponding to the spacing region, thereby ensuring that at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer can be electrically isolated by the structure formed by the first and second dielectric layers. Furthermore, this prevents the first and / or second doped semiconductor layers from having low carrier collection efficiency due to a larger width of the spacing region between the first and second doped semiconductor layers due to a larger width of the portion of the second dielectric layer corresponding to the spacing region. Furthermore, when the second dielectric layer and the second doped semiconductor layer are continuous and integral, the width of the portion of the second dielectric layer corresponding to the spacing region is within the above-mentioned range. This also prevents the second doped semiconductor layer from having low carrier collection efficiency due to a smaller thickness of the second doped semiconductor layer due to a smaller width of the portion of the second dielectric layer corresponding to the spacing region, thereby ensuring high operating performance of the back-contact cell.

[0047] As a possible implementation, when the first dielectric layer includes an integral and continuous first dielectric portion and a third dielectric portion, the back-contact cell further includes a third dielectric layer located between the third dielectric portion and the first doped semiconductor layer. The first conductive window extends through the third dielectric layer.

[0048] When employing the above-described technical solution, during the actual manufacturing process, after forming a full-layer first doped semiconductor layer on the backlight side, it is necessary to selectively etch the first doped semiconductor layer using a mask at least on the portion of the third dielectric layer corresponding to the first region. Therefore, if the first dielectric layer includes the aforementioned third dielectric portion located on the side of the first doped semiconductor layer facing away from the semiconductor substrate, the selective etching of the material used to form the second dielectric layer can be stopped at the third dielectric portion without affecting the underlying third dielectric layer. In this case, if the back-contact cell includes the aforementioned third dielectric layer located above the first region, the portion of the third dielectric layer corresponding to the first region is not removed after the selective etching of the first doped semiconductor layer, thereby reducing the number of manufacturing steps in the back-contact cell and improving manufacturing efficiency.

[0049] As a possible implementation, along the arrangement direction of the first and second regions, the width of the portions of the third dielectric layer located on both sides of the first conductive window is equal. This helps to achieve a more regular structure for the back-contact battery. Furthermore, the equal width of the portions of the third dielectric layer located on both sides of the first conductive window also helps to ensure that the distances along the width direction of at least the corresponding electrode formed in the first conductive window and the film layer or electrode of the opposite conductivity type are equal, thereby suppressing leakage.

[0050] As a possible implementation solution, along the arrangement direction of the first region and the second region, a width of a portion of the third dielectric layer located on at least one side of the first conductive window is greater than or equal to 40 μm and less than or equal to 220 μm.

[0051] When the above technical solution is employed, the width of the portion of the third dielectric layer located on at least one side of the first conductive window is within the above range. This can prevent the smaller width of the portion of the third dielectric layer located on at least one side of the first conductive window from causing a smaller distance between the corresponding electrode formed in the first conductive window and the film layer or electrode of the opposite conductivity type along the width direction, thereby suppressing leakage. It can also prevent the larger width of the portion of the third dielectric layer located on at least one side of the first conductive window from causing the range of the first region corresponding to the third dielectric layer to be smaller than the range of the spacing region and / or the second region located on the backlight side together with the first region. This ensures that at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer are electrically isolated by the first dielectric layer and the second dielectric layer formed at least in the spacing region, ensuring that the second doped semiconductor layer formed on the second region has an appropriate formation range, thereby ensuring that the second doped semiconductor layer has a higher carrier collection efficiency.

[0052] As one possible implementation, the material of the first doped semiconductor layer contains silicon, and the third dielectric layer comprises a doped silica glass layer. In this case, the doping of the first doped semiconductor layer can be achieved through a diffusion process. After diffusion, a doped silica glass layer can be formed on the side of the first doped semiconductor layer facing away from the semiconductor substrate. Therefore, when the material of the first doped semiconductor layer contains silicon, and the third dielectric layer comprises a doped silica glass layer, there is no need to add an additional deposition step to form the third dielectric layer, simplifying the manufacturing process of the back-contact cell.

[0053] As a possible implementation, the second doped semiconductor layer includes a first doped portion and a third doped portion that are electrically connected. The first doped portion is located on the second region, and the third doped portion is located on the spacing region. The doping concentration of impurities in the third doped portion is lower than the doping concentration of impurities in the first doped portion.

[0054] When the above technical solution is adopted, in the actual manufacturing process, the width of the gap region between the first region and the adjacent second region is made larger due to machine accuracy and / or for the purpose of preventing leakage. Based on this, the second doped semiconductor layer includes not only the first doped portion located on the second region, but also the third doped portion located on part of the gap region. At this time, when the back contact battery is in an operating state, the second doped semiconductor layer can not only promptly collect and guide the electrons or holes corresponding to the second region, but also promptly collect and guide the electrons or holes corresponding to part of the gap region. Therefore, while electrically isolating at least part of the first doped semiconductor layer from at least part of the second doped semiconductor layer through the structure formed by the first dielectric layer and the second dielectric layer, it can also reduce the carrier recombination rate in the wider gap region, further improving the photoelectric conversion efficiency of the back contact battery. In addition, because the third doped portion is located between the first doped portion and the first doped semiconductor layer, when the doping concentration of the impurities in the third doped portion located on the partial spacing area is less than the doping concentration of the impurities in the first doped portion located on the second area, the conductivity of the third doped portion can be reduced, and the electrical breakdown penetrating the first dielectric layer and the second dielectric layer can be reduced. At the same time, the diffusion of impurities in the third doped portion into the second dielectric layer can be suppressed or even eliminated, ensuring that the structure formed by the first dielectric layer and the second dielectric layer has a good electrical isolation effect and ensuring that the back contact battery has good electrical performance.

[0055] As a possible implementation solution, the doping concentration of the impurities in the third doping portion is greater than or equal to 1E15 cm -3 , and less than or equal to 5E21cm -3 .

[0056] When using the above technical solution, the impurity concentration within the third doped portion is within the above range. This prevents the third doped portion from having poor carrier collection capabilities due to a low impurity concentration, further improving the degree to which the third doped portion reduces the carrier recombination rate in the gap region. Furthermore, it prevents carriers from easily diffusing into the intrinsic semiconductor layer due to a high impurity concentration within the third doped portion, ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0057] As a possible implementation solution, the doping concentration of impurities in the third doped portion gradually decreases along the direction from the second region to the first region. In this case, while maintaining a certain doping concentration of impurities in the third doped portion, thereby enabling the third doped portion to have a certain lateral carrier collection capability, the portion of the third doped portion with the lowest impurity concentration can also be brought into contact with the second dielectric layer, reducing the carrier concentration gradient at the contact point between the two, further suppressing or even eliminating the diffusion of impurities in the third doped portion into the second dielectric layer, and ensuring that the structure formed by the first and second dielectric layers has good electrical isolation.

[0058] As a possible implementation solution, along the arrangement direction of the first region and the second region, a ratio of the width of the third doped portion to the width of the first doped portion is greater than or equal to 1:20,000 and less than or equal to 2:700.

[0059] When the above technical solution is adopted, when the ratio of the width of the third doping portion to the width of the first doping portion is within the above range, the width of the first doping portion is much larger than the width of the third doping portion, which can prevent the first doping portion from having a poor carrier collection ability due to its small width. It can also prevent the width of the spacing region and the first region, which are located on the backlight side together with the second region, from being small due to the large width of the first doping portion, thereby ensuring that at least part of the first doped semiconductor layer and at least part of the second doped semiconductor layer can be electrically isolated by the first dielectric layer and the second dielectric layer formed at least in the spacing region, ensuring that the first doped semiconductor layer formed on the first region has a suitable formation range, and further ensuring that the first doped semiconductor layer has a high carrier collection efficiency.

[0060] As a possible implementation, the back-contact cell further includes a first electrode and a second electrode. The first electrode is formed on the first doped semiconductor layer and is in ohmic contact with the first doped semiconductor layer. The second electrode is formed on the first doped portion and is in ohmic contact with the first doped portion. Along the arrangement direction of the first and second regions, the distance between the geometric center of the portion of the second electrode adjacent to the third doped portion and the third doped portion is greater than or equal to 110 μm and less than or equal to 380 μm.

[0061] When the above technical solution is adopted, the second electrode is formed on the first doped part and is in ohmic contact with the first doped part. In this case, the distance between the geometric center of the second electrode and the part adjacent to the third doped part included in the second doped semiconductor layer and the third doped part will affect the width of the first doped part along the arrangement direction of the first region and the second region, thereby affecting the carrier collection efficiency of the first doped part. Based on this, the distance between the geometric center of the second electrode and the part adjacent to the third doped part and the third doped part is within the above range, which can prevent the carrier collection efficiency of the first doped part from being low due to the small distance between the geometric center of the second electrode and the part adjacent to the third doped part and the third doped part. In addition, it can also prevent the width of the spacing area and / or the first area located on the backlight side of the second region from being small due to the large width of the first doped part. The beneficial effect of preventing the width of the spacing area and / or the first area from being small can be referred to the above text and will not be repeated here.

[0062] As a possible implementation solution, a groove structure is provided on one side of the backlight surface of the semiconductor substrate, and the second region and the spacing region are both located in the groove structure.

[0063] When adopting the above technical solution, the second region and the spacing region are both located in the groove structure, so that the surface of the second region and the surface of the spacing region can be staggered relative to the surface of the first region along the thickness direction of the semiconductor substrate, which is beneficial to at least partially stagger the first doped semiconductor layer and the second doped semiconductor layer that are located on the backlight side and have opposite conductivity types along the thickness direction of the semiconductor substrate, further reducing the leakage risk on the backlight side and improving the working performance of the back contact battery.

[0064] As a possible implementation solution, a portion of the bottom surface of the groove structure corresponding to the spacing area is flush with a portion of the bottom surface of the groove structure corresponding to the second area.

[0065] When using the above technical solution, during the actual manufacturing process, after forming a full-layer first doped semiconductor layer on the backlight side and selectively etching the first doped semiconductor layer, the portion of the semiconductor substrate corresponding to the spacing region and the second region can be simultaneously etched to form a groove structure. In this case, the depth of each portion of the groove structure is the same. Based on this, when the portion of the bottom surface of the groove structure corresponding to the spacing region and the portion of the bottom surface of the groove structure corresponding to the second region are flush, the depth of the portion of the groove structure corresponding to the spacing region and the depth of the portion of the groove structure corresponding to the second region are the same. In this case, it is not necessary to selectively etch the spacing region or the second region after selectively etching the first doped semiconductor layer. This simplifies the manufacturing process of the back-contact cell and can also reduce the thickness of the semiconductor substrate material, facilitating thin-sheet production.

[0066] As one possible implementation, along the direction from the light-facing surface to the backlight surface of the semiconductor substrate, the portion of the bottom surface of the groove structure corresponding to the spacing region is lower than the portion of the bottom surface of the groove structure corresponding to the second region. In this case, the depth difference between the first doped semiconductor layer and the second doped semiconductor layer corresponding to the groove structure is greater. At least a portion of the first dielectric layer and at least a portion of the second dielectric layer are formed in the spacing region, and the structure formed by the first and second dielectric layers has an electrical isolation effect. Therefore, in this case, the risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer can be further reduced.

[0067] As a possible implementation solution, the depth of the groove structure is greater than or equal to 0.3 μm and less than or equal to 3 μm.

[0068] When using the above technical solution, the depth of the groove structure is within the above range. This prevents the first doped semiconductor layer and the second doped semiconductor layer, both located on the backlight side of the silicon substrate and having opposite conductivity types, from being offset less along the thickness of the semiconductor substrate due to the smaller depth of the groove, further reducing the risk of leakage on the backlight side. Furthermore, the need for a thicker semiconductor substrate due to the greater depth of the groove structure is avoided, thereby reducing the manufacturing cost of back-contact cells and facilitating the thin-film production of back-contact cells.

[0069] As a possible implementation solution, the above-mentioned back-contact cell further includes a first passivation layer located between the first doped semiconductor layer and the semiconductor substrate.

[0070] When adopting the above technical solution, the first passivation layer and the first doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the corresponding area on the backlight surface of the semiconductor substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0071] As a possible implementation solution, the above-mentioned back-contact cell further includes a second passivation layer located between the second doped semiconductor layer and the semiconductor substrate.

[0072] When adopting the above-mentioned technical solution, the second passivation layer and the second doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the corresponding area on the backlight surface of the semiconductor substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0073] As a possible implementation, when the back contact battery further includes a second passivation layer, the first dielectric layer and the second passivation layer are continuous and / or the porosity of the first dielectric layer is smaller than that of the second passivation layer.

[0074] When the above technical solution is adopted, when the first dielectric layer and the second passivation layer are continuous as one, the first dielectric layer and the second passivation layer can be formed simultaneously based on the same material in the same manufacturing step, which simplifies the manufacturing process of the back contact battery, improves the manufacturing efficiency of the back contact battery, and reduces the manufacturing cost of the back contact battery. In addition, compared with other dielectric materials, the dielectric constant of air is relatively small. Based on this, when the porosity of the first dielectric layer is less than the porosity of the second passivation layer, it is beneficial to make the dielectric constant of the first dielectric layer greater than the dielectric constant of the second passivation layer, which is beneficial to improve the dielectric properties of the first dielectric layer, and ensure that at least part of the first doped semiconductor layer and at least part of the second doped semiconductor layer can be electrically isolated by the structure formed by the first dielectric layer and the second dielectric layer. Secondly, it can also prevent the transmission resistance of the second passivation layer from being high, further improving the working performance of the back contact battery.

[0075] As a possible implementation solution, the second dielectric layer and the second doped semiconductor layer are integrally continuous. The beneficial effects of this case can be analyzed with reference to the beneficial effects of the first dielectric layer and the second passivation layer being integrally continuous as described above, and will not be repeated here.

[0076] As a possible implementation, the back-contact cell further includes a surface passivation layer. The surface passivation layer covers the second doped semiconductor layer and extends above the first doped semiconductor layer along the arrangement direction of the first and second regions. A first conductive window is provided through the portion of the surface passivation layer corresponding to the first region, with the bottom of the first conductive window exposing at least a portion of the first doped semiconductor layer. A second conductive window is provided through the portion of the surface passivation layer corresponding to the second region, with the bottom of the second conductive window exposing at least a portion of the second doped semiconductor layer.

[0077] As a possible implementation, the back-contact battery further includes a first electrode and a second electrode. The first electrode is formed on the first doped semiconductor layer and is in ohmic contact with the first doped semiconductor layer. The second electrode is formed on the second doped semiconductor layer and is in ohmic contact with the second doped semiconductor layer. The first electrode and the second electrode each include a plurality of collector electrodes and a plurality of bus electrodes. The collector electrodes included in the first electrode and the collector electrodes included in the second electrode both extend along a first direction and are alternately spaced along a second direction. The first direction is different from the second direction. The bus electrodes included in the first electrode and the bus electrodes included in the second electrode both extend along the second direction and are alternately spaced along the first direction. Each bus electrode is electrically connected to a collector electrode of the same polarity as itself and is insulated from a collector electrode of opposite polarity. In the above case, the width of the portion of the structure formed by the first dielectric layer and the second dielectric layer between two adjacent collector electrodes of opposite polarity along the width direction of the spacing region is approximately the same as the thickness of the second doped semiconductor layer. And / or, the length of the portion of the structure formed by the first and second dielectric layers between two adjacent collector electrodes of opposite polarity along the direction in which the spacing region extends is greater than or equal to 300 μm and less than or equal to 3000 μm. And / or, the width of the portion of the structure formed by the first and second dielectric layers between two adjacent collector electrodes of opposite polarity and a bus electrode along the width direction of the spacing region is substantially the same as the thickness of the second doped semiconductor layer. And / or, the length of the portion of the structure formed by the first and second dielectric layers between two adjacent collector electrodes of opposite polarity and a bus electrode along the direction in which the spacing region extends is greater than or equal to 200 μm and less than or equal to 700 μm. And / or, the spacing between two adjacent collector electrodes of opposite polarity is greater than or equal to 200 μm and less than or equal to 700 μm. And / or, the width of the collector electrode is greater than or equal to 15 μm and less than or equal to 60 μm.

[0078] When the above technical solution is adopted, the second doped semiconductor layer has a certain carrier collection efficiency and needs to have a corresponding thickness. Based on this, when the width of the structure formed by the first and second dielectric layers between two adjacent collector electrodes of opposite polarity along the width direction of the spacing region is approximately the same as the thickness of the second doped semiconductor layer, it can prevent the poor electrical isolation effect caused by the smaller width of the structure formed by the first and second dielectric layers. Secondly, the first and second dielectric layers can be formed using the same manufacturing process and materials at the same time as the second doped semiconductor layer is manufactured, simplifying the manufacturing process of the back-contact battery. The beneficial effect of the structure formed by the first and second dielectric layers having the width of the spacing region between two adjacent collector electrodes of opposite polarity and the thickness of the second doped semiconductor layer being approximately the same is similar to the beneficial effect of the structure formed by the first and second dielectric layers having the width of the spacing region between two adjacent collector electrodes of opposite polarity and the thickness of the second doped semiconductor layer being approximately the same, and will not be repeated here.

[0079] Furthermore, when the length of the structure formed by the first and second dielectric layers between two adjacent collector electrodes of opposite polarity along the direction extending the spacing region is greater than or equal to 300 μm and less than or equal to 3000 μm, this shorter length can prevent the region in the first and second doped semiconductor layers electrically isolated by the structure formed by the first and second dielectric layers from being smaller, thereby ensuring that the back-contact cell has a low leakage current under normal operating conditions. The beneficial effects of the structure formed by the first and second dielectric layers between two adjacent collector electrodes of opposite polarity and a bus electrode having a length greater than or equal to 200 μm and less than or equal to 700 μm along the direction extending the spacing region can be analyzed with reference to the beneficial effects of the structure formed by the first and second dielectric layers between two adjacent collector electrodes of opposite polarity having a length greater than or equal to 300 μm and less than or equal to 3000 μm along the direction extending the spacing region.

[0080] Furthermore, a spacing of 200 μm or greater and 700 μm or less between adjacent collector electrodes of opposite polarity prevents a smaller reduction in leakage risk between adjacent collector electrodes of opposite polarity due to this smaller spacing. This also prevents a larger spacing between adjacent collector electrodes of opposite polarity from resulting in a larger width of the spacing region, which would otherwise increase the carrier recombination rate in the portion of the back-contact battery corresponding to the spacing region, thereby ensuring higher operating performance of the back-contact battery.

[0081] Furthermore, a collector electrode width of 15 μm or greater and 60 μm or less can prevent the contact resistance between the collector electrode and the corresponding doped semiconductor layer from being high due to a smaller collector electrode width, thereby improving the contact performance between the collector electrode and the corresponding doped semiconductor layer. Furthermore, this can prevent the metal recombination associated with the collector electrode from being high due to a larger collector electrode width, thereby reducing metal recombination losses, thereby achieving a balance between contact performance and metal recombination losses associated with the collector electrode.

[0082] As a possible implementation, the portion of the first dielectric layer and the second dielectric layer corresponding to the portion between the first doped semiconductor layer and the second doped semiconductor layer is located over all regions of the spacing region along its own extension direction, thereby electrically isolating the first doped semiconductor layer and the second doped semiconductor layer. Alternatively, the portion of the first dielectric layer and the second dielectric layer corresponding to the portion between the first doped semiconductor layer and the second doped semiconductor layer has a discontinuity along the extension direction of the spacing region. The back-contact cell further includes a conductive structure located at least within the discontinuity. The conductive structure has a conductivity type opposite to that of one of the first doped semiconductor layer and the second doped semiconductor layer, and only portions of the first doped semiconductor layer and only portions of the second doped semiconductor layer are electrically connected to the conductive structure.

[0083] When the above technical solution is employed, when the portion of the first and second dielectric layers corresponding to the space between the first and second doped semiconductor layers is located throughout the entire region of the spacing region along its own extension direction, the structure formed by the first and second dielectric layers can electrically isolate the various portions of the first and second doped semiconductor layers, thereby minimizing the risk of leakage between the first and second doped semiconductor layers. Furthermore, when the portion of the first and second dielectric layers corresponding to the space between the first and second doped semiconductor layers has a discontinuity along the extension direction of the spacing region, and the back-contact cell further includes a conductive structure located at least within the discontinuity, the first and second doped semiconductor layers can be electrically connected by creating a local leakage point to form a built-in diode with a low reverse breakdown voltage, thereby facilitating a low reverse breakdown voltage when the back-contact cell is shielded. Secondly, only part of the area of ​​the first doped semiconductor layer and only part of the area of ​​the second doped semiconductor layer are electrically connected to the conductive structure, respectively. In other words, part of the area in the first doped semiconductor layer and the corresponding part of the area in the second doped semiconductor layer are electrically connected to at least one of the above-mentioned conductive structures, while the remaining area in the first doped semiconductor layer and the corresponding area in the second doped semiconductor layer are still electrically isolated by the structure formed by the first dielectric layer and the second dielectric layer. This prevents the back contact battery from having a large leakage current under normal working conditions due to the conductive structure being provided between all the areas of the first doped semiconductor layer and the second doped semiconductor layer, thereby preventing the back contact battery from having a low working efficiency due to the large leakage current under normal working conditions. This ensures that the photovoltaic module including the back contact battery provided by the present application has a high photoelectric conversion efficiency in the forward voltage region.

[0084] As a possible implementation, when the back-contact cell further includes a conductive structure, at least a portion of the conductive structure is continuous with the second doped semiconductor layer. The beneficial effects of this scenario are similar to those of the previously described continuous first dielectric layer and second passivation layer, and are not further elaborated here.

[0085] As a possible implementation, when the back-contact cell also includes a conductive structure, the structure formed by the first dielectric layer and the second dielectric layer is continuous with the conductive structure. The beneficial effects of this scenario are similar to those of the previously described continuous first dielectric layer and second passivation layer, and are not further elaborated here.

[0086] As a possible implementation, a non-pyramid structure is formed on the surface of the first region, and the base of the non-pyramid structure on the surface of the first region has a one-dimensional size greater than or equal to 0.5 μm and less than or equal to 20 μm. The base of the non-pyramid structure is closer to the semiconductor substrate than the top of the non-pyramid structure.

[0087] When the above technical solution is adopted, the non-pyramid-shaped velvet surface has a light-trapping effect. Therefore, when a non-pyramid-shaped structure is formed on the surface of the first region, it is beneficial for more light to be transmitted from the backlight side and through the surface of the first region into the semiconductor substrate and be utilized by the semiconductor substrate. In addition, when a non-pyramid-shaped structure is formed on the surface of the first region, the surface of the first region has an uneven topography. Based on this, the first doped semiconductor layer is formed on the first region, which is beneficial for the side of the first doped semiconductor layer facing away from the first region to also have corresponding undulating features, which is beneficial for increasing the contact area between the first doped semiconductor layer and the corresponding electrode, increasing the connection strength between the two, and reducing the contact resistance between the two. Furthermore, the one-dimensional size of the base of the non-pyramid structure on the surface of the first region is within the above-mentioned range, which can prevent the small undulation of the surface of the first region due to the small one-dimensional size, resulting in poor light trapping effect in the first region and a small contact area between the first doped semiconductor layer and the corresponding electrode; secondly, it can also prevent the large thinning of the semiconductor substrate when forming the non-pyramid structure on the surface of the first region due to the large one-dimensional size, which is conducive to the thin-film production of back-contact batteries.

[0088] As a possible implementation scheme, a non-pyramid structure is formed on the surface of the second region, and the base one-dimensional size of the non-pyramid structure on the surface of the second region is greater than or equal to 10 μm and less than or equal to 50 μm. The base of the non-pyramid structure is close to the semiconductor substrate relative to its top. The beneficial effects in this case are similar to the beneficial effects of the non-pyramid structure formed on the surface of the first region described above, and the base one-dimensional size of the non-pyramid structure on the surface of the first region is greater than or equal to 0.5 μm and less than or equal to 20 μm, and will not be repeated here.

[0089] As a possible implementation, a non-pyramid structure is formed on the surface of the spacer region, and the base of the non-pyramid structure on the surface of the spacer region has a one-dimensional size greater than or equal to 10 μm and less than or equal to 50 μm. The base of the non-pyramid structure is closer to the semiconductor substrate than the top of the non-pyramid structure.

[0090] When employing the above-described technical solution, the non-pyramid-shaped velvet surface has a light-trapping effect. Therefore, when a non-pyramid-shaped structure is formed on the surface of the spacer region, more light is facilitated to be transmitted from the backlight side through the spacer region surface into the semiconductor substrate and utilized by the semiconductor substrate. Furthermore, if the base one-dimensional size of the non-pyramid-shaped structure on the spacer region surface is within the above-described range, this can prevent the spacer region from having a poor light-trapping effect due to the smaller surface undulations of the spacer region caused by this smaller one-dimensional size. Furthermore, this can also prevent the semiconductor substrate from being significantly thinned when the non-pyramid-shaped structure on the spacer region surface is formed due to a larger one-dimensional size, thereby facilitating the thin-sheet production of back-contact cells.

[0091] In a second aspect, the present application provides a method for manufacturing a back-contact battery, which comprises: first, providing a semiconductor substrate; the backlight surface of the semiconductor substrate has first and second regions that are alternately spaced, and a spacing region between each first region and the second region adjacent to it. Next, forming a first doped semiconductor layer on the first region of the backlight surface. Next, forming a second doped semiconductor layer on at least the second region of the backlight surface. The second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. Next, forming a first dielectric layer and a second dielectric layer on at least the spacing region of the backlight surface. At least a portion of the first dielectric layer and at least a portion of the second dielectric layer are stacked between the first doped semiconductor layer and the second doped semiconductor layer along the arrangement direction of the first and second regions. At least a portion of the first dielectric layer is in contact with the first doped semiconductor layer, and at least a portion of the second dielectric layer is in contact with the second doped semiconductor layer. The materials of the first dielectric layer and the second dielectric layer are different.

[0092] As a possible implementation, forming a first doped semiconductor layer on a first region of the backlight surface includes: forming the first doped semiconductor layer entirely on the backlight surface, and a third dielectric layer located on a portion of the first doped semiconductor layer corresponding to the first region; or forming the first doped layer and the third dielectric layer entirely on the backlight surface, and heat-treating the portion of the third dielectric layer corresponding to the second region and the spacing region using a laser irradiation process; after the heat treatment, forming a mask on the portion of the third dielectric layer corresponding to the first region. Next, using the mask on the portion of the third dielectric layer corresponding to the first region, removing the portion of the first doped semiconductor layer corresponding to the second region and the spacing region.

[0093] As a possible implementation scheme, after providing a semiconductor substrate, before forming a second doped semiconductor layer at least on a second area having a backlight surface, the manufacturing method of a back-contact battery includes: forming a first passivation layer on the first area, and a first doped semiconductor layer located on the side of the first passivation layer away from the semiconductor substrate.

[0094] As a possible implementation scheme, after forming a first doped semiconductor layer on the first area of ​​the backlight surface and before forming a second doped semiconductor layer on the second area of ​​the backlight surface, the manufacturing method of the back-contact battery also includes: forming a second passivation layer on at least the second area of ​​the backlight surface.

[0095] As a possible implementation, forming a second doped semiconductor layer, a second passivation layer, a first dielectric layer, and a second dielectric layer includes: sequentially forming a passivation material layer and an intrinsic semiconductor layer along the thickness direction of the semiconductor substrate, stacked and covering the first doped semiconductor layer, the spacing region, and the second region. Next, selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region. After the selective doping, at least the portion of the intrinsic semiconductor layer corresponding to the second region forms the second doped semiconductor layer, at least the portion of the intrinsic semiconductor layer corresponding to a portion of the spacing region forms the second dielectric layer, the portion of the passivation material layer located between the second doped semiconductor layer and the semiconductor substrate forms the second passivation layer, and at least the portion of the passivation material layer corresponding to a portion of the spacing region forms the first dielectric layer.

[0096] As one possible implementation, after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, the back-contact cell manufacturing method includes retaining the portion of the passivation material layer corresponding to the first region and the portion of the intrinsic semiconductor layer corresponding to the first region. Next, forming a first conductive window above the first region, penetrating the third dielectric layer, the passivation material layer, and the intrinsic semiconductor layer.

[0097] As one possible implementation, after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, the back-contact cell manufacturing method includes: selectively removing the portion of the intrinsic semiconductor layer corresponding to the first region, while retaining the portion of the passivation material layer corresponding to the first region. Next, forming a first conductive window above the first region, penetrating the third dielectric layer and the passivation material layer.

[0098] As a possible implementation scheme, after forming a passivation material layer and an intrinsic semiconductor layer stacked and covering the first doped semiconductor layer, the spacing region and the second region in sequence along the thickness direction of the semiconductor substrate, and before selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, the manufacturing method of the back contact battery also includes: lightly doping the side of the intrinsic semiconductor layer away from the semiconductor substrate.

[0099] As one possible implementation, after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, the back-contact cell manufacturing method includes retaining the portion of the passivation material layer corresponding to the first region and the portion of the lightly doped intrinsic semiconductor layer corresponding to the first region. Next, a first conductive window is formed above the first region, penetrating the third dielectric layer, the passivation material layer, and the lightly doped intrinsic semiconductor layer.

[0100] As a possible implementation scheme, after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, the manufacturing method of the back contact battery also includes: selectively removing the portion of the intrinsic semiconductor layer and the passivation material layer corresponding to the first region; next, removing the portion of the third dielectric layer corresponding to the first region.

[0101] As a possible implementation, after forming the first doped semiconductor layer on the first region of the backlight surface and before forming the second doped semiconductor layer on at least the second region of the backlight surface, the method for manufacturing a back-contact cell further includes: selectively etching the backlight surface side of the semiconductor substrate to form a groove structure on the backlight surface side. The second region and the spacer region are both located within the groove structure.

[0102] As a possible implementation scheme, after forming the first dielectric layer and the second dielectric layer at least on the spacing area of ​​the backlight surface, the manufacturing method of the back-contact battery further includes: forming a surface passivation layer on one side of the backlight surface. The surface passivation layer covers the upper part of the second doped semiconductor layer and extends to the upper part of the first doped semiconductor layer along the arrangement direction of the first region and the second region. Next, a first conductive window is opened through the portion of the surface passivation layer corresponding to the first region, and a second conductive window is opened through the portion of the surface passivation layer corresponding to the second region. The bottom of the first conductive window exposes at least a portion of the first doped semiconductor layer. The bottom of the second conductive window exposes at least a portion of the second doped semiconductor layer.

[0103] The beneficial effects of the second aspect and its various implementations in this application can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0104] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0105] FIG1 is a schematic longitudinal cross-sectional view of a back-contact battery according to an embodiment of the present application;

[0106] FIG2 is a second schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0107] FIG3 is a third schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0108] FIG4 is a fourth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0109] FIG5 is a fifth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0110] FIG6 is a sixth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0111] FIG7 is a seventh schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0112] FIG8 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0113] FIG9 is a ninth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0114] FIG10 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0115] FIG11 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application;

[0116] FIG12 is a first schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

[0117] FIG13 is a second schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0118] FIG14 is a third schematic longitudinal cross-sectional view of the structure of a back-contact battery during the manufacturing process provided by an embodiment of the present application;

[0119] FIG15 is a fourth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0120] FIG16 is a fifth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0121] FIG17 is a sixth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

[0122] FIG18 is a seventh schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

[0123] FIG19 is a schematic diagram of a longitudinal cross-section of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present application;

[0124] FIG20 is a ninth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided in an embodiment of the present application;

[0125] FIG21 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0126] FIG22 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present application;

[0127] FIG23 is a schematic longitudinal cross-sectional view 12 of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0128] FIG24 is a thirteenth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0129] FIG25 is a schematic diagram of a longitudinal cross-section of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0130] FIG26 is a schematic diagram of a longitudinal cross-section of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0131] FIG27 is a sixteenth longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0132] FIG28 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present application;

[0133] FIG29 is a schematic diagram of a longitudinal cross-section of the structure of a back-contact battery provided in an embodiment of the present application during the manufacturing process;

[0134] FIG30 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present application;

[0135] FIG31 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell provided in an embodiment of the present application during the manufacturing process;

[0136] FIG32 is a schematic diagram 21 of a longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process provided by an embodiment of the present application;

[0137] FIG33 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present application;

[0138] FIG34 is a schematic diagram of a longitudinal cross-section of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present application;

[0139] FIG35 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present application;

[0140] FIG36 is a schematic diagram of a longitudinal cross-sectional view of the structure of the back-contact battery provided in an embodiment of the present application during the manufacturing process.

[0141] Figure numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is a spacing region, 15 is a first doped semiconductor layer, 16 is a second doped semiconductor layer, 17 is a first dielectric layer, 18 is a second dielectric layer, 19 is a first dielectric portion, 20 is a second dielectric portion, 21 is a third dielectric portion, 22 is a first conductive window, 23 is a first doped portion, 24 is a second doped portion, 25 is a third dielectric layer, 26 is a third doped portion, 27 is a first electrode, 28 is a second electrode, 29 is a first passivation layer, 30 is a second passivation layer, 31 is a surface passivation layer, 32 is a second conductive window, 33 is a conductive structure, 34 is a passivation material layer, and 35 is an intrinsic semiconductor layer. DETAILED DESCRIPTION

[0142] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0143] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0144] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application more clearly understood, the application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain this application and are not intended to limit this application.

[0145] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0146] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0147] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells are devices that convert sunlight into electricity. Specifically, they use the principle of photovoltaics to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0148] When both the positive and negative electrodes of a solar cell are located on the back side of the solar cell, the solar cell is called a back-contact cell. The most significant feature of a back-contact cell is that it has no metal electrode blocking the front side, resulting in a higher short-circuit current (Isc). This makes back-contact cells one of the current technological advancements in achieving high-efficiency crystalline silicon cells.

[0149] Specifically, the above-mentioned back-contact battery generally includes a semiconductor substrate, a first doped semiconductor layer and a second doped semiconductor layer. In which, along a direction parallel to the surface of the semiconductor substrate, the first doped semiconductor layer and the second doped semiconductor layer are alternately formed on the same side of the semiconductor substrate. Moreover, the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types. Along the arrangement direction of the first doped semiconductor layer and the second doped semiconductor layer, the first doped semiconductor layer and the second doped semiconductor layer are separated by a single dielectric layer (such as a surface passivation layer, etc.) with poor insulation effect, resulting in a high risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types and alternately distributed on the backlight side in the existing back-contact battery, which is not conducive to improving the working performance of the back-contact battery.

[0150] In order to solve the above technical problems, in the first aspect, an embodiment of the present application provides a back-contact battery. As shown in Figure 1, the back-contact battery includes: a semiconductor substrate 11, a first doped semiconductor layer 15, a second doped semiconductor layer 16, a first dielectric layer 17, and a second dielectric layer 18. The backlight surface of the above-mentioned semiconductor substrate 11 has first regions 12 and second regions 13 that are alternately spaced, and a spacing region 14 located between each first region 12 and the second region 13 adjacent to itself. The first doped semiconductor layer 15 is formed on the first region 12 on the backlight surface. The second doped semiconductor layer 16 is formed at least on the second region 13 on the backlight surface; the conductivity type of the second doped semiconductor layer 16 and the first doped semiconductor layer 15 are opposite. The first dielectric layer 17 and the second dielectric layer 18 are formed at least on the spacing region 14 on the backlight surface. At least a portion of the first dielectric layer 17 and at least a portion of the second dielectric layer 18 are stacked and arranged between the first doped semiconductor layer 15 and the second doped semiconductor layer 16 along the arrangement direction of the first region 12 and the second region 13. At least a portion of the first dielectric layer 17 is in contact with the first doped semiconductor layer 15, and at least a portion of the second dielectric layer 18 is in contact with the second doped semiconductor layer 16. The first dielectric layer 17 and the second dielectric layer 18 are made of different materials. The structure formed by the first dielectric layer 17 and the second dielectric layer 18 is used to electrically isolate at least a portion of the first doped semiconductor layer 15 from at least a portion of the second doped semiconductor layer 16.

[0151] When the above technical solution is adopted, as shown in FIG1 , in the back-contact cell provided in the embodiment of the present application, the first doped semiconductor layer 15 and the second doped semiconductor layer 16 of opposite conductivity types are both located on the backlight side of the semiconductor substrate 11. Furthermore, the region between the first doped semiconductor layer 15 and the second doped semiconductor layer 16 corresponding to the backlight side of the semiconductor substrate 11 is a spacing region 14. The presence of the spacing region 14 can spatially separate the first doped semiconductor layer 15 and the second doped semiconductor layer 16 in a direction parallel to the backlight side. Furthermore, the back-contact cell provided in the embodiment of the present application further includes a first dielectric layer 17 and a second dielectric layer 18 formed at least on the spacing region 14 on the backlight side. At least a portion of the first dielectric layer 17 and at least a portion of the second dielectric layer 18 are stacked between the first doped semiconductor layer 15 and the second doped semiconductor layer 16 along the arrangement direction of the first region 12 and the second region 13. As can be seen, along the arrangement direction of the first region 12 and the second region 13, two dielectric layers, a first dielectric layer 17 and a second dielectric layer 18, are provided between at least a portion of the first doped semiconductor layer 15 and at least a portion of the second doped semiconductor layer 16 to achieve electrical isolation. Compared to existing back-contact cells in which the first doped semiconductor layer 15 and the second doped semiconductor layer are isolated only by a single dielectric layer with poor insulation (such as a surface passivation layer), the structure formed by the first dielectric layer 17 and the second dielectric layer 18 in the present embodiment has a higher electrical isolation effect, reducing the risk of leakage between at least a portion of the first doped semiconductor layer 15 and at least a portion of the second doped semiconductor layer 16, thereby improving the operating performance of the back-contact cell. In addition, at least a portion of the first dielectric layer 17 is in contact with the first doped semiconductor layer 15, and at least a portion of the second dielectric layer 18 is in contact with the second doped semiconductor layer 16. Moreover, the materials of the first dielectric layer 17 and the second dielectric layer 18 are different, which facilitates determining the materials of the first dielectric layer 17 and the second dielectric layer 18 according to the different distribution positions of the first dielectric layer 17 and the second dielectric layer 18, the different contact objects, and different actual needs, thereby improving the applicability of the back-contact battery provided in the embodiment of the present application in different application scenarios.

[0152] In actual application, in terms of materials, the semiconductor substrate may be a substrate made of semiconductor materials such as a silicon substrate, a silicon-germanium substrate or a germanium substrate.

[0153] In terms of conductivity type, the semiconductor substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate.

[0154] From a structural perspective, as shown in Figure 1, the light-facing surface of the semiconductor substrate 11 can be a polished surface, i.e., a relatively flat surface. Alternatively, as shown in Figure 2, the light-facing surface of the semiconductor substrate 11 can be a velvet surface. In this case, the light-facing surface of the semiconductor substrate 11 has a certain light-trapping effect, which can increase the refractive index of light transmitted from the light-facing surface to the semiconductor substrate 11, further improving the photoelectric conversion efficiency of the back-contact cell.

[0155] Furthermore, as shown in FIG1 , the backlight surface of the semiconductor substrate 11 comprises first regions 12 and second regions 13 arranged alternately, as well as a spacing region 14 located between each first region 12 and its adjacent second region 13. It should be understood that the boundaries between the first regions 12, second regions 13, and spacing regions 14 are virtual boundaries. Furthermore, because the first doped semiconductor layers 15 are formed on the first regions 12, the position, quantity, and specifications of the first regions 12 on the backlight surface of the semiconductor substrate 11 affect the position, quantity, and specifications of the subsequently formed first doped semiconductor layers 15. Accordingly, because the second doped semiconductor layers 16 are formed at least on the second regions 13, the position, quantity, and specifications of the second regions 13 on the semiconductor substrate 11 affect the position, quantity, and specifications of the subsequently formed second doped semiconductor layers 16 corresponding to the second regions 13 of the semiconductor substrate 11. With respect to the spacing regions 14, once the ranges of the first regions 12 and the second regions 13 are determined, the area between each first region 12 and its adjacent second region 13 on the backlight surface becomes the spacing region 14. Based on this, the specific position, quantity and specifications of the above-mentioned first region 12, second region 13 and spacing region 14 on the semiconductor substrate 11 can be set according to the requirements of information such as the position of the corresponding parts of the first doped semiconductor layer 15 and the second doped semiconductor layer 16 in the actual application scenario, and no specific limitation is made here.

[0156] Specifically, the surfaces of the first region, second region, and spacer region on the backlight side of the semiconductor substrate can be flush. Alternatively, as shown in FIG1 , the backlight side of the semiconductor substrate 11 can also be provided with a groove structure; and both the second region 13 and the spacer region 14 are located within the groove structure. In this case, along the direction from the light-facing side to the backlight side of the semiconductor substrate 11, the surface of the spacer region 14 and the surface of the second region 13 on the backlight side are both located at a lower height than the surface of the first region 12 on the backlight side. In this case, the second region 13 and the spacer region 14 are both located within the groove structure, allowing the surfaces of the second region 13 and the spacer region 14 to be offset relative to the surface of the first region 12 along the thickness direction of the semiconductor substrate 11. This facilitates at least partial offsetting of the first doped semiconductor layer 15 and the second doped semiconductor layer 16, both located on the backlight side and having opposite conductivity types, along the thickness direction of the semiconductor substrate 11, further reducing the risk of leakage on the backlight side and improving the performance of the back-contact cell.

[0157] Specifically, the depth of the groove structure can be determined according to the leakage protection requirements of the first doped semiconductor layer and the second doped semiconductor layer in actual application scenarios, as well as the thickness requirements of the semiconductor substrate, and is not specifically limited here.

[0158] Exemplarily, the depth of the groove structure can be greater than or equal to 0.3 μm and less than or equal to 3 μm. For example, the depth of the groove structure can be 0.3 μm, 0.5 μm, 0.8 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm or 3 μm, etc. In this case, the depth of the groove structure is within the above range, which can prevent the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity types, which are located on the backlight side of the silicon substrate and have opposite conductivity types, from being offset to a smaller extent along the thickness direction of the semiconductor substrate due to the small depth of the groove, thereby further reducing the risk of leakage on the backlight side. In addition, it can also prevent the use of a thicker semiconductor substrate due to the large depth of the groove structure, thereby reducing the manufacturing cost of the back-contact battery while facilitating the thin-film production of the back-contact battery.

[0159] In addition, as shown in FIG1 , the portion of the bottom surface of the groove structure corresponding to the spacing region 14 and the portion of the bottom surface of the groove structure corresponding to the second region 13 can be flush. Alternatively, the portion of the bottom surface of the groove structure corresponding to the spacing region 14 can be lower or higher than the portion of the bottom surface of the groove structure corresponding to the second region 13; in this case, the embodiment of the present application does not specifically limit the height difference between the surface of the spacing region and the surface of the second region.

[0160] It is worth noting that in the actual manufacturing process, after forming a full-layer first doped semiconductor layer on the backlight side and selectively etching the first doped semiconductor layer, the portion of the semiconductor substrate corresponding to the spacing region and the second region can be etched simultaneously to form a groove structure. In this case, the depth of each portion of the groove structure is the same. Based on this, when the portion of the bottom surface of the groove structure corresponding to the spacing region and the portion of the bottom surface of the groove structure corresponding to the second region are flush, the depth of the portion of the groove structure corresponding to the spacing region is the same as the depth of the portion of the groove structure corresponding to the second region. In this case, it is not necessary to selectively etch the spacing region or the second region after selectively etching the first doped semiconductor layer. This simplifies the manufacturing process of the back-contact battery and can also reduce the material thickness of the semiconductor substrate, facilitating thin-film production.

[0161] In addition, when the portion of the bottom surface of the groove structure corresponding to the spacing region is lower than the portion of the bottom surface of the groove structure corresponding to the second region, the depth difference between the first doped semiconductor layer and the second doped semiconductor layer corresponding to the groove structure is greater, and at least a portion of the first dielectric layer and at least a portion of the second dielectric layer are formed on the spacing region, and the structure formed by the first dielectric layer and the second dielectric layer has an electrical isolation effect. Therefore, in this case, the leakage risk between the first doped semiconductor layer and the second doped semiconductor layer can be further reduced.

[0162] Specifically, in the actual manufacturing process, after forming the first doped semiconductor layer on the first region, a first selective etching can be performed simultaneously on at least the spacer region and the second region on the backlight side. Furthermore, after forming the second doped semiconductor layer, a second selective etching can be performed on the spacer region on the backlight side, thereby making the portion of the bottom surface of the groove structure corresponding to the spacer region lower than the portion of the bottom surface of the groove structure corresponding to the second region. Alternatively, after performing the first selective etching, a second selective etching can be performed on the spacer region before forming the second doped semiconductor layer. Alternatively, after forming the first doped semiconductor layer on the first region, selective etching can be performed on the second region and the spacer region separately.

[0163] The surface topography of the first, second, and spacer regions of the backlight surface of the semiconductor substrate can be customized based on actual needs. As shown in Figure 1 , the surfaces of the first, second, and spacer regions 12, 13, and 14 can all be planar. Alternatively, at least one of the first, second, and spacer regions 12, 13, and 14 can have a textured surface to enhance light trapping in the corresponding region.

[0164] Specifically, when a textured structure is formed on the surface of at least one of the first region, the second region, and the spacing region, the present embodiment does not specifically limit the type of textured structure or the one-dimensional size of the textured structure. The textured structure may be a velvet structure such as a regular pyramidal structure or an inverted pyramidal structure, or may be a non-pyramid structure or a polished structure.

[0165] For example, a non-pyramid structure may be formed on the surface of the first region, and the base of the non-pyramid structure on the surface of the first region has a one-dimensional size greater than or equal to 0.5 μm and less than or equal to 20 μm. The base of the non-pyramid structure is closer to the semiconductor substrate than the top of the non-pyramid structure.

[0166] The non-pyramid structure may be a hole structure, a V-groove structure, a boss structure, etc. Specifically, the surface of the first region having the boss structure may be a polished pyramid velvet surface, and the non-pyramid structure on the surface of the first region is a polished pyramid base structure.

[0167] As for the one-dimensional size of the base of the non-pyramid structure, it can refer to the length, width, diagonal length, diameter or height of the base of the non-pyramid structure. Which dimension of the base of the non-pyramid structure the one-dimensional size is can be determined according to the morphology of the non-pyramid structure. For example, when the non-pyramid structure is a pyramid base structure after polishing, the one-dimensional size of the base of the non-pyramid structure can be the side length, diagonal length or height of the pyramid base structure after polishing. In addition, the one-dimensional size of the base of the non-pyramid structure on the surface of the first area can be any value greater than or equal to 0.5μm and less than or equal to 20μm. For example, the one-dimensional size of the base of the non-pyramid structure on the surface of the first area can be 0.5μm, 1μm, 3μm, 8μm, 12μm, 15μm or 20μm, etc. Of course, according to the requirements of the actual application scenario, the one-dimensional size of the base of the non-pyramid structure on the surface of the first area can be set to other suitable values ​​less than 0.5μm or greater than 20μm.

[0168] When employing the above-described technical solution, the non-pyramid structure has a light-trapping effect. Therefore, when the non-pyramid structure is formed on the surface of the first region, more light is transmitted from the backlight side through the surface of the first region into the semiconductor substrate and utilized by the semiconductor substrate. Furthermore, when the non-pyramid structure is formed on the surface of the first region, the surface of the first region exhibits a bumpy topography. Based on this, when the first doped semiconductor layer is formed on the first region, the side of the first doped semiconductor layer facing away from the first region also exhibits corresponding undulations, which increases the contact area between the first doped semiconductor layer and the corresponding electrode, strengthens the connection between the two, and reduces the contact resistance between the two. Furthermore, when the base one-dimensional dimension of the non-pyramid structure on the surface of the first region is within the above-described range, it can prevent the first region's surface undulation from being too small, resulting in poor light-trapping in the first region and a smaller contact area between the first doped semiconductor layer and the corresponding electrode. Furthermore, it can also prevent the semiconductor substrate from being significantly thinned when the non-pyramid structure on the surface of the first region is formed, which can facilitate the thin-film production of back-contact solar cells.

[0169] Exemplarily, a non-pyramid structure may be formed on the surface of the second region, and the base one-dimensional size of the non-pyramid structure on the surface of the second region is greater than or equal to 10 μm and less than or equal to 50 μm. And the base of the non-pyramid structure is close to the semiconductor substrate relative to its top. In the above case, when the non-pyramid structure is formed on the surface of the second region, the type of the non-pyramid structure, the morphology of the non-pyramid structure, and the meaning of the base one-dimensional size of the non-pyramid structure can refer to the type of the non-pyramid structure, the morphology of the non-pyramid structure, and the meaning of the base one-dimensional size of the non-pyramid structure when the non-pyramid structure is formed on the surface of the first region mentioned above. In addition, the beneficial effects in this case are similar to the beneficial effects of the non-pyramid structure formed on the surface of the first region mentioned above, and the base one-dimensional size of the non-pyramid structure on the surface of the first region is greater than or equal to 0.5 μm and less than or equal to 20 μm, and will not be repeated here.

[0170] Furthermore, in this case, the one-dimensional base size of the non-pyramid-shaped structure on the surface of the second region can be any value greater than or equal to 10 μm and less than or equal to 50 μm. For example, the one-dimensional base size of the non-pyramid-shaped structure on the surface of the second region can be 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm. Of course, the one-dimensional base size of the non-pyramid-shaped structure on the surface of the second region can also be set to other suitable values ​​less than 10 μm or greater than 50 μm according to the requirements of the actual application scenario.

[0171] In addition, when the non-pyramid structure is formed on the surfaces of the first region and the second region, the types of the non-pyramid structures formed on the surfaces of the first region and the second region may be the same or different. Secondly, when the types of the non-pyramid structures corresponding to the surfaces of the first region and the second region are the same, the base one-dimensional size of the non-pyramid structures formed on the surfaces of the first region and the second region may be equal or unequal. Wherein, when the non-pyramid structure is formed on the surfaces of the first region and the second region, when the types of the non-pyramid structures corresponding to the surfaces of the first region and the second region and / or the base one-dimensional size of the non-pyramid structures are different, it is beneficial to make the surface morphologies of the first region and the second region different. The first doped semiconductor layer is formed on the first region, and the side surface of the first doped semiconductor layer facing away from the semiconductor substrate has a surface undulation morphology corresponding to the first region. Similarly, at least a portion of the second doped semiconductor layer formed on the second region has a surface with a surface undulation corresponding to the second region on the side facing away from the semiconductor substrate. Therefore, when the surface morphologies of the first region and the second region are different, it is beneficial to make the first doped semiconductor layer and at least a portion of the second doped semiconductor layer have different surface morphologies on the side facing away from the semiconductor substrate, thereby facilitating the distinction of the positions of the first doped semiconductor layer and the portion of the second doped semiconductor layer located on the second region on the backlight side, and preventing the deviation of the formation position of the first electrode in ohmic contact with the first doped semiconductor layer and the second electrode in ohmic contact with the portion of the second doped semiconductor layer located on the second region from the target position due to the inability to distinguish the positions of the two doped semiconductor layers when forming the first electrode. This increases the risk of leakage and ensures that the back-contact battery has higher electrical reliability.

[0172] Exemplarily, a non-pyramid structure may be formed on the surface of the above-mentioned spacer region, and the one-dimensional size of the base of the non-pyramid structure on the surface of the spacer region is greater than or equal to 10 μm and less than or equal to 50 μm. The base of the non-pyramid structure is close to the semiconductor substrate relative to its own top. In this case, the non-pyramid velvet surface has a light-trapping effect. Therefore, when a non-pyramid structure is formed on the surface of the spacer region, it is beneficial for more light to be transmitted from the backlight side and through the surface of the spacer region into the semiconductor substrate and be utilized by the semiconductor substrate. In addition, the one-dimensional size of the base of the non-pyramid structure on the surface of the spacer region is within the above-mentioned range, which can prevent the spacer region from having a poor light-trapping effect due to the small undulation of the spacer region surface caused by the small one-dimensional size; secondly, it can also prevent the semiconductor substrate from being thinned more when the non-pyramid structure on the surface of the spacer region is formed due to the large one-dimensional size, which is beneficial to the thin-film production of back-contact batteries.

[0173] Specifically, when a non-pyramid structure is formed on the surface of the spacer area, the type of the non-pyramid structure, the morphology of the non-pyramid structure, and the meaning of the base one-dimensional size of the non-pyramid structure can refer to the meaning of the type of the non-pyramid structure, the morphology of the non-pyramid structure, and the base one-dimensional size of the non-pyramid structure when a non-pyramid structure is formed on the surface of the first region above. In addition, in this case, the base one-dimensional size of the non-pyramid structure on the spacer area surface can be any numerical value greater than or equal to 10 μm and less than or equal to 50 μm. For example: the base one-dimensional size of the non-pyramid structure on the spacer area surface can be 10 μm, 20 μm, 30 μm, 40 μm or 50 μm, etc. Of course, the base one-dimensional size of the non-pyramid structure on the spacer area surface can also be set to less than 10 μm, or greater than other suitable numerical values ​​of 50 μm according to the actual application scenario requirements.

[0174] In addition, when the non-pyramid structure is formed on the surfaces of the spacer and the second region, the types of the non-pyramid structures formed on the surfaces of the spacer and the second region can be the same or different. Secondly, when the types of the non-pyramid structures corresponding to the surfaces of the spacer and the second region are the same, the base one-dimensional size of the non-pyramid structure formed on the surfaces of the spacer and the second region can be equal or unequal. Wherein, when the non-pyramid structure is formed on the surfaces of the spacer and the second region, the types of the non-pyramid structures corresponding to the surfaces of the spacer and the second region and the base one-dimensional size of the non-pyramid structure are the same, it is not necessary to separately perform corresponding texturing treatment on the spacer and the second region after selective etching of the first doped semiconductor layer. While simplifying the manufacturing process of the back contact battery, the material selection thickness of the semiconductor substrate can also be reduced, which is conducive to realizing thin-film production.

[0175] For the above-mentioned first dielectric layer and second dielectric layer, from the material aspect, the difference in materials between the first dielectric layer and the second dielectric layer may refer to different types of at least some elements in the materials of the first dielectric layer and the second dielectric layer; it may also refer to different ratios of atomic weights of at least some elements in the materials of the two dielectric layers; or it may refer to different crystal phases of the two dielectric layers.

[0176] The material of at least one of the first dielectric layer and the second dielectric layer may include any insulating material having dielectric properties. Alternatively, the material of at least one of the first dielectric layer and the second dielectric layer may include a semiconductor material. The specific material types of the first dielectric layer and the second dielectric layer can be determined based on actual needs and the actual manufacturing process and are not specifically limited here.

[0177] For example, the material of the first dielectric layer may contain oxygen. In this case, the dielectric layer containing oxygen (such as a silicon dioxide layer or a silicon oxynitride layer) has a high dielectric property, which can improve the electrical isolation effect of the first dielectric layer and further reduce the risk of leakage between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer.

[0178] For example, the material of the first dielectric layer may contain silicon. In this case, silicon is abundant in nature, and there are many types of dielectric materials containing silicon, such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbide. This facilitates selection of the appropriate type based on different practical needs, thereby improving the applicability of the back-contact cell provided by the embodiments of the present application in different application scenarios.

[0179] Exemplarily, the first dielectric layer may include a tunneling oxide layer. In this case, in addition to being an insulating dielectric layer with a relatively large thickness, the first dielectric layer may also include a tunneling oxide layer with a relatively small thickness, providing another optional solution for the structure of the first dielectric layer. In addition, the manufacturing process of the tunneling oxide layer is relatively mature. Therefore, when the first dielectric layer includes a tunneling oxide layer, the compatibility of the back-contact battery provided in the embodiment of the present application with the existing back-contact battery manufacturing process can be improved, and the manufacturing difficulty of the first dielectric layer can be reduced. The embodiment of the present application does not specifically limit the material of the tunneling oxide layer.

[0180] Exemplarily, the material of the first dielectric layer may include at least one of silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and zinc oxide. For example, the material of the first dielectric layer may be only any one of silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and zinc oxide. For another example, the material of the first dielectric layer may include a combination of any two of silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and zinc oxide. For another example, the material of the first dielectric layer may include a combination of any three of silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and zinc oxide. When the material of the first dielectric layer includes at least two types, the present embodiment of the application does not specifically limit the distribution of the different types of materials in the first dielectric layer. In this case, there are multiple options for the material of the first dielectric layer, facilitating selection of the appropriate type based on different practical needs, thereby improving the applicability of the back-contact battery provided by the present embodiment of the application in different application scenarios. Furthermore, silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide, and zinc oxide all have excellent electrical isolation properties, further reducing the risk of leakage between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer.

[0181] As for the aforementioned second dielectric layer, it may comprise a crystalline silicon layer. Furthermore, the doping type of the crystalline silicon layer includes at least one of intrinsic and lightly doped. Specifically, the doping type of the crystalline silicon layer may be exclusively intrinsic, exclusively lightly doped, or may be such that the doping type of a portion of the crystalline silicon layer is intrinsic and another portion is lightly doped. In this case, intrinsic crystalline silicon material has a relatively poor conductivity. Therefore, when the doping type of the crystalline silicon layer is intrinsic, the second dielectric layer provides excellent electrical isolation, ensuring that the structure formed by the first and second dielectric layers can reduce the risk of leakage between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer. However, during the actual manufacturing process, when at least the second doped semiconductor layer is doped with impurities, the impurities therein may diffuse into the contacting portion of the second dielectric layer, thereby causing the doping type of at least a portion of the second dielectric layer to become lightly doped. Therefore, when the doping type of the crystalline silicon layer is lightly doped, strict control of manufacturing conditions is not required to ensure the conductivity of the crystalline silicon layer is intrinsic, thereby reducing the manufacturing difficulty of back-contact solar cells.

[0182] Specifically, when the doping type of the crystalline silicon layer includes a lightly doped type, the embodiment of the present application does not specifically limit the doping concentration of impurities in the crystalline silicon layer, as long as at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer can be electrically isolated by the structure formed by the first dielectric layer and the second dielectric layer.

[0183] For example, when the doping type of the crystalline silicon layer includes a lightly doped type, the doping concentration of the impurities in the crystalline silicon layer may be greater than 0 and less than or equal to 5E21 / cm 3 Wherein, when the doping type of the crystalline silicon layer includes a lightly doped type, the doping concentration of the impurities in the crystalline silicon layer may be greater than or equal to 1E15 / cm 3 , and less than or equal to 5E21 / cm 3 For example, the doping concentration of impurities in the crystalline silicon layer can be 1E15 / cm 3 、5E15 / cm 3 、1E16 / cm 3 、5E16 / cm 3 、1E17 / cm 3 、5E17 / cm 3 、1E18 / cm 3 、5E18 / cm 3 or 5E21 / cm 3In this case, it can be understood that, within a certain range, the greater the impurity doping concentration in the crystalline silicon layer, the better its conductivity. Based on this, when the doping type of the crystalline silicon layer includes a lightly doped type, the impurity doping concentration in the crystalline silicon layer is within the above-mentioned range. This can prevent the dielectric properties of the second dielectric layer from being lowered due to the high impurity doping concentration in the crystalline silicon layer, thereby ensuring a high degree of electrical isolation between at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer.

[0184] In addition, when the doping type of the crystalline silicon layer includes intrinsic type and lightly doped type, the distribution between the portion of the crystalline silicon layer with intrinsic type doping and the portion of the crystalline silicon layer with lightly doped type doping can be determined based on the actual application scenario. For example, the portion of the crystalline silicon layer with lightly doped type doping and the portion of the crystalline silicon layer with intrinsic type doping are distributed along the direction of the second dielectric layer approaching the second doped semiconductor layer, and the intrinsic type portion is in contact with the second doped semiconductor layer.

[0185] Alternatively, the intrinsically doped portion of the crystalline silicon layer and the lightly doped portion of the crystalline silicon layer may be distributed along the second dielectric layer in a direction close to the second doped semiconductor layer, with the lightly doped portion in contact with the second doped semiconductor layer. In this case, as shown in FIG1 , at least a portion of the second dielectric layer 18 is in contact with the second doped semiconductor layer 16. Furthermore, the intrinsically doped portion of the crystalline silicon layer and the lightly doped portion of the crystalline silicon layer may be distributed along the second dielectric layer 18 in a direction close to the second doped semiconductor layer 16, with the lightly doped portion in contact with the second doped semiconductor layer. Based on this, during the actual manufacturing process, when at least the second doped semiconductor layer 16 is doped with impurities, the impurities therein may diffuse into the contacting portion of the second dielectric layer 18, thereby causing the doping type of at least a portion of the second dielectric layer 18 to become lightly doped. This allows for the fabrication of the crystalline silicon layer without requiring additional doping treatments to form the crystalline silicon layer, thereby simplifying the manufacturing process and manufacturing difficulty of the second dielectric layer 18.

[0186] In terms of crystal phase, the crystal phase of the first dielectric layer can be amorphous, and the crystal phase of the second dielectric layer can include at least one of microcrystal, nanocrystal, polycrystalline or single crystal. In this case, the different materials of the first dielectric layer and the second dielectric layer can also mean that the crystal phases of the first dielectric layer and the second dielectric layer are different, which provides a screening direction for the material selection of the first dielectric layer and the second dielectric layer. In addition, the crystal phase of the second dielectric layer has multiple optional options, and the second dielectric layer with different crystal phases may have different physical properties, which facilitates improving the applicability of the back contact battery provided by the embodiment of the present application in different application scenarios.

[0187] Specifically, when the crystal phase of the first dielectric layer is amorphous, the material of the first dielectric layer may be silicon dioxide or an amorphous silicon layer. Furthermore, the crystal phase of the second dielectric layer may be only one of microcrystalline, nanocrystalline, polycrystalline, or single crystal; for example, the second dielectric layer may be a microcrystalline silicon layer, a nanocrystalline silicon layer, a polycrystalline silicon layer, or a single crystal silicon layer. Alternatively, the crystal phase of the second dielectric layer may include at least two of microcrystalline, nanocrystalline, polycrystalline, or single crystal; for example, the second dielectric layer may be a mixed layer of microcrystalline and nanocrystalline silicon layers.

[0188] In terms of dielectric properties, the first dielectric layer and the second dielectric layer can both be non-conductive dielectric layers; for example, the first dielectric layer is a non-conductive dielectric layer made of insulating material, and the second dielectric layer is a non-conductive dielectric layer made of intrinsic semiconductor material.

[0189] Alternatively, one of the first dielectric layer and the second dielectric layer may be a dielectric layer having a certain electrical conductivity. For example, the first dielectric layer may be a tunneling passivation layer, and the second dielectric layer may be a non-conductive dielectric layer made of an intrinsic semiconductor material. Another example may be the first dielectric layer may be a non-conductive dielectric layer made of an insulating material, and the second dielectric layer may include a conductive dielectric layer made of a lightly doped semiconductor material.

[0190] Specifically, in the embodiments of the present application, there is no specific limitation on the dielectric properties of the first dielectric layer and the second dielectric layer, as long as the structure formed by the first dielectric layer and the second dielectric layer can electrically isolate at least a portion of the first doped semiconductor layer from at least a portion of the second doped semiconductor layer.

[0191] In terms of the formation range, as shown in FIG. 1 and FIG. 2 , the first dielectric layer 17 may be located only on the spacer region 14 .

[0192] Alternatively, as shown in FIG3 , the first dielectric layer 17 may also include a first dielectric portion 19 and a second dielectric portion 20 that are integrally connected. Along the arrangement direction of the first region 12 and the second region 13, the first dielectric portion 19 is located between the second dielectric layer 18 and the first doped semiconductor layer 15. The second dielectric portion 20 is located between the second dielectric layer 18 and the semiconductor substrate 11. In this case, as shown in FIG3 , the first dielectric layer 17 is located not only on the side of the second dielectric layer 18 that is closer to the first doped semiconductor layer 15, but also on the side of the second dielectric layer 18 that is closer to the semiconductor substrate 11. Therefore, in the actual manufacturing process, after depositing a complete layer of material disposed on the backlight side and used to form the first dielectric layer 17, there is no need for additional etching to remove the portion of the material layer located between the second dielectric layer 18 and the semiconductor substrate 11 before forming the second dielectric layer 18, thereby simplifying the manufacturing process for the first dielectric layer 17.

[0193] Alternatively, as shown in Figure 4, the first dielectric layer 17 may include an integral, continuous first dielectric portion 19 and a third dielectric portion 21. Along the alignment of the first and second regions 12, 13, the first dielectric portion 19 is located between the second dielectric layer 18 and the first doped semiconductor layer 15. The third dielectric portion 21 is located on the side of the first doped semiconductor layer 15 facing away from the semiconductor substrate 11, and a first conductive window is defined through the third dielectric portion 21. In this case, the first dielectric layer 17 is not only located between the second dielectric layer 18 and the first doped semiconductor layer 15 along the alignment of the first and second regions 12, 13, but also on the side of the first doped semiconductor layer 15 facing away from the semiconductor substrate 11. This increases the range over which the first dielectric layer 17 can be formed, reduces the extent of selective etching of the material layer used to form the first dielectric layer 17, which is deposited entirely on the backlight side during actual manufacturing, and improves etching efficiency and throughput. Secondly, the presence of the third dielectric portion 21 also facilitates passivation of the surface of the first doped semiconductor layer 15 facing away from the semiconductor substrate 11, thereby reducing the number of defects on the side of the first doped semiconductor layer 15 facing away from the semiconductor substrate 11. Furthermore, a first conductive window extending through the second dielectric portion 20 facilitates direct contact between the first doped semiconductor layer 15 and the corresponding electrode, reducing the contact resistance between the two and ensuring high performance of the back-contact cell.

[0194] 5 , the first dielectric layer 17 may include the first dielectric portion 19, the second dielectric portion 20, and the third dielectric portion 21. The beneficial effects of this case can be found in the foregoing description and will not be elaborated here.

[0195] In addition, in actual application, as shown in FIG4 , when the first dielectric layer 17 includes an integral and continuous first dielectric portion 19 and a third dielectric portion 21 , the third dielectric portion 21 can be directly formed on the side of the first doped semiconductor layer 15 away from the semiconductor substrate 11 .

[0196] Alternatively, as shown in Figure 5, if the first dielectric layer 17 includes an integral, continuous first dielectric portion 19 and a third dielectric portion 21, the back-contact cell may further include a third dielectric layer 25 located between the third dielectric portion 21 and the first doped semiconductor layer 15. The first conductive window also extends through the third dielectric layer 25 (i.e., the first conductive window extends through at least the third dielectric layer 25 and the third dielectric portion 21). In this case, during the actual manufacturing process, after forming the entire first doped semiconductor layer 15 on the backlight side, selective etching of the first doped semiconductor layer 15 is performed using a mask at least on the portion of the third dielectric layer 25 corresponding to the first region 12. Therefore, if the first dielectric layer 17 includes the third dielectric portion 21 located on the side of the first doped semiconductor layer 15 facing away from the semiconductor substrate 11, selective etching of the material used to form the second dielectric layer 18 can stop at the third dielectric portion 21, without affecting the underlying third dielectric layer 25. In this case, when the back contact battery includes the above-mentioned third dielectric layer 25 located above the first region 12, it means that after the first doped semiconductor layer 15 is selectively etched, the portion of the third dielectric layer 25 corresponding to the first region 12 is not removed, thereby reducing the manufacturing steps of the back contact battery and improving manufacturing efficiency.

[0197] Specifically, the material of the third dielectric layer can be any dielectric material having a masking function, and can be determined according to the material of the first doped semiconductor layer, the actual manufacturing process, and the actual application scenario.

[0198] Exemplarily, the third dielectric layer may include a silicon nitride layer.

[0199] For example, when the material of the first doped semiconductor layer contains silicon, the third dielectric layer may comprise a doped silica glass layer. In this case, the doping of the first doped semiconductor layer can be achieved through a diffusion process. After diffusion, a doped silica glass layer can be formed on the side of the first doped semiconductor layer facing away from the semiconductor substrate. Therefore, when the material of the first doped semiconductor layer contains silicon and the third dielectric layer comprises a doped silica glass layer, no additional deposition steps are required to form the third dielectric layer, simplifying the manufacturing process of the back-contact cell.

[0200] As for the specifications of the third dielectric layer, the embodiment of the present application does not specifically limit the thickness of the third dielectric layer. Secondly, as shown in Figure 5, the first conductive window penetrates the third dielectric layer 25. In addition, the corresponding electrode needs to pass through the first conductive window, penetrate the third dielectric layer 25 and the third dielectric portion 21, and make ohmic contact with the first doped semiconductor layer 15. Based on this, it can be understood that along the arrangement direction of the first region 12 and the second region 13, the width of the portion of the third dielectric layer 25 located on both sides of the first conductive window affects the distance between the two sides of the corresponding electrode formed in the first conductive window and the film layer or electrode of the opposite conductivity type, thereby affecting the leakage risk of the corresponding electrode formed in the first conductive window. Based on this, the width of the portion of the third dielectric layer 25 located on each side of the first conductive window can be determined based on the leakage protection requirements for the electrode set in the first conductive window in the actual application scenario.

[0201] Illustratively, along the arrangement direction of the first region and the second region, the width of the portion of the third dielectric layer located on at least one side of the first conductive window can be greater than or equal to 40 μm and less than or equal to 220 μm. For example, the width of the portion of the third dielectric layer located on at least one side of the first conductive window can be 40 μm, 60 μm, 80 μm, 120 μm, 160 μm, 180 μm, or 220 μm, etc. In this case, the width of the portion of the third dielectric layer located on at least one side of the first conductive window is within the above range. This can prevent the distance between the corresponding electrode formed in the first conductive window and the film layer or electrode of the opposite conductivity type along the width direction from being shortened due to the smaller width of the portion of the third dielectric layer located on at least one side of the first conductive window, thereby suppressing leakage. It can also prevent the range of the spacing region and / or the second region located on the backlight side together with the first region from being smaller due to the width of the portion of the third dielectric layer located on at least one side of the first conductive window being larger, thereby ensuring that at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer can be electrically isolated by at least the first dielectric layer and the second dielectric layer formed in the spacing region, ensuring that the second doped semiconductor layer formed on the second region has a suitable formation range, and further ensuring that the second doped semiconductor layer has a higher carrier collection efficiency.

[0202] Specifically, along the arrangement direction of the first region and the second region, the widths of the portions of the third dielectric layer located on both sides of the first conductive window can be equal or unequal. When the widths of the portions of the third dielectric layer located on both sides of the first conductive window are equal, this helps to achieve a more regular structure for the back-contact battery. Furthermore, the equal widths of the portions of the third dielectric layer located on both sides of the first conductive window also help to equalize the distances along the width direction between at least the corresponding electrode formed within the first conductive window and the film layer or electrode of the opposite conductivity type, thereby suppressing leakage.

[0203] As for the second dielectric layer, as shown in FIG. 1 , the second dielectric layer 18 may be located only on the spacing region 14 .

[0204] Alternatively, the second dielectric layer may extend above the first region. In this case, when the second dielectric layer is a non-conductive dielectric layer, the portion of the second dielectric layer extending above the first region may be directly disposed on the side of the first doped semiconductor layer facing away from the semiconductor substrate. In this case, a first conductive window is provided through the portion of the second dielectric layer corresponding to the first region. Alternatively, as shown in FIG6 , when the first dielectric layer 17 includes the third dielectric portion 21, the second dielectric layer 18 may extend onto the third dielectric portion 21 included in the first dielectric layer 17, and the first conductive window also extends through the portion of the second dielectric layer 18 corresponding to the first region 12 (i.e., the first conductive window extends through at least the portion of the second dielectric layer 18 corresponding to the first region 12 and the third dielectric portion 21). In this case, the second dielectric layer 18 may be a non-conductive dielectric layer or a dielectric layer with a certain electrical conductivity, as long as the structure formed by the first dielectric layer 17 and the second dielectric layer 18 can electrically isolate at least a portion of the first doped semiconductor layer 15 from at least a portion of the second doped semiconductor layer 16.

[0205] When the second dielectric layer extends onto the third dielectric portion of the first dielectric layer, the back-contact cell may include a third dielectric layer located between the third dielectric portion and the semiconductor substrate. The materials and other aspects of this third dielectric layer can be found in the previous section and are not further described here. In this case, the first conductive window extends through the portion of the second dielectric layer corresponding to the first region, the third dielectric portion, and the third dielectric layer.

[0206] Notably, when the second dielectric layer extends above the first region, it increases the area over which the second dielectric layer is formed, reducing the extent of selective etching of the material layer deposited throughout the backlight side and used to form the second dielectric layer during actual manufacturing, thereby improving etching efficiency and production capacity. Furthermore, the first conductive window extends through the portion of the second dielectric layer corresponding to the first region, facilitating direct contact between the first doped semiconductor layer and the corresponding electrode, thereby reducing contact resistance between the two.

[0207] Furthermore, regarding the distribution along the extension direction of the spacing region, the portion of the first dielectric layer and the second dielectric layer corresponding to the portion between the first doped semiconductor layer and the second doped semiconductor layer can be located throughout the entire region of the spacing region along its own extension direction, thereby electrically isolating the first doped semiconductor layer from the second doped semiconductor layer. In other words, the structure formed by the first dielectric layer and the second dielectric layer can electrically isolate the first doped semiconductor layer from the second doped semiconductor layer, thereby minimizing the risk of leakage between the first doped semiconductor layer and the second doped semiconductor layer.

[0208] Alternatively, the first dielectric layer and the second dielectric layer have a discontinuity along the extension direction of the spacing region corresponding to the portion between the first doped semiconductor layer and the second doped semiconductor layer. As shown in FIG7 , the back contact cell may further include a conductive structure 33 located at least within the discontinuity. The conductive type of the conductive structure 33 is opposite to the conductive type of one of the first doped semiconductor layer 15 and the second doped semiconductor layer 16, and only a portion of the first doped semiconductor layer 15 and only a portion of the second doped semiconductor layer 16 are electrically connected to the conductive structure 33, respectively. In this case, the first doped semiconductor layer 15 and the second doped semiconductor layer 16 can be electrically connected by creating a local leakage point to form a built-in diode with a lower reverse breakdown voltage, thereby facilitating the back contact cell to have a lower reverse breakdown voltage when it is blocked. Secondly, only partial areas of the first doped semiconductor layer 15 and only partial areas of the second doped semiconductor layer 16 are electrically connected to the conductive structure 33, respectively. In other words, partial areas of the first doped semiconductor layer 15 and corresponding partial areas of the second doped semiconductor layer 16 are electrically connected to the at least one conductive structure 33, respectively, while the remaining areas of the first doped semiconductor layer 15 and corresponding areas of the second doped semiconductor layer 16 are still electrically isolated by the structure formed by the first dielectric layer 17 and the second dielectric layer 18. This prevents the back contact battery from having a large leakage current under normal working conditions due to the provision of conductive structures 33 between all areas of the first doped semiconductor layer 15 and the second doped semiconductor layer 16, thereby preventing the back contact battery from having a low working efficiency due to a large leakage current under normal working conditions. This ensures that the photovoltaic module including the back contact battery provided in the embodiment of the present application has a high photoelectric conversion efficiency in the forward voltage region.

[0209] Specifically, as described above, the provision of a conductive structure can achieve localized leakage between the first and second doped semiconductor layers, thereby reducing the reverse breakdown voltage of the back-contact battery. In actual applications, when the proportion of the conductive structure in the direction of the spacing region increases to a certain range, the reverse breakdown voltage of the back-contact battery no longer decreases, but the leakage current of the back-contact battery under normal operation is relatively high. Based on this, the proportion of the conductive structure in the spacing region can be determined based on the reverse breakdown voltage and leakage current requirements of the back-contact battery in the actual application scenario.

[0210] The material and conductivity type of the conductive structure can be determined according to actual needs and the actual manufacturing process.

[0211] For example, when the back-contact cell further includes a conductive structure, at least a portion of the conductive structure can be integrally continuous with the second doped semiconductor layer. In this case, the material and conductivity type of at least a portion of the conductive structure can be the same as those of the second doped semiconductor layer. The beneficial effects of this scenario are similar to those of the integrally continuous first dielectric layer and second passivation layer described above and are not further elaborated here.

[0212] For example, when the back-contact cell also includes a conductive structure, the structure formed by the first dielectric layer and the second dielectric layer is integrally continuous with the conductive structure. The beneficial effects of this case are similar to the beneficial effects of the first dielectric layer and the second passivation layer being integrally continuous as described above and are not further described here. It should be noted that in this case, by selectively doping the portions of the material layer used to manufacture the first dielectric layer, the second dielectric layer, and the conductive structure corresponding to the discontinuity, the portions of the material layer corresponding to the discontinuity have conductive properties, while the material layer corresponding to the first dielectric layer and the second dielectric layer has electrical isolation properties.

[0213] Secondly, in the case where the back-contact cell further includes a conductive structure, at least part of the conductive structure, the second dielectric layer and the second doped semiconductor layer can be continuous as one.

[0214] Alternatively, the conductive structure may be formed separately from the first dielectric layer, the second dielectric layer, and the second doped semiconductor layer, at least within the discontinuity. In this case, the conductive structure may have a conductivity type opposite to that of the first doped semiconductor layer, or may have a conductivity type opposite to that of the second doped semiconductor layer. The conductive structure may be made of only doped semiconductor material, a doped semiconductor material and a tunneling passivation material, or a doped semiconductor material and an intrinsic amorphous semiconductor material.

[0215] In terms of specifications, at least part of the first dielectric layer and at least part of the second dielectric layer are distributed on the spacing area along the arrangement direction of the first area and the second area. Based on this, it can be understood that, along the arrangement direction of the first area and the second area, the width of the portion of the first dielectric layer corresponding to the spacing area and the width of the portion of the second dielectric layer corresponding to the spacing area will affect the electrical isolation effect of the structure composed of the first dielectric layer and the second dielectric layer, as well as the width of the spacing area. In addition, when the formation methods of the first dielectric layer and the second dielectric layer are different, their own widths in the spacing area will also be affected. Therefore, along the arrangement direction of the first area and the second area, the width of the portion of the first dielectric layer corresponding to the spacing area and the width of the portion of the second dielectric layer corresponding to the spacing area can be determined based on the requirements for the electrical isolation effect and the width of the spacing area of ​​the structure composed of the first dielectric layer and the second dielectric layer in the actual application scenario, as well as the formation methods of the first dielectric layer and the second dielectric layer, and are not specifically limited here.

[0216] For the above-mentioned first doped semiconductor layer and the second doped semiconductor layer, in terms of conductivity type, the conductivity type of the first doped semiconductor layer can be N-type, and in this case the conductivity type of the second doped semiconductor layer is P-type; or, the conductivity type of the first doped semiconductor layer can also be P-type, and in this case the conductivity type of the second doped semiconductor layer is N-type.

[0217] In terms of materials, the materials of the first doped semiconductor layer and the second doped semiconductor layer can include any semiconductor material as long as it can be applied to the back contact battery provided in the embodiments of the present application.

[0218] Exemplarily, the first doped semiconductor layer and / or the second doped semiconductor layer may be a doped amorphous silicon layer or a doped crystalline silicon layer; wherein, when the first doped semiconductor layer and / or the second doped semiconductor layer is a doped crystalline silicon layer, the material of the doped crystalline silicon layer may include microcrystalline silicon, single crystal silicon, polycrystalline silicon and nanocrystalline silicon, etc.

[0219] It is worth noting that compared with the doped amorphous silicon layer, the doped crystalline silicon layer has a higher carrier lateral transport characteristic. Therefore, when the first doped semiconductor layer and / or the second doped semiconductor layer is a doped crystalline silicon layer, the first doped semiconductor layer and / or the second doped semiconductor layer can have a higher carrier collection characteristic, thereby reducing the carrier recombination efficiency in the first region and / or the second region.

[0220] In terms of the formation position, the first doped semiconductor layer can be directly formed on the first area of ​​the backlight surface. Alternatively, as shown in Figure 1, the above-mentioned back-contact cell may further include a first passivation layer 29 located between the first doped semiconductor layer 15 and the semiconductor substrate 11. In this case, the first passivation layer 29 and the first doped semiconductor layer 15 can form a selective contact structure to chemically passivate the corresponding area on the backlight surface of the semiconductor substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side, which is conducive to improving the photoelectric conversion efficiency of the back-contact cell.

[0221] Specifically, the material of the above-mentioned first passivation layer can be determined according to the requirements for the type of selective contact structure composed of the first passivation layer and the first doped semiconductor layer in the actual application scenario, and no specific limitation is made here. For example: when the actual application scenario requires that the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure, the first passivation layer is a tunneling passivation layer (the material of the tunneling passivation layer can be silicon oxide, titanium oxide or aluminum oxide and other materials), and the first doped semiconductor layer is a doped polycrystalline silicon layer. For another example: when the actual application scenario requires that the selective contact structure composed of the first passivation layer and the first doped semiconductor layer is a heterogeneous contact structure, the material of the first passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the first doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon. In addition, the embodiment of the present application does not specifically limit the thickness of the first passivation layer.

[0222] As for the second doped semiconductor layer, the portion of the second doped semiconductor layer corresponding to the second region can be directly formed on the second region on the backlight surface. Alternatively, as shown in FIG1 , the back contact cell may further include a second passivation layer 30 located between the second doped semiconductor layer 16 and the semiconductor substrate 11. In this case, the second passivation layer 30 and the second doped semiconductor layer 16 may constitute a selective contact structure to chemically passivate the corresponding region on the backlight surface of the semiconductor substrate 11 and selectively collect carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, and thus improving the photoelectric conversion efficiency of the back contact cell.

[0223] Specifically, the material of the second passivation layer can be determined according to the requirements for the type of selective contact structure composed of the second passivation layer and the second doped semiconductor layer in the actual application scenario, and is not specifically limited here. For example: when the actual application scenario requires that the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a tunneling passivation contact structure, the second passivation layer is a tunneling passivation layer, and the second doped semiconductor layer is a doped polycrystalline silicon layer. For another example: when the actual application scenario requires that the selective contact structure composed of the second passivation layer and the second doped semiconductor layer is a heterogeneous contact structure, the material of the second passivation layer includes intrinsic amorphous silicon and / or intrinsic microcrystalline silicon, and the material of the second doped semiconductor layer is doped amorphous silicon and / or doped microcrystalline silicon.

[0224] In actual applications, when the back-contact battery also includes a second passivation layer, the first dielectric layer and the second passivation layer can be formed as a continuous whole. In this case, when the first dielectric layer and the second passivation layer are formed as a continuous whole, the first dielectric layer and the second passivation layer can be formed simultaneously using the same material in the same manufacturing step, thereby simplifying the manufacturing process of the back-contact battery, improving the manufacturing efficiency of the back-contact battery, and reducing the manufacturing cost of the back-contact battery. Of course, in the actual manufacturing process, the first dielectric layer and the second passivation layer can also be formed separately in different manufacturing steps.

[0225] In addition, the porosity of the first dielectric layer can be smaller than the porosity of the second passivation layer. In this case, the dielectric constant of air is smaller than that of other dielectric materials. Based on this, when the porosity of the first dielectric layer is smaller than the porosity of the second passivation layer, it is beneficial to make the dielectric constant of the first dielectric layer greater than the dielectric constant of the second passivation layer, which is beneficial to improve the dielectric properties of the first dielectric layer, and ensure that at least part of the first doped semiconductor layer and at least part of the second doped semiconductor layer can be electrically isolated by the structure formed by the first dielectric layer and the second dielectric layer. Secondly, it can also prevent the transmission resistance of the second passivation layer from being high, further improving the working performance of the back contact battery. Of course, the porosity of the first dielectric layer can also be equal to the porosity of the second passivation layer.

[0226] As for the second dielectric layer, the second dielectric layer and the second doped semiconductor layer can be formed as a continuous, integrated structure. The beneficial effects of this scenario can be referenced in the analysis of the beneficial effects of the first dielectric layer and the second passivation layer being formed as a continuous, integrated structure, as described above, and will not be further elaborated here. Of course, in actual manufacturing processes, the second dielectric layer and the second doped semiconductor layer can also be formed separately in different manufacturing steps.

[0227] In terms of the formation range, as shown in FIG. 1 and FIG. 2 , the first doped semiconductor layer 15 is located on the first region 12 .

[0228] As for the second doped semiconductor layer, as shown in FIG. 1 and FIG. 2 , the second doped semiconductor layer 16 may be located only on the second region 13 .

[0229] Alternatively, as shown in Figures 8 and 9, the second doped semiconductor layer 16 may include an electrically connected first doped portion 23 and a second doped portion 24. The first doped portion 23 is located on the second region 13. The second doped portion 24 is located on the side of the second dielectric layer 18 facing away from the first dielectric layer 17, and the doping concentration of impurities in the second doped portion 24 is lower than the doping concentration of impurities in the first doped portion 23. In this case, the formation range of the second doped semiconductor layer 16 is increased, and the selective etching range of the intrinsic semiconductor layer used to form the second doped semiconductor layer 16, which is formed by deposition and other processes in the actual manufacturing process, is reduced, thereby improving etching efficiency and production capacity. In addition, the doping concentration of impurities in the second doped portion 24 is lower than the doping concentration of impurities in the first doped portion 23, which helps prevent short circuits caused by electrical connection between the first doped semiconductor layer 15 and the first doped portion 23 through the second doped portion 24, ensuring high electrical reliability of the back-contact cell.

[0230] Specifically, as shown in FIG. 8 , the second doped portion 24 may be located only in the spacing region 14 , and the second doped portion 24 is located on a side of the second dielectric layer 18 away from the first dielectric layer 17 along the arrangement direction of the first region 12 and the second region 13 .

[0231] Alternatively, when the first dielectric layer includes the first dielectric portion and the third dielectric portion, the second doped portion can be positioned in the spacing region and extend into the first region. In this case, the portion of the second doped portion corresponding to the spacing region is located on the side of the second dielectric layer facing away from the first dielectric layer, and the portion of the second doped portion corresponding to the first region is located above the third dielectric portion facing away from the first doped semiconductor layer. Furthermore, the first conductive window extends through at least the portion of the second doped portion corresponding to the first region and the third dielectric portion. In this case, the second doped portion can not only be positioned within the spacing region but can also extend into the first region, further increasing the range over which the second doped semiconductor layer can be formed and improving the efficiency and throughput of selectively etching the second doped semiconductor layer.

[0232] Alternatively, when the second dielectric layer extends above the first region, the second doped portion can be arranged in the spacing region and extend to the first region. Furthermore, the portion of the second doped portion corresponding to the first region is located on the portion of the second dielectric layer corresponding to the first region. The first conductive window at least penetrates the second dielectric layer and the portion of the second doped portion corresponding to the first region. Specifically, when the first dielectric layer includes only the first dielectric portion and the second dielectric portion, the first conductive window can only penetrate the portion of the second dielectric layer and the second doped portion corresponding to the first region. As shown in FIG9 , when the first dielectric layer 17 also includes the first dielectric portion 19 and the third dielectric portion 21, the second dielectric layer 18 extends onto the third dielectric portion 21 included in the first dielectric layer 17, and the first conductive window needs to penetrate the portion of the third dielectric portion 21, the second dielectric layer 18, and the second doped portion 24 corresponding to the first region 12.

[0233] It is worth noting that, as shown in FIG9 , when the second doped portion 24 included in the second doped semiconductor layer 16 is not only located within the spacing region 14 but also extends to the first region 12, the second dielectric layer 18 also extends onto the third dielectric portion 21 included in the first dielectric layer 17. In this case, the first conductive window needs to penetrate the second doped portion 24, the portion of the second dielectric layer 18 corresponding to the first region 12, and the third dielectric portion 21. The presence of not only the third dielectric portion 21 but also the portion of the second dielectric layer 18 corresponding to the first region 12 between the second doped portion 24 of opposite conductivity type and the first doped semiconductor layer 15 ensures high electrical isolation between the portion of the second doped portion 24 corresponding to the first region 12 and the first doped semiconductor layer 15.

[0234] In one example, when the second doped portion extends onto the first region and the first dielectric layer includes a third dielectric portion, the back-contact cell may further include a third dielectric layer located between the third dielectric portion and the first doped semiconductor layer. The first conductive window also extends through the third dielectric layer. In this case, as shown in Figure 9, the second doped portion 24 of opposite conductivity type and the first doped semiconductor layer 15 are separated not only by the third dielectric portion 21 but also by the third dielectric layer 25, ensuring high electrical isolation between the portion of the second doped portion 24 corresponding to the first region 12 and the first doped semiconductor layer 15.

[0235] As for the thickness of the second doped portion, since in actual applications, the second dielectric layer and the second doped semiconductor layer are integrally formed, the thickness of the second doped portion is inversely proportional to the thickness of the second dielectric layer. The thickness of the second dielectric layer, in turn, affects the dielectric properties of the structure formed by the first and second dielectric layers. This thickness can be determined based on the formation method of the second dielectric layer in actual application scenarios, the dielectric properties of the structure formed by the first and second dielectric layers, and actual manufacturing precision, and is not specifically limited here.

[0236] Exemplarily, the thickness of the second doping part can be greater than or equal to 40nm and less than or equal to 150nm. For example, the thickness of the second doping part can be 40nm, 60nm, 80nm, 100nm, 120nm or 150nm, etc. In this case, the thickness of the second doping part is within the above range, which can prevent the high control accuracy of the doping conditions during the manufacturing process due to the small thickness of the second doping part, thereby reducing the difficulty of manufacturing the second doping part. In addition, when the second dielectric layer and the second doped semiconductor layer are continuous as one, the thickness of the second doping part is within the above range, which can also prevent the large thickness of the second doping part from causing the small thickness of the second dielectric layer, resulting in a low degree of leakage risk reduced by the first dielectric layer and the second dielectric layer for at least part of the first doped semiconductor layer and at least part of the second doped semiconductor layer, thereby ensuring that the back contact battery has high working performance.

[0237] The doping concentration of the impurities in the first doping portion can be determined according to the actual application scenario and is not specifically limited here. The doping concentration of the impurities in the second doping portion can be any value less than the doping concentration of the impurities in the first doping portion and is not specifically limited here.

[0238] For example, the doping concentration of the impurities in the second doping portion may be greater than 0 and less than or equal to 1E20 cm -3 For example, the doping concentration of the impurities in the second doping portion can be 1E15cm -3 、6E15cm -3 、1E16cm -3 、5E16cm -3 、1E17cm -3 、5E17cm -3 、1E18cm -3 、1E19cm -3 or 1E20cm -3 In this case, the doping concentration of the impurities in the second doped portion is within the above range, which can prevent the second doped portion from having a relatively high doping concentration of the impurities and thus having a relatively high conductivity, thereby preventing the leakage risk of at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer from being reduced by the first dielectric layer and the second dielectric layer, thereby ensuring high operating performance of the back-contact battery.

[0239] Alternatively, as shown in Figures 3, 10, and 11, the second doped semiconductor layer 16 may include an electrically connected first doped portion 23 and a third doped portion 26. The first doped portion 23 is located on the second region 13, and the third doped portion 26 is located on the spacing region 14. The doping concentration of impurities in the third doped portion 26 is lower than the doping concentration of impurities in the first doped portion. In this case, during the actual manufacturing process, the width of the spacing region 14 between the first region 12 and the adjacent second region 13 is increased due to machine accuracy and / or to prevent leakage. Based on this, the second doped semiconductor layer 16 includes not only the first doped portion 23 located on the second region 13, but also the third doped portion 26 located on the partial spacing region. At this time, when the back contact battery is in the working state, the second doped semiconductor layer 16 can not only collect and export the electrons or holes corresponding to the second region 13 in a timely manner, but also collect and export the electrons or holes corresponding to the partial spacing region 14 in a timely manner. Therefore, while being able to electrically isolate at least a portion of the first doped semiconductor layer 15 and at least a portion of the second doped semiconductor layer 16 through the structure formed by the first dielectric layer 17 and the second dielectric layer 18, it can also reduce the carrier recombination rate in the wider spacing region 14, thereby further improving the photoelectric conversion efficiency of the back contact battery. In addition, because the third doped portion 26 is located between the first doped portion 23 and the first doped semiconductor layer 15, when the doping concentration of impurities in the third doped portion 26 located on the partial spacing region 14 is lower than the doping concentration of impurities in the first doped portion 23 located on the second region 13, the conductivity of the third doped portion 26 can be reduced, reducing the risk of electrical breakdown penetrating the first dielectric layer 17 and the second dielectric layer 18. At the same time, the diffusion of impurities in the third doped portion 26 into the second dielectric layer 18 is suppressed or even eliminated, ensuring that the structure formed by the first dielectric layer 17 and the second dielectric layer 18 has good electrical isolation, and ensuring that the back-contact battery has good electrical performance.

[0240] Specifically, in terms of impurity doping concentration, the specific doping concentration of impurities in the first doping part and the third doping part can be determined according to the actual application scenario, as long as the doping concentration of impurities in the third doping part is lower than the doping concentration of impurities in the first doping part.

[0241] For example, the doping concentration of the impurities in the third doping portion may be greater than or equal to 1E15 cm -3 , and less than or equal to 5E21cm -3 For example, the doping concentration of the impurities in the third doping portion can be 1E15cm -3 、5E15cm -3 、1E16cm -3 、5E16cm -3 、1E17cm -3 、5E17cm -3、1E18cm -3 、5E18cm -3 、1E19cm -3 、1E20cm -3 、1E21cm -3 or 5E21cm -3 In this case, the impurity concentration within the third doped portion is within the above range, which can prevent the third doped portion from having a poor carrier collection capability due to a low impurity concentration, further improving the degree to which the third doped portion reduces the carrier recombination rate in the gap region. Furthermore, it can prevent the third doped portion from easily diffusing carriers into the intrinsic semiconductor layer due to a high impurity concentration, thus ensuring that the intrinsic semiconductor layer has good electrical isolation.

[0242] For example, the doping concentration of impurities in the third doped portion can gradually decrease along the direction from the second region to the first region. In this case, while ensuring that the impurities in the third doped portion have a certain doping concentration, thereby enabling the third doped portion to have a certain carrier lateral collection capability, the portion of the third doped portion with the lowest impurity doping concentration can also be brought into contact with the second dielectric layer, reducing the carrier concentration gradient at the contact point between the two, further suppressing or even eliminating the diffusion of impurities in the third doped portion into the second dielectric layer, and ensuring that the structure formed by the first dielectric layer and the second dielectric layer has good electrical isolation.

[0243] The extent to which the doping concentration of the impurities in the third doping portion gradually decreases along the direction from the second region to the first region can be determined according to actual application scenarios and is not specifically limited here.

[0244] In terms of size, because the third doped portion, at least a portion of the first dielectric layer, and at least a portion of the second dielectric layer are all located in the spacing region, and the width of the structure formed by the first and second dielectric layers along the direction from the first region to the second region affects the isolation effect of the structure, the width of the spacing region and the width of the third doped portion can be determined based on the requirements for electrical isolation of the structure formed by the first and second dielectric layers in actual application scenarios. This embodiment of the present application does not specifically limit the width of the spacing region, the width of the third doped portion, or the ratio of the width of the third doped portion to the width of the first doped portion.

[0245] Exemplarily, the width of the spacing region can be greater than or equal to 30 μm and less than or equal to 200 μm. For example, the width of the spacing region can be 30 μm, 50 μm, 80 μm, 100 μm, 150 μm, or 200 μm. In this case, the width of the spacing region is within the above range, which can prevent the difficulty of providing a third doped portion, at least a portion of the first dielectric layer, and the second dielectric layer with a reasonable width within a smaller width range due to the smaller range of the spacing region, thereby ensuring that the structure composed of the third doped portion, the first dielectric layer, and the second dielectric layer has the functions described above. In addition, it can also prevent the first doped semiconductor layer and / or the second doped semiconductor layer from being smaller due to the larger width of the spacing region, thereby ensuring that the first doped semiconductor layer and the second doped semiconductor layer can collect and guide the carriers corresponding to the first region and the second region in a timely manner, further reducing the carrier recombination rate on the second surface.

[0246] For example, along the arrangement direction of the first region and the second region, the ratio of the width of the third doped portion to the width of the first doped portion may be greater than or equal to 1:20,000 and less than or equal to 2:700. For example, along the arrangement direction of the first region and the second region, the ratio of the width of the third doped portion to the width of the first doped portion may be 1:20,000, 1:15,000, 1:12,000, 1:10,000, 1:5,000, 1:1000, or 2:700, etc. In this case, when the ratio of the width of the third doped portion to the width of the first doped portion is within the above range, the width of the first doped portion is much larger than the width of the third doped portion, which can prevent the first doped portion from having a poor carrier collection ability due to its smaller width. It can also prevent the width of the spacing region and the first region, which are located on the backlight side together with the second region, from being smaller due to the larger width of the first doped portion, thereby ensuring that at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer can be electrically isolated by at least the first dielectric layer and the second dielectric layer formed in the spacing region, ensuring that the first doped semiconductor layer formed on the first region has a suitable formation range, and further ensuring that the first doped semiconductor layer has a higher carrier collection efficiency.

[0247] It should be noted that, as shown in FIG. 9 , the second doped semiconductor layer 16 may also include the first doped portion 23 , the second doped portion 24 and the third doped portion 26 .

[0248] It is understood that, as shown in Figures 8 and 9, when the second doped semiconductor layer 16 includes the aforementioned second doped portion 24 and / or third doped portion 26, if the second dielectric layer 18 and the second doped semiconductor layer 16 are integrally continuous, the presence of the second doped portion 24 and / or third doped portion 26 will affect the width of the second dielectric layer 18 along the arrangement direction of the first and second regions 12 and 13. When the second dielectric layer 18 is formed solely on the spacing region 14, the thickness of the second dielectric layer 18 is related to the width of the spacing region 14. Regarding the first dielectric layer 17, when the first dielectric layer 17 is integrally continuous with the second passivation layer 30, the thickness of the first dielectric layer 17 is equal to the thickness of the second passivation layer 30. When the first dielectric layer 17 is formed solely on the spacing region 14, the thickness of the first dielectric layer 17 is related to the width of the spacing region 14. In these cases, the thicknesses of the first and second dielectric layers 17 and 18 can be determined based on their formation methods, the width of the spacing region 14, and the structure of the second doped semiconductor layer 16, and are not specifically limited herein.

[0249] For example, along the arrangement direction of the first and second regions, the width of the portion of the first dielectric layer corresponding to the spacing region can be greater than or equal to 1 nm and less than or equal to 3 nm. For example, the width of the portion of the first dielectric layer corresponding to the spacing region can be 1 nm, 1.2 nm, 1.5 nm, 2 nm, 2.2 nm, 2.5 nm, or 3 nm. In this case, the width of the portion of the first dielectric layer corresponding to the spacing region within the above range can prevent the first dielectric layer from having poor dielectric properties along the arrangement direction of the first and second regions due to the smaller width of the portion of the first dielectric layer corresponding to the spacing region, thereby ensuring that at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer can be electrically isolated by the structure formed by the first and second dielectric layers. Furthermore, this can prevent the first doped semiconductor layer and / or the second doped semiconductor layer from having low carrier collection efficiency due to the larger width of the portion of the first dielectric layer corresponding to the spacing region, which results in a larger width of the spacing region between the first and second doped semiconductor layers. Furthermore, when the first dielectric layer is continuous with the second passivation layer located between the second doped semiconductor layer and the semiconductor substrate, the width of the portion of the first dielectric layer corresponding to the spacing area is within the above range, which can also prevent the carrier transfer resistance corresponding to the second passivation layer from being larger due to the larger width making the thickness of the second passivation layer also larger, thereby ensuring that the back-contact battery has higher working performance.

[0250] Of course, the width of the portion of the first dielectric layer corresponding to the spacing region may also be other appropriate values ​​that are less than 1 nm and greater than 3 nm.

[0251] For example, along the arrangement direction of the first region and the second region, the width of the portion of the second dielectric layer corresponding to the spacing region can be greater than or equal to 80 nm and less than or equal to 300 nm. For example, the width of the portion of the second dielectric layer corresponding to the spacing region can be 80 nm, 100 nm, 150 nm, 180 nm, 200 nm, 250 nm, 280 nm, or 300 nm. In this case, the width of the portion of the second dielectric layer corresponding to the spacing region is within the above range, which prevents the first doped semiconductor layer and / or the second doped semiconductor layer from having a lower carrier collection efficiency due to the larger width of the portion of the second dielectric layer corresponding to the spacing region, which results in a larger width of the spacing region between the first doped semiconductor layer and the second doped semiconductor layer. Secondly, it can also prevent the use of a larger amount of consumables in manufacturing the second dielectric layer due to the larger width of the portion of the second dielectric layer corresponding to the spacing region, thereby helping to control the manufacturing cost of the back-contact battery. In addition, when the second dielectric layer and the second doped semiconductor layer are continuous as one, the width of the portion of the second dielectric layer corresponding to the spacing region is within the above-mentioned range. This can also prevent the carrier collection efficiency of the second doped semiconductor layer from being low due to the smaller thickness of the second doped semiconductor layer caused by the smaller width of the portion of the second dielectric layer corresponding to the spacing region, thereby ensuring that the back-contact battery has higher working performance.

[0252] For example, when the second doped semiconductor layer includes electrically connected first and second doped portions, the width of the portion of the second dielectric layer corresponding to the spacing region along the arrangement direction of the first and second regions can be greater than or equal to 40 nm and less than or equal to 150 nm. For example, the width of the portion of the second dielectric layer corresponding to the spacing region can be 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, or 150 nm. In this case, the width of the portion of the second dielectric layer corresponding to the spacing region within the above range can prevent the second dielectric layer from having poor dielectric properties along the arrangement direction of the first and second regions due to the smaller width of the portion of the second dielectric layer corresponding to the spacing region, thereby ensuring that at least a portion of the first doped semiconductor layer and at least a portion of the second doped semiconductor layer can be electrically isolated by the structure formed by the first and second dielectric layers. Furthermore, this can prevent the first and / or second doped semiconductor layers from having low carrier collection efficiency due to the larger width of the portion of the second dielectric layer corresponding to the spacing region, which results in a larger width of the spacing region between the first and second doped semiconductor layers. In addition, when the second dielectric layer and the second doped semiconductor layer are continuous as one, the width of the portion of the second dielectric layer corresponding to the spacing region is within the above-mentioned range. This can also prevent the carrier collection efficiency of the second doped semiconductor layer from being low due to the smaller thickness of the second doped semiconductor layer caused by the smaller width of the portion of the second dielectric layer corresponding to the spacing region, thereby ensuring that the back-contact battery has higher working performance.

[0253] In practical applications, carriers collected by the first and second doped semiconductor layers need to be conducted through corresponding electrodes to generate photocurrent. Once the back-contact cell layout is determined, the distance between the corresponding electrode in ohmic contact with the second doped semiconductor layer and the boundary between the second region and the spacer region is a fixed value. Based on this, the width of a portion of the second region and a portion of the first doped region can also be indirectly determined by the geometric center of the corresponding electrode and the adjacent portion of the third doped region, as well as the spacing between the third doped region and the third doped region.

[0254] For example, as shown in Figures 3, 5, and 6, the back-contact cell may further include a first electrode 27 and a second electrode 28. The first electrode 27 is formed on the first doped semiconductor layer 15 and is in ohmic contact with the first doped semiconductor layer 15. The second electrode 28 is formed on the first doped portion 23 and is in ohmic contact with the first doped portion 23. In this case, along the arrangement direction of the first region 12 and the second region 13, the distance between the geometric center of the portion of the second electrode 28 adjacent to the third doped portion 26 and the third doped portion 26 may be greater than or equal to 110 μm and less than or equal to 380 μm. For example, the distance between the geometric center of the portion of the second electrode 28 adjacent to the third doped portion 26 and the third doped portion 26 may be 110 μm, 150 μm, 180 μm, 200 μm, 240 μm, 260 μm, 300 μm, 340 μm, or 380 μm. In this case, the second electrode 28 is formed on the first doped portion 23 and is in ohmic contact with the first doped portion 23. In this case, the distance between the geometric center of the portion adjacent to the second electrode 28 and the third doped portion 26 included in the second doped semiconductor layer 16 and the third doped portion 26 will affect the width of the first doped portion 23 along the arrangement direction of the first region 12 and the second region 13, thereby affecting the carrier collection efficiency of the first doped portion 23. Based on this, the distance between the geometric center of the portion adjacent to the second electrode 28 and the third doped portion 26 and the third doped portion 26 is within the above range, which can prevent the carrier collection efficiency of the first doped portion 23 from being low due to the small distance between the geometric center of the portion adjacent to the second electrode 28 and the third doped portion 26 and the third doped portion 26. In addition, it can also prevent the width of the spacing region 14 and / or the first region 12 located on the backlight side together with the second region 13 from being small due to the large width of the first doped portion 23. The beneficial effect of preventing the width of the spacing region 14 and / or the first region 12 from being small can be referred to the above and will not be repeated here.

[0255] In one example, as shown in FIG1 , the back-contact cell may further include a surface passivation layer 31. The surface passivation layer 31 covers the second doped semiconductor layer 16 and extends to the top of the first doped semiconductor layer 15 along the arrangement direction of the first region 12 and the second region 13. A first conductive window is provided through the portion of the surface passivation layer 31 corresponding to the first region 12, and the bottom of the first conductive window exposes at least a portion of the first doped semiconductor layer 15. A second conductive window is provided through the portion of the surface passivation layer 31 corresponding to the second region 13, and the bottom of the second conductive window exposes at least a portion of the second doped semiconductor layer 16.

[0256] Specifically, the present embodiments do not impose any specific restrictions on the material and thickness of the surface passivation layer, as long as it can be applied to the back-contact battery provided in the present embodiments. The surface passivation layer can be a single-layer structure made of only one passivation material, or it can be a stacked structure made of multiple passivation materials.

[0257] In addition, as shown in Figures 10 and 11, the above-mentioned back-contact battery may also include an interface passivation layer formed on the light-facing side of the semiconductor substrate 11 to passivate the surface defects on the light-facing side of the semiconductor substrate 11 and reduce the carrier recombination rate on the light-facing side. The material of the interface passivation layer may include any passivation material such as silicon oxide, silicon nitride or aluminum oxide. Secondly, in the actual application process, the interface passivation layer can be formed simultaneously with the above-mentioned surface passivation layer. At this time, the material and thickness of the interface passivation layer are respectively the same as the material and thickness of the surface passivation layer. Of course, the interface passivation layer and the surface passivation layer can also be formed separately in different steps.

[0258] In one example, as shown in FIG1 , the back-contact cell further includes a first electrode 27 and a second electrode 28. The first electrode 27 is formed on the first doped semiconductor layer 15 and makes ohmic contact with the first doped semiconductor layer 15. The second electrode 28 is formed on the second doped semiconductor layer 16 and makes ohmic contact with the second doped semiconductor layer 16. The specific structures of the first electrode 27 and the second electrode 28 can be determined according to the type of back-contact cell.

[0259] Exemplarily, in the case of a busbarless back-contact cell, the first electrode and the second electrode each include a plurality of collector electrodes. Furthermore, the collector electrodes of the first electrode and the collector electrodes of the second electrode both extend along a first direction and are alternately spaced along a second direction. The first direction is different from the second direction. Specifically, the first direction is the direction in which the first region and the second region extend, and the second direction is the direction in which the first region and the second region are arranged.

[0260] Exemplarily, in the case where the back-contact cell is a busbar back-contact cell, the first electrode and the second electrode each include a plurality of collector electrodes and a plurality of bus electrodes. The collector electrodes included in the first electrode and the collector electrodes included in the second electrode both extend along a first direction and are alternately spaced along a second direction. The first direction is different from the second direction; the bus electrodes included in the first electrode and the bus electrodes included in the second electrode both extend along the second direction and are alternately spaced along the first direction; each bus electrode is electrically connected to a collector electrode of the same polarity as itself and is insulated from a collector electrode of an opposite polarity.

[0261] Specifically, the collecting electrodes included in the first electrode have opposite polarities to the collecting electrodes and bus electrodes included in the second electrode, and have the same polarity as the bus electrodes included in the first electrode. Similarly, the collecting electrodes included in the second electrode have opposite polarities to the collecting electrodes and bus electrodes included in the first electrode, and have the same polarity as the bus electrodes included in the second electrode. In addition, each bus electrode can be insulated from the collecting electrodes of opposite polarity by insulating materials such as insulating glue. Alternatively, each collecting electrode can be a discontinuous collecting electrode, in which case each bus electrode can be insulated from the collecting electrodes of opposite polarity by having discontinuities in the collecting electrodes and having opposite polarity.

[0262] In addition, the embodiments of the present application do not specifically limit the number, shape, spacing between adjacent collecting electrodes, spacing between adjacent bus electrodes, etc. of the collecting electrodes and bus electrodes included in the first electrode and the second electrode, which can be determined according to actual needs.

[0263] Exemplarily, the spacing between two adjacent collecting electrodes with opposite polarity can be greater than or equal to 200μm and less than or equal to 700μm. For example, the spacing between two adjacent collecting electrodes with opposite polarity can be 200μm, 300μm, 400μm, 500μm, 600μm or 700μm, etc. In this case, it can be prevented that the leakage risk of two adjacent collecting electrodes with opposite polarity is reduced to a small extent due to the small spacing. It can also be prevented that the spacing between two adjacent collecting electrodes with opposite polarity is large, resulting in a larger width of the spacing area, resulting in a higher carrier recombination rate in the portion of the back contact battery corresponding to the spacing area, thereby ensuring that the back contact battery has higher working performance.

[0264] Exemplarily, the width of the collector electrode can be greater than or equal to 15 μm and less than or equal to 60 μm. For example, the width of the collector electrode can be 15 μm, 20 μm, 30 μm, 40 μm, 50 μm, or 60 μm. In this case, the contact resistance between the collector electrode and the corresponding doped semiconductor layer can be prevented from being large due to the small width of the collector electrode, thereby improving the contact performance between the collector electrode and the corresponding doped semiconductor layer. In addition, the metal composite loss can be reduced by preventing the metal composite loss corresponding to the collector electrode from being high due to the large width of the collector electrode, thereby achieving a balance between the contact performance and metal composite loss of the collector electrode.

[0265] In actual application, when the first electrode and the second electrode include the above-mentioned multiple collecting electrodes and multiple bus electrodes, the distribution of the structure composed of the first dielectric layer and the second dielectric layer between the first electrode and the second electrode can be determined according to the actual application scenario.

[0266] For example, the width of the structure formed by the first dielectric layer and the second dielectric layer in the portion between two adjacent collector electrodes of opposite polarity along the width direction of the spacing region is approximately the same as the thickness of the second doped semiconductor layer. In this case, the second doped semiconductor layer has a certain carrier collection efficiency and needs to have a corresponding thickness. Based on this, when the width of the structure formed by the first dielectric layer and the second dielectric layer in the portion between two adjacent collector electrodes of opposite polarity along the width direction of the spacing region is approximately the same as the thickness of the second doped semiconductor layer, it can prevent the electrical isolation effect of the structure formed by the first dielectric layer and the second dielectric layer from being poor due to the smaller width. Secondly, the first dielectric layer or the second dielectric layer can be formed based on the same manufacturing process and manufacturing materials at the same time as the second doped semiconductor layer is manufactured, thereby simplifying the manufacturing process of the back-contact battery.

[0267] For example, the width of the portion of the structure formed by the first dielectric layer and the second dielectric layer between adjacent collector electrodes and bus electrodes of opposite polarity along the width direction of the spacing region is substantially equal to the thickness of the second doped semiconductor layer. The beneficial effect of this case is similar to the beneficial effect of the structure formed by the first dielectric layer and the second dielectric layer between adjacent collector electrodes of opposite polarity along the width direction of the spacing region being substantially equal to the thickness of the second doped semiconductor layer, and is not further described here.

[0268] Exemplarily, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between two adjacent collector electrodes of opposite polarity along the extending direction of the spacing region can be greater than or equal to 300 μm and less than or equal to 3000 μm. For example, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between two adjacent collector electrodes of opposite polarity along the extending direction of the spacing region can be 300 μm, 500 μm, 1000 μm, 1500 μm, 2000 μm, 25000 μm, or 3000 μm, etc. In this case, this can prevent the region in the first doped semiconductor layer and the second doped semiconductor layer electrically isolated by the structure formed by the first dielectric layer and the second dielectric layer from being smaller due to the smaller length, thereby ensuring that the back-contact cell has a low leakage current under normal operating conditions.

[0269] Exemplarily, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between adjacent collector electrodes and bus electrodes of opposite polarity along the direction in which the spacing region extends can be greater than or equal to 200 μm and less than or equal to 700 μm. For example, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between adjacent collector electrodes and bus electrodes of opposite polarity along the direction in which the spacing region extends can be 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, or 700 μm, etc. The beneficial effects in this case can be analyzed with reference to the beneficial effects of the portion of the structure formed by the first dielectric layer and the second dielectric layer between two adjacent collector electrodes of opposite polarity along the direction in which the spacing region extends being greater than or equal to 300 μm and less than or equal to 3000 μm.

[0270] It should be noted that when the back contact cell is a busbar-free back contact cell, the width of the structure formed by the first dielectric layer and the second dielectric layer between the two collecting electrodes with opposite polarities can refer to the corresponding width corresponding to the busbar back contact cell described above, and will not be repeated here.

[0271] Secondly, embodiments of the present application also provide a method for manufacturing a back-contact cell. The manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 12 to 36. Specifically, the method for manufacturing a back-contact cell includes the following steps: First, as shown in Figure 12, a semiconductor substrate 11 is provided; the backlight surface of the semiconductor substrate 11 has first regions 12 and second regions 13 alternately spaced, and a spacing region 14 located between each first region 12 and the adjacent second region 13. Next, as shown in Figure 14, a first doped semiconductor layer 15 is formed on the first region 12 on the backlight surface. Next, as shown in Figures 18 to 28, a second doped semiconductor layer 16 is formed on at least the second region 13 on the backlight surface. The second doped semiconductor layer 16 and the first doped semiconductor layer 15 have opposite conductivity types. Next, as shown in Figures 18 to 28, a first dielectric layer 17 and a second dielectric layer 18 are formed on at least the spacing region 14 on the backlight surface. At least a portion of the first dielectric layer 17 and at least a portion of the second dielectric layer 18 are stacked and disposed between the first doped semiconductor layer 15 and the second doped semiconductor layer 16 along the arrangement direction of the first region 12 and the second region 13. At least a portion of the first dielectric layer 17 is in contact with the first doped semiconductor layer 15, and at least a portion of the second dielectric layer 18 is in contact with the second doped semiconductor layer 16. The first dielectric layer 17 and the second dielectric layer 18 are made of different materials.

[0272] Among them, the structure of the back-contact battery formed by the manufacturing method provided in the second aspect of the embodiment of the present application is the same. Therefore, the material of the semiconductor substrate in the manufacturing method, the range and morphology of each area on the backlight side of the semiconductor substrate, the material and formation range of the first doped semiconductor layer and the second doped semiconductor layer, and the material and formation range of the first dielectric layer and the second dielectric layer can be referred to the previous text and will not be repeated here.

[0273] In an actual manufacturing process, forming the first doped semiconductor layer on the first region of the backlight surface may include the following steps: forming the first doped semiconductor layer as a whole layer on the backlight surface, and a third dielectric layer located on the portion of the first doped semiconductor layer corresponding to the first region; or forming the first doped semiconductor layer and the third dielectric layer as a whole layer on the backlight surface, and heat-treating the portion of the third dielectric layer corresponding to the second region and the spacing region using a laser irradiation process; forming a mask on the portion of the third dielectric layer corresponding to the first region after the heat treatment. Next, using the mask of the portion of the third dielectric layer corresponding to the first region, removing the portion of the first doped semiconductor layer corresponding to the second region and the spacing region.

[0274] Specifically, if the first doped semiconductor layer in the manufactured back-contact cell is formed directly on the first region of the backlight surface, a process such as chemical vapor deposition can be used to form an entire intrinsic semiconductor layer disposed on the backlight side. The intrinsic semiconductor layer can then be doped using diffusion, ion implantation, or dopant source coating to form the first doped semiconductor layer. A third dielectric layer is then formed on the portion of the first doped semiconductor layer corresponding to the first region. When the first doped semiconductor layer is made of silicon and the intrinsic semiconductor layer is doped using a diffusion process, simultaneously with the formation of the first doped semiconductor layer, a third dielectric layer comprising a doped silicon glass layer is also formed on the side of the first doped semiconductor layer facing away from the semiconductor substrate. In this case, the portion of the third dielectric layer corresponding to the second region and the spacer region can be heat-treated using a method such as laser irradiation to make the portion of the third dielectric layer corresponding to the second region and the spacer region more porous than the portion of the third dielectric layer corresponding to the first region. After the heat treatment, the portion of the third dielectric layer corresponding to the first region forms a mask, and the portion of the third dielectric layer corresponding to the second region and the spacer region can subsequently be selectively removed using a process such as wet etching. If the third dielectric layer is made of undoped silica glass, additional deposition and photolithography processes can be used to form the third dielectric layer only on the portion of the first doped semiconductor layer corresponding to the first region. After the third dielectric layer is formed, a wet etching process or other process is used, using the third dielectric layer as a mask, to remove the portion of the first doped semiconductor layer corresponding to the second region and the spacer region, thereby forming the first doped semiconductor layer only on the first region of the backlight surface.

[0275] Alternatively, in the actual manufacturing process, the above-mentioned method can be used to form a first doped semiconductor layer entirely on the backlight side. Then, under the masking action of a corresponding mask layer or reticle, and using a process such as chemical vapor deposition, the third dielectric layer can be formed only on the portion of the first doped semiconductor layer corresponding to the first region.

[0276] When the manufactured back-contact battery includes a first passivation layer, after providing a semiconductor substrate and before forming a second doped semiconductor layer on at least a second area of ​​the backlight surface, the manufacturing method of the back-contact battery includes: forming a first passivation layer on the first area, and a first doped semiconductor layer located on the side of the first passivation layer away from the semiconductor substrate.

[0277] Specifically, before forming the first doped semiconductor layer, a deposition and photolithography process may be used to form a first passivation layer only on the first region. Alternatively, as shown in FIG13 , before forming the first doped semiconductor layer 15, a first passivation layer 29 may be formed as a whole layer on the backlight side. Then, the above-mentioned method is used to form the first doped semiconductor layer 15 as a whole layer on the first passivation layer 29, as well as the third dielectric layer 25 on the portion of the first doped semiconductor layer 15 corresponding to the first region 12. Next, as shown in FIG14 , under the masking action of the portion of the third dielectric layer 25 corresponding to the first region 12, selective etching of the first passivation layer 29 and the first doped semiconductor layer 15 is simultaneously achieved to simplify the manufacturing process of the back-contact battery and improve the manufacturing efficiency of the back-contact battery.

[0278] Secondly, as mentioned above, in the case where the backlight side of the semiconductor substrate in the manufactured back-contact battery has a groove structure, after forming the first doped semiconductor layer on the first area of ​​the backlight surface, before forming the second doped semiconductor layer at least on the second area of ​​the backlight surface, the above-mentioned back-contact battery manufacturing method also includes the steps of: as shown in Figure 15, selectively etching the backlight side of the semiconductor substrate 11 to form a groove structure on the backlight side; the second area 13 and the spacer area 14 are both located in the groove structure.

[0279] Specifically, the backlight side of the semiconductor substrate can be selectively etched using a dry or wet etching process under the masking effect of the portion of the third dielectric layer corresponding to the first region to form a groove structure.

[0280] It should be noted that after forming the first doped semiconductor layer or the groove structure, the third dielectric layer above the first region may be retained, or the portion of the third dielectric layer corresponding to the first region may be removed before forming the second doped semiconductor layer.

[0281] Next, a second doped semiconductor layer is formed at least on the second region of the backlight surface. The formation process of the second doped semiconductor layer can be determined according to its own formation range.

[0282] For example, when the second doped semiconductor layer is only located on the second region, a process such as chemical vapor deposition can be used to form an intrinsic semiconductor layer arranged as a whole on the first doped semiconductor layer, the spacing region, and the second region. Then, the portion of the intrinsic semiconductor layer corresponding to the second region is selectively doped so that the portion of the intrinsic semiconductor layer corresponding to the second region forms the second doped semiconductor layer. As to whether the portion of the intrinsic semiconductor layer corresponding to the first region and the spacing region needs to be removed, it can be determined based on whether the second dielectric layer is integrally continuous with the second doped semiconductor layer. When the second dielectric layer is integrally continuous with the second doped semiconductor layer, it is necessary to retain at least the portion of the intrinsic semiconductor layer corresponding to the spacing region, and form the second dielectric layer based on at least the portion of the intrinsic semiconductor layer corresponding to the spacing region. When the second dielectric layer is not integrally continuous with the second doped semiconductor layer, it is necessary to selectively remove the portion of the intrinsic semiconductor layer corresponding to the first region and the spacing region.

[0283] Secondly, in the case where the manufactured back-contact battery also includes a second passivation layer, after forming the first doped semiconductor layer on the first area of ​​the backlight surface and before forming the second doped semiconductor layer on the second area of ​​the backlight surface, the above-mentioned manufacturing method of the back-contact battery also includes the step of forming a second passivation layer at least on the second area of ​​the backlight surface.

[0284] Specifically, the formation process of the second passivation layer can refer to the formation process of the first passivation layer described above. It should be noted that when the first dielectric layer and the second passivation layer are integrally continuous, at least the portion of the material for making the second passivation layer corresponding to the gap region needs to be retained. If the first dielectric layer and the second passivation layer are not integrally continuous, the portion of the material for making the second passivation layer corresponding to the gap region and the first region needs to be selectively removed.

[0285] In the actual manufacturing process, the formation order and specific formation process of the second doped semiconductor layer and the second passivation layer, as well as the first dielectric layer and the second dielectric layer on the backlight side can be determined based on the formation range of the first dielectric layer, the second dielectric layer, and the second doped semiconductor layer, the specific structure of the second doped semiconductor layer, and the actual application scenario described above. The following is divided into the following four types of formation processes based on whether the first dielectric layer and the second dielectric layer are respectively integrated and continuous with the second passivation layer and the second doped semiconductor layer:

[0286] In the first type, the first dielectric layer and the second passivation layer are not continuous as a whole, and the second dielectric layer and the second doped semiconductor layer are not continuous as a whole.

[0287] In the first case, if the first dielectric layer includes only the aforementioned first dielectric portion, after forming the first doped semiconductor layer, a process such as chemical vapor deposition can be used to form a first dielectric material layer entirely over the first doped semiconductor layer, the spacer region, and the second region. Subsequently, a process such as dry etching or laser etching is used to remove the portions of the first dielectric material layer corresponding to the first and second regions. Because the portion of the first dielectric material layer corresponding to the first doped semiconductor layer is relatively high along the thickness of the semiconductor substrate, this portion is retained to form the first dielectric layer.

[0288] In the first case, if the first dielectric layer includes only the first dielectric portion and the second dielectric portion, or the first dielectric portion includes only the first dielectric portion and the third dielectric portion, or the first dielectric layer includes the first dielectric portion, the second dielectric portion, and the third dielectric portion, then the above-described method can be used to form a first dielectric material layer entirely over the first doped semiconductor layer, the spacing region, and the second region. A mask layer is then formed over the portion of the first dielectric material layer to be retained, and the mask layer selectively removes the portion of the first dielectric material layer to be removed. For example, if the first dielectric layer includes only the first dielectric portion and the second dielectric portion, a mask layer is formed over the portion of the first dielectric material layer corresponding to the spacing region, and the mask layer selectively removes the portion of the first dielectric material layer corresponding to the first region and the second region.

[0289] Regarding the formation process of the second dielectric layer in the first case, after forming the first dielectric layer, a second dielectric material layer can be formed entirely over the side of the first doped semiconductor layer facing away from the semiconductor substrate, over the portion of the first dielectric layer corresponding to the spacing region, and over the second region using a process such as chemical vapor deposition. Subsequently, at least the portion of the second dielectric material layer corresponding to the second region is selectively removed using a mask formed by a corresponding mask layer.

[0290] It should be noted that when the first dielectric layer includes the third dielectric portion and / or the second dielectric layer further extends above the first region, a process such as laser etching is also required to form a first conductive window in the first region that penetrates at least the portion of the third dielectric portion and / or the second dielectric layer extending above the first region. The bottom of the first conductive window exposes at least a portion of the first doped semiconductor layer.

[0291] As for the formation process of the second passivation layer and the second doped semiconductor layer in the first case, reference may be made to the foregoing.

[0292] In the second type, the first dielectric layer and the second passivation layer are integrally continuous, and the second dielectric layer and the second doped semiconductor layer are not integrally continuous.

[0293] In the second case, a second passivation material layer can be formed entirely on the first doped semiconductor layer, the spacing region, and the second region using a process such as chemical vapor deposition. The portion of the second passivation material layer corresponding to the second region is the second passivation layer. The portion of the second passivation material layer corresponding to the spacing region is the first dielectric portion and the second dielectric portion included in the first dielectric layer. Whether the portion of the second passivation material layer corresponding to the first region needs to be removed depends on whether the first dielectric layer includes a third dielectric portion. It is understood that when the first dielectric layer includes a third dielectric portion, the portion of the second passivation material layer corresponding to the first region needs to be retained; otherwise, it needs to be removed.

[0294] As for the formation process of the second dielectric layer in the second case, reference may be made to the formation process of the second dielectric layer in the first case. As for the formation process of the second doped semiconductor layer in the second case, reference may be made to the above.

[0295] It should be noted that when the first dielectric layer includes the third dielectric portion and / or the second dielectric layer further extends above the first region, a process such as laser etching is also required to form a first conductive window in the first region that penetrates at least the portion of the third dielectric portion and / or the second dielectric layer extending above the first region. The bottom of the first conductive window exposes at least a portion of the first doped semiconductor layer.

[0296] The third type is that the first dielectric layer and the second passivation layer are not integrally continuous, and the second dielectric layer and the second doped semiconductor layer are integrally continuous.

[0297] The formation process of the first dielectric layer in the third scenario can be referenced to the formation process of the first dielectric layer in the first scenario described above. After the first dielectric layer is formed, a second passivation material layer can be formed entirely on the backlight side using a process such as chemical vapor deposition. Then, using a mask layer or reticle, the portion of the second passivation material layer corresponding to the first region and at least a portion of the spacing region is selectively removed, leaving the remaining portion of the second passivation material layer to form the second dielectric layer.

[0298] As for the formation process of the second dielectric layer in the third case, after forming the second passivation layer, a process such as chemical vapor deposition can be used to form a complete intrinsic semiconductor layer above the side of the first doped semiconductor layer facing away from the semiconductor substrate, on the portion of the first dielectric layer corresponding to the spacing region, and on the second passivation layer. Then, the portion of the intrinsic semiconductor layer corresponding to the second region is selectively doped. After selective doping, the second doped semiconductor layer can be formed only in the portion of the intrinsic semiconductor layer corresponding to the second region; or after selective doping, impurities are not only doped into the portion of the intrinsic semiconductor layer corresponding to the second region, but also doped into the portion of the intrinsic semiconductor layer located in the spacing region by diffusion, so that the portions of the intrinsic semiconductor layer corresponding to the second region and the portion of the spacing region form the first doped portion and the third doped portion included in the second doped semiconductor layer.

[0299] In the case where the second doped semiconductor layer also includes a second doped portion, after forming the intrinsic semiconductor layer, before selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, it is necessary to lightly dope the side of the intrinsic semiconductor layer away from the semiconductor substrate to form the second doped portion.

[0300] Regarding the portion of the intrinsic semiconductor layer corresponding to the first region after forming the second doped semiconductor layer in the third case, if the second dielectric layer in the manufactured back-contact cell does not extend over the first region, the portion of the intrinsic semiconductor layer corresponding to the first region needs to be removed after forming the second doped semiconductor layer. If the second dielectric layer extends over the first region and the second doped portion does not extend over the first region, only the portion of the intrinsic semiconductor layer opposite the extension direction of the second doped portion and located above the first region needs to be removed after forming the second doped semiconductor layer. If both the second dielectric layer and the second doped portion extend over the first region, the portion of the intrinsic semiconductor layer corresponding to the first region needs to be retained after forming the second doped semiconductor layer.

[0301] In a fourth embodiment, the first dielectric layer and the second passivation layer are continuous and integrated, and the second dielectric layer and the second doped semiconductor layer are continuous and integrated.

[0302] In the fourth case, forming the second doped semiconductor layer, the second passivation layer, the first dielectric layer, and the second dielectric layer may include the following steps: As shown in FIG16 , a passivation material layer 34 and an intrinsic semiconductor layer 35 are sequentially formed along the thickness direction of the semiconductor substrate 11, stacked and covering the first doped semiconductor layer 15, the spacing region 14, and the second region 13. Next, as shown in FIG17 , a selective doping treatment is performed on the portion of the intrinsic semiconductor layer corresponding to the second region 13. After the selective doping treatment, at least the portion of the intrinsic semiconductor layer corresponding to the second region 13 forms the second doped semiconductor layer 16, at least the portion of the intrinsic semiconductor layer corresponding to a portion of the spacing region 14 forms the second dielectric layer 18, the portion of the passivation material layer between the second doped semiconductor layer 16 and the semiconductor substrate 11 forms the second passivation layer 30, and at least the portion of the passivation material layer corresponding to a portion of the spacing region 14 forms the first dielectric layer 17.

[0303] In this fourth case, chemical vapor deposition and other processes can be used to form the above-mentioned passivation material layer and intrinsic semiconductor layer. Then, under the masking action of the corresponding mask layer or mask, diffusion, ion implantation or dopant source coating and other processes can be used to selectively dope the portion of the intrinsic semiconductor layer corresponding to the second region. As shown in FIG17 , when the material of the intrinsic semiconductor layer contains silicon and the diffusion process is used for selective doping, after the second doped semiconductor layer 16 is formed, a corresponding doped silicon glass layer is formed at least on the side of the second doped semiconductor layer 16 facing away from the semiconductor substrate. Furthermore, after the selective doping treatment, the doped silicon glass layer can be removed by wet etching and other processes.

[0304] Specifically, after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, whether the portions of the intrinsic semiconductor layer and the passivation material layer corresponding to the first region are removed depends on the formation range of the first dielectric layer and the second dielectric layer.

[0305] For example, when the first dielectric layer, the second dielectric layer, and the second doped semiconductor layer do not extend onto the first region, as shown in FIG20 , after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region 13, the above-mentioned back-contact battery manufacturing method further includes the step of selectively removing the portion of the intrinsic semiconductor layer and the passivation material layer corresponding to the first region 12. Next, the portion of the third dielectric layer corresponding to the first region is removed. In this case, the structure of the manufactured back-contact battery is relatively simple, and the difficulty of subsequently forming the first conductive window can be reduced, which is conducive to improving the yield of the back-contact battery.

[0306] For another example, where the first dielectric layer includes a third dielectric portion and the second dielectric layer does not extend over the first region, after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, it is necessary to selectively remove the portion of the intrinsic semiconductor layer corresponding to the first region, while retaining the portion of the passivation material layer corresponding to the first region. Next, a first conductive window is formed above the first region, penetrating the third dielectric layer and the passivation material layer.

[0307] For another example, when the first dielectric layer includes a third dielectric portion and the second dielectric layer extends onto the third dielectric portion, after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region, it is necessary to retain the portion of the passivation material layer corresponding to the first region and the portion of the intrinsic semiconductor layer corresponding to the first region. Next, a first conductive window is formed above the first region, penetrating the third dielectric layer, the passivation material layer, and the intrinsic semiconductor layer.

[0308] Furthermore, in the actual manufacturing process, after sequentially forming a passivation material layer and an intrinsic semiconductor layer stacked and covering the first doped semiconductor layer, the spacer region, and the second region along the thickness direction of the semiconductor substrate, and before performing a selective doping treatment on the portion of the intrinsic semiconductor layer corresponding to the second region, the above-mentioned back-contact cell manufacturing method may further include the following steps: as shown in FIG24 , lightly doping the side of the intrinsic semiconductor layer facing away from the semiconductor substrate 11 to form a second doped portion 24 included in the second doped semiconductor layer 16. In this case, whether the portions of the intrinsic semiconductor layer and the passivation material layer corresponding to the first region are removed after the light doping and selective doping treatments is determined based on the formation range of the first dielectric layer, the second dielectric layer, and the second doped portion.

[0309] For example, when the first dielectric layer, the second dielectric layer, and the second doped semiconductor layer do not extend onto the first region, as shown in FIG26 , after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region 13, the above-mentioned back-contact battery manufacturing method further includes the step of selectively removing the portions of the intrinsic semiconductor layer and the passivation material layer corresponding to the first region 12. Next, the portion of the third dielectric layer corresponding to the first region is removed.

[0310] For another example, when the first dielectric layer includes a third dielectric portion, and the second dielectric layer and the second doped portion sequentially extend onto the third dielectric portion, as shown in FIG27 , after selectively doping the portion of the intrinsic semiconductor layer corresponding to the second region 13, it is necessary to retain the portion of the passivation material layer corresponding to the first region 12 and the portion of the intrinsic semiconductor layer that has been lightly doped and corresponds to the first region 12. Next, as shown in FIG28 , a first conductive window 22 is formed above the first region 12, penetrating the third dielectric layer 25, the passivation material layer (the portion of the passivation material layer corresponding to the first region is the third dielectric portion 21), and the lightly doped intrinsic semiconductor layer (the portion of the lightly doped intrinsic semiconductor layer corresponding to the first region includes the portion of the second dielectric layer 18 extending into the first region and the portion of the second doped portion 24 extending into the first region).

[0311] From the manufacturing processes of the first to fourth cases described above and the structures shown in Figures 16 to 28, it can be seen that the formation ranges of the first dielectric layer 17, the second dielectric layer 18, and the second doped semiconductor layer 16 may be different in different cases, and the corresponding selective etching ranges and formation range methods may be different. Therefore, the first dielectric layer 17, the second dielectric layer 18, and the second doped semiconductor layer 16 can be manufactured by a suitable method based on the requirements for the formation ranges of the first dielectric layer 17, the second dielectric layer 18, and the second doped semiconductor layer 16, as well as the selective etching range, in actual application scenarios.

[0312] Furthermore, when the manufactured back-contact battery also includes a conductive structure, the portion of the intrinsic semiconductor layer corresponding to the second region can be selectively doped while the portion of the intrinsic semiconductor layer at least located at the discontinuity is also selectively doped, so that at least the portion of the intrinsic semiconductor layer at the discontinuity forms a conductive structure. Alternatively, in the actual manufacturing process, after forming the first and second dielectric layers, the portions of the first and second dielectric layers corresponding to the discontinuity can be selectively removed, and then a deposition process or other process can be used to form a conductive structure at the discontinuity. The material and conductivity type of the conductive structure can be referred to above.

[0313] Next, if the back-contact cell also includes a surface passivation layer, after forming the first dielectric layer and the second dielectric layer at least on the spacer region of the backlight surface, the back-contact cell manufacturing method further includes the following steps: As shown in Figures 29 and 30, a surface passivation layer 31 is formed on the backlight side; this surface passivation layer 31 covers the second doped semiconductor layer 16 and extends above the first doped semiconductor layer 15 along the arrangement direction of the first region 12 and the second region 13. Next, as shown in Figures 31 to 33, a first conductive window 22 is formed through the portion of the surface passivation layer 31 corresponding to the first region 12, and a second conductive window 32 is formed through the portion of the surface passivation layer 31 corresponding to the second region 13. The bottom of the first conductive window 22 exposes at least a portion of the first doped semiconductor layer 15. The bottom of the second conductive window 32 exposes at least a portion of the second doped semiconductor layer 16.

[0314] The material and thickness of the surface passivation layer can be found in the previous section and will not be further described here. Alternatively, a process such as chemical vapor deposition can be used to form a complete surface passivation layer disposed on the backlight side. Laser etching or other methods can then be used to create a first conductive window and a second conductive window, respectively, penetrating at least the portion of the surface passivation layer corresponding to the first and second regions.

[0315] It should be noted that, as shown in Figure 27, when the thickness of the film layer formed on the first doped semiconductor layer 15 is relatively large, before forming the surface passivation layer 31, the corresponding film layer located on the first doped semiconductor layer 15 can be selectively etched by laser etching or other methods to form a penetrating contact window.

[0316] In addition, when the back-contact cell also includes an interface passivation layer on the light-facing side, the interface passivation layer can be formed on the light-facing side at the same time as the surface passivation layer is formed. Alternatively, the interface passivation layer can be formed on the light-facing side by additional processes such as chemical vapor deposition before or after the surface passivation layer is formed.

[0317] Next, as shown in FIG. 34 to FIG. 36 , a first electrode 27 may be formed at least in the first conductive window, and a second electrode 28 may be formed at least in the second conductive window by screen printing, electroplating, sputtering, or evaporation.

[0318] The beneficial effects of the second aspect and its various implementations in the embodiments of the present application can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0319] Example 1

[0320] The method for manufacturing a back contact cell may include the following steps:

[0321] 1. The raw silicon wafer is polished and cleaned on both sides. A flat pyramid base structure is formed on the backlight side, and the one-dimensional size of the flat pyramid base structure is greater than or equal to 0.5 μm and less than or equal to 20 μm.

[0322] 2. Depositing a tunneling silicon oxide layer (for subsequent formation of a first passivation layer) and an undoped polysilicon layer (for subsequent formation of a first doped semiconductor layer) on one surface of a clean silicon wafer. The thickness of the tunneling silicon oxide layer is greater than or equal to 1 nm and less than or equal to 3 nm. The thickness of the undoped polysilicon layer is greater than or equal to 100 nm and less than or equal to 400 nm, and its width along the arrangement direction of the first and second regions is greater than or equal to 200 μm and less than or equal to 700 μm.

[0323] 3. As shown in FIG13 , the undoped polysilicon layer is doped and crystallized by diffusion or annealing, so that the undoped polysilicon layer is transformed into a doped polysilicon layer. The doping concentration of the doped polysilicon layer is greater than or equal to 5E18 / cm 3 , and less than or equal to 5E20 / cm 3 Its crystallization rate is greater than or equal to 83% and less than or equal to 100%. After the crystallization process, the surface of the doped polysilicon layer is covered with a layer of oxidation byproducts (for the subsequent formation of the third dielectric layer), the thickness of which is greater than or equal to 15nm and less than or equal to 80nm. At this time, the porosity of the tunneling silicon oxide layer is 1:1500, and the doping concentration gradient of the tunneling silicon oxide layer is in the range of 1E15 / cm 3 and 5E20 / cm 3 between.

[0324] 4. As shown in FIG14 , portions of the tunneling silicon oxide layer and the doped polysilicon layer corresponding to the spacing region 14 and the second region 13 are removed using any patterning method (e.g., laser debonding, slurry printing with etching properties, or slurry printing with protective properties). The remaining portion of the tunneling silicon oxide layer in the first region 12 forms a first passivation layer 29, and the remaining portion of the doped polysilicon layer in the first region 12 forms a first doped semiconductor layer 15. Furthermore, a flattened pyramid base structure is formed on the surfaces of the spacing region 14 and the second region 13, with a one-dimensional dimension greater than or equal to 10 μm and less than or equal to 50 μm.

[0325] 5. As shown in Figure 16, a tunneling oxide layer (for the subsequent formation of a second passivation layer and a first dielectric layer) and an undoped polysilicon layer (for the subsequent formation of a second doped semiconductor layer and a second dielectric layer) are deposited entirely on the side of the silicon wafer where the first doped semiconductor layer 15 has been formed. The width of the undoped polysilicon layer covering the side of the first doped semiconductor layer 15 near the spacer region 14 is greater than or equal to 80 nm and less than or equal to 300 nm. The thickness of the tunneling oxide layer is greater than or equal to 1 nm and less than or equal to 3 nm, and the thickness of the undoped polysilicon layer is greater than or equal to 80 nm and less than or equal to 300 nm.

[0326] 6. As shown in FIG17 , a non-limited doping method (such as ion implantation, printing doping paste, laser doping, or high-temperature annealing) is used to locally dope the portion of the undoped polysilicon layer corresponding to the second region 13, and crystallize the portion at the same time. After the above treatment, the portion of the polysilicon layer corresponding to the local doping forms a second doped semiconductor layer 16, and the portion of the tunneling oxide layer located between the second doped semiconductor layer 16 and the silicon wafer forms a second passivation layer 30. The crystallization rate of the second doped semiconductor layer 16 is greater than or equal to 83% and less than or equal to 100%. In addition, the second doped semiconductor layer 16 includes a first doping portion 23 and a third doping portion 26, and the width of the third doping portion 26 is approximately between 10 nm and 2000 nm. The doping concentration of the impurities in the third doping portion 26 gradually decreases in the direction close to the second dielectric layer 18, and the gradient range is between 1E15 / cm 3 to 5E21 / cm 3 . The width ratio of the third doping portion 26 to the first doping region is between 1:20000 and 2:700. The porosity of the tunneling oxide layer is 1:1000 (i.e., there are 1000 pores per square millimeter). After local doping, the porosity of the tunneling oxide layer corresponding to the second region 13 can be the same as or different from the porosity of the portion of the tunneling oxide layer corresponding to the spacing region 14. In addition, during crystallization, the entire surface is covered with a layer of oxidation byproducts, the thickness of which is greater than or equal to 30 nm and less than or equal to 100 nm.

[0327] 7. Using any patterning method (such as laser film opening or slurry printing with corrosion properties) to remove the third dielectric layer located on top of the first doped semiconductor layer.

[0328] 8. Perform anti-reflection velvet processing on the light-facing surface of the silicon wafer. Also, as shown in FIG20 , remove the tunneling oxide layer and the undoped polysilicon layer on top of the first doped semiconductor layer.

[0329] 9. A surface passivation layer is formed on both the light-facing side and the backlight side of the silicon wafer.

[0330] 10. As shown in Figure 3, metal electrodes, namely, first electrodes 27 and second electrodes 28, are printed on top of the first doped semiconductor layer 15 and the second doped semiconductor layer 16. The distance between the first electrode 27 and the second electrode 28 is 200 μm to 700 μm.

[0331] Example 2

[0332] The method for manufacturing a back contact cell may include the following steps:

[0333] 1. The raw silicon wafer is polished and cleaned on both sides. A flat pyramid base structure is formed on the backlight side, and the one-dimensional size of the flat pyramid base structure is greater than or equal to 0.5 μm and less than or equal to 20 μm.

[0334] 2. Deposit a tunneling silicon oxide layer (for the subsequent formation of a first passivation layer) and an undoped polysilicon layer (for the subsequent formation of a first doped semiconductor layer) on one surface of a clean silicon wafer. The undoped polysilicon layer has a thickness of greater than or equal to 100 nm and less than or equal to 400 nm, and a width along the arrangement direction of the first and second regions of the silicon wafer of greater than or equal to 200 μm and less than or equal to 700 μm. The tunneling silicon oxide layer has a thickness of greater than or equal to 1 nm and less than or equal to 3 nm.

[0335] 3. As shown in FIG13 , the undoped polysilicon layer is doped by diffusion or annealing, and crystallized at the same time. The doping concentration of the doped polysilicon layer is greater than or equal to 5E18 / cm 3 , and less than or equal to 5E20 / cm 3 Its crystallization rate is greater than or equal to 83% and less than or equal to 100%. After the crystallization process, the surface of the doped polysilicon layer is covered with a layer of oxidation byproducts (for the subsequent formation of the third dielectric layer), the thickness of which is greater than or equal to 15nm and less than or equal to 80nm. At this time, the porosity of the tunneling silicon oxide layer is 1:1500, and the doping concentration gradient of the tunneling silicon oxide layer is in the range of 1E15 / cm 3 and 5E20 / cm 3 between.

[0336] 4. As shown in FIG14 , portions of the tunneling silicon oxide layer and the doped polysilicon layer corresponding to the spacing region 14 and the second region 13 are removed using any patterning method (e.g., laser debonding, slurry printing with etching properties, or slurry printing with protective properties). The remaining portion of the tunneling silicon oxide layer in the first region 12 forms a first passivation layer 29, and the remaining portion of the doped polysilicon layer in the first region 12 forms a first doped semiconductor layer 15. Furthermore, a flattened pyramid base structure is formed on the surfaces of the spacing region 14 and the second region 13, with a one-dimensional dimension greater than or equal to 10 μm and less than or equal to 50 μm.

[0337] 5. As shown in Figure 16, a tunneling oxide layer (for the subsequent formation of a second passivation layer and a first dielectric layer) and an undoped polysilicon layer (for the subsequent formation of a second doped semiconductor layer and a second dielectric layer) are deposited entirely on the side of the silicon wafer where the first doped semiconductor layer 15 has been formed. The width of the undoped polysilicon layer covering the side of the first doped semiconductor layer 15 near the spacer region 14 is greater than or equal to 80 nm and less than or equal to 300 nm. The thickness of the tunneling oxide layer is greater than or equal to 1 nm and less than or equal to 3 nm, and the thickness of the undoped polysilicon layer is greater than or equal to 80 nm and less than or equal to 300 nm.

[0338] 6. As shown in FIG17 , the portion of the undoped polysilicon layer corresponding to the second region 13 is locally doped and crystallized using any of a variety of doping methods (e.g., ion implantation, laser doping using printed doping paste, or high-temperature annealing). After the above treatment, the portion of the polysilicon layer corresponding to the locally doped portion forms a second doped semiconductor layer 16, and the portion of the polysilicon layer corresponding to the first region and a portion of the spacer region forms a second dielectric layer 18. The portion of the tunneling oxide layer between the second doped semiconductor layer 16 and the silicon wafer forms a second passivation layer 30, and the portion of the tunneling oxide layer corresponding to the spacer region and the first region forms a first dielectric layer 17. The crystallization rate of the second doped semiconductor layer 16 is greater than or equal to 83% and less than or equal to 100%. Furthermore, the second doped semiconductor layer 16 includes a first doped portion 23 and a third doped portion 26, the width of which is approximately between 10 nm and 2000 nm. The doping concentration of impurities in the third doped portion 26 gradually decreases as it approaches the second dielectric layer 18, with the gradient ranging from 1E15 / cm2 to 1E15 / cm3. 3 to 5E21 / cm 3 . The width ratio of the third doping portion 26 to the first doping region is between 1:20000 and 2:700. The porosity of the tunneling oxide layer is 1:1000 (i.e., there are 1000 pores per square millimeter). After local doping, the porosity of the tunneling oxide layer corresponding to the second region 13 can be the same as or different from the porosity of the portion of the tunneling oxide layer corresponding to the spacing region 14. In addition, during crystallization, the entire surface is covered with a layer of oxidation byproducts, the thickness of which is greater than or equal to 30 nm and less than or equal to 100 nm.

[0339] 7. As shown in FIG28 , the third dielectric layer 25, tunneling oxide layer, and undoped polysilicon layer on top of the first doped semiconductor layer 15 are partially opened using an unrestricted patterning method (e.g., laser film opening or etch-resistant slurry printing), leaving the third dielectric layer 25. The width of the opening is between 20 μm and 120 μm. The width of the third dielectric layer 25 on at least one side of the opening is greater than or equal to 40 μm and less than or equal to 220 μm, and the width of the third dielectric layer 25 on both sides of the opening is equal. In this case, the manufacturing method provided in Example 2 does not remove the third dielectric layer 25, tunneling oxide layer, and undoped polysilicon layer on top of the first doped semiconductor layer 15. Instead, the third dielectric layer 25, tunneling oxide layer, and undoped polysilicon layer on top of the first doped semiconductor layer 15 are partially opened to form a through-window. This improves the throughput of the patterning process in this step without affecting the operating performance of the back-contact cell, thereby enhancing the manufacturing efficiency of the back-contact cell.

[0340] 8. The light-facing surface of the silicon wafer is subjected to anti-reflective velvet production, and the exposed oxidation byproduct layer is removed during the velvet production.

[0341] 9. A surface passivation layer is formed on both the light-facing side and the backlight side of the silicon wafer.

[0342] 10. As shown in Figure 35, metal electrodes, namely, first electrodes 27 and second electrodes 28, are printed on top of the first doped semiconductor layer 15 and the second doped semiconductor layer 16. The distance between the first electrode 27 and the second electrode 28 is 200 μm to 700 μm.

[0343] Example 3

[0344] The method for manufacturing a back contact cell may include the following steps:

[0345] 1. The raw silicon wafer is polished and cleaned on both sides. A flat pyramid base structure is formed on the backlight side, and the one-dimensional size of the flat pyramid base structure is greater than or equal to 0.5 μm and less than or equal to 20 μm.

[0346] 2. Deposit a tunneling silicon oxide layer (for the subsequent formation of a first passivation layer) and an undoped polysilicon layer (for the subsequent formation of a first doped semiconductor layer) on one surface of a clean silicon wafer. The undoped polysilicon layer has a thickness of greater than or equal to 100 nm and less than or equal to 400 nm, and a width along the arrangement direction of the first and second regions of the silicon wafer of greater than or equal to 200 μm and less than or equal to 700 μm. The tunneling silicon oxide layer has a thickness of greater than or equal to 1 nm and less than or equal to 3 nm.

[0347] 3. As shown in FIG13 , the undoped polysilicon layer is doped by diffusion or annealing, and crystallized at the same time. The doping concentration of the doped polysilicon layer is greater than or equal to 5E18 / cm3 , and less than or equal to 5E20 / cm 3 Its crystallization rate is greater than or equal to 83% and less than or equal to 100%. After the crystallization process, the surface of the doped polysilicon layer is covered with a layer of oxidation byproducts (for the subsequent formation of the third dielectric layer), the thickness of which is greater than or equal to 15nm and less than or equal to 80nm. At this time, the porosity of the tunneling silicon oxide layer is 1:1500, and the doping concentration gradient of the tunneling silicon oxide layer is in the range of 1E15 / cm 3 and 5E20 / cm 3 between.

[0348] 4. As shown in FIG14 , portions of the tunneling silicon oxide layer and the doped polysilicon layer corresponding to the spacing region 14 and the second region 13 are removed using any patterning method (e.g., laser debonding, slurry printing with etching properties, or slurry printing with protective properties). The remaining portion of the tunneling silicon oxide layer in the first region 12 forms a first passivation layer 29, and the remaining portion of the doped polysilicon layer in the first region 12 forms a first doped semiconductor layer 15. Furthermore, a flattened pyramid base structure is formed on the surfaces of the spacing region 14 and the second region 13, with a one-dimensional dimension greater than or equal to 10 μm and less than or equal to 50 μm.

[0349] 5. As shown in Figure 16, a tunneling oxide layer (for the subsequent formation of a second passivation layer and a first dielectric layer) and an undoped polysilicon layer (for the subsequent formation of a second doped semiconductor layer and a second dielectric layer) are deposited entirely on the side of the silicon wafer where the first doped semiconductor layer 15 has been formed. The width of the undoped polysilicon layer covering the side of the first doped semiconductor layer 15 near the spacer region 14 is greater than or equal to 80 nm and less than or equal to 300 nm. The thickness of the tunneling oxide layer is greater than or equal to 1 nm and less than or equal to 3 nm, and the thickness of the undoped polysilicon layer is greater than or equal to 80 nm and less than or equal to 300 nm.

[0350] 6. As shown in Figures 24 and 25, the undoped polysilicon layer is lightly doped using any doping method (such as ion implantation, printing doping paste, laser doping, or high-temperature annealing). After annealing, the doping depth is greater than or equal to 40nm and less than or equal to 150nm, and the doping concentration is greater than or equal to 5E18 / cm 3 , and less than or equal to 1E20 / cm 3. The thickness of the undoped polysilicon below the lightly doped part is between 40 nm and 150 nm. Then, the part of the polysilicon layer corresponding to the second region 13 is locally heavily doped and crystallized at the same time. After the above treatment, the part of the polysilicon layer corresponding to the locally heavily doped part forms a second doped semiconductor layer 16, and the part of the polysilicon layer corresponding to the first region and part of the spacing region forms a second dielectric layer 18. The part of the tunneling oxide layer located between the second doped semiconductor layer 16 and the silicon wafer forms a second passivation layer 30, and the part of the tunneling oxide layer corresponding to the spacing region and the first region forms a first dielectric layer 17. The crystallization rate of the second doped semiconductor layer 16 is greater than or equal to 83% and less than or equal to 100%. In addition, the second doped semiconductor layer 16 includes a first doping part 23, a second doping part 24 and a third doping part 26, and the width of the third doping part 26 is approximately between 10 nm and 2000 nm. The doping concentration of impurities in the third doping part 26 gradually decreases in the direction close to the second dielectric layer 18, and the gradient range is between 1E15 / cm 3 to 5E21 / cm 3 . The width ratio of the third doping portion 26 to the first doping region is between 1:20000 and 2:700. The porosity of the tunneling oxide layer is 1:1000 (i.e., there are 1000 pores per square millimeter). After local doping, the porosity of the tunneling oxide layer corresponding to the second region 13 can be the same as or different from the porosity of the portion of the tunneling oxide layer corresponding to the spacing region 14. In addition, during crystallization, the entire surface is covered with a layer of oxidation byproducts, the thickness of which is greater than or equal to 30 nm and less than or equal to 100 nm.

[0351] 7. Partially open the third dielectric layer, tunnel oxide layer, and undoped polysilicon layer on top of the first doped semiconductor layer using any patterning method (e.g., laser opening or etch-resistant slurry printing), retaining the third dielectric layer. The width of the opening is between 20 μm and 120 μm. The width of the third dielectric layer on at least one side of the opening is greater than or equal to 40 μm and less than or equal to 220 μm, and the width of the third dielectric layer on both sides of the opening is equal.

[0352] 8. The light-facing surface of the silicon wafer is subjected to anti-reflective velvet production, and the exposed oxidation byproduct layer is removed during the velvet production.

[0353] 9. As shown in FIG30 , a surface passivation layer 31 is formed simultaneously on the light-facing side and the backlight-facing side of the silicon wafer.

[0354] 10. As shown in Figure 9, metal electrodes, namely, first electrodes 27 and second electrodes 28, are printed on top of the first doped semiconductor layer 15 and the second doped semiconductor layer 16. The distance between the first electrode 27 and the second electrode 28 is 200 μm to 700 μm.

[0355] It should be noted that the difference between Example 2 and Example 1 is that, as shown in FIG20 , after selectively doping the polysilicon layer used to form the second doped semiconductor layer, Example 1 selectively removes the third dielectric layer and portions of the tunneling oxide layer and the first region corresponding to the polysilicon layer. However, as shown in FIG22 , after selectively doping the polysilicon layer used to form the second doped semiconductor layer, Example 2 retains portions of the third dielectric layer and portions of the tunneling oxide layer and the first region corresponding to the polysilicon layer, and forms a first conductive window that penetrates the third dielectric layer and portions of the tunneling oxide layer and the polysilicon layer corresponding to the first region.

[0356] The difference between Example 3 and Example 2 is that, after forming the polycrystalline silicon layer for forming the second doped semiconductor layer and before selectively doping the portion of the polycrystalline silicon layer corresponding to the second region, the manufacturing method corresponding to Example 2 does not perform a light doping treatment on the side of the polycrystalline silicon layer facing away from the semiconductor substrate. However, after forming the polycrystalline silicon layer for forming the second doped semiconductor layer and before selectively doping the portion of the polycrystalline silicon layer corresponding to the second region, the manufacturing method corresponding to Example 3 requires performing a light doping treatment on the side of the polycrystalline silicon layer facing away from the semiconductor substrate.

[0357] While the above description does not provide detailed technical details regarding the patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0358] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, wherein a backlight surface of the semiconductor substrate has first regions and second regions that are alternately spaced, and a spacing region between each first region and the second region adjacent to the first region; A first doped semiconductor layer is formed on a first region of the backlight surface; a second doped semiconductor layer formed at least on the second region of the backlight surface; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types; A first dielectric layer and a second dielectric layer are formed at least on a spaced region of the backlight surface; at least a portion of the first dielectric layer and at least a portion of the second dielectric layer are stacked and arranged between the first doped semiconductor layer and the second doped semiconductor layer along an arrangement direction of the first region and the second region, at least a portion of the first dielectric layer is in contact with the first doped semiconductor layer, and at least a portion of the second dielectric layer is in contact with the second doped semiconductor layer; The first dielectric layer and the second dielectric layer are made of different materials; the structure formed by the first dielectric layer and the second dielectric layer is used to electrically isolate at least a portion of the first doped semiconductor layer from at least a portion of the second doped semiconductor layer.

2. The back contact battery according to claim 1, characterized in that The material of the first dielectric layer contains oxygen; and / or, The material of the first dielectric layer contains silicon.

3. The back contact battery according to claim 2, characterized in that The first dielectric layer includes a tunneling oxide layer; and / or, The material of the first dielectric layer includes at least one of silicon dioxide, silicon oxynitride, hafnium oxide, aluminum oxide and zinc oxide; and / or, The second dielectric layer includes a crystalline silicon layer; the doping type of the crystalline silicon layer includes at least one of an intrinsic type and a lightly doped type.

4. The back contact battery according to claim 3, characterized in that In the case where the doping type of the crystalline silicon layer includes a lightly doped type, the doping concentration of the impurities in the crystalline silicon layer is greater than or equal to 1E15 / cm 3 , and less than or equal to 5E21 / cm 3 and / or, In the case where the doping types of the crystalline silicon layer include intrinsic type and lightly doped type, a portion of the crystalline silicon layer with an intrinsic doping type and a portion of the crystalline silicon layer with a lightly doped doping type are distributed along the direction of the second dielectric layer close to the second doped semiconductor layer, and the lightly doped portion is in contact with the second doped semiconductor layer.

5. The back contact battery according to claim 1 or 2, characterized in that The crystal phase of the first dielectric layer is amorphous, and the crystal phase of the second dielectric layer includes at least one of microcrystal, nanocrystal, polycrystal or single crystal.

6. The back contact battery according to claim 1, characterized in that Along the arrangement direction of the first region and the second region, the width of the portion of the first dielectric layer corresponding to the spacing region is greater than or equal to 1 nm and less than or equal to 3 nm; and / or, Along the arrangement direction of the first region and the second region, a width of a portion of the second dielectric layer corresponding to the spacing region is greater than or equal to 80 nm and less than or equal to 300 nm.

7. The back contact battery according to claim 1, characterized in that The first dielectric layer includes a first dielectric portion and a second dielectric portion that are continuous as a whole; along the arrangement direction of the first region and the second region, the first dielectric portion is located between the second dielectric layer and the first doped semiconductor layer; and the second dielectric portion is located between the second dielectric layer and the semiconductor substrate.

8. The back contact cell according to claim 1 or 7, characterized in that The first dielectric layer includes an integral and continuous first dielectric portion and a third dielectric portion; along the arrangement direction of the first region and the second region, the first dielectric portion is located between the second dielectric layer and the first doped semiconductor layer; the third dielectric portion is located on a side of the first doped semiconductor layer facing away from the semiconductor substrate, and a first conductive window is provided through the third dielectric portion.

9. The back contact battery according to claim 8, characterized in that The second dielectric layer extends onto the third dielectric portion included in the first dielectric layer, and the first conductive window penetrates a portion of the second dielectric layer corresponding to the first region.

10. The back contact battery according to claim 1 or 7, characterized in that The second doped semiconductor layer includes a first doped portion and a second doped portion that are electrically connected; the first doped portion is located on the second region; the second doped portion is located on a side of the second dielectric layer away from the first dielectric layer, and the doping concentration of impurities in the second doped portion is less than the doping concentration of impurities in the first doped portion.

11. The back contact battery according to claim 8, characterized in that The second doped semiconductor layer includes a first doped portion and a second doped portion that are electrically connected; the first doped portion is located on the second region; the second doped portion is arranged in the spacing region and extends to the first region, a portion of the second doped portion corresponding to the spacing region is located on a side of the second dielectric layer facing away from the first dielectric layer, and a portion of the second doped portion corresponding to the first region is located above the third dielectric portion facing away from the first doped semiconductor layer; the doping concentration of impurities in the second doped portion is lower than the doping concentration of impurities in the first doped portion.

12. The back contact battery according to claim 11, characterized in that The second dielectric layer extends onto the third dielectric portion included in the first dielectric layer, and the portion of the second doped portion corresponding to the first region is located on the portion of the second dielectric layer corresponding to the first region; the first conductive window penetrates the second dielectric layer and the portion of the second doped portion corresponding to the first region; and / or, The back contact cell further includes a third dielectric layer located between the third dielectric portion and the first doped semiconductor layer; the first conductive window penetrates the third dielectric layer.

13. The back contact cell according to claim 10 or 11, characterized in that The thickness of the second doped portion is greater than or equal to 40 nm and less than or equal to 150 nm; and / or, The doping concentration of the impurities in the second doping portion is greater than 0 and less than or equal to 1E20 cm -3 and / or, Along the arrangement direction of the first region and the second region, a width of a portion of the second dielectric layer corresponding to the spacing region is greater than or equal to 40 nm and less than or equal to 150 nm.

14. The back contact battery according to claim 8 or 9, characterized in that The back contact cell further includes a third dielectric layer located between the third dielectric portion and the first doped semiconductor layer; the first conductive window penetrates the third dielectric layer.

15. The back contact battery according to claim 14, characterized in that Along the arrangement direction of the first region and the second region, the widths of portions of the third dielectric layer located on both sides of the first conductive window are equal; and / or, Along the arrangement direction of the first region and the second region, a width of a portion of the third dielectric layer located on at least one side of the first conductive window is greater than or equal to 40 μm and less than or equal to 220 μm.

16. The back contact battery according to claim 14, characterized in that The material of the first doped semiconductor layer contains silicon, and the third dielectric layer includes a doped silicon glass layer.

17. The back contact battery according to claim 1, characterized in that The second doped semiconductor layer includes a first doped portion and a third doped portion that are electrically connected; the first doped portion is located on the second region, and the third doped portion is located on the spacing region; the doping concentration of impurities in the third doped portion is lower than the doping concentration of impurities in the first doped portion.

18. The back contact cell according to claim 17, characterized in that The doping concentration of the impurities in the third doping portion is greater than or equal to 1E15 cm -3 , and less than or equal to 5E21cm -3 and / or, Along the direction from the second region to the first region, the doping concentration of impurities in the third doping portion gradually decreases.

19. The back contact cell according to claim 17, characterized in that Along an arrangement direction of the first region and the second region, a ratio of a width of the third doped portion to a width of the first doped portion is greater than or equal to 1:20,000 and less than or equal to 2:

700.

20. The back contact cell according to claim 17, characterized in that The back contact battery further includes a first electrode and a second electrode; the first electrode is formed on the first doped semiconductor layer and is in ohmic contact with the first doped semiconductor layer; the second electrode is formed on the first doped portion and is in ohmic contact with the first doped portion; Along the arrangement direction of the first region and the second region, a distance between a geometric center of a portion of the second electrode adjacent to the third doped portion and the third doped portion is greater than or equal to 110 μm and less than or equal to 380 μm.

21. The back contact cell according to claim 1, 7 or 17, characterized in that A groove structure is provided on one side of the backlight surface of the semiconductor substrate; the second region and the spacing region are both located in the groove structure.

22. The back contact cell according to claim 21, characterized in that The portion of the bottom surface of the groove structure corresponding to the spacing region is flush with the portion of the bottom surface of the groove structure corresponding to the second region, or, along the direction from the light-facing surface to the backlight surface of the semiconductor substrate, the portion of the bottom surface of the groove structure corresponding to the spacing region is lower than the portion of the bottom surface of the groove structure corresponding to the second region; and / or The depth of the groove structure is greater than or equal to 0.3 μm and less than or equal to 3 μm.

23. The back contact battery according to claim 1, characterized in that The back contact cell further comprises a first passivation layer located between the first doped semiconductor layer and the semiconductor substrate; and / or, The back-contact cell further includes a second passivation layer located between the second doped semiconductor layer and the semiconductor substrate.

24. The back contact cell according to claim 23, characterized in that In the case where the back contact cell further comprises the second passivation layer, The first dielectric layer and the second passivation layer are integrally continuous; and / or the porosity of the first dielectric layer is smaller than the porosity of the second passivation layer.

25. The back contact cell according to claim 1, 3 or 4, characterized in that The second dielectric layer and the second doped semiconductor layer are integrally continuous.

26. The back contact cell according to claim 1, characterized in that The back contact battery further includes a surface passivation layer; the surface passivation layer covers the second doped semiconductor layer and extends to the top of the first doped semiconductor layer along the arrangement direction of the first region and the second region; A first conductive window is provided through the portion of the surface passivation layer corresponding to the first area, and the bottom of the first conductive window exposes at least a portion of the first doped semiconductor layer; a second conductive window is provided through the portion of the surface passivation layer corresponding to the second area, and the bottom of the second conductive window exposes at least a portion of the second doped semiconductor layer.

27. The back contact cell according to claim 1, characterized in that The back contact cell further includes a first electrode and a second electrode; the first electrode is formed on the first doped semiconductor layer and is in ohmic contact with the first doped semiconductor layer; The second electrode is formed on the second doped semiconductor layer and is in ohmic contact with the second doped semiconductor layer; wherein, The first electrode and the second electrode each include a plurality of collecting electrodes and a plurality of bus electrodes; the collecting electrodes included in the first electrode and the collecting electrodes included in the second electrode each extend along a first direction and are alternately spaced along a second direction; the first direction is different from the second direction; the bus electrodes included in the first electrode and the bus electrodes included in the second electrode each extend along the second direction and are alternately spaced along the first direction; each bus electrode is electrically connected to a collecting electrode of the same polarity as itself and is insulated from a collecting electrode of an opposite polarity; The width of the portion of the structure formed by the first dielectric layer and the second dielectric layer between two adjacent collector electrodes with opposite polarities along the width direction of the spacing region is substantially the same as the thickness of the second doped semiconductor layer; and / or, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between two adjacent collector electrodes with opposite polarities along the extension direction of the spacing region is greater than or equal to 300 μm and less than or equal to 3000 μm; and / or, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between the adjacent collector electrodes with opposite polarities and the busbar is substantially the same as the thickness of the second doped semiconductor layer; and / or, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between the adjacent collector electrodes with opposite polarities and the busbar is substantially the same as the thickness of the second doped semiconductor layer; and / or The width of the portion between the electrodes along the width direction of the spacing region is approximately the same as the thickness of the second doped semiconductor layer; and / or, the length of the portion of the structure formed by the first dielectric layer and the second dielectric layer between the adjacent collecting electrodes and bus electrodes with opposite polarity along the extension direction of the spacing region is greater than or equal to 200 μm and less than or equal to 700 μm; and / or, the spacing between two adjacent collecting electrodes with opposite polarity is greater than or equal to 200 μm and less than or equal to 700 μm; and / or, the width of the collecting electrode is greater than or equal to 15 μm and less than or equal to 60 μm.

28. The back contact cell according to claim 1, characterized in that Portions of the first dielectric layer and the second dielectric layer corresponding to the portions between the first doped semiconductor layer and the second doped semiconductor layer are located on all regions of the spacing region along its own extension direction, and are used to electrically isolate the first doped semiconductor layer from the second doped semiconductor layer; or, The first dielectric layer and the second dielectric layer have a discontinuity in a portion corresponding to the first doped semiconductor layer and the second doped semiconductor layer along an extension direction of the spacing region; the back contact cell further includes a conductive structure located at least within the discontinuity; The conductive structure has a conductivity type opposite to that of one of the first doped semiconductor layer and the second doped semiconductor layer, and only a portion of the first doped semiconductor layer and only a portion of the second doped semiconductor layer are electrically connected to the conductive structure, respectively.

29. The back contact cell according to claim 28, characterized in that In the case where the back contact cell further comprises the conductive structure, at least a portion of the conductive structure is integrally continuous with the second doped semiconductor layer; and / or, In the case where the back-contact battery further includes the conductive structure, the structure formed by the first dielectric layer and the second dielectric layer is integrally continuous with the conductive structure.

30. The back contact cell according to claim 1, characterized in that A non-pyramid structure is formed on the surface of the first region, and a base of the non-pyramid structure on the surface of the first region has a one-dimensional size greater than or equal to 0.5 μm and less than or equal to 20 μm; the base of the non-pyramid structure is closer to the semiconductor substrate than the top thereof; and / or, A non-pyramid structure is formed on the surface of the second region, and a base of the non-pyramid structure on the surface of the second region has a one-dimensional size greater than or equal to 10 μm and less than or equal to 50 μm; the base of the non-pyramid structure is closer to the semiconductor substrate than the top thereof; and / or, A non-pyramid structure is formed on the surface of the spacing region, and the base of the non-pyramid structure on the surface of the spacing region has a one-dimensional size greater than or equal to 10 μm and less than or equal to 50 μm; the base of the non-pyramid structure is close to the semiconductor substrate relative to its top.

31. A method for manufacturing a back contact battery, characterized in that: include: providing a semiconductor substrate; The backlight surface of the semiconductor substrate comprises first areas and second areas that are alternately spaced and an interval area between each first area and the second area adjacent to the first area; forming a first doped semiconductor layer on the first region of the backlight surface; forming a second doped semiconductor layer at least on the second region of the backlight surface; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types; forming a first dielectric layer and a second dielectric layer at least on the spacing area of ​​the backlight surface; At least a portion of the first dielectric layer and at least a portion of the second dielectric layer are stacked and arranged between the first doped semiconductor layer and the second doped semiconductor layer along an arrangement direction of the first region and the second region; at least a portion of the first dielectric layer is in contact with the first doped semiconductor layer, and at least a portion of the second dielectric layer is in contact with the second doped semiconductor layer; the first dielectric layer and the second dielectric layer are made of different materials.

32. The method for manufacturing a back contact battery according to claim 31, wherein: The forming of a first doped semiconductor layer on the first region of the backlight surface comprises: forming a first doped semiconductor layer disposed entirely on the backlight surface, and a third dielectric layer located on a portion of the first doped semiconductor layer corresponding to the first region; or forming a first doped semiconductor layer and a third dielectric layer disposed entirely on the backlight surface, and heat-treating a portion of the third dielectric layer corresponding to the second region and the spacing region using a laser irradiation process; after the heat treatment, forming a mask on the portion of the third dielectric layer corresponding to the first region; Under the masking action of the portion of the third dielectric layer corresponding to the first region, the portion of the first doped semiconductor layer corresponding to the second region and the spacer region is removed.

33. The method for manufacturing a back contact battery according to claim 31, wherein: After providing a semiconductor substrate and before forming a second doped semiconductor layer at least on the second region of the backlight surface, the method for manufacturing a back contact cell includes: A first passivation layer and the first doped semiconductor layer located on a side of the first passivation layer facing away from the semiconductor substrate are formed on the first region.

34. The method for manufacturing a back contact battery according to claim 32, wherein: After forming the first doped semiconductor layer on the first area of ​​the backlight surface and before forming the second doped semiconductor layer on the second area of ​​the backlight surface, the manufacturing method of the back contact battery further includes: forming a second passivation layer at least on the second area of ​​the backlight surface.

35. The method for manufacturing a back contact battery according to claim 34, characterized in that: Forming the second doped semiconductor layer, the second passivation layer, the first dielectric layer, and the second dielectric layer includes: forming a passivation material layer and an intrinsic semiconductor layer stacked and covering the first doped semiconductor layer, the spacer region, and the second region in sequence along a thickness direction of the semiconductor substrate; A selective doping treatment is performed on a portion of the intrinsic semiconductor layer corresponding to the second region; after the selective doping treatment, at least a portion of the intrinsic semiconductor layer corresponding to the second region forms the second doped semiconductor layer, at least a portion of the intrinsic semiconductor layer corresponding to a portion of the spacing region forms the second dielectric layer, a portion of the passivation material layer located between the second doped semiconductor layer and the semiconductor substrate forms the second passivation layer, and at least a portion of the passivation material layer corresponding to a portion of the spacing region forms the first dielectric layer.

36. The method for manufacturing a back contact battery according to claim 35, characterized in that: After the selective doping treatment is performed on the portion of the intrinsic semiconductor layer corresponding to the second region, the method for manufacturing the back contact cell includes: retaining a portion of the passivation material layer corresponding to the first region and a portion of the intrinsic semiconductor layer corresponding to the first region; A first conductive window is formed above the first region and penetrates the third dielectric layer, the passivation material layer, and the intrinsic semiconductor layer.

37. The method for manufacturing a back contact battery according to claim 35, wherein: After the selective doping treatment is performed on the portion of the intrinsic semiconductor layer corresponding to the second region, the method for manufacturing the back contact cell includes: selectively removing a portion of the intrinsic semiconductor layer corresponding to the first region, and retaining a portion of the passivation material layer corresponding to the first region; A first conductive window is formed above the first region and penetrates the third dielectric layer and the passivation material layer.

38. The method for manufacturing a back contact battery according to claim 35, wherein: After sequentially forming a passivation material layer and an intrinsic semiconductor layer stacked and covering the first doped semiconductor layer, the spacer region, and the second region along the thickness direction of the semiconductor substrate, and before performing the selective doping treatment on the portion of the intrinsic semiconductor layer corresponding to the second region, the method for manufacturing a back contact battery further includes: A light doping process is performed on a side of the intrinsic semiconductor layer facing away from the semiconductor substrate.

39. The method for manufacturing a back contact battery according to claim 38, wherein: After the selective doping treatment is performed on the portion of the intrinsic semiconductor layer corresponding to the second region, the method for manufacturing the back contact cell includes: retaining a portion of the passivation material layer corresponding to the first region and a portion of the intrinsic semiconductor layer corresponding to the first region after the lightly doped layer; A first conductive window is formed above the first region, penetrating the third dielectric layer, the passivation material layer, and the lightly doped intrinsic semiconductor layer.

40. The method for manufacturing a back contact battery according to claim 35 or 38, characterized in that: After the selective doping treatment is performed on the portion of the intrinsic semiconductor layer corresponding to the second region, the method for manufacturing the back contact battery further includes: selectively removing portions of the intrinsic semiconductor layer and the passivation material layer corresponding to the first region; A portion of the third dielectric layer corresponding to the first region is removed.

41. The method for manufacturing a back contact battery according to claim 31, wherein: After forming the first doped semiconductor layer on the first area of ​​the backlight surface and before forming the second doped semiconductor layer at least on the second area of ​​the backlight surface, the method for manufacturing a back-contact cell further includes: Selectively etching the backlight side of the semiconductor substrate to form a groove structure on the backlight side; the second region and the spacer region are both located in the groove structure.

42. The method for manufacturing a back contact battery according to claim 31, wherein: After forming the first dielectric layer and the second dielectric layer at least on the spaced region of the backlight surface, the method for manufacturing the back contact cell further comprises: forming a surface passivation layer on the backlight side; the surface passivation layer covers the second doped semiconductor layer and extends to the top of the first doped semiconductor layer along the arrangement direction of the first region and the second region; A first conductive window is opened through the portion of the surface passivation layer corresponding to the first region, and a second conductive window is opened through the portion of the surface passivation layer corresponding to the second region; the bottom of the first conductive window exposes at least a portion of the first doped semiconductor layer; the bottom of the second conductive window exposes at least a portion of the second doped semiconductor layer.

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