Back-contact battery and manufacturing method therefor

Abstract

The present invention relates to the technical field of photovoltaics. Disclosed are a back-contact battery and a manufacturing method therefor, for use in improving the light utilization on the back surfaces of back-contact batteries, enhancing the photoelectric conversion efficiency and yield of the back-contact batteries. The back-contact battery comprises a silicon substrate, and first doped semiconductor layers and second doped semiconductor layers alternately distributed at intervals on the back surface of the silicon substrate. In the back surface of the silicon substrate, the region corresponding to the first doped semiconductor layers is a first region, the region corresponding to the second doped semiconductor layers is a second region, and the region between the first region and the second region adjacent thereto is a spacing region. The surface of the second region is recessed into the silicon substrate with respect to the surface of the first region. The surface of the spacing region is recessed into the silicon substrate with respect to the surface of the second region. The bottom surface of the spacing region, the first side surface of the spacing region close to the first region, and the second side surface of the spacing region close to the second region are all textured surfaces.

Description

Back contact battery and manufacturing method thereof Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a back-contact cell and a manufacturing method thereof. Background Art

[0002] A back-contact cell refers to a solar cell in which the light-facing side of the cell has no electrode, and both the positive and negative electrodes are arranged on the backlight side of the cell. This can reduce the shading of the electrode on the cell, increase the short-circuit current of the cell, and improve the energy conversion efficiency of the cell.

[0003] However, the light utilization rate on the backlight side of the existing back-contact cell is reduced, which is not conducive to improving the photoelectric conversion efficiency of the back-contact cell. In addition, since the doping regions with opposite conductivity types (i.e., n-region and p-region) of the back-contact cell are all located on the same side, the alignment requirements for each process stage are relatively high. Summary of the Invention

[0004] The object of the present invention is to provide a back-contact cell and a method for manufacturing the same, which are used to improve the light utilization rate on the backlight side of the back-contact cell, thereby improving the photoelectric conversion efficiency and yield of the back-contact cell.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a back-contact battery, which includes: a silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed on one side of the backlight surface of the silicon substrate. The conductivity types of the first doped semiconductor layer and the second doped semiconductor layer are opposite. In the backlight surface of the silicon substrate, the area corresponding to the first doped semiconductor layer is the first area, the area corresponding to the second doped semiconductor layer is the second area, and the area between the first area and the second area adjacent to itself is the spacing area. The surface of the second area is concave into the silicon substrate relative to the surface of the first area. The surface of the spacing area is concave into the silicon substrate relative to the surface of the second area. The bottom surface of the spacing area, the first side surface of the spacing area close to the first area, and the second side surface of the spacing area close to the second area are all velvet.

[0006] Using the above technical solution, in the back-contact cell provided by the present invention, first doped semiconductor layers and second doped semiconductor layers of opposite conductivity types are alternately spaced on the backlight side of the silicon substrate. Based on this, the spacing region on the backlight side of the silicon substrate can isolate the first doped semiconductor layer formed on the first region from the second doped semiconductor layer formed on the second region, reducing the carrier recombination rate at the lateral interface between the first doped semiconductor layer and the second doped semiconductor layer, thereby improving the photoelectric conversion efficiency of the back-contact cell. Secondly, the surface of the above-mentioned second region is recessed into the silicon substrate relative to the surface of the first region, and the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, indicating that in the actual manufacturing process, after forming a first doped semiconductor layer covering the entire backlight side, the portion of the first doped semiconductor layer located on the second region and the spacing region has been completely removed; and, after selective etching of the first doped semiconductor layer and deposition of the entire second doped semiconductor layer, the portion of the second doped semiconductor layer located on the first doped semiconductor layer and the spacing region has been completely removed, preventing leakage caused by residues remaining on the surface of the corresponding region after selective etching of the first doped semiconductor layer and / or the second doped semiconductor layer; at the same time, when the surface of the second region is recessed into the silicon substrate relative to the surface of the first region, it is also beneficial to at least partially stagger the first doped semiconductor layer and the second doped semiconductor layer, which are both located on the backlight side of the silicon substrate and have opposite conductivity types, along the thickness direction of the silicon substrate, further reducing the leakage risk on the backlight side and improving the electrical reliability of the back-contact battery.

[0007] In addition, in the back contact cell provided by the present invention, not only the bottom surface of the above-mentioned spacing area is a velvet surface, but also the first side surface of the spacing area close to the first area, and the second side surface of the spacing area close to the second area are both velvet surfaces. Compared with a plane, the velvet surface has an uneven surface feature, which makes it have a better light trapping effect, and can reduce the reflectivity of the bottom surface, the first side surface, and the second side surface of the spacing area. Moreover, a velvet structure is formed on each area of ​​the first side surface and the second side surface, that is, each area of ​​the first side surface and the second side surface has a high specific surface area and light trapping effect. In this case, compared with the first side surface and the second side surface of the existing back contact cell being a plane, the back contact cell provided by the present invention is conducive to allowing more light to be refracted from the above-mentioned first side surface and the second side surface into the silicon substrate and utilized by the silicon substrate, thereby helping to improve the photoelectric conversion efficiency of the back contact cell.

[0008] As a possible implementation solution, the first side surface and the second side surface are both inclined relative to the horizontal plane, so that the cross-sectional area of ​​the spacing region gradually increases from the light-facing surface to the backlight surface.

[0009] When the above technical solution is adopted, the cross-sectional area of ​​the spacing region close to the light-facing side is smaller than the cross-sectional area of ​​the spacing region close to the backlight side, which is beneficial to increase the distance between the first doped semiconductor layer and the second doped semiconductor layer of opposite conductivity type, reduce the risk of leakage on the backlight side of the back contact cell, and ensure that the back contact cell has high electrical reliability. In addition, compared with the first side surface and the second side surface being perpendicular to the horizontal plane, the first side surface and the second side surface being inclined relative to the horizontal plane can also increase the area ratio of the orthographic projection of the first side surface and the second side surface on the backlight side, which can further reduce the reflectivity on the backlight side, and further allow more light to enter the silicon substrate from the backlight side of the back contact cell under the light trapping effect of the first side surface and the second side surface, thereby improving the photoelectric conversion efficiency of the back contact cell.

[0010] As a possible implementation solution, the angles formed between the first side surface and the second side surface of the spacing area and the horizontal plane are greater than or equal to 52° and less than or equal to 58°.

[0011] When the above technical solution is adopted, the angles between the first side surface and the second side surface and the horizontal plane are respectively within the above range, which can prevent the effect of reducing the reflectivity on the backlight side through the first side surface and the second side surface from being not obvious due to the large angle, thereby ensuring that the backlight side of the back-contact battery has a higher light utilization rate; in addition, it can also prevent the depth of the surface of the spacing area relative to the surface of the second area concave into the silicon substrate from being smaller due to the small angle, thereby ensuring that after the entire deposited second doped semiconductor layer is selectively etched, its portion located on the spacing area and the first doped semiconductor layer is completely removed, thereby preventing leakage and ensuring that the back-contact battery has higher electrical reliability.

[0012] As a possible implementation solution, the morphology of the suede structure on the first side surface and the second side surface is different from the morphology of the suede structure on the bottom surface of the spacing area.

[0013] When the above technical solution is adopted, the bottom surface of the above-mentioned spacing region is roughly parallel to the horizontal plane; secondly, because the bottom surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, the first side surface of the spacing region close to the first region and the second side surface of the spacing region close to the second region are respectively arranged at an angle or perpendicular to the horizontal plane. It can be seen that the relative positional relationship between the bottom surface of the spacing region and the horizontal plane is different from the relative positional relationship between the first side surface and the second side surface and the horizontal plane, respectively. Therefore, the surface crystal orientation of the bottom surface of the spacing region is different from that of the first side surface and the second side surface. It can be understood that the surface texturing treatment to form the textured structure is based on the different etching rates of the etchant on the portions of the silicon substrate along different crystal directions. Therefore, when the surface crystal orientation of the bottom surface of the spacing region is different from that of the first side surface and the second side surface, respectively, the morphology of the textured structure formed by the etchant on the first side surface and the second side surface is different from the morphology of the textured structure formed on the bottom surface of the spacing region. In this case, when the morphology of the velvet structure on the first side surface and the second side surface of the back contact battery provided by the present invention is different from the morphology of the velvet structure on the bottom surface of the spacing area, there is no need to perform other additional operations to form velvet structures with roughly the same morphology on the bottom surface, the first side surface and the second side surface of the spacing area. This reduces the manufacturing difficulty of the back contact battery and helps to simplify the manufacturing process of the back contact battery.

[0014] As a possible implementation, the longitudinal cross-sections of the first and second side surfaces are serrated. In this case, the serrations have multiple sharp corners. Based on this, when other factors are the same, compared with smooth transitions such as arcs or curves, the serrations have greater roughness. Therefore, when the longitudinal cross-sections of the first and second side surfaces are serrated, the first and second side surfaces have greater roughness, which in turn helps further reduce the reflectivity of the first and second side surfaces, further improving the back-contact cell's light utilization efficiency.

[0015] As a possible implementation, the velvet structures on both the first and second side surfaces are triangular prism-like structures. The beneficial effects of this scenario are similar to those described above when the longitudinal cross-sections of the first and second side surfaces are serrated, and are not further elaborated here. Furthermore, the triangular prism-like structures are polyhedral, which helps increase the specific surface area of ​​the first and second side surfaces and further reduce the reflectivity of the first and second side surfaces.

[0016] As a possible implementation solution, the suede structure on the bottom surface of the spacing area is a pyramid-like structure.

[0017] When the above technical solution is adopted, the pyramid-like structure is a pentahedral-like structure. Compared with a velvet structure with a smaller number of V-shaped grooves, for example, when the velvet structure on the bottom surface of the spacer region is a pyramid-like structure, the specific surface area of ​​the bottom surface of the spacer region is increased. In addition, the velvet structure on the bottom surface of the spacer region has a concave surface, that is, the surface of the velvet structure is uneven, which can further increase the roughness of the bottom surface of the spacer region, thereby helping to reduce the reflectivity of the spacer region.

[0018] As a possible implementation solution, the depth of the surface of the second region recessed into the silicon substrate relative to the surface of the first region is greater than or equal to 0.5 μm and less than or equal to 3 μm.

[0019] When the above technical solution is adopted, the depth of the second region's surface recessed into the silicon substrate is within the above range. This can prevent the first doped semiconductor layer and the second doped semiconductor layer, which are co-located on the backlight side of the silicon substrate and have opposite conductivity types, from being offset less along the thickness direction of the silicon substrate due to the smaller depth of the second region's surface recessed into the silicon substrate, thereby further reducing the risk of leakage on the backlight side. In addition, the spacer region is recessed into the silicon substrate relative to the second region, that is, the spacer region is recessed deeper into the silicon substrate than the second region. Therefore, the depth of the second region's surface recessed into the silicon substrate is within the above range. This can prevent the second region's surface recessed deeper into the silicon substrate, which would result in the spacer region recessing deeper into the silicon substrate, thereby ensuring that the distance traveled by some carriers bypassing the spacer region to the first doped semiconductor layer or the second doped semiconductor layer is shorter. At the same time, it can also prevent the need for a thicker silicon substrate due to the larger depth of the second region and the spacer region recessed into the silicon substrate, thereby reducing the manufacturing cost of the back-contact cell and facilitating the thin-film production of the back-contact cell.

[0020] As a possible implementation solution, the bottom surface of the spacing region is recessed into the silicon substrate by a depth greater than or equal to 2.5 μm and less than or equal to 9 μm relative to the surface of the first region.

[0021] When the above technical solution is adopted, the depth of the bottom surface of the spacer region recessed into the silicon substrate relative to the surface of the first region is within the above range. This can prevent the smaller depth from causing the etching time to be strictly controlled after the portion of the second doped semiconductor layer located above the spacer region is completely removed during the actual manufacturing process, thereby reducing the etching difficulty. It can also prevent the larger depth from causing carriers of the corresponding conductivity type to travel a longer distance around the spacer region to be transported to the first doped semiconductor layer or the second doped semiconductor layer, thereby ensuring that carrier collection efficiency can be improved.

[0022] As a possible implementation solution, the above-mentioned back-contact cell further includes a first passivation layer located between the silicon substrate and the first doped semiconductor layer.

[0023] When adopting the above technical solution, the first passivation layer and the first doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the first area on the backlight surface of the silicon substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0024] As a possible implementation solution, the above-mentioned back-contact cell further includes a second passivation layer located between the silicon substrate and the second doped semiconductor layer.

[0025] When adopting the above-mentioned technical solution, the second passivation layer and the second doped semiconductor layer can form a selective contact structure to achieve chemical passivation of the second area on the backlight surface of the silicon substrate and selective collection of carriers of the corresponding conductive type, thereby reducing the carrier recombination rate on the backlight side, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0026] As a possible implementation solution, the surface of the first region and / or the second region is a plane.

[0027] When the above technical solution is employed, when the surface of the first region is planar, the surface of the first region is relatively flat, which helps improve the quality of the first doped semiconductor layer formed on the surface of the first region, thereby improving the ability of the first doped semiconductor layer to transport carriers of the corresponding conductivity type, thereby improving the operating performance of the back-contact battery. Furthermore, the beneficial effects of a planar surface of the second region can be referenced to the beneficial effects of a planar surface of the first region and will not be further elaborated here.

[0028] As a possible implementation solution, the back-contact cell further includes an alignment mark located on the first doped semiconductor layer and / or the second doped semiconductor layer.

[0029] When adopting the above technical solution, since the first side surface is located between the bottom surface of the spacing area and the first doped semiconductor layer, and the second side surface is located between the bottom surface of the spacing area and the second doped semiconductor layer, as the boundary area of ​​different structures, the velvet structure formed on the entire first side surface and the second side surface can make the area where the first side surface and the second side surface are located darker, which is beneficial to improving the contrast of the captured image, thereby more accurately identifying the alignment mark and improving the yield of battery production.

[0030] In a second aspect, the present invention provides a method for manufacturing a back-contact battery, which comprises the following steps: first, providing a silicon substrate. The backlight surface of the silicon substrate has a first region and a second region that are alternately spaced, and a spacer region between the first region and the second region adjacent to the first region. Next, forming a first doped semiconductor layer on the first region, and making the surfaces of the second region and the spacer region concave into the silicon substrate relative to the surface of the first region. Next, forming a second doped semiconductor layer in the second region. The conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer. Then, making the surface of the spacer region concave into the silicon substrate relative to the surface of the second region, and performing a texturing treatment on the bottom surface of the spacer region, the first side surface of the spacer region close to the first region, and the second side surface of the spacer region close to the second region, so that the bottom surface, the first side surface, and the second side surface of the spacer region all form a velvet surface.

[0031] As a possible implementation solution, the texturing treatment of the bottom surface of the spacing region, the first side surface of the spacing region adjacent to the first region, and the second side surface of the spacing region adjacent to the second region includes: performing a first texturing treatment on the bottom surface of the spacing region to form a preformed velvet structure on the bottom surface of the spacing region. Then, performing a second texturing treatment on the bottom surface, the first side surface, and the second side surface of the spacing region to adjust the morphology of the preformed velvet structure and form a velvet surface on the first side surface and the second side surface.

[0032] When using the above technical solution, a first texturing treatment is first performed on the bottom surface of the spacer region, forming a pre-formed velvet structure on the bottom surface of the spacer region. A second texturing treatment is then performed on the bottom surface, first side surface, and second side surface of the spacer region. While ensuring that the velvet surface is formed on the first and second side surfaces, the morphology of the pre-formed velvet structure can also be adjusted to ensure that the surface of the spacer region has a low reflectivity, further increasing the amount of light absorbed by the backlight side of the back-contact cell, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0033] As a possible implementation solution, the preformed velvet structure is a pyramid-like structure; and / or the height of the preformed velvet structure is greater than or equal to 0.5 μm and less than or equal to 3 μm.

[0034] When the above technical solution is employed, if the preformed velvet structure is a pyramid-like structure, the velvet structure on the bottom surface of the spacer region after the second texturing treatment is advantageously formed to have a pyramid-like morphology, further increasing the specific surface area of ​​the bottom surface of the spacer region and reducing its reflectivity. Furthermore, if the height of the preformed velvet structure is within the above range, this can prevent the specific surface area of ​​the bottom surface of the spacer region from being reduced due to a smaller height of the preformed velvet structure, thereby ensuring that the bottom surface of the spacer region has a lower reflectivity. Furthermore, this can also prevent the depth of corrosion of the portion of the silicon substrate corresponding to the spacer region from being increased due to the larger height of the preformed velvet structure, which would require the bottom surface of the spacer region to be recessed deeper into the silicon substrate relative to the surface of the second region, thereby facilitating thin-film production. Furthermore, if the preformed velvet structure is a pyramid-like structure, if the height of the preformed velvet structure is within the above range, this can also prevent the number of preformed velvet structures formed on the bottom surface of the spacer region from being reduced due to the larger overall size of the preformed velvet structure due to the larger height of the preformed velvet structure, thereby ensuring that the bottom surface of the spacer region has a good light-trapping effect after the second texturing treatment.

[0035] As a possible implementation, the wet chemical etching solution used in the second texturing treatment contains a texturing additive, and the volume ratio of the texturing additive in the wet chemical etching solution is greater than or equal to 0.01% and less than or equal to 5%. Furthermore, the treatment temperature of the second texturing treatment is greater than or equal to 50°C and less than or equal to 85°C. Furthermore, the treatment time of the second texturing treatment is greater than or equal to 30 seconds and less than or equal to 240 seconds.

[0036] In the above technical solution, the wet chemical etching solution contains a texturing additive to ensure that a textured surface is formed on the first and second side surfaces after the second texturing treatment, thereby reducing the reflectivity of the first and second side surfaces. Furthermore, the volume ratio of the texturing additive in the wet chemical etching solution is within the above-mentioned range. This prevents the textured structure formed on the first and second side surfaces after the second texturing treatment from being smaller in size and / or smaller in number due to the relatively small volume, thereby ensuring that the first and second side surfaces have higher surface roughness after the second texturing treatment. It also prevents the textured structure formed on the bottom surface of the spacer region based on the pre-formed textured structure from being significantly adjusted due to the relatively large volume, thereby ensuring that the bottom surface of the spacer region has good light trapping properties. Furthermore, the treatment temperature and treatment time of the second texturing treatment both affect the size of the textured structure formed on the bottom surface, first and second side surfaces of the spacer region. Therefore, the treatment temperature of the second texturing treatment is within the above-mentioned range, thereby preventing the textured structure from being smaller in size due to lower treatment temperatures. Furthermore, it also prevents the textured structure from being larger in size due to higher treatment temperatures. The beneficial effects of preventing the velvet structure from being too large or too small can be referred to above. Secondly, the beneficial effects of the treatment time within the above range are similar to those of the treatment temperature being greater than or equal to 50°C and less than or equal to 85°C, and will not be repeated here.

[0037] As a possible implementation, the above-mentioned forming of the first doped semiconductor layer on the first region and causing the surfaces of the second region and the spacer region to be recessed into the silicon substrate relative to the surface of the first region includes: forming a first doped semiconductor layer disposed entirely on the backlight surface of the silicon substrate, and a first mask layer located over the portion of the first doped semiconductor layer corresponding to the first region. Subsequently, under the masking action of the first mask layer, the portions of the first doped semiconductor layer located over the spacer region and the second region are selectively removed; and the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region.

[0038] As a possible implementation, the above-mentioned method for manufacturing a back-contact cell includes, after the surfaces of the second region and the spacer region are recessed into the silicon substrate relative to the surface of the first region, performing the following steps: depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region; and forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region. Next, under the masking effect of the second mask layer, selectively removing the portion of the second doped semiconductor layer corresponding to the first region and the spacer region; recessing the surface of the spacer region relative to the surface of the second region into the silicon substrate; and performing a texturing treatment on the bottom surface of the spacer region, a first side surface of the spacer region adjacent to the first region, and a second side surface of the spacer region adjacent to the second region.

[0039] As a possible implementation scheme, the material of the above-mentioned first doped semiconductor layer includes silicon. Furthermore, the above-mentioned formation of the first doped semiconductor layer as a whole layer on the backlight surface of the silicon substrate and the first mask layer located on the portion of the first doped semiconductor layer corresponding to the first region includes: forming a first intrinsic semiconductor layer as a whole layer on the backlight surface of the silicon substrate. Next, the first intrinsic semiconductor layer is doped to form the first doped semiconductor layer from the first intrinsic semiconductor layer, and a first doped silicon glass layer as a whole layer is formed on the first doped semiconductor layer. Next, the portion of the first doped silicon glass layer corresponding to the spacing region and the second region is heat-treated to form the first mask layer from the portion of the first doped silicon glass layer that has not been heat-treated. Then, the heat-treated portion of the first doped silicon glass layer is removed.

[0040] When the above technical solution is employed, when the material of the first doped semiconductor layer includes silicon, the material of the first intrinsic semiconductor layer used to form the first doped semiconductor layer also includes silicon. Based on this, after doping the first intrinsic semiconductor layer, not only can the first doped semiconductor layer be obtained, but a first doped silica glass layer can also be formed entirely on the first doped semiconductor layer. Subsequently, a laser etching process is used to heat treat a portion of the first doped silica glass layer. During this process, the laser-treated portion of the first doped silica glass layer has reduced density and is easily removed. In contrast, the untreated portion of the first doped silica glass layer has a higher density and is not easily removed. Consequently, after the heat treatment, different portions of the first doped silica glass layer have different etching selectivities, resulting in a first mask layer for patterning the first doped semiconductor layer. This eliminates the need for additional mask materials or mask deposition steps to obtain the first mask layer, thereby reducing the manufacturing cost of back-contact solar cells and simplifying the manufacturing process for back-contact solar cells.

[0041] As a possible implementation, a wet chemical process is used to selectively remove portions of the first doped semiconductor layer located on the spacer region and the second region under the masking action of a first mask layer; and the surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region. The process temperature of the wet chemical process is greater than or equal to 60°C and less than or equal to 85°C. And / or, the process time of the wet chemical process is greater than or equal to 40 seconds and less than or equal to 300 seconds. And / or, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 2% and less than or equal to 20%. And / or, the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 5%.

[0042] When the above technical solution is adopted, the process temperature and process time of the wet chemical process will affect the depth to which the surfaces of the second region and the spacer region are recessed into the silicon substrate relative to the surface of the first region through the wet chemical process. Based on this, the process temperature of the wet chemical process is within the above range, which can prevent the depth to which the surfaces of the second region and the spacer region are recessed into the silicon substrate relative to the surface of the first region due to a low process temperature. In addition, it can also prevent the depth to which the surfaces of the second region and the spacer region are recessed into the silicon substrate relative to the surface of the first region due to a high process temperature. Among them, the beneficial effects of preventing the surfaces of the second region and the spacer region from being recessed into the silicon substrate at a smaller and larger depth relative to the surface of the first region can be referred to the above. Secondly, the beneficial effects of the process time and the volume ratio of the alkaline component within the above range are similar to the beneficial effects of the process temperature being greater than or equal to 60°C and less than or equal to 85°C, and will not be repeated here. In addition, the volume ratio of the polishing additive in the wet chemical etching solution is within the above-mentioned range, which can improve the flatness of the surface of the second region and the spacing region after selective removal, which is beneficial to improving the formation quality of the second doped semiconductor layer and the formation quality of the velvet structure formed on the surface of the spacing region, ensuring that the velvet structure formed on the surface of the spacing region is evenly distributed, so that each part of the spacing region has a good light trapping effect.

[0043] As a possible implementation scheme, the material of the above-mentioned second doped semiconductor layer includes silicon. Furthermore, the above-mentioned depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region; and forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region, includes: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region. Next, doping the second intrinsic semiconductor layer to form the second doped semiconductor layer, and forming a second doped silicon glass layer disposed entirely on the second doped semiconductor layer. Next, heat-treating the portion of the second doped silicon glass layer corresponding to the first region and the spacing region to form a second mask layer on the portion of the second doped silicon glass layer corresponding to the second region. Then, removing the heat-treated portion of the second doped silicon glass layer.

[0044] In the above technical solution, when the material of the second doped semiconductor layer includes silicon, the material of the second intrinsic semiconductor layer used to form the second doped semiconductor layer also includes silicon. Based on this, after doping the second intrinsic semiconductor layer, not only the second doped semiconductor layer is obtained, but also a second doped silica glass layer can be formed entirely on the second doped semiconductor layer. Then, a laser etching process is used to heat treat the portions of the second doped silica glass layer corresponding to the first region and the spacing region. During this process, the laser-treated portions of the second doped silica glass layer have reduced density and are easily removed. Meanwhile, the portions of the second doped silica glass layer corresponding to the second region are not laser-treated and have higher density, making them less easily removed. Consequently, after the heat treatment, different portions of the second doped silica glass layer have different etching selectivities, resulting in a second mask layer for patterning the second doped semiconductor layer. This eliminates the need for additional mask materials and mask deposition steps to obtain the second mask layer, thereby reducing the manufacturing cost of back-contact solar cells and simplifying the manufacturing process for back-contact solar cells.

[0045] As a possible implementation, the back-contact cell manufacturing method further includes: forming a first passivation layer on the first region before forming the first doped semiconductor layer on the first region. And / or, the back-contact cell manufacturing method further includes: forming a second passivation layer on the second region before forming the second doped semiconductor layer on a portion of the second region.

[0046] As a possible implementation solution, the method for manufacturing a back-contact battery further includes forming an alignment mark on the first doped semiconductor layer and / or the second doped semiconductor layer.

[0047] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0049] FIG1 is a scanning electron microscope (SEM) image of a structure of a spacer region between a first doped semiconductor layer and a second doped semiconductor layer in the related art;

[0050] FIG2 is a structural SEM image of a portion of the spacer region in the related art;

[0051] FIG3 is a schematic longitudinal cross-sectional view of a back-contact battery according to an embodiment of the present invention;

[0052] FIG4 is an enlarged longitudinal cross-sectional view of a portion of the structure at the spacing region in one embodiment of the present invention;

[0053] FIG5 is a first SEM image of a first side surface and a portion of a spacing region in one embodiment of the present invention;

[0054] FIG6 is a second SEM image of the first side surface and a portion of the spacing region in one embodiment of the present invention;

[0055] FIG7 is a third SEM image of the first side surface and a portion of the spacing region in one embodiment of the present invention;

[0056] FIG8 is a fourth SEM image of the first side surface and a portion of the spacing region in one embodiment of the present invention;

[0057] FIG9 is a SEM image of the first side surface or the second side surface in one embodiment of the present invention;

[0058] FIG10 is a fifth SEM image of the first side surface and a portion of the spacing region in one embodiment of the present invention;

[0059] FIG11 is a sixth SEM image of the first side surface and a portion of the spacing region in one embodiment of the present invention;

[0060] FIG12 is a seventh SEM image of the first side surface and a portion of the spacing region in one embodiment of the present invention;

[0061] FIG13 is a second schematic longitudinal cross-sectional view of the structure of a back-contact battery provided by one embodiment of the present invention;

[0062] FIG14 is a first schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0063] FIG15 is a second schematic longitudinal cross-sectional view of the structure of a back-contact battery during the manufacturing process according to one embodiment of the present invention;

[0064] FIG16 is a third schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0065] FIG17 is a fourth schematic longitudinal cross-sectional view of the structure of a back-contact battery during the manufacturing process according to an embodiment of the present invention;

[0066] FIG18 is a fifth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0067] FIG19 is a sixth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0068] FIG20 is a seventh schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0069] FIG21 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to one embodiment of the present invention;

[0070] FIG22 is a ninth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0071] FIG23 is a schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present invention during the manufacturing process;

[0072] FIG24 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0073] FIG25 is a schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0074] FIG26 is a thirteenth schematic longitudinal cross-sectional view of the structure of a back-contact cell during the manufacturing process according to an embodiment of the present invention;

[0075] FIG27 is a fourteenth schematic longitudinal cross-sectional view of the structure of a back-contact battery provided in an embodiment of the present invention during the manufacturing process.

[0076] Figure numerals: 11 is a silicon substrate, 12 is a first doped semiconductor layer, 13 is a second doped semiconductor layer, 14 is a first region, 15 is a second region, 16 is a spacing region, 17 is a first passivation layer, 18 is a second passivation layer, 19 is a first mask layer, 20 is a second mask layer, 21 is a first intrinsic semiconductor layer, 22 is a first doped silicon glass layer, 23 is a second intrinsic semiconductor layer, and 24 is a second doped silicon glass layer. DETAILED DESCRIPTION

[0077] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0078] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0079] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0081] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0082] At present, solar cells are used more and more widely as a new energy alternative. Among them, photovoltaic solar cells are devices that convert sunlight energy into electrical energy. Specifically, solar cells use the principle of photovoltaics to generate carriers, and then use electrodes to lead out the carriers, thereby facilitating the effective use of electrical energy. Among them, when the positive and negative electrodes included in the solar cell are both located on the back of the solar cell, the solar cell is a back contact cell. Because the front of the back contact cell is not affected by the metal electrode, it has a higher short-circuit current I sc , which is one of the current technical directions for achieving high-efficiency crystalline silicon cells.

[0083] Specifically, existing back-contact cells include at least a silicon substrate and a first doped semiconductor layer formed on a portion of the backlight side of the silicon substrate. This first doped semiconductor layer can have a conductivity type opposite to that of the silicon substrate; alternatively, the first doped semiconductor layer can have the same conductivity type as the silicon substrate. In this case, the back-contact cell also includes a second doped semiconductor layer formed on a portion of the backlight side of the silicon substrate. This second doped semiconductor layer has a conductivity type opposite to that of the first doped semiconductor layer. Regardless of which of the above structures the back-contact cell has, the backlight side of the back-contact cell has two doped regions of opposite conductivity types, and these two doped regions of opposite conductivity types are spaced apart to prevent short circuits.

[0084] In the actual manufacturing process of the above-mentioned back-contact battery, it is necessary to first form a layer of doped semiconductor material on the backlight side of the silicon substrate, and then selectively remove the doped semiconductor material layer located in a portion of the backlight area to obtain the above-mentioned first doped semiconductor layer. Correspondingly, the above-mentioned method is also used to form a second doped semiconductor layer on a local area of ​​the backlight surface. As shown in Figures 1 and 2, to prevent the first doped semiconductor layer 12 and the second doped semiconductor layer 13 from conducting and causing a short circuit, the existing manufacturing method uses wet chemical etching or other methods to form a spacer region 16 of a certain width between the two, and the surface of the spacer region 16 is recessed into the silicon substrate relative to the surface of the silicon substrate 11.

[0085] However, as shown in Figures 1 and 2, in the existing back-contact cell, only the bottom surface of the spacing region 16 arranged between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 is velvet, while the side surface of the spacing region 16 close to the first doped semiconductor layer 12 and the side surface of the spacing region 16 close to the second doped semiconductor layer 13 are relatively flat surfaces with less roughness, resulting in a higher reflectivity of these two side surfaces to light, resulting in a lower light utilization rate of the back-contact cell, which is not conducive to improving the photoelectric conversion efficiency of the back-contact cell.

[0086] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a back-contact battery. As shown in Figures 3 and 4, the back-contact battery includes: a silicon substrate 11, and a first doped semiconductor layer 12 and a second doped semiconductor layer 13 alternately distributed on the backlight side of the silicon substrate 11. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types. On the backlight side of the silicon substrate 11, the area corresponding to the first doped semiconductor layer 12 is the first area 14, the area corresponding to the second doped semiconductor layer 13 is the second area 15, and the area between the first area 14 and the second area 15 adjacent to it is the spacing area 16. The surface of the second area 15 is concave into the silicon substrate 11 relative to the surface of the first area 14. The surface of the spacing area 16 is concave into the silicon substrate 11 relative to the surface of the second area 15. The bottom surface of the spacing area 16, the first side surface of the spacing area 16 close to the first area 14, and the second side surface of the spacing area 16 close to the second area 15 are all velvet.

[0087] It should be noted that, as shown in Figures 3 to 12, when the bottom surface, first side surface and second side surface of the above-mentioned spacing area 16 are velvet, a velvet structure is formed on each area of ​​the bottom surface, first side surface and second side surface of the spacing area 16, that is, each area of ​​the bottom surface, first side surface and second side surface of the spacing area 16 has a higher specific surface area and light trapping effect.

[0088] When the above technical solution is adopted, as shown in Figure 3, in the back-contact cell provided by the embodiment of the present invention, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of opposite conductivity types are alternately spaced and distributed on the backlight side of the silicon substrate 11. Based on this, the spacing region 16 provided on the backlight side of the silicon substrate 11 can isolate the first doped semiconductor layer 12 formed on the first region 14 from the second doped semiconductor layer 13 formed on the second region 15, reducing the carrier recombination rate at the lateral intersection of the first doped semiconductor layer 12 and the second doped semiconductor layer 13, thereby improving the photoelectric conversion efficiency of the back-contact cell. Secondly, the surface of the second region 15 is recessed into the silicon substrate 11 relative to the surface of the first region 14, and the surface of the spacer region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15. This indicates that in the actual manufacturing process, after forming the entire first doped semiconductor layer 12 covering the backlight side, the portion of the first doped semiconductor layer 12 located on the second region 15 and the spacer region 16 has been completely removed; and after achieving selective etching of the first doped semiconductor layer 12 and depositing the entire second doped semiconductor layer 13, the second doped semiconductor layer 13 located on the first doped semiconductor layer has been completely removed. The body layer 12 and the portion on the spacer region 16 are completely removed to prevent leakage caused by residues remaining on the surface of the corresponding regions after selective etching of the first doped semiconductor layer 12 and / or the second doped semiconductor layer 13. At the same time, when the surface of the second region 15 is recessed into the silicon substrate 11 relative to the surface of the first region 14, it is also beneficial to at least partially stagger the first doped semiconductor layer 12 and the second doped semiconductor layer 13, which are located on the backlight side of the silicon substrate 11 and have opposite conductivity types, along the thickness direction of the silicon substrate 11, further reducing the risk of leakage on the backlight side and improving the electrical reliability of the back-contact cell. In addition, as shown in Figures 3 and 4, in the back-contact cell provided by the embodiment of the present invention, not only the bottom surface of the spacer region 16 is a velvet surface, but also the first side surface of the spacer region 16 near the first region 14 and the second side surface of the spacer region 16 near the second region 15 are also velvet surfaces. Compared with a flat surface, the velvet surface has uneven surface features, which makes it have a better light trapping effect and can reduce the reflectivity of the bottom surface, first side surface, and second side surface of the spacer region 16. In this case, compared with the first side surface and the second side surface of the existing back contact cell being planes, the back contact cell provided by the embodiment of the present invention is conducive to allowing more light to be refracted from the above-mentioned first side surface and the second side surface into the silicon substrate 11 and utilized by the silicon substrate 11, thereby helping to improve the photoelectric conversion efficiency of the back contact cell.

[0089] Specifically, the back contact cell further includes an alignment mark located on the first doped semiconductor layer 12 and / or the second doped semiconductor layer 13 .

[0090] Since the first side surface is located between the bottom surface of the spacing region and the first doped semiconductor layer, and the second side surface is located between the bottom surface of the spacing region and the second doped semiconductor layer, as the boundary area of ​​different structures, the velvet structure formed on the entire first side surface and the second side surface can make the area where the first side surface and the second side surface are located darker, which is beneficial to improving the contrast of the captured image, thereby more accurately identifying the alignment mark and improving the yield of battery production.

[0091] In actual applications, the light-facing surface of the silicon substrate can be flat; or, as shown in FIG3 , the light-facing surface of the silicon substrate 11 can be a velvet surface. Because the velvet surface traps light, the reflectivity of the light-facing surface can be reduced when the light-facing surface of the silicon substrate 11 is a velvet surface, allowing more light to be refracted from the light-facing surface into the silicon substrate 11 and absorbed and utilized by the silicon substrate 11, thereby improving the photoelectric conversion efficiency of the back-contact solar cell.

[0092] In addition, in terms of scope, the boundaries of the first region 14, the second region 15, and the spacing region 16 on the backlight side of the silicon substrate are virtual boundaries. As shown in Figure 3, the first doped semiconductor layer 12 is formed on the first region 14. Therefore, the scope of the first region 14 on the backlight side of the silicon substrate 11 can be determined based on the requirements for the formation scope of the first doped semiconductor layer 12 in the actual application scenario. Secondly, the second doped semiconductor layer 13 is formed on the second region 15. Therefore, the scope of the second region 15 on the backlight side of the silicon substrate 11 can be determined based on the requirements for the formation scope of the second doped semiconductor layer 13 in the actual application scenario. As for the spacing region 16, as mentioned above, the spacing region 16 can isolate the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of opposite conductivity types to suppress leakage. Therefore, the scope of the spacing region 16 on the backlight side can be determined based on the requirements for the anti-leakage spacing between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 in the actual application scenario.

[0093] Exemplarily, along the arrangement direction of the first region and the second region, the length of the spacing region can be greater than or equal to 20 μm and less than or equal to 110 μm. For example, the length of the spacing region can be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm or 110 μm, etc. In this case, the length of the spacing region is within the above range, which can prevent leakage between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 due to the small spacing, thereby ensuring that the back contact battery has high electrical reliability. In addition, it can also prevent the carriers on the backlight side from being collected by the first doped semiconductor layer 12 and / or the second doped semiconductor layer 13 in a timely manner and being led out by the corresponding electrodes due to the large spacing, thereby further reducing the carrier recombination rate on the backlight side.

[0094] In terms of the depth of the recess, the depth of the recess of the second region 15 and the spacing region 16 on the backlight surface of the silicon substrate 11 into the silicon substrate can be determined according to the actual application scenario, as long as the surface of the second region 15 is recessed into the silicon substrate 11 relative to the surface of the first region 14, and the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15.

[0095] Exemplarily, the depth of the surface of the second region 15 recessed into the silicon substrate 11 relative to the surface of the first region 14 can be greater than or equal to 0.5 μm and less than or equal to 3 μm. For example, the depth of the surface of the second region 15 recessed into the silicon substrate 11 relative to the surface of the first region 14 can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm. In this case, the depth of the surface of the second region 15 recessed into the silicon substrate 11 is within the above range, which can prevent the first doped semiconductor layer 12 and the second doped semiconductor layer 13, which are co-located on the backlight side of the silicon substrate and have opposite conductivity types, from being less offset along the thickness direction of the silicon substrate due to the small depth of the recessed surface of the second region 15 into the silicon substrate 11, thereby further reducing the risk of leakage on the backlight side. In addition, the spacer region 16 is recessed into the silicon substrate 11 relative to the second region 15, that is, compared with the second region 15, the depth of the recessed spacer region 16 into the silicon substrate 11 is greater. Therefore, the depth of the recessed surface of the second region 15 into the silicon substrate 11 is within the above-mentioned range, which can prevent the surface of the second region 15 from being recessed into the silicon substrate 11 to a greater depth, resulting in the spacer region 16 being recessed into the silicon substrate 11 to a greater depth, thereby ensuring that the movement distance of some carriers bypassing the spacer region 16 to be transmitted to the first doped semiconductor layer 12 or the second doped semiconductor layer 13 is smaller; at the same time, it can also prevent the need to use a thicker silicon substrate 11 due to the greater depth of the recessed second region 15 and the spacer region 16 into the silicon substrate 11, thereby reducing the manufacturing cost of the back-contact battery while facilitating the thin-film production of the back-contact battery.

[0096] For example, the depth of the recess of the surface of the spacer region 16 relative to the surface of the first region 14 into the silicon substrate 11 can be greater than or equal to 2.5 μm and less than or equal to 9 μm. For example, the depth of the recess of the surface of the spacer region 16 relative to the surface of the first region 14 into the silicon substrate can be 2.5 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, or 9 μm. In this case, the depth of the recess of the surface of the spacer region 16 relative to the surface of the first region 14 into the silicon substrate 11 is within the above range. This can prevent the etchant from etching the spacer region 16 to a relatively small depth in the actual manufacturing process after completely removing the portion of the second doped semiconductor layer 13 located on the spacer region 16, thereby reducing the etching difficulty. It can also prevent the corresponding conductivity type from traveling a large distance to bypass the spacer region 16 and be transmitted to the first doped semiconductor layer 12 or the second doped semiconductor layer 13 due to the large depth, thereby ensuring that the carrier collection efficiency can be improved.

[0097] It should be noted that, since the bottom surface of the spacer region 16 is a velvet surface, the depth of the bottom surface of the spacer region 16 recessed into the silicon substrate 11 relative to the surface of the first region 14 is equal to the vertical distance from the middle of the velvet structure formed by the bottom surface of the spacer region 16 to the surface of the first region 14.

[0098] In terms of surface morphology, the surface of the first region 14 and the surface of the second region 15 on the backlight side of the silicon substrate 11 can be a velvet surface; alternatively, as shown in FIG3 , the surface of the first region 14 and the surface of the second region 15 can be planar. When the surface of the first region 14 is planar, the surface of the first region 14 is relatively flat, which helps improve the quality of the first doped semiconductor layer 12 formed on the surface of the first region 14, thereby improving the ability of the first doped semiconductor layer 12 to transport carriers of the corresponding conductivity type, thereby improving the operating performance of the back-contact battery. Furthermore, the beneficial effects of a planar surface of the second region 15 can be referenced to the beneficial effects of a planar surface of the first region 14, and will not be further elaborated here.

[0099] As for the spacing region 16, the bottom surface of the spacing region 16 is a velvet surface. The specific morphology of the velvet structure formed thereon can be determined according to actual needs and the actual manufacturing process. For example, the velvet structure formed on the bottom surface of the spacing region 16 can be a pyramid-like structure, a V-shaped groove structure, or an inverted pyramid-like structure.

[0100] Exemplarily, as shown in Figures 4 to 12, the velvet structure on the bottom surface of the above-mentioned spacer region 16 can be a pyramid-like structure with a concave surface. In this case, the pyramid-like structure is a pentahedral structure. Compared with a velvet structure with a smaller number of surfaces such as V-shaped grooves, when the velvet structure on the bottom surface of the spacer region 16 is a pyramid-like structure, it is beneficial to increase the specific surface area of ​​the bottom surface of the spacer region 16. In addition, the surface of the velvet structure on the bottom surface of the spacer region 16 has a concave surface, that is, the surface of the velvet structure is uneven, which can further increase the roughness of the bottom surface of the spacer region 16, thereby helping to reduce the reflectivity of the spacer region 16.

[0101] As for the morphology of the first side surface of the spacer region 16 close to the first region 14, and the second side surface of the spacer region 16 close to the second region 15, the first side surface and the second side surface can be arranged perpendicularly relative to the horizontal plane. Alternatively, as shown in Figures 3 and 4, the first side surface and the second side surface can also be arranged inclined relative to the horizontal plane, so that the cross-sectional area of ​​the spacer region 16 gradually increases from the light-facing side to the backlight side. The horizontal plane mentioned in this application refers to the horizontal plane where the silicon substrate of the back contact battery is located. In this case, the cross-sectional area of ​​the spacer region 16 close to the light-facing side is smaller than the cross-sectional area of ​​the spacer region 16 close to the backlight side, which is beneficial to increase the distance between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of the opposite conductivity type, reduce the leakage risk on the backlight side of the back contact battery, and ensure that the back contact battery has high electrical reliability. In addition, compared with the first side surface and the second side surface being arranged vertically relative to the horizontal plane, the first side surface and the second side surface being inclined relative to the horizontal plane respectively can also increase the area ratio of the positive projection of the first side surface and the second side surface on the backlight side, which can further reduce the reflectivity on the backlight side, and further allow more light to enter the silicon substrate 11 from the backlight side of the back contact cell under the light trapping effect of the first side surface and the second side surface, thereby helping to improve the photoelectric conversion efficiency of the back contact cell.

[0102] In the above case, the angles between the first side surface and the second side surface and the horizontal plane can be determined based on the requirements for the reflectivity of the backlight side in the actual manufacturing process, and the depth of the recess of the spacer area 16 relative to the surface of the second area 15 into the silicon substrate 11, and no specific limitation is made here.

[0103] For example, as shown in Figures 3 and 4, the angles between the first side surface and the second side surface and the horizontal plane may be greater than or equal to 52° and less than or equal to 58°. For example, the angles between the first side surface and the second side surface and the horizontal plane may be 52°, 53°, 54°, 55°, 56°, 57°, or 58°, etc. In this case, the angles between the first side surface and the second side surface and the horizontal plane are within the above range, which can prevent the effect of reducing the reflectivity on the backlight side through the first side surface and the second side surface from being unclear due to the smaller area of ​​the positive projections of the first side surface and the second side surface on the backlight side due to the larger angle, thereby ensuring that the backlight side of the back-contact battery has a higher light utilization rate; in addition, it can also prevent the depth of the surface of the spacer area 16 recessed into the silicon substrate 11 relative to the surface of the second area 15 due to the smaller angle, thereby ensuring that after the entire deposited second doped semiconductor layer 13 is selectively etched, the portion thereof located on the spacer area 16 and the first doped semiconductor layer 12 is completely removed, thereby preventing leakage and ensuring that the back-contact battery has higher electrical reliability.

[0104] In addition, the first side surface and the second side surface are also velvet. Specifically, the morphology of the velvet structure on the first side surface and the second side surface can be roughly the same as the morphology of the velvet structure on the bottom surface of the spacing region 16. Alternatively, as shown in Figures 5 to 12, the morphology of the velvet structure on the first side surface and the second side surface can also be different from the morphology of the velvet structure on the bottom surface of the spacing region 16. Wherein, referring to Figures 3 to 12, the bottom surface of the spacing region 16 is roughly parallel to the horizontal plane; secondly, because the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, the first side surface of the spacing region 16 close to the first region 14 and the second side surface of the spacing region 16 close to the second region 15 are respectively inclined or perpendicular to the horizontal plane. It can be seen that the relative positional relationship between the bottom surface of the spacing region 16 and the horizontal plane is not the same as the relative positional relationship between the first side surface and the second side surface and the horizontal plane, so the bottom surface of the spacing region 16 has a different surface crystal orientation from the first side surface and the second side surface. It can be understood that the texturing treatment of the surface to form a velvet structure is achieved based on the different etching rates of the etchant on the portions of the silicon substrate 11 along different crystal orientations. Therefore, when the bottom surface of the spacer region 16 has a different surface crystal orientation from the first side surface and the second side surface, respectively, the morphology of the velvet structure formed by the etchant on the first side surface and the second side surface is different from the morphology of the velvet structure formed on the bottom surface of the spacer region 16. In this case, in the back-contact battery provided in an embodiment of the present invention, where the morphology of the velvet structure on the first side surface and the second side surface is different from the morphology of the velvet structure on the bottom surface of the spacer region 16, there is no need to perform additional operations to form velvet structures with roughly the same morphology on the bottom surface, the first side surface, and the second side surface of the spacer region 16, which reduces the manufacturing difficulty of the back-contact battery and helps to simplify the manufacturing process of the back-contact battery.

[0105] Specifically, when the morphology of the velvet structure on the first side surface and the second side surface is different from the morphology of the velvet structure on the bottom surface of the spacing area, the morphology of the velvet structure on the first side surface and the second side surface can be determined based on the angles between the first side surface and the second side surface and the horizontal plane, respectively, and the actual manufacturing process, and is not specifically limited here.

[0106] For example, as shown in Figures 4 to 8, the longitudinal cross-section of the first side surface and the second side surface may be sawtooth-shaped. Specifically, the longitudinal cross-section is a longitudinal section extending in the arrangement direction of the first region and the second region. For example, Figure 4 is a schematic diagram of a longitudinal cross-section of a portion of a back-contact battery. In this case, the sawtooth shape has multiple sharp corners. Based on this, when other factors are the same, the sawtooth shape has a greater roughness than a smooth transition shape such as an arc or curve. Therefore, when the longitudinal cross-section of the first side surface and the second side surface is sawtooth-shaped, it is beneficial to make the first side surface and the second side surface have a greater roughness, which in turn helps to further reduce the reflectivity of the first side surface and the second side surface, and further improve the utilization rate of light by the back-contact battery.

[0107] For example, as shown in Figures 9 to 12, the velvet structures on both the first and second side surfaces can be triangular prism-like structures. The beneficial effects of this scenario are similar to those described above when the longitudinal cross-sections of the first and second side surfaces are serrated, and will not be further elaborated here. Furthermore, the triangular prism-like structures are polyhedral, which helps increase the specific surface area of ​​the first and second side surfaces and further reduce the reflectivity of the first and second side surfaces.

[0108] Regarding the first doped semiconductor layer 12 and the second doped semiconductor layer 13, the material of the first doped semiconductor layer 12 or the second doped semiconductor layer 13 can be a semiconductor material such as silicon, silicon germanium, germanium, or gallium arsenide. Regarding the arrangement of the materials, the crystalline phase of the first doped semiconductor layer 12 or the second doped semiconductor layer 13 can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline. Regarding the conductivity type, the conductivity type of the first doped semiconductor layer 12 or the second doped semiconductor layer 13 can be opposite to or the same as the conductivity type of the silicon substrate 11, as long as the conductivity types of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are opposite. The thickness of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 can be set according to actual needs and is not specifically limited here. For example, the thickness of the first doped semiconductor layer 12 or the second doped semiconductor layer 13 can be greater than or equal to 100 nm and less than or equal to 500 nm.

[0109] In actual applications, as shown in FIG3 , the first doped semiconductor layer 12 can be formed directly on the first region 14 of the silicon substrate 11. Alternatively, as shown in FIG13 , the back-contact cell may further include a first passivation layer 17 located between the silicon substrate 11 and the first doped semiconductor layer 12. In this case, the first passivation layer 17 and the first doped semiconductor layer 12 may form a selective contact structure to chemically passivate the first region 14 on the backlight side of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0110] Specifically, the material of the first passivation layer 17 can be determined according to the material of the first doped semiconductor layer 12 and the type of selective contact structure formed by the first passivation layer 17 and the first doped semiconductor layer 12 in actual application scenarios, and is not specifically limited here.

[0111] For example, when the selective contact structure formed by the first passivation layer 17 and the first doped semiconductor layer 12 is a tunneling passivation contact structure, the first doped semiconductor layer 12 is a doped polysilicon layer, and the first passivation layer 17 is a tunneling passivation layer. The material of the tunneling passivation layer may include silicon oxide, aluminum oxide, or titanium oxide.

[0112] For another example, when the selective contact structure formed by the first passivation layer 17 and the first doped semiconductor layer 12 is a heterogeneous contact structure, the first doped semiconductor layer 12 is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer 17 is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0113] The thickness of the first passivation layer 17 can be set according to actual needs and is not specifically limited here. For example, the thickness of the first passivation layer 17 can be greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0114] As for the second doped semiconductor layer 13, as shown in FIG3 , the second doped semiconductor layer 13 can be formed directly on the second region 15 of the silicon substrate 11. Alternatively, as shown in FIG13 , the back-contact cell can further include a second passivation layer 18 located between the silicon substrate 11 and the second doped semiconductor layer 13. In this case, the second passivation layer 18 and the second doped semiconductor layer 13 can form a selective contact structure to chemically passivate the second region 15 on the backlight side of the silicon substrate 11 and selectively collect carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the backlight side and improving the photoelectric conversion efficiency of the back-contact cell.

[0115] Specifically, the material and thickness of the second passivation layer 18 may refer to the material and thickness of the first passivation layer 17 described above, and will not be repeated here.

[0116] In a second aspect, embodiments of the present invention provide a method for manufacturing a back-contact battery. The manufacturing process will be described below based on the cross-sectional views of the operations shown in Figures 14 to 27. Specifically, the method for manufacturing a back-contact battery includes the following steps:

[0117] First, a silicon substrate is provided, wherein the backlight surface of the silicon substrate comprises first regions and second regions that are alternately distributed and an interval region between the first region and the second region adjacent to the first region.

[0118] Specifically, the ranges of the first area, the second area, and the spacing area on one side of the backlight surface can be referred to above and will not be described in detail here.

[0119] Next, as shown in FIG. 19 , a first doped semiconductor layer 12 is formed on the first region 14 , and surfaces of the second region 15 and the spacer region 16 are recessed into the silicon substrate 11 relative to the surface of the first region 14 .

[0120] In an actual manufacturing process, as shown in FIG17 , after providing a silicon substrate 11, a first doped semiconductor layer 12 is formed entirely on the backlight surface of the silicon substrate 11, along with a first mask layer 19 located on the portion of the first doped semiconductor layer 12 corresponding to the first region 14. Next, as shown in FIG18 , under the masking action of the first mask layer 19, the portion of the first doped semiconductor layer 12 located on the spacing region 16 and the second region 15 is selectively removed, and the surfaces of the spacing region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14.

[0121] The material and thickness of the first doped semiconductor layer 12, as well as the depth to which the surfaces of the spacer region 16 and the second region 15 are respectively recessed into the silicon substrate 11 after the operation, can be referred to above. As for the aforementioned first mask layer, the material of the first mask layer can be any material that has a masking function and is not specifically limited here. Secondly, the formation process and specific formation process of the first doped semiconductor layer 12 and the first mask layer 19 can be determined based on the specific materials of the first doped semiconductor layer 12 and the first mask layer 19.

[0122] For example, when the material of the first doped semiconductor layer 12 includes silicon, the above-mentioned steps of forming the first doped semiconductor layer 12 disposed entirely on the backlit surface of the silicon substrate 11 and the first mask layer 19 located on the portion of the first doped semiconductor layer 12 corresponding to the first region 14 may include the following steps: as shown in FIG14 , forming the first intrinsic semiconductor layer 21 disposed entirely on the backlit surface of the silicon substrate 11. Next, as shown in FIG15 , the first intrinsic semiconductor layer 21 is doped to form the first doped semiconductor layer 12 from the first intrinsic semiconductor layer 21, and forming the first doped silicon glass layer 22 disposed entirely on the first doped semiconductor layer 12. Next, as shown in FIG16 , the portions of the first doped silicon glass layer corresponding to the spacing regions 16 and the second regions 15 are heat-treated using a laser etching process to form the first mask layer 19 in the portions of the first doped silicon glass layer 22 that have not been heat-treated. Then, as shown in FIG17 , the heat-treated portions of the first doped silicon glass layer 22 are removed.

[0123] Specifically, the material of the first doped semiconductor layer 12 includes silicon, which may mean that the material of the first doped semiconductor layer 12 only includes silicon; or it may also mean that the material of the first doped semiconductor layer 12 includes both silicon and other semiconductor materials such as silicon germanium. Secondly, in the actual manufacturing process, a process such as chemical vapor deposition can be used to form a first intrinsic semiconductor layer 21 that is arranged on the backlight side as a whole layer. Next, the first intrinsic semiconductor layer 21 can be doped using a process such as diffusion. After the above-mentioned doping treatment, not only the first doped semiconductor layer 12 can be obtained, but also a first doped silicon glass layer 22 that is arranged as a whole layer can be formed on the first doped semiconductor layer 12. Then, a laser etching process is used to heat-treat part of the first doped silicon glass layer 22. At this time, as shown in FIG16 , the density of the laser-treated portion of the first doped silicon glass layer 22 becomes poorer, and it is easy to be removed. The portions of the first doped silica glass layer 22 that have not been laser-treated are denser and less easily removed. Consequently, after heat treatment, different portions of the first doped silica glass layer 22 have different etching selectivities, resulting in a first mask layer 19 for patterning the first doped semiconductor layer 12. This eliminates the need for forming additional mask materials or performing additional mask deposition steps to obtain the first mask layer 19, thereby reducing the manufacturing cost of back-contact cells and simplifying the manufacturing process for back-contact cells. The specific conditions for the laser etching process can be set based on the actual application scenario and are not specifically limited here.

[0124] For example, the laser used in the laser etching process may be a nanosecond laser, a picosecond laser, or a femtosecond laser, etc. The laser etching process may have a power greater than or equal to 10W and less than or equal to 100W, and the diameter of the laser spot may be greater than or equal to 50 μm and less than or equal to 300 μm.

[0125] Of course, when the material of the first doped semiconductor layer 12 includes silicon, or when the material of the first doped semiconductor layer 12 does not include silicon, chemical vapor deposition and doping processes can also be used to form the entire first doped semiconductor layer 12 disposed on the backlight side. Then, chemical vapor deposition and etching processes can be used to form a first mask layer 19 made of other materials such as silicon nitride that have a masking function.

[0126] In addition, after forming the first mask layer 19, a wet chemical process can be used to selectively remove the portion of the first doped semiconductor layer 12 located on the spacer region 16 and the second region 15 under the masking effect of the first mask layer 19. The surfaces of the spacer region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14 to prevent damage to the silicon substrate 11 caused by the high-temperature laser, thereby improving the yield of the back-contact cell. Specifically, the process conditions for selectively etching the first doped semiconductor layer 12 can be determined based on the etching process used, the material of the first doped semiconductor layer 12, and the depth to which the surfaces of the spacer region 16 and the second region 15 are recessed into the silicon substrate 11 after the operation, and are not specifically limited here.

[0127] For example, when a wet chemical process is used under the mask of the first mask layer 19 to selectively remove the portion of the first doped semiconductor layer 12 located on the spacer region 16 and the second region 15 so that the surfaces of the spacer region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14, the process temperature of the wet chemical process can be greater than or equal to 60°C and less than or equal to 85°C. In addition, the process time of the wet chemical process can be greater than or equal to 40 seconds and less than or equal to 300 seconds. Furthermore, the wet chemical etching solution used in the wet chemical process can be an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (such as NaOH or KOH) in the alkaline wet chemical etching solution can be greater than or equal to 2% and less than or equal to 20%. For example, the process temperature of the wet chemical process can be 60°C, 70°C, 75°C, 78°C, or 80°C. The process time of the wet chemical process can be 40 seconds, 80 seconds, 100 seconds, 150 seconds, 200 seconds, 260 seconds, or 300 seconds. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution can be 2%, 3%, 6%, 9%, 12%, 15%, or 20%, etc. In this case, the process temperature and process time of the wet chemical process both affect the depth to which the surfaces of the second region 15 and the spacer region 16 are recessed into the silicon substrate 11 relative to the surface of the first region 14 during the wet chemical process. Therefore, keeping the process temperature of the wet chemical process within the above range can prevent the surfaces of the second region 15 and the spacer region 16 from recessing into the silicon substrate 11 to a smaller depth relative to the surface of the first region 14 due to a lower process temperature. Furthermore, it can also prevent the surfaces of the second region 15 and the spacer region 16 from recessing into the silicon substrate 11 to an excessively large depth relative to the surface of the first region 14 due to a higher process temperature. The beneficial effects of preventing the surfaces of the second region 15 and the spacer region 16 from recessing into the silicon substrate 11 to a smaller or greater depth relative to the surface of the first region 14 can be found in the above description. Secondly, the beneficial effects of the process time and the volume ratio of the alkaline component within the above ranges are similar to the beneficial effects of the process temperature being greater than or equal to 60° C. and less than or equal to 85° C., and will not be repeated here.

[0128] In addition, polishing additives can be added to the wet chemical etching solution to improve the flatness of the surface of the spacer region 16 and the second region 15 after the operation, which is beneficial to improving the formation quality of the second doped semiconductor layer 12 and the formation quality of the velvet structure formed on the surface of the spacer region 16, ensuring that the velvet structure formed on the surface of the spacer region 16 is evenly distributed, so that each part of the spacer region 16 has a good light trapping effect. Specifically, the composition of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution can be determined according to the actual application scenario, and are not specifically limited here. For example, the polishing additive may include sodium benzoate, a defoaming agent, and a surfactant. The volume ratio of the polishing additive in the wet chemical etching solution may be greater than or equal to 0.5% and less than or equal to 5%.

[0129] It should be noted that when the manufactured back-contact battery also includes a first passivation layer located between the first region and the first doped semiconductor layer, the manufacturing method of the above-mentioned back-contact battery, after providing a silicon substrate and before forming the first doped semiconductor layer on the first region, also includes the step of: using a deposition and etching process to first form a first passivation layer on the first region.

[0130] Alternatively, as shown in FIG14 , after providing a silicon substrate 11, a process such as chemical vapor deposition can be used to form a first passivation layer 17 entirely on the backlight side. Then, as shown in FIG17 and FIG18 , after forming a first mask layer 19 and selectively etching the first doped semiconductor layer 12 under the masking action of the first mask layer 19, the first passivation layer 17 is selectively etched. In this case, there is no need to form an additional mask layer for forming the first passivation layer 17, simplifying the manufacturing process of the back-contact cell.

[0131] 24 , a second doped semiconductor layer 13 is formed in the second region 15. The second doped semiconductor layer 13 and the first doped semiconductor layer 12 have opposite conductivity types.

[0132] In an actual manufacturing process, as shown in FIG23 , after the surfaces of the second region 15 and the spacer region 16 are recessed into the silicon substrate 11 relative to the surface of the first region 14, the second doped semiconductor layer 13 is deposited on the first doped semiconductor layer 12, the spacer region 16, and the second region 15. Furthermore, a second mask layer 20 is formed on the portion of the second doped semiconductor layer 13 corresponding to the second region 15. Next, as shown in FIG25 and FIG26 , under the masking action of the second mask layer 20, the portion of the second doped semiconductor layer 13 corresponding to the first region 14 and the spacer region 16 is selectively removed.

[0133] Specifically, the material and thickness of the second doped semiconductor layer 13, as well as the depth of the recess of the surface of the spacer region 16 into the silicon substrate 11 after the operation, can be referred to above and will not be repeated here. As for the second mask layer 20, its material can be any material that can function as a mask. In the actual manufacturing process, the formation process and specific formation process of the second doped semiconductor layer 13 and the second mask layer 20 can be determined based on the materials of the second doped semiconductor layer 13 and the second mask layer 20.

[0134] For example, when the material of the second doped semiconductor layer includes silicon, the above-mentioned steps of depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region; and forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region may include the following steps: as shown in FIG20 , depositing a second intrinsic semiconductor layer 23 on the first doped semiconductor layer 12, the spacer region 16, and the second region 15. Next, as shown in FIG21 , doping the second intrinsic semiconductor layer 23 to form the second doped semiconductor layer 13, and forming a second doped silicon glass layer 24 entirely on the second doped semiconductor layer 13. Next, as shown in FIG22 , heat-treating the portion of the second doped silicon glass layer 24 corresponding to the first region 14 and the spacer region 16 using a laser etching process to form a second mask layer 20 on the portion of the second doped silicon glass layer 24 corresponding to the second region 15. Then, as shown in FIG23 , removing the heat-treated portion of the second doped silicon glass layer 24.

[0135] Specifically, the material of the second doped semiconductor layer 13 including silicon may mean that the material of the second doped semiconductor layer 13 only includes silicon; or it may also mean that the material of the second doped semiconductor layer 13 includes both silicon and other semiconductor materials such as silicon germanium. Secondly, in the actual manufacturing process, a process such as chemical vapor deposition can be used to form a second intrinsic semiconductor layer 23 that is disposed on the backlight side as a whole layer. Next, a process such as diffusion can be used to dope the second intrinsic semiconductor layer 23. After the above-mentioned doping treatment, not only the second doped semiconductor layer 13 can be obtained, but also a second doped silicon glass layer 24 that is disposed as a whole layer on the second doped semiconductor layer 13 can be formed. Then, a laser etching process is used to heat-treat the portion of the second doped silicon glass layer 24 corresponding to the first region 14 and the spacing region 16. At this time, as shown in FIG22 , the density of the laser-treated portion of the second doped silicon glass layer 24 becomes poorer and is easily removed. The portion of the second doped silicon glass layer corresponding to the second region 15 has not been laser processed. At this time, the portion of the second doped silicon glass layer 24 corresponding to the second region 15 has a higher density and is not easy to be removed. As a result, after heat treatment, different portions of the second doped silicon glass layer 24 have different etching selectivities, thereby obtaining a second mask layer 20 for patterning the second doped semiconductor layer 13. There is no need to additionally form other mask materials or other mask deposition processes in order to obtain the above-mentioned second mask layer 20, which is beneficial to reducing the manufacturing cost of the back-contact battery and simplifying the manufacturing process of the back-contact battery.

[0136] The specific conditions of the laser etching process can be set according to the actual application scenario and are not specifically limited here. For example, the laser used in the laser etching process can be a nanosecond laser, a picosecond laser, or a femtosecond laser. The laser etching process can have a power greater than or equal to 10W and less than or equal to 100W, and the laser spot diameter can be greater than or equal to 50μm and less than or equal to 350μm.

[0137] Of course, when the material of the second doped semiconductor layer 13 includes silicon, or when the material of the second doped semiconductor layer 13 does not include silicon, chemical vapor deposition and doping processes can also be used to form the entire second doped semiconductor layer 13 disposed on the backlight side. Then, chemical vapor deposition and etching processes can be used to form a second mask layer 20 made of other materials such as silicon nitride that have a masking function.

[0138] Furthermore, after forming the second mask layer 20, a wet chemical process or other process can be employed, and under the masking action of the second mask layer 20, the portion of the second doped semiconductor layer 13 located on the spacer region 16 and the first doped semiconductor layer 14 can be selectively removed. Furthermore, the surface of the spacer region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15 to prevent damage to the silicon substrate 11 caused by the high-temperature laser, thereby improving the yield of the back-contact cell. Specifically, the process conditions for selectively etching the second doped semiconductor layer 13 can be determined based on the etching process used, the material of the second doped semiconductor layer 13, and the depth of the recess of the surface of the spacer region 16 into the silicon substrate 11, and are not specifically limited herein.

[0139] Then, as shown in Figure 27, the surface of the spacing region 16 is recessed into the silicon substrate relative to the surface of the second region 15, and the bottom surface of the spacing region 16, the first side surface of the spacing region 16 close to the first region 14, and the second side surface of the spacing region 16 close to the second region 15 are textured so that the bottom surface, the first side surface and the second side surface of the spacing region 16 all form a velvet surface.

[0140] In the actual manufacturing process, as shown in Figures 24 to 26, in the process of forming the above-mentioned second doped semiconductor layer 13, if the above-mentioned second mask layer is formed, the surface of the spacer region 16 can be concave into the silicon substrate relative to the surface of the second region 15 under the masking action of the second mask layer, and the above-mentioned texturing treatment can be performed on the bottom surface of the spacer region 16, the first side surface of the spacer region 16 close to the first region 14, and the second side surface of the spacer region 16 close to the second region 15.

[0141] Specifically, the specific process of the above-mentioned texturing treatment can be determined according to the morphology of the velvet structure on the bottom surface, the first side surface and the second side surface of the spacing region 16. For example, as shown in FIG25 , after completely removing the portion of the second doped semiconductor layer 13 located on the first doped semiconductor layer 12 and the spacing region 16, the bottom surface of the spacing region 16 can be subjected to a first texturing treatment to form a pre-formed velvet structure on the bottom surface of the spacing region 16. Then, as shown in FIG26 , the bottom surface, the first side surface and the second side surface of the spacing region 16 are subjected to a second texturing treatment to adjust the morphology of the pre-formed velvet structure and to form velvet on the first side surface and the second side surface. In this case, the first texturing treatment is first performed on the bottom surface of the spacing region 16 to form a pre-formed velvet structure on the bottom surface of the spacing region 16. The bottom surface, the first side surface and the second side surface of the spacer area 16 are further subjected to a second texturing treatment to ensure that the first side surface and the second side surface form a velvet surface. At the same time, the morphology of the pre-formed velvet structure can be adjusted to ensure that the surface of the spacer area 16 has a lower reflectivity, further increasing the amount of light absorbed by the backlight side of the back contact battery, thereby improving the photoelectric conversion efficiency of the back contact battery.

[0142] Specifically, the morphology and size of the preformed texture structure formed on the bottom surface of the spacer region 16 after the first texturing treatment can refer to the morphology and size of the texture structure on the bottom surface of the spacer region 16 in the manufactured back contact battery.

[0143] For example, as shown in FIG25 , the preformed velvet structure may be a pyramid-like structure. In this case, when the preformed velvet structure is a pyramid-like structure, it is advantageous that after the second velvet treatment, the velvet structure of the bottom surface of the spacer region 16 has a pyramid-like morphology, further increasing the specific surface area of ​​the bottom surface of the spacer region 16 and reducing its reflectivity.

[0144] Exemplarily, the height of the preformed velvet structure may be greater than or equal to 0.5 μm and less than or equal to 3 μm. For example, the height of the preformed velvet structure may be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, or 3 μm. In this case, if the height of the preformed velvet structure is within the above range, the specific surface area of ​​the bottom surface of the spacer region 16 may be prevented from being smaller due to the smaller height of the preformed velvet structure, thereby ensuring that the bottom surface of the spacer region 16 has a lower reflectivity. At the same time, it can also prevent the bottom surface of the spacing area 16 from needing to be recessed deeper into the silicon substrate 11 relative to the surface of the second area 15 due to the large height of the pre-formed velvet structure, resulting in a large corrosion depth of the portion of the silicon substrate 11 corresponding to the spacing area 16, which is conducive to the realization of thin-film production; secondly, in the case that the pre-formed velvet structure is a pyramid-like structure, the height of the pre-formed velvet structure is within the above-mentioned range, which can also prevent the number of pre-formed velvet structures formed on the bottom surface of the spacing area 16 from being small due to the overall size of the pre-formed velvet structure being large due to the large height of the pre-formed velvet structure, thereby ensuring that the surface of the spacing area has a good light-trapping effect after the second velvet treatment.

[0145] In addition, the embodiment of the present invention does not specifically limit the conditions of the above-mentioned first texturing treatment and the second texturing treatment, as long as a pre-formed velvet structure with corresponding morphology can be formed on the bottom surface of the spacing area 16 after the first texturing treatment, and a velvet structure that meets the corresponding morphology requirements can be formed on the bottom surface, first side surface and second side surface of the spacing area 16 after the second texturing treatment.

[0146] Specifically, the wet chemical etching solution used in the second texturing treatment contains a texturing additive to ensure that a velvet surface is formed on the first and second side surfaces after the second texturing treatment, thereby reducing the reflectivity of the first and second side surfaces. The type of texturing additive and its volume ratio in the wet chemical etching solution can be determined based on the size of the velvet structure and the actual application scenario. For example, the texturing additive may include sodium benzoate, a defoaming agent, and a surfactant.

[0147] Exemplarily, the volume ratio of the above-mentioned texturing additive in the wet chemical etching solution can be greater than or equal to 0.01% and less than or equal to 5%. For example, the volume ratio of the texturing additive in the wet chemical etching solution can be 0.01%, 0.5%, 1%, 2%, 3%, 4% or 5%, etc. In this case, the volume ratio of the texturing additive in the wet chemical etching solution is within the above-mentioned range, which can prevent the velvet structure formed on the first side surface and the second side surface after the second texturing treatment from being smaller in size and / or smaller in number due to the relatively small volume, thereby ensuring that the first side surface and the second side surface have higher surface roughness after the second texturing treatment; it can also prevent the morphology of the velvet structure formed based on the pre-formed velvet structure on the bottom surface of the spacing area after the second texturing treatment from being adjusted to a large extent due to the relatively large volume, thereby ensuring that the surface of the spacing area has a good light trapping effect.

[0148] Exemplarily, the processing temperature of the above-mentioned second texturing treatment may be greater than or equal to 50°C and less than or equal to 85°C. In addition, the processing time of the second texturing treatment may be greater than or equal to 30s and less than or equal to 240s. For example, the processing temperature of the second texturing treatment may be 50°C, 55°C, 60°C, 65°C, 70°C, 75°C, 80°C or 85°C, etc. In addition, the processing time of the second texturing treatment may be 30s, 50s, 100s, 150s, 200s or 240s, etc. In this case, both the processing temperature and processing time of the second texturing treatment will affect the size of the velvet structure formed on the bottom surface, the first side surface and the second side surface of the spacing area by the second texturing treatment. Based on this, the processing temperature of the second texturing treatment is within the above-mentioned range, which can prevent the velvet structure from being smaller in size due to a lower processing temperature. In addition, it can also prevent the velvet structure from being larger in size due to a higher processing temperature. Among them, the beneficial effects of preventing the velvet structure from being larger or smaller in size can be referred to the above. Secondly, the beneficial effects of the treatment time within the above range are similar to the beneficial effects of the treatment temperature being greater than or equal to 50° C. and less than or equal to 85° C., and will not be repeated here.

[0149] It should be noted that when the manufactured back-contact battery also includes a second passivation layer located between the second region and the second doped semiconductor layer, the manufacturing method of the back-contact battery, after the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, and before the second doped semiconductor layer is formed on part of the second region, also includes the step of: using a deposition and etching process to first form a second passivation layer on the second region.

[0150] Alternatively, as shown in FIG20 , after the surfaces of the spacer region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14, and before the second doped semiconductor layer 13 is formed on a portion of the second region 15, a second passivation layer 18 can be deposited on the first doped semiconductor layer 12, the second region 15, and the spacer region 16 using a process such as chemical vapor deposition. Then, as shown in FIG23 and FIG24 , after forming a second mask layer 20 and selectively etching the second doped semiconductor layer 13 under the masking action of the second mask layer 20, the second passivation layer 18 is selectively etched. In this case, there is no need to form an additional mask layer for forming the second passivation layer 18, thereby simplifying the manufacturing process of the back-contact cell.

[0151] In addition, an alignment mark may be formed on the first doped semiconductor layer 12 and / or the second doped semiconductor layer 13 in an appropriate process. For example, after the first doped semiconductor layer 12 and / or the second doped semiconductor layer 13 are formed, the alignment mark may be formed on the first doped semiconductor layer 12 and / or the second doped semiconductor layer 13 using a laser process.

[0152] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0153] While the above description does not provide detailed technical details regarding the patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0154] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A back contact battery, characterized in that: include: A silicon substrate, and a first doped semiconductor layer and a second doped semiconductor layer alternately distributed on a backlight side of the silicon substrate; wherein, The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; on the backlight side of the silicon substrate, the area corresponding to the first doped semiconductor layer is a first area, the area corresponding to the second doped semiconductor layer is a second area, and the area between the first area and the second area adjacent to the first area is a spacing area; The surface of the second region is recessed into the silicon substrate relative to the surface of the first region; the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region; the bottom surface of the spacing region, the first side surface of the spacing region close to the first region, and the second side surface of the spacing region close to the second region are all velvet surfaces.

2. The back contact battery according to claim 1, characterized in that The first side surface and the second side surface are both inclined relative to a horizontal plane, so that the cross-sectional area of ​​the spacing region gradually increases from the light-facing surface to the backlight surface; and / or, The angle between the first side surface of the spacing area and the horizontal plane is greater than or equal to 52° and less than or equal to 58°, and the angle between the second side surface of the spacing area and the horizontal plane is greater than or equal to 52° and less than or equal to 58°; and / or The topography of the textured structures on the first side surface and the second side surface is different from the topography of the textured structure on the bottom surface of the spacing region.

3. The back contact battery according to claim 1 or 2, characterized in that The longitudinal sections of the first side surface and the second side surface are sawtooth-shaped; and / or, The suede structures on the first side surface and the second side surface are both triangular prism-like structures.

4. The back contact battery according to claim 1 or 2, characterized in that The velvet structure on the bottom surface of the spacing area is a pyramid-like structure.

5. The back contact battery according to claim 1, characterized in that The depth of the surface of the second region recessed into the silicon substrate relative to the surface of the first region is greater than or equal to 0.5 μm and less than or equal to 3 μm; and / or, A bottom surface of the spacer region is recessed into the silicon substrate by a depth greater than or equal to 2.5 μm and less than or equal to 9 μm relative to a surface of the first region.

6. The back contact battery according to claim 1, characterized in that The back contact cell further includes a first passivation layer located between the silicon substrate and the first doped semiconductor layer; and / or, The back contact cell further comprises a second passivation layer located between the silicon substrate and the second doped semiconductor layer; and / or, The surface of the first region and / or the second region is flat.

7. The back contact battery according to claim 1, characterized in that The back-contact cell further includes an alignment mark located on the first doped semiconductor layer and / or the second doped semiconductor layer.

8. A method for manufacturing a back contact battery, characterized in that: include: A silicon substrate is provided; a backlight surface of the silicon substrate has first and second regions alternately spaced and a spacing region between the first and second regions; forming a first doped semiconductor layer on the first region, and making the surfaces of the second region and the spacer region concave into the silicon substrate relative to the surface of the first region; forming a second doped semiconductor layer in the second region; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types; The surface of the spacing area is recessed into the silicon substrate relative to the surface of the second area, and the bottom surface of the spacing area, the first side surface of the spacing area close to the first area, and the second side surface of the spacing area close to the second area are subjected to a texturing treatment so that the bottom surface of the spacing area, the first side surface, and the second side surface all form a texturing surface.

9. The method for manufacturing a back contact battery according to claim 8, characterized in that: The texturing process is performed on the bottom surface of the spacer area, the first side surface of the spacer area close to the first area, and the second side surface of the spacer area close to the second area, comprising: performing a first texturing process on the bottom surface of the spacer area to form a preformed texturing structure on the bottom surface of the spacer area; A second texturing treatment is performed on the bottom surface of the spacing area, the first side surface, and the second side surface to adjust the morphology of the pre-formed texture structure and form texture on the first side surface and the second side surface.

10. The method for manufacturing a back contact battery according to claim 9, characterized in that: The preformed velvet structure is a pyramid-like structure; and / or the height of the preformed velvet structure is greater than or equal to 0.5 μm and less than or equal to 3 μm; and / or, The wet chemical etching solution used in the second texturing treatment contains a texturing additive, and the volume ratio of the texturing additive in the wet chemical etching solution is greater than or equal to 0.01% and less than or equal to 5%; and / or, the processing temperature of the second texturing treatment is greater than or equal to 50°C and less than or equal to 85°C; and / or, the processing time of the second texturing treatment is greater than or equal to 30s and less than or equal to 240s.

11. The method for manufacturing a back contact battery according to claim 8, wherein: The step of forming a first doped semiconductor layer on the first region and causing surfaces of the second region and the spacer region to be recessed into the silicon substrate relative to the surface of the first region comprises: forming a first doped semiconductor layer as a whole layer on the backlight surface of the silicon substrate, and a first mask layer located on a portion of the first doped semiconductor layer corresponding to the first region; then, under the masking action of the first mask layer, selectively removing portions of the first doped semiconductor layer located on the spacer region and the second region; and causing surfaces of the spacer region and the second region to be recessed into the silicon substrate relative to the surface of the first region; and / or, The manufacturing method of the back-contact battery includes, after making the surfaces of the second region and the spacer region concave into the silicon substrate relative to the surface of the first region, performing the following steps: depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacer region and the second region; and forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region; then, under the masking action of the second mask layer, selectively removing the portion of the second doped semiconductor layer corresponding to the first region and the spacer region; and making the surface of the spacer region concave into the silicon substrate relative to the surface of the second region, and performing the texturing treatment on the bottom surface of the spacer region, the first side surface of the spacer region close to the first region, and the second side surface of the spacer region close to the second region.

12. The method for manufacturing a back contact battery according to claim 11, wherein: The material of the first doped semiconductor layer includes silicon; The first doped semiconductor layer formed entirely on the backlight surface of the silicon substrate and the first mask layer located on a portion of the first doped semiconductor layer corresponding to the first region include: forming a first intrinsic semiconductor layer on the backlight surface of the silicon substrate; performing a doping treatment on the first intrinsic semiconductor layer so that the first intrinsic semiconductor layer forms the first doped semiconductor layer, and forming a first doped silicon glass layer entirely disposed on the first doped semiconductor layer; performing heat treatment on portions of the first doped silicon glass layer corresponding to the spacer region and the second region, so that portions of the first doped silicon glass layer not subjected to the heat treatment form the first mask layer; The heat-treated portion of the first doped silicon glass layer is removed.

13. The method for manufacturing a back contact battery according to claim 11, wherein: A wet chemical process is used to selectively remove portions of the first doped semiconductor layer located on the spacer region and the second region under the masking action of the first mask layer; and surfaces of the spacer region and the second region are recessed into the silicon substrate relative to the surface of the first region; wherein, The process temperature of the wet chemical process is greater than or equal to 60°C and less than or equal to 85°C; and / or, the process time of the wet chemical process is greater than or equal to 40s and less than or equal to 300s; and / or, the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is greater than or equal to 2% and less than or equal to 20%; and / or, the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is greater than or equal to 0.5% and less than or equal to 5%.

14. The method for manufacturing a back contact battery according to claim 11, wherein: The material of the second doped semiconductor layer includes silicon; depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacer region and the second region; and forming a second mask layer on a portion of the second doped semiconductor layer corresponding to the second region, comprising: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spacer region, and the second region; performing a doping treatment on the second intrinsic semiconductor layer so that the second intrinsic semiconductor layer forms a second doped semiconductor layer, and forming a second doped silicon glass layer entirely disposed on the second doped semiconductor layer; performing heat treatment on a portion of the second doped silicon glass layer corresponding to the first region and the spacer region, so that the portion of the second doped silicon glass layer corresponding to the second region forms the second mask layer; The heat-treated portion of the second doped silicon glass layer is removed.

15. The method for manufacturing a back contact battery according to any one of claims 8 to 14, characterized in that: The method for manufacturing a back-contact battery further includes: forming a first passivation layer on the first region before forming the first doped semiconductor layer on the first region; and / or, The method for manufacturing a back-contact battery further includes forming a second passivation layer on the second region before forming a second doped semiconductor layer on a portion of the second region.

16. The method for manufacturing a back contact battery according to any one of claims 8 to 14, characterized in that: The method further includes forming an alignment mark on the first doped semiconductor layer and / or the second doped semiconductor layer.

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