A method of generating a quantum control signal

Abstract

Disclosed herein is a computer-implemented method for generating an output signal which approximates a desired signal, the output signal being for use in a quantum control system. The desired signal comprises a first and a second region, the first region being symmetric with the second region, and the desired signal is segmented into a plurality of segments. The method comprises retrieving, from one or more memory elements, one or more first parameter values for each segment in the first region, and using a first iterative algorithm and the retrieved one or more first parameter values to generate at least one value of the output signal for each segment in the first region. The method further comprises using a second iterative algorithm and one or more second parameter values to generate at least one value of the output signal for each segment in the second region, wherein the one or more second parameter values are generated based on the one or more first parameter values.

Description

[0001]A METHOD OF GENERATING A QUANTUM CONTROL SIGNAL This disclosure relates to generating a signal, and in particular to methods and associated systems for generating a signal for use in a quantum control system. Background Although they have become exponentially faster over the preceding decades, the “classical” computers of today are effectively limited to solving the same classes of problems as the first digital computers developed during the mid-twentieth century. In contrast, by exploiting the peculiarities of quantum physics, “quantum” computers promise to solve problems that are intractable on classical computers, such as factoring large numbers and simulating quantum systems. Control signals such as radiofrequency (RF) pulses are important tools for controlling quantum systems, and for performing the quantum operations required for realising quantum computers. Many, if not all, quantum computing architectures are controlled via RF pulses. Control over parameters such as the time-dependent amplitude, phase and frequency of the RF pulse is important to attain maximal efficiency and to mitigate errors. For signals comprising a large array of data, it is untenable to load the time resolved pulse parameters into a memory of the control electronics as a time indexed array. Interpolation techniques such as cubic spline interpolation can be used to address this issue. Spline interpolation is a technique which involves dividing a desired signal into segments. The desired signal can be approximated within each segment using an interpolating polynomial, which in turn can be defined using one or more polynomial coefficients. However, there is a trade-off: the accuracy of the cubic spline interpolation increases with the number of segments, but increasing the number of segments requires more memory. Accurate pulse generation is invaluable for controlling quantum systems, but using more spline segments and consuming more memory becomes particularly problematic when control of a system demands a large number of individual pulses, for example when the system has a large number of qubits. The present invention seeks to address these and other disadvantages encountered in the prior art by providing an improved method for generating a signal for use in a quantum control system. Summary According to a first aspect of the invention, there is provided a computer-implemented method for generating an output signal which approximates a desired signal, the output signal being for use in a quantum control system. The desired signal comprises a first and a second region, the first region being symmetric with the second region, and the desired signal is segmented into a plurality of segments. The method comprises retrieving, from one or more memory elements, one or more first parameter values for each segment in the first region, and using a first iterative algorithm and the retrieved one or more first parameter values to generate at least one value of the output signal for each segment in the first region. The method further comprises using a second iterative algorithm and one or more second parameter values to generate at least one value of the output signal for each segment in the second region, wherein the one or more second parameter values are generated based on the one or more first parameter values. The method exploits symmetry within a desired signal such that a reduced number of parameters need to be stored in order to approximate a desired signal on hardware. A reduced number of parameters allows for a reduced memory overhead, which is particularly useful when reconstructing desired signals comprising large arrays of data. Reducing memory overhead is also particularly useful in this context of communicating with quantum control systems, due to the sheer volume of data associated with these carefully-controlled systems. Optionally, generating the at least one value of the output signal for each segment in the first region comprises, for each segment in the first region, inputting the one or more first parameter values into the first iterative algorithm to generate at least one value of the output signal. The first iterative algorithm comprises iteratively updating the one or more first parameters until one or more updated first parameter values are reached for each of the one or more first parameter values, wherein the at least one value of the output signal is generated based on the one or more updated first parameter values. Optionally, the one or more updated first parameter values are the one or more second parameter values. In this way, the updated first parameter values produced for a particular segment in the first region via the first iterative algorithm may be used as the starting parameters of the second iterative algorithm in a corresponding segment in the second region. Optionally, each iteration of the first iterative algorithm generates a respective value of the output signal. Optionally, for each segment, the one or more updated first parameter values are reached during a final iteration of the first iterative algorithm. Optionally a predetermined number of values of the output signal are generated for each segment according to a sampling rate, and the final iteration of the first iterative algorithm for each segment is reached when the predetermined number of values of the output signal have been reached. In an implementation, the algorithm is provided with initial, ‘first’ parameter values for each segment, e.g. one or more of ^^^^0, ^^^^0, ^^^^0, ^^^^0which will be described in greater detail below. Each iteration of the first algorithm generates a value of the output signal. The number of iterations changes depending on how many values of the output signal are to be generated for the segment in question, which may be determined by a sampling rate and may be different for each segment if the lengths of each segment are not uniform. The first iterative algorithm is iterated until the necessary number of output values have been generated for the segment in question. The final iteration of Bowler’s algorithm for a segment generates the final output value for thatsegment, and is generated using the final parameter values, e.g. one or more of At the end of this final iteration, the parameters are deemed the “updated’ first parameters. These updated first parameters may also be described as “final” first parameters for the segment. These parameters may be the “second parameters” which are used as the starting parameters for the second iterative algorithm in a corresponding segment in the second region. Optionally, generating the at least one value of the output signal for each segment in the second region comprises, for each segment in the second region, inputting the one or more second parameter values into the second iterative algorithm to generate the at least one value of the output signal. The at least one value of the output signal for each segment in the second region may be generated using the second parameter values at any stage of the second iterative algorithm. Optionally, a value of the desired signal varies with a variable parameter. Optionally, the first region is defined between a first region starting value and a first region ending value of the variable parameter, and the second region is defined between a second region starting value and a second region ending value of the variable parameter. Optionally, the first region ending value is equal to the second region starting value to define a symmetrical centre point halfway between the first region starting value and the second region ending value. Optionally, the variable parameter is time and each segment has a length, wherein the sum of the lengths of each segment in the first region is equal to the sum of the lengths of each segment in the second region. Optionally, the generated signal is used for shaping a control pulse of a quantum control system. Optionally, the generated signal is an envelope signal, and shaping the control pulse comprises one of modulating an amplitude of the control pulse and modulating a phase envelope of the control pulse. Optionally, each segment in the first region is associated with one or more polynomial coefficients and, for each segment in the first region, the one or more polynomial coefficients define an interpolating polynomial that approximates values of the desired signal within the segment. Optionally, for each segment in the first region, the one or more first parameter values for the segment are based on the polynomial coefficients for the segment. Optionally, the method may further comprise generating the one or more first parameter values for each segment in the first region based on the polynomial coefficients. Optionally, the method may further comprise generating the one or more polynomial coefficients for each segment in the first region using a fitting algorithm. Optionally, the first iterative algorithm comprises a plurality of addition steps and the second iterative algorithm comprises a plurality of corresponding subtraction steps, or the first iterative algorithm comprises a plurality of subtraction steps and the second iterative algorithm comprises a plurality of corresponding addition steps. Optionally, the plurality of addition steps are performed in a first order, and the plurality of subtraction steps are performed in a second order, the second order being reversed relative to the first order. Optionally, the sum of the number of segments in the first region and the number of segments in the second region is an even number. Optionally, the method may further comprise segmenting the desired signal into the plurality of segments. Optionally, each segment in the first region has a corresponding segment in the second region, and the one or more second parameter values for a particular segment in the second region are generated based on the one or more first parameter values from a segment in the first region which corresponds with the particular segment in the second region. Optionally, values of the desired signal in corresponding segments are symmetric with each other. Optionally, the values of the desired signal in corresponding segments are equal but reversed in order relative to one another. Optionally, the desired signal comprises a third and a fourth region, the third region being symmetric with the fourth region. The method further comprises obtaining one or more third parameter values for each segment in the third region. The method further comprises using the first iterative algorithm and the one or more third parameter values to generate at least one value of the output signal for each segment in the third region. The method further comprises using the second iterative algorithm and one or more fourth parameter values to generate at least one value of the output signal for each segment in the fourth region, wherein the one or more fourth parameter values are generated based on the one or more third parameter values. Optionally, obtaining the one or more first parameter values for each segment in the first region comprises retrieving the one or more first parameter values from one or more memory elements. According to a second aspect of the invention, there is provided a computer-readable medium comprising instructions which, when executed by one or more processors, cause the one or more processors to perform any of the above methods, or any of the methods disclosed herein. According to a third aspect of the invention, there is provided an apparatus for generating a signal for use in a quantum control system, the apparatus comprising one or more memory elements, and one or more processors configured to perform any of the above methods, or any of the methods disclosed herein. Optionally, the apparatus is a pulse shaper configured to shape a control pulse of the quantum control system. According to a fourth aspect of the invention, there is provided a quantum control system comprising a quantum computer comprising one or more qubits. The system further comprises a pulse generator configured to generate a control pulse for controlling a state of the one or more qubits. The system further comprises a pulse shaper configured to shape the control pulse generated by the pulse generator using an output signal. The pulse shaper comprising one or more memory elements and one or more processors configured to generate the output signal by performing any of the above methods, or any of the methods disclosed herein. Figures Specific implementations are now described, by way of example only, with reference to the drawings, in which: Fig.1a is a graph depicting a desired signal segmented into a plurality of segments and an optimised fit to the desired pulse using standard cubic spline interpolation; Fig.1b is a graph depicting the error between the desired signal and the optimised fit shown in Fig. 1a; Fig.2 depicts the desired signal shown in Fig.1a; Fig.3 depicts a method according to the present disclosure; Fig.4a depicts a graph of a desired signal segmented into a plurality of segments and an optimised fit to the desired pulses which exploits a region of symmetry according to the methods of the present disclosure; Fig.4b is a graph depicting the error between the desired pulse and the optimised fit shown in Fig.4a; Fig.5a depicts a logic diagram for an implementation of a first, additive iterative algorithm according to the present disclosure; Fig.5b depicts a logic diagram for an implementation of a second, subtractive iterative algorithm according to the present disclosure; Fig.6 depicts a structure of an apparatus for generating a signal according to the present disclosure; Fig.7 depicts a computer architecture which may be used to perform the methods of the present disclosure; Fig.8 depicts a computer-readable medium according to the present disclosure. Detailed Description In overview, and without limitation, the application discloses a method for generating a signal, such as a signal suitable for use in a quantum control system. The generated signal may be suitable for shaping or otherwise modulating a control pulse, for example. The skilled person will be familiar with fitting algorithms based on interpolation methods, such as cubic spline interpolation. Using these methods, a desired signal can be segmented into multiple segments, and an interpolating polynomial can be found for each segment which approximates the desired signal within the segment. The interpolating polynomial for each segment may be defined by one or more polynomial coefficients. The interpolating polynomials for each segment, or else other parameters generated based on these coefficients, may be loaded into memory for use by a signal generator. The signal generator then uses these coefficients when generating an output signal that approximates the desired signal. However, the memory load associated with loading all these parameters into memory for every segment of the desired signal can be high. It is possible to reduce the memory load associated with this technique by reducing the number of segments, however this can adversely affect the accuracy of the output signal. The present method involves exploiting one or more regions of symmetry in the desired signal. By exploiting regions of symmetry, it is possible to significantly reduce the number of parameters which need to be loaded into memory, thereby reducing memory load without increasing the fitting error. As explained herein, for a desired signal that is entirely symmetric, for example about a central point of symmetry, the memory load can be halved. Alternatively, by using the presently disclosed methods, it is possible to significantly improve the fitting accuracy by increasing the number of segments, without incurring the cost of increased memory load which would otherwise be incurred using existing approaches. Figs.1a and 1b help depict the current state of the art when it comes to cubic spline interpolation techniques. Both figures depict a graph, with the x axis depicting duration in unit clock cycles. The y axis of Fig.1a depicts an amplitude displayed in the form of 16 bit integer values and the y axis of Fig.1b depicts an absolute percentage error. Fig.1a depicts the polynomial fit of a desired pulse using a fitting algorithm. Specifically, Fig.1a depicts polynomial fitting using cubic spline interpolation. The desired pulse is displayed in Fig.1a as a Gaussian pulse which is symmetric about its centre in amplitude. The desired pulse is displayed as a solid line and denoted by the label ‘Desired pulse’. The desired pulse has been split into segments, with boundaries displayed as vertical dashed lines and denoted by the label ‘segment boundary’. The standard fit to the desired pulse, using cubic spline interpolation, is displayed as a solid line and denoted by the label ‘Generated pulse’, showing a 36-bit representation. As would be expected, the desired pulse and depicted standard fit are very similar to one another and are hard to distinguish on the graph. The desired signal / pulse can be defined by a function, and herein terms such as ‘pulse’, ‘signal’ and ‘function’ may be used interchangeably. The desired pulse may be reconstructed using interpolation methods, such as spline interpolation. An example of a suitable interpolation technique is cubic spline interpolation. Cubic spline interpolation can be used to represent an arbitrary, smooth, continuous function defined over a domain. The function has been segmented into a plurality of segments, where each segment may satisfy continuity at the segment boundary in amplitude and first derivative. This may also be extended to second derivatives. One or more polynomial coefficients for a particular segment define an interpolating polynomial that approximates values of the desired signal within the particular segment. In the depicted example, eachsegment is associated with stored coefficients ^^^^, ^^^^, ^^^^ and ^^^^ which define a cubic function of the form ^^^^(^^^^) =^^^^ + ^^^^^^^^ + ^^^^^^^^2 + ^^^^^^^^3. ^^^^(^^^^) may be an amplitude of the function within the segment with a variable parameter^^^^. ^^^^(^^^^)may represent any relevant quantity associated with the function, for example amplitude or phase. ^^^^ may represent any relevant quantity that varies with the function, for example time, such as in unit clock cycles, or spatial dimensions. Although cubic spline interpolation is described herein, any fitting algorithm may be used, such as any polynomial spline interpolation. For example, if instead quadratic spline interpolation is used, there may only be three stored coefficients for the quadratic function within each segment. In Fig.1a, the signal has been segmented into a plurality of segments. Specifically, in Fig.1a, the desired pulse is segmented into 8 segments, with each segment defined by segment boundaries. Here, the desired signal has a duration of 800 clock cycles and each segment of the 8 segments has a duration of 100 clock cycles. Each segment is associated with polynomial coefficients which define the cubic function in that segment, for example coefficients ^^^^, ^^^^, ^^^^ and ^^^^. In Fig.1a, each segment where the cubic coefficients are stored in memory is shaded. In Fig.1a the curve shown by standard cubic spline interpolation looks similar to the desired pulse, however the difference between the two is quantitatively shown in Fig.1b, as discussed below. The fitting algorithm used to generate the polynomial coefficients within each segments is a known algorithm according to the state of the art. A standard gradient-based minimisation algorithm has been used to fit interpolating polynomials to each segment. In particular, the scipy.CubicSpline module in python has been used to fit functions to the cubic spline segments in Fig.1a. Fig.1b depicts the difference between the desired pulse and the reconstructed pulse using spline interpolation methods. Specifically, Fig.1b depicts the absolute value of the percentage error between the desired pulse and the curve reconstructed by cubic spline interpolation, assuming perfect floating point arithmetic to isolate the error in pulse representation arising from the curve fitting. The error is displayed as a solid line and denoted by the label ‘Relative error’. The error between the desired signal and reconstructed signal can be measured in metrics such as the average least squares or maximum least squares absolute percentage error. In Fig.1b, the maximum least squares error is 1.13% and the average least squares error is 0.358%. A time-consuming and / or memory inefficient way of calculating values of the signal may be to compute the cubic function ^^^^(^^^^) at the desired values of ^^^^ with the stored coefficients. For example, if the user would like tocalculate the value of the signal ^^^^(^^^^) in the segment 202a at the value ^^^^ = 10 clock cycles with the storedcoefficients ^^^^ = 1, ^^^^ = 2, ^^^^ = 3 and ^^^^ = 4, the value of the signal could be calculated by performing ^^^^(10) =1 + (2 × 10) + (3 × 102) + (4 × 103). These values of the signal ^^^^(^^^^) could then be stored as a large time-indexed array. This requires a substantial amount of time to calculate each value of ^^^^(^^^^) and a substantial amount of memory to store the entire time-indexed array of these values. It is of interest to reduce the absolute percentage error between the desired pulse and the reconstructed pulse. Large errors in the spline interpolation compared to the desired pulse are undesirable when a generated pulse is for use in systems such quantum control systems. Errors in the signal may lead to problems such as incorrectly manipulating qubits or incorrectly reading qubit states. Fig.2 depicts a graph of the same desired signal as in Fig.1a. Each segment used in the cubic spline interpolation is labelled as 202a-d and 204a-d. The desired signal is again depicted by a solid line and has a duration of 800 clock cycles. The desired signal displays some symmetry, and comprises a region of symmetry. The desired signal, and region of symmetry, can be split into a first region and a second region, the first region being symmetric with the second region. The first and second region are symmetric about a symmetry centre point 210. In the depicted example, the symmetry centre point 210 has a value of 400 clock cycles. A first region of the desired signal is defined by segments 202a-d, and a second region of the desired signal is defined by segments 204a-d. The two segments closest to the symmetry-centre point 210 are symmetric with one another, the two next- closest segments to the symmetry-centre point 210 are symmetric with one another, and so on. In other words, and with reference to Fig.2, segments 202a and 204a are symmetric with each other, segments 202b an 204b are symmetric with each other, and so on. In this way, each segment 202, 204 in the region of symmetry comprises a corresponding segment. Segment 202a corresponds with segment 204a, segment 202b corresponds with segment 204b, and so on. The sum of the number of segments 202a-d in the first region and in the second region 204a-d is an even number. The values of the desired signal in corresponding segments are equal, but reversed with respect to the variable parameter. It will be appreciated that, when starting at the symmetry-centre point 210, the desired signal has the same values, regardless of the direction moved in. The first region is defined between two values of the variable parameter. The first region is defined between a first region starting value 211, and a first region ending value. The second region is defined between a second region starting value and a second region ending value 212. In the depicted example of a gaussian-like desired pulse, the first region ending value and second region starting value are the same point, the symmetry centre point 210. In the depicted example, the variable parameter is time, in units of number of clock cycles, and therefore each segment has a length measurable in time. The sum of the lengths of each segment 202 in the first region is equal to the sum of the lengths of each segment 204 in the second region. Considering all the segments of the desired signal, i.e. not just those which are part of the region of symmetry, the sum of the lengths of each segment of the plurality of segments equals the total duration of the signal. Fig.3 depicts a method 300 according to the present disclosure. The method is suitable for generating an output signal which approximates a desired signal. The method 300 makes use of iterative algorithms and exploits one or more regions of symmetry in a desired signal when generating the output signal. An example of a desired signal is provided in Fig.2, which shows a desired signal comprising a first region and a second region which are symmetric with one another. The method 300 comprises blocks 302, 304 and 306. At block 302, one or more first parameter values are obtained for each segment in the first region of the desired signal. The one or more first parameter values may be retrieved from one or more memory elements, such as memory elements embodied on suitable hardware such as a field programmable gate array (FPGA), as will be discussed later. With reference to the example depicted in Fig.2 and described above, one or more first parameter values are obtained for each segment 202a-d in the first region. The one or more first parameter values are suitable for inputting into a first iterative algorithm at block 304. The one or more first parameter values may comprise, or be generated based on, polynomial coefficients. As described above with respect to Fig.2, each segment in the first region is associated with one or more polynomial coefficients. These polynomial coefficients may have been generated by a fitting algorithm and loaded into one or more memory elements, for example, such that at block 302 these polynomial coefficients can be retrieved when an output signal is to be generated. While not shown in method 300, the methods disclosed herein may additionally comprise generating the one or more polynomial coefficients for each segment in the first region using the fitting algorithm and / or storing them in the one or more memory elements, ready for retrieval. The polynomial coefficients for a particular segment define an interpolating polynomial that approximates values of the desired signal within the particular segment. Block 302 may comprise obtaining the four polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ for each segment in the first region of the desired signal. For example, with respect to Fig.2, block 302 may comprise: retrieving or otherwise obtaining the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ which are used to describe the polynomial function in the segment 202d, retrieving or otherwise obtaining the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ which are used to describe the polynomial function in the segment 202c, retrieving or otherwise obtaining the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ which are used to describe the polynomial function in the segment 202b, and so on. The iterative algorithms employed in method 300 may take the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ directly as an input; or, the first iterative algorithm may instead take other first parameter values as an input. Instead of taking the polynomial coefficients directly as an input, for example, the first parameter values for a particular segment may be based on, e.g. generated using, the polynomial coefficients for that segment. For example, the first iterative algorithm may take one or more of parameters ^^^^0, ^^^^0, ^^^^0, ^^^^0as an input. In such an implementation, each segment in the first region is associated with a respective ^^^^0, ^^^^0, ^^^^0, ^^^^0.These parameters for each segment have been generated based on the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ for that segment. Depending on the implementation, the algorithms may take a combination of polynomial coefficients and such parameters as an input. Block 302 may therefore comprise retrieving one or more parameters, ^^^^0, ^^^^0, ^^^^0, ^^^^0from the memory elements, depending on the implementation and exact algorithms used at blocks 304 and 306. Block 302 may therefore comprise retrieving a combination of these types of coefficients, depending on the implementation. The first parameters obtained at block 302 may be the starting values of the Bowler’s algorithm, which will be described later. At block 304, a first iterative algorithm and the obtained one or more first parameters are used to generate at least one value of the output signal for each segment in the first region. Preferably, the one or more values are a plurality of values of the output signal. In this way, the desired signal is approximated within each segment of the first region. The first iterative algorithm is an algorithm that involves using iteration, or equivalently recursion. Herein, the words iterative and recursive may be used interchangeably. Direct computation of the signal values in each segment, using multiplication operations, would be costly on the type of hardware typically used for control electronics, e.g. FPGAs. Therefore, the first iterative algorithm uses a plurality of addition steps, and preferably a series of steps which comprise only additive steps, to generate signal values. The first iterative algorithm may therefore be described as an additive iterative algorithm. A suitable iterative algorithm is Bowler’s algorithm, described in detail below. The steps of the first iterative algorithm are performed in a first order. As discussed above, a fitting algorithm may have been used to generate polynomial coefficients for each segment, where the polynomial coefficients define an interpolating polynomial for each segment. Using a known algorithm, such as Bowler’s algorithm, the interpolating polynomial’s samples are retrieved using a series of iterative addition steps that can be more easily and efficiently performed by hardware. Block 304 may comprise inputting the one or more first parameter values obtained at block 302 into the first iterative algorithm to generate values of the output signal. The first iterative algorithm comprises iteratively updating one or more parameter values, starting with initial first parameter values ^^^^0, ^^^^0, ^^^^0, ^^^^0. The first parameters are updated at each step of the first iterative algorithm such that, at any iteration ‘t’ of the first iterative algorithm, the parameters may be represented as ^^^^^^^^, ^^^^^^^^, ^^^^^^^^, ^^^^^^^^, until the final iteration of the first iterative algorithm generates the updated, or ‘final’ first parameter values, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^. Each iteration of the first iterative algorithm generates a respective value of the output signal. This means that every value of ^^^^^^^^, ^^^^^^^^, ^^^^^^^^, ^^^^^^^^is associated with a particular output value. For each segment, the final, ‘updated’ first parameter values are reached during a final iteration. A predetermined number of values of the output signal are generated for each segment according to a sampling rate, and the final iteration of the first iterative algorithm for each segment is reached when the predetermined number of values of the output signal have been reached. In other words, the stopping criterion for the first iterative algorithm is when a predetermined number of iterations have been carried out, and the same predetermined number of output values have been generated. At block 306, a second iterative algorithm and one or more second parameter values are used to generate one or more values of the signal for each segment in the second region. The one or more second parameter values are generated based on the one or more first parameter values used at block 304. For example, the updated (or final) first parameter values ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, these updated first parameter values, may be used as the one or more second parameters. When discussing these values within the context of being input into the second iterative algorithm, the values ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, are re-labelled ^^^^′,^^^^′, ^^^^′,^^^^′. These one or more second parameters may be inputted into thesecond iterative algorithm at block 306. In other words, the updated parameter values generated by the first iterative algorithm at block 304 may be inputted into the second iterative algorithm at block 306. Generating the at least one value of the output signal for each segment in the second region may therefore comprise, for each segment in the second region, inputting the one or more second parameter values into the second iterative algorithm to generate the at least one value of the output signal. The second iterative algorithm is an algorithm that involves using iteration, or equivalently recursion. The second iterative algorithm may be closely related to the first iterative algorithm, but uses a plurality of subtraction steps, and preferably a series of steps which comprise only subtraction steps, to generate signal values. The second iterative algorithm may therefore be described as a subtractive iterative algorithm. The steps of the second iterative algorithm may be the same as the steps of the first iterative algorithm, but using subtraction instead of addition and performed in a second order, the second order being reversed relative to the first order. As discussed above with respect to Fig.2, each segment in the first region has a corresponding segment in the second region. Following method 300, the one or more second parameter values for a particular segment in the second region are generated based on the one or more first parameter values from a segment in the first region which corresponds with the particular segment in the second region. The values of the desired signal in corresponding segments are symmetric with each other, and for example the values of the desired signal in corresponding segments are equal but reversed in order relative to one another. For example, the first parameter values within a first segment of a first region of the desired signal may be ^^^^0, ^^^^0, ^^^^0, ^^^^0. At block 304, using the first iterative algorithm, the first parameter values ^^^^0, ^^^^0, ^^^^0, ^^^^0for the first region may be updated to updated first parameter values ^^^^^^^^, ^^^^^^^^, ^^^^^^^^at each time ^^^^ of the first iterative algorithm. The updated parameter values are updated until the end of the segment, and hence the last iteration of the first iterative algorithm, is reached. At the end of the first region, the updated first parameter values ^^^^^^^^, ^^^^^^^^, ^^^^^^^^, ^^^^^^^^are updated to ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, where ^^^^^^^^^^^^^^^^^^^^^^^^denotes the last iteration of the first iterative algorithm within the first region, in this case. The final first parameter values may be the one or more second parameter values used in the second iterative algorithm, at block 306. Therefore the second parameter values may be ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^in a second region of the desired signal. To differentiate between the last iteration of the first parameter values and the first iteration of the secondparameter values, the second parameter values may instead be written as ^^^^′,^^^^′, ^^^^′, ^^^^′ when discussing theuse of these coefficients in a second region. The steps described in Fig.3 may be performed in different orders, but in a preferred implementation, the method generates the output values of the signal “in order”, from a lower value (e.g.0) toward a higher value of the clock cycle (e.g. N). For the example depicted in figure 2, the first parameter values are retrieved for the first segment 202d in the first region at block 302, and values of the output signal are generated for that segment at block 304. The first parameters for the second segment 202c are retrieved at block 302, and values of the output signal are generated for that segment at block 304, and so on until values of the output signal have been generated for every segment in the first region. At the point of symmetry, i.e. at N / 2, the values of the output signal are generated for each of the segments of the second region, in order (e.g.204a, 204b, 204c, and 204d) at block 306. An example of the workflow according to method 300 with respect to the desired signal shown in Fig.2 will now be described. First, at block 302, one or more first parameter values, ^^^^0, ^^^^0, ^^^^0are obtained for a first segment 202d. These parameters are retrieved from memory, such as from one or more memory elements. These first parameters are input into the first iterative algorithm at block 304, and the first parameter values are iteratively updated. At each step of the iteration, the values of ^^^^^^^^, ^^^^^^^^, ^^^^^^^^are updated such that they are used to generate values of the signal in the segment 202d in each iteration. The values of ^^^^^^^^, ^^^^^^^^, ^^^^^^^^, ^^^^^^^^are updated until the final updated first parameter values ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^are reached at the final step of the iteration process for segment 202d. This process may involve performing a series of addition steps in a first order, for example. Then, the initial first parameters ^^^^0, ^^^^0, ^^^^0, ^^^^0for segment 202c are obtained. In segment 202c, once again, the first iterative algorithm is used to generate values of the signal, generating an output value at each iteration, until final first parameter values are reached for the second segment 202c. In this way, blocks 302 and 304 are repeated in an appropriate order until signal values of the output signal have been generated for each of the segments 202d-a in the first region of the desired signal. Then, at block 306, values of the output signal are generated for segment 204a. Segment 204a is in the second region, and has a corresponding segment 202a in the first region. The final parameter values generated by the first iterative algorithm for segment 202a, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^, ^^^^^^^^^^^^^^^^^^^^^^^^^^^^are used as the second parameters^^^^′,^^^^′, ^^^^′, ^^^^′ for segment 204. ^^^^′,^^^^′, ^^^^′,^^^^′ are input into the second iterative algorithm. The second iterativealgorithm involves performing a series of subtraction steps, which correspond with the addition steps used by the first algorithm for the corresponding segment 202a. Just as with the first iterative algorithm, the second iterative algorithm generates a value of the output at each iteration until a final iteration is performed. In this way, output signal values are generated by the second iterative algorithm for segment 204a. Next, output values are generated for the next segment in the second region, segment 204b, by inputting the final first parameter values from the corresponding segment 202b from the first region into the second iterative algorithm. The process continues until the output signal has been generated for each segment 204a-d in the second region. As can be appreciated, the present method exploits the symmetry in one or more regions of the desired signal. The method involves generating an output signal using first parameters for a first region of the signal, and using second parameters for a second region of the signal. However, since the second parameters are generated based on the first parameters, it is only necessary to store the first parameters in memory. This significantly reduces the memory load associated with the present method compared to prior methods of generating a signal, and makes better use of computer resources when generating a signal. Considering the trade-off between the number of segments (and hence accuracy of signal generation) and memory usage, the present method enables improvements on either side of the trade-off depending on the desired implementation. By removing the need to pre-generate and store any parameters for use when generating the signal in the second region, the present method enables improved use of computer resources such as memory, and / or more accurate signal generation. For example, it may be desirable to reduce memory load without increasing the error in the output signal with respect to the desired signal. Methods of the present disclosure enable this aim to be met while keeping the same number of total segments in the desired signal by reducing the number of segments for which parameters need to be pre-generated and loaded into memory. To give an idea of the memory overhead savings which are possible, each segment may contain a total memory load of 8x(3x36+16) bits which is stored and loaded in memory, because ^^^^0is 16 bits and the computation of the first and second iterative algorithms are done using 36 bits. In another example, it may be desirable to improve, i.e. reduce, the error of the output signal with respect to the desired signal without creating a corresponding increase in memory load. Methods of the present disclosure enable this aim to be met by allowing an increase in the number of segments used, without incurring a corresponding increase in memory load. Within each region of symmetry, the number of stored polynomial coefficients needed to generate the signal may be reduced by a half, thereby reducing the memory load. The memory load may be further reduced if there are further degrees of symmetry, for example phase and amplitude of the desired signal. For example, if the desired signal has one or more regions of symmetry in amplitude and the same regions of symmetry in phase of signal, the memory load may be reduced by a factor of 4 within each local region of symmetry. Also, in the case of a segment being identical to another segment, for example in a repeating function, the number of polynomial coefficients needed to be stored may be further reduced. Fig.4a depicts a graph that takes a similar form as Fig.1a, and in particular has the same y and x-axes, and depicts the same Gaussian-like desired signal in solid line. The amplitude of the desired pulse at any point within the pulse duration is the same in Fig.1a and Fig.4a. In Fig.4a, the desired signal is segmented into a plurality of segments, much like the desired signal in Fig.1a, but in Fig.4a the desired pulse is segmented into 16 segments (rather than 8). Each segment is defined by segment boundaries shown by dashed lines in the y- direction. The desired pulse is reconstructed using cubic spline interpolation methods, displayed as a solid line and denoted by the label ‘Generated pulse’, similar to that shown in Fig.1a. In Fig.4a, the signal comprises a first and second region, the first region being symmetric with the second region. The first region comprises the first 8 segments of the 16 segments, between 0 and 400 clock cycles in Fig.4a. The second region comprises the last 8 segments of the 16 segments, between 400 and 800 clock cycles in Fig.4a. The 8 segments in the first region are shaded. The shaded segments depict the segments in which the cubic coefficients used for the cubic spline interpolation are stored to enable the method 300. In Fig. 4a, it is therefore apparent that cubic coefficients need only be stored for the first 8 of the 16 segments. Fig.4a involves 16 segments, whereas Fig.1a involves 8 segments. Fig.4a therefore has double the number of segments as shown in Fig.1a. Using method 300, the fitting error of the spline interpolated signal is improved with respect to the desired signal, compared to the spline interpolated signal in Fig.1a, by doubling the number of segments compared to Fig.1a. Qualitatively, the spline interpolated signal in Fig.4a has an improved fit to the desired signal, compared to the spline interpolated signal in Fig.1a. The quantitative difference between the fit spline interpolated signal and the desired signal is also improved, as can be seen in Fig.4b. Fig.4b depicts the difference between the desired pulse and the reconstructed (output) signal. Specifically, Fig. 4b depicts the absolute value of the percentage error between the desired pulse and the curve reconstructed by cubic spline interpolation, as shown in Fig.4a. Fig.4b shows the same segmentation as in Fig.4a. The graph shown in Fig.4b is similar to the graph shown in Fig.1b, however it shows an improved absolute percentage error from using method 300. In Fig.4b, the maximum least squares error is 0.0544% and the average least squares error is 0.0109%. These error metrics are much improved compared to those from Fig.1b. Therefore, exploiting the symmetry of the desired signal, as described in method 300, enables a desired signal to be split into a larger number of segments while keeping the memory load the same. Therefore the present method reduces an error of a generated output signal. Reducing the error of the output signal in this way leads to further improvements in manipulating qubits and reading qubit states. The first and second iterative algorithm may be based on an algorithm referred to herein as ‘Bowler’s algorithm’ (Bowler, R., ‘Coherent Transport in a Multi-electrode Trap Array’, University of Colorado, 2015, pages 93-94). Bowler’s algorithm is a quick and memory efficient way to generate approximated values of ^^^^(^^^^). Depending on the usage of the algorithm, Bowler’s algorithm comprises either a plurality of addition or a plurality of subtraction steps. The use of either additions or subtractions in this way is in contrast with calculating the mathematical description of a cubic function using multiplications. Multiplications may be much more time-consuming operations than additions on hardware, such as FPGAs. For example, when controlling signals for use in a quantum control system, the difference in the time it takes to perform a multiplication compared to an addition may become a significant factor and possibly bottleneck the preparation, manipulation, or read-out of qubit states. It is therefore desirable to use algorithms that instead only use additions and / or subtractions, such as Bowler’s algorithm which will be detailed below. While reference is made primarily to Bowler’s algorithm herein, any other iterative algorithm that may also calculate values of the signal using additions and / or subtractions instead of multiplications and / or divisions may still be suitable for this purpose. Bowler’s algorithm is a deconstruction of a polynomial function using only recursive additions in a first version, or subtractions in a second version as described later. For example, for each segment of a desired signal, Bowler’s algorithm can be used to deconstruct the interpolating polynomial for that segment. For calculating a value of a polynomial function, Bowler’s algorithm uses four parameters, which may be referred to herein assub-functions, and which may be referred to herein as ^^^^,^^^^, ^^^^ and ^^^^. These sub-functions ^^^^,^^^^, ^^^^ and ^^^^ varywith the variable parameter ^^^^, and hence can be written as ^^^^(^^^^),^^^^(^^^^), ^^^^(^^^^) and ^^^^(^^^^), respectively. Howeverthe short-hand notation is used herein for simplicity. These parameters or sub-functions ^^^^,^^^^, ^^^^ and ^^^^ areassociated with the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ that describe the polynomial function in a segment of the desired signal. Bowler’s algorithm takes as an input of a first iteration, first parameter values ^^^^0, ^^^^0, ^^^^0, ^^^^0, each of which is generated based on the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^ in the manner shown below. ^^^^0, ^^^^0, ^^^^0, ^^^^0may be linear combinations of the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^. In order to reconstruct acubic function with coefficients ^^^^, ^^^^, ^^^^ and ^^^^, Bowler’s algorithm iteratively adds sub-functions ^^^^,^^^^, ^^^^ and ^^^^ inthe manner defined below. The parameter values for the first iteration are the following combinations of ^^^^, ^^^^, ^^^^ and ^^^^: ^^^^(0) = ^^^^^^^^(0) = ^^^^ − ^^^^ + ^^^^^^^^(0) = 2^^^^ − ^^^^^^^^(0) = 6^^^^.To compute ^^^^(^^^^) = ^^^^ + ^^^^^^^^ + ^^^^^^^^2 + ^^^^^^^^3 on hardware such as an FPGA, ^^^^(^^^^) can be expressed as:when ^^^^ = 0 + ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) when ^^^^ > 0,where the sub-functions used for the iterations of the algorithm are: ^^^^(^^^^) = ^^^^(^^^^ − 1) + ^^^^(0)^^^^(^^^^) = ^^^^(^^^^ − 1) + ^^^^(^^^^)^^^^(^^^^) = ^^^^(^^^^ − 1) + ^^^^(^^^^)^^^^(^^^^) = ^^^^(0). Therefore it is clear that, in an implementation in which the first iterative algorithm is based on Bowler’s algorithm, the stored parameter values that are retrieved in block 302 may comprise the polynomial coefficients ^^^^, ^^^^, ^^^^ and ^^^^. These polynomial coefficients are used to determine the parameters^^^^0, ^^^^0, ^^^^0, ^^^^0, in a first step of the iterative algorithm and these parameters act as the starting point for the iteration. Or, the starting parameters ^^^^0, ^^^^0, ^^^^0, ^^^^0may have been pre-determined for each segment in the first region, in which case the parameters ^^^^0, ^^^^0, ^^^^0, ^^^^0can be retrieved from the memory elements.The parameters are used as inputs into the sub-functions ^^^^(^^^^),^^^^(^^^^), ^^^^(^^^^) and ^^^^(^^^^) of the iterative Bowler’salgorithm in order to calculate values of the signal ^^^^(^^^^) for each segment using additions instead of multiplications. For calculating the value of a cubic polynomial, Bowler’s algorithm may comprise 5 addition operations. This number of addition operations may vary depending on the order of polynomial function. It is also notable that the 5 addition operations needed to calculate the value of a cubic polynomial may be reduced to 3 addition operations by using the recursive definitions of ^^^^ and ^^^^. The value of ^^^^(^^^^)may actually be equal to ^^^^ using the following expansion: ^^^^(^^^^) = ^^^^(^^^^ − 1) + ^^^^(^^^^)= ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) + ^^^^(^^^^)= ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) + ^^^^(0)= ^^^^(^^^^).Equation 1Therefore, ^^^^(^^^^) may only need to be calculated using 3 additions, ^^^^(^^^^) = ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) +^^^^(0), instead of 5 additions. This reduction in the number of additions needed to calculate the value of the signal may result in an even quicker computation of the value of the signal compared to the standard Bowler’s algorithm. The second iterative algorithm may be a very similar algorithm to the first iterative algorithm. For example, the second iterative algorithm may be Bowler’s algorithm, but with a slight alteration. The values of the signal within the second region may be calculated by reversing the recursive sum, as previously described, into a recursive difference. The recursive difference may start from the end point of the recursive sum for the firstregion and reverse all the arithmetic steps as previously described, ^^^^(^^^^) = ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) + ^^^^(^^^^ − 1) +^^^^(0), in a second, reversed order. The version of Bowler’s algorithm described using recursive differences is herein referred to as subtractive Bowler’s algorithm. The version of Bowler’s algorithm described using recursive additions is herein referred to as additive Bowler’s algorithm. Similarly to additive Bowler’s algorithm, subtractive Bowler’s algorithm uses four sub-functions, herein called^^^^′,^^^^′, ^^^^′ and ^^^^′. These sub-functions contain a prime symbol to distinguish them from the sub-functions usedin additive Bowler’s algorithm above. These sub-functions used in subtractive Bowler’s algorithm ^^^^′,^^^^′, ^^^^′ and^^^^′ are associated with the sub-functions ^^^^,^^^^, ^^^^ and ^^^^ used in additive Bowler’s algorithm. The sub-functions^^^^,^^^^, ^^^^ and ^^^^ used to calculate the polynomial function in a first region are used to calculate the sub-functions^^^^′,^^^^′, ^^^^′ and ^^^^′ in a second region. The sub-functions for the first iteration of subtractive Bowler’s algorithmuse the sub-functions for the final iteration of additive Bowler’s algorithm: Here, ^^^^^^^^^^^^^^^^^^^^^^^^is the final time step of a corresponding segment in the first region, where additive Bowler’s algorithm has been used to calculate values of the signal in the first region and subtractive Bowler’s algorithm is used to calculate values of the signal in the second region.To compute ^^^^(^^^^) = ^^^^ + ^^^^^^^^ + ^^^^^^^^2 + ^^^^^^^^3 in a second region on hardware such as an FPGA, ^^^^(^^^^) can beexpressed as: ^^^^(^^^^) = ^^^^′(^^^^) when ^^^^ = 0^^^^(^^^^) = ^^^^′(^^^^) + ^^^^′(^^^^) + ^^^^′(^^^^) + ^^^^′(^^^^) when ^^^^ > 0,where the sub-functions used for the iterations of the algorithm are: Therefore the outputs of the first iterative algorithm in block 304 may be used as inputs to the second iterative algorithm in block 306 in order to calculate values of the signal ^^^^(^^^^) in a second region of the desired signal. In practice, the modifications of additive Bowler’s algorithm into subtractive Bowler’s algorithm in order to exploit the symmetry of a second region with a first region, in a region of symmetry with N total segments, can be summarised in four steps: 1. Storing N / 2 segments with parameters ^^^^0, ^^^^0, ^^^^0, ^^^^0with the N / 2-indexed segment terminating at a symmetrical centre point halfway between the first region starting value and the second region ending value. 2. Inverting the indices of the segments in the second region, such that the segments in the second region are indexed as N / 2, N / 2-1,…,0 instead of 0, 1,…, N / 2, as in the first region. 3. Remapping the sub-functions ^^^^,^^^^, ^^^^ and ^^^^ for each segment at the end of the recursive sum calculationfor segments with indices less than or equal to N / 2. For example, the values of ^^^^(0),^^^^(0), ^^^^(0) and^^^^(0) for a segment in the first region are replaced with ^^^^�^^^^^^^^^^^^^^^^^^^^^^^^�,^^^^�^^^^^^^^^^^^^^^^^^^^^^^^�, ^^^^�^^^^^^^^^^^^^^^^^^^^^^^^� and ^^^^�^^^^^^^^^^^^^^^^^^^^^^^^�when the last recursive sum has been calculated for that segment. 4. Calculating the recursive difference for the segments with indices greater than N / 2, using the sub- functions ^^^^′,^^^^′, ^^^^′ and ^^^^′ in subtractive Bowler’s algorithm.Figs.5a and 5b depict implementations of Bowler’s algorithm 500, 510 in flow logic. Fig.5a depicts an additive Bowler’s algorithm 500. Fig.5b depicts a subtractive Bowler’s algorithm. The shapes, such as trapezia, circles and rectangles, in Figs.5a and 5b depict logical operations. The lines in Figs.5a and 5b show inputs to or outputs of the logical operations. The general flow of the diagrams in Figs.5a and 5b are interpreted from left to right. Fig.5a depicts an implementation of Bowler’s additive algorithm 500, which uses 3 adders instead of the conventional 5 adders, using Equation 1 above. Additive Bowler’s algorithm 500, as shown in Fig.5a, may be the first iterative algorithm used at block 304 of method 300 in Fig.3. Additive Bowler’s algorithm 500 may be used to iteratively sum combinations of parameters and / or polynomial coefficients to produce values of the signal ^^^^(^^^^). Additive Bowler’s algorithm 500 may be implemented in logic using parameters and / or polynomial coefficients, adders and logic gates. The iterative nature of additive Bowler’s algorithm 500 is demonstrated by the three circular loops A,B,C in Fig.5a. The sub-functions used in Fig.5a are the sub-functions used in Equation 1. Multiplexers 502a,b,c may be used to select the input used for the addition step at the adders 504a,b,c. For example, in the loop A of Fig.5a, the input to the multiplexer 502a may either be ^^^^(0) or ^^^^(^^^^). The output of the multiplexer 502a may then be either one of the two inputs to the multiplexer 502a, for example the output may be either ^^^^(0) or ^^^^(^^^^). Each of the adders 504a,b,c are used to add two inputs. For example, the two inputs to the adder 504a in loop A are either ^^^^(0) and ^^^^(0), or ^^^^(0) and ^^^^(^^^^). The two inputs to each of the adders 504a,b,c are summed by the adder 504a,b,c to give a single output value. The output value of the adder 504a,b,c is used as an input to the corresponding memory register 506a,b,c. The memory register 506a,b,c is used to store the input value to the memory register 506a,b,c. For example, in loop A, the memory register 506a may store the output of the addition operation of the adder 504a. The output of the memory register 506a,b,c is the same as the input to the memory register 506a,b,c, when the output is requested. For example, the output of the memory register 506a is shown in loop A as ^^^^(^^^^). The output of the memory registers 506a and 506b may be used as an input to the next loop, B and C, respectively. Alternatively the output may be used as an input to perform the same loop again, due to the iterative nature of the Bowler’s algorithm. The output of the memory register in the last loop, for example loop C in Fig.5a, may be used as an input to perform the same loop again. This output may also be the value of the signal ^^^^(^^^^), when the algorithm is finished. Fig.5b depicts an implementation of subtractive Bowler’s algorithm 510. Bowler’s algorithm is conventionally additive, however a subtractive version may be used for the second iterative algorithm at block 306 of method 300 in Fig.3, as previously discussed. Fig.5b depicts an implementation of a subtractive Bowler’s algorithm 510, which uses 3 subtractors. Subtractive Bowler’s algorithm 510 shown in Fig.5b may be used to iteratively subtract combinations of sub-functions to produce values of the signal ^^^^′(^^^^). Fig.5b shows a similar structure and similar components to those in Fig.5a, however the main difference is the use of subtractors instead of adders. The general flow of the diagram can still be read from left to right, with the first loop at the bottom of the diagram. The iterative nature of subtractive Bowler’s algorithm 510 is demonstrated by the three circular loops D,E,F in Fig.5b. However, in Fig.5b, the sub-functions contain a prime symbol to distinguish them from the sub-functions used in Fig.5a. Similarly to in Fig.5a, multiplexers 512d,e,f are used to select an input into the subtractors 514d,e,f, and the memory registers 516d,e,f are used to store outputs of previous operations. The implementation of Bowler’s algorithm shown in Figs.5a and 5b can be efficiently used on hardware by implementing an efficient pipeline structure. The registers 506a,b,c and 516d,e,f are used to store data in order to implement an efficient pipeline structure. The pipeline structure will be discussed later in relation to Fig.7. The above details of Fig.5a and Fig.5b demonstrate specifics of Bowler’s algorithm, the additive version being the first iterative algorithm and the subtractive version being the second iterative algorithm. The iterative algorithms used in method 300 may be other iterative algorithms and Figs.5a and 5b demonstrate only one implementation of iterative algorithms. The components shown in Figs.5a and b are multiplexers, adders, subtractors and memory elements, however other suitable elements may be used in addition to or instead of these components when implementing Bowler’s algorithm or any other relevant iterative algorithm. There may be more or fewer of each component in the implementation. Figs.5a and 5b demonstrate the iterative structure of each version of Bowler’s algorithm using 3 iterative loops, A, B and C in Fig.5a and D, E and F in Fig.5b. Although fewer operations may be beneficial for reducing runtime on hardware, more or fewer adders / subtractors may be used in the implementation of Bowler’s algorithm or any other similar iterative algorithm. Having a larger or smaller number of adders / subtractors would result in more iterative loops being added to the logic flow diagrams in Fig.5a and Fig.5b. Fig.6 depicts a pulse shaper 600 according to the present disclosure. Fig.6 depicts a pulse shaper 600 used for implementing method 300. The pulse shaper 600 is used to generate a signal for use in a quantum control system. The pulse shaper 600 comprises an Avalon® interface 602, a multiplexer 604, a block random access memory (BRAM) unit 606, memory elements such as registers 610a,b, digital signal processing (DSP) blocks 608, and a finite state machine 612. The Avalon® interface 602 is configured for allowing the communication between the apparatus 600 and software or other devices. The Avalon® interface 602 is a lightweight memory mapped protocol that is used to read from and / or write to software processes and control off-chip devices. In use, the Avalon® interface 602 takes multiple inputs from software or other devices and provides them to the pulse shaper 600. In Fig.6, the Avalon® interface 602 has three inputs named avs_write, writedata and avs_address. The inputs to the Avalon® interface 602 can then be used for further operations on the Avalon® interface 602. The finite state machine 612 is configured to control the operations of the pulse shaper 600 using control logic. Specifically, the finite state machine 612 may be configured for generating trigger pulses that control the components on the pulse shaper 600. The finite state machine 612 is configured to ensure the continuous flow of data in the pipeline. The finite state machine 612 is connected to the various components on the pulse shaper 600. In Fig.6, the finite state machine 612 has three inputs start_pulse, start_addr and seg_num. The finite state machine 612 enters different states, for example a ‘start state’ and an ‘idle state’, depending on the input received, such that trigger pulses can be sent to or delayed to the various components on the pulse shaper 600. In general, the finite state machine 612 can control the timing of different logic operations associated with the pulse shaper 600 and can decide the loading of and timing of inputting data into the pipeline. An efficient pipeline structure can be implemented on the pulse shaper 600 in order to maximise throughput of the pulse shaper 600. An efficient pipeline structure would continuously process data, without causing latency overhead. By using sub-functions for the next segment at the correct time, such that the pipeline is never empty, data is continuously processed. Efficiently implementing a pipelined structure can result in data being produced at the clock rate of the pulse shaper. The finite state machine 612 outputs trigger pulses in order to efficiently control the pipeline structure. The data output from the Avalon® interface 602 is used as an input to the multiplexer 604. The multiplexer 604 is a configured outputs to be sent to the BRAM 606. The multiplexer 604 in Fig.6 has one input from the Avalon® interface 602. The multiplexer 604 is shown to have four outputs in Fig.6. The four outputs are thesub-functions to be used in Bowler’s algorithm, for example ^^^^(0),^^^^(0), ^^^^(0) and ^^^^(0). The control logic 612 isused to control which of the four outputs are given by the multiplexer 604 at any one time. Specifically, the control logic 612 can control which parameters are transferred into memory from an AVS (Adaptive Voltage Scaling) bus. The data output from the multiplexer 604 is used as an input to the BRAM 606. The BRAM 606 is a type of random access memory embedded in systems, such as FPGAs, for data storage. The BRAM 606 can be allocated to store data. In Fig.6, the BRAM 606 is being used to store sub-functions describing the segmented data. In Fig.6, four inputs to the BRAM 606 shows the four different sub-functions that can be inputted into the BRAM 606 at one time. The data output from the BRAM 606 is used as an input to the memory register 610a. The use of registers in the pulse shaper 600 and therefore also in the DSP blocks 608 is useful for implementing a pipeline structure and therefore maximising the throughput of the pulse shaper 600. The BRAM 606 is used as a longer term storage than the memory registers 610a, 610b. For example, the BRAM 606 may store data for the length of an entire quantum experiment. The data output from the memory register 610a is used as an input to a DSP block 608. In Fig.6 there are three DPS blocks 608, each defining a loop in additive Bowler’s algorithm, as shown in Fig.5a. The DSP blocks 608 are dedicated digital signal processing units configured for arithmetic operations. DSP blocks 608 are advantageous because of the ability to run operations at a higher clock speed compared to, for example, simple logic implementations. Specifically, in Fig.5a, the DSP blocks 608 are DSP48 units. The final value of the algorithm is passed to and stored in the memory register 610b. The values of the signal are then passed out of the pulse shaper 600, as shown by pulse_out in Fig.6. Data is usually maintained for multiple clock cycles in the registers 610a, 610b, for example until the next segment is processed. The apparatus described herein is a pulse shaper 600, however more generally the depicted apparatus may be a signal generator or any other relevant hardware for modifying or generating a signal. There may also be more or fewer of each component on the pulse shaper 600, or they may be arranged in a different structure. The algorithm implemented on the DSP blocks 608 may be Bowler’s algorithm or any other iterative algorithm. The pulse shaper 600 may instead have different relevant inputs and / or outputs. The pulse shaper 600 may form part of a quantum control system, comprising a quantum computer comprising one or more qubits. In this system, the pulse shaper 600 is configured to receive a control pulse from a pulse generator, and shape it using a generated signal. Appropriately shaped control pulses can drive the qubits to the desired quantum states. The present disclosure relates to a computer-implemented method for generating an output signal which approximates a desired signal, where the output signal is suitable for use in a quantum control system. Fig.7 illustrates an exemplary quantum computer 700 in schematic form which comprises a quantum control system, shown here as the classical interface 101 of the quantum computer 700. Control pulses may be transmitted from the classical interface 101 to a quantum processing unit (QPU) 104 of the quantum computer 800. A quantum computer is a machine that uses the properties of quantum physics to perform computations. The quantum computer 100 comprises a classical interface 101 and a QPU 104. The classical interface 101 is the portion of the quantum computer 100 that handles user inputs (e.g. quantum circuits / programs) and generates and sends digital control signals (QDIG) to the QPU 104. The QPU 104 is the portion of the quantum computer 100 which manipulates qubits to create quantum states and perform quantum operations by leveraging low-level control signals (QLOW) that are generated based on the digital control signals. The classical interface 101 comprises a classical processing unit in the form of a conventional central processing unit (CPU or Cl.CPU) 102, and a classical programmable logic unit (Cl.PROG) 103, which may be a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), a structured application- specific integrated circuit (structed ASIC), a custom-made digital signal processor (DSP) or similar. The CPU 102 and programmable logic unit 103 are communicatively coupled to each other, e.g. directly or via a traditional bus or similar. The programmable logic unit 103 may comprise, or take the form of, the pulse shaper 600 depicted in Fig.6. The QPU 104 comprises in-fridge logic (QLOG) 105 and a quantum system (QSYS) 106 with a plurality of qubits. The in-fridge logic 105 converts the digital control signals received from the classical interface 101 (more specifically, received from the programmable logic unit 103 of the classical interface 101) into the low-level control signals which are used to manipulate the qubits to perform quantum computations with the quantum system 106. It should be noted that the quantum computer 700 illustrated in Figure 7 is merely exemplary, and other configurations having additional components, fewer components, or functionally equivalent components are also envisaged. The QPU may be based on any suitable quantum computing architecture, such as photonic- based, semiconducting, superconducting, ion-traps, neutral atoms etc. Within the classical programmable logic unit (Cl.PROG) 103, the quantum computer 700 may comprise a pulse generator configured to generate a control pulse for controlling a state of the one or more qubits, and a pulse shaper configured to shape the control pulse generated by the pulse generator using an output signal. The output signal may be generated according to any of the methods or methodologies disclosed herein, and in particular using the method 300 depicted in figure 3. As described above with respect to figure 6, the pulse shaper may comprise one or more memory elements and one or more processors configured to enable generation of the output signal. The various methods described herein may be implemented by a computer program, which may be run on CPU 102, for example, or any other suitable processing device. The computer program may include computer code arranged to instruct a computer to perform the functions of one or more of the various methods described above. The computer program and / or the code for performing such methods may be provided to an apparatus, such as a computer, on one or more computer readable media or, more generally, a computer program product. The computer readable media may be transitory or non-transitory. The one or more computer readable media could be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium for data transmission, for example for downloading the code over the Internet. Alternatively, the one or more computer readable media could take the form of one or more physical computer readable media such as semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and an optical disk, such as a CD-ROM, CD-R / W or DVD. In an implementation, the modules, components and other features described herein can be implemented as discrete components or integrated in the functionality of hardware components such as ASICS, FPGAs, DSPs or similar devices. In addition, the modules and components can be implemented as firmware or functional circuitry within hardware devices. Further, the modules and components can be implemented in any combination of hardware devices and software components, or only in software (e.g., code stored or otherwise embodied in a machine- readable medium or in a transmission medium). Unless specifically stated otherwise, as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as " receiving”, “determining”, “comparing ”, “enabling”, “maintaining,” “identifying,” or the like, refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices. Fig.8 depicts a computer-readable medium according to the present disclosure. The various methods described above may be implemented by a computer program. The computer program may include computer code (e.g. instructions) 810 arranged to instruct a computer to perform the functions of one or more of the various methods described above. The steps of the methods described above may be performed in any suitable order. For example, step 302 of method 300 may be performed before, after, simultaneously or substantially simultaneously with step 304. The computer program and / or the code 810 for performing such methods may be provided to an apparatus, such as a computer, on one or more computer readable media or, more generally, a computer program product), depicted in Fig.8. The computer readable media may be transitory or non-transitory. The one or more computer readable media 800 could be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, or a propagation medium for data transmission, for example for downloading the code over the Internet. Alternatively, the one or more computer readable media could take the form of one or more physical computer readable media such as semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and an optical disk, such as a CD-ROM, CD- R / W or DVD. It will be understood that the above description of specific embodiments is by way of example only and is not intended to limit the scope of the present disclosure. Many modifications of the described embodiments, some of which are now described, are envisaged and intended to be within the scope of the present disclosure. While the method has been described in relation to pulses and signals segmented into 6, 12 and 16 segments, it should be appreciated that any suitable number of segments may be used. Similarly, while the method has been primarily described in relation to cubic spline interpolation, the skilled person will understand that other interpolation techniques may be used, for example quadratic spline interpolation or quartic spline interpolation. The graphs included in the present application all depict desired signals which are gaussian-like and symmetric about a central point of symmetry. This type of signal / pulse is common in quantum control systems, but the present method is not limited to this type of pulse. For example, the signal may be discontinuous such that the first and second region referred to in the method 300 are separated from one another by intermediate signal values which are not part of either the first or the second region. The desired signal may also comprise a third and a fourth region, the third region being symmetric with the fourth region. An example of such a desired signal might be a gaussian pulse followed by a second, smaller and / or flatter gaussian-like pulse, for example. To generate an output signal to approximate this kind of desired signal, the method may further comprise performing method 300 again in respect of the third and fourth region. This may comprise obtaining one or more third parameter values for each segment in the third region, and using the first iterative algorithm and the one or more third parameter values to generate at least one value of the output signal for each segment in the third region. The second iterative algorithm and one or more fourth parameter values can then be used generate at least one value of the output signal for each segment in the fourth region, wherein the one or more fourth parameter values are generated based on the one or more third parameter values. The skilled person will appreciate that the above disclosure relating to the “first region” applies similarly to the “third region”, and the above disclosure which relates to the “second region” applies similarly to the “fourth region”. In this way, multiple regions of symmetry may be exploited within a desired signal. While the first iterative algorithm has been described primarily as an additive algorithm and the second iterative algorithm has been described primarily as a subtractive algorithm, this may be reversed. For example, for a desired signal which comprises an “inverted gaussian” shape, the first iterative algorithm may comprise a plurality of subtraction steps, and the second iterative algorithm may comprise a plurality of addition steps. In Figs.1a, 1b and 2, the desired signal is a Gaussian pulse, however the desired signal may be any signal that comprises at least one region of symmetry with a first and second region, the first region being symmetric with the second region. The desired signal may for example be a Gaussian function or a trigonometric function. The desired signal may be a complicated signal, be asymmetric and / or may only contain one short region of symmetry within the duration of the signal. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other implementations will be apparent to those of skill in the art upon reading and understanding the above description. Although the present disclosure has been described with reference to specific example implementations, it will be recognized that the disclosure is not limited to the implementations described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative sense rather than a restrictive sense. The scope of the disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

Claims 1. A computer-implemented method for generating an output signal which approximates a desired signal, the output signal for use in a quantum control system, wherein: the desired signal comprises a first and a second region, the first region being symmetric with the second region; and the desired signal is segmented into a plurality of segments, wherein values of the signal in each segment can be approximated using one or more parameter values; the method comprising: obtaining one or more first parameter values for each segment in the first region; using a first iterative algorithm and the one or more first parameter values to generate at least one value of the output signal for each segment in the first region; and using a second iterative algorithm and one or more second parameter values to generate at least one value of the output signal for each segment in the second region, wherein the one or more second parameter values are generated based on the one or more first parameter values.

2. The method of claim 1, wherein generating the at least one value of the output signal for each segment in the first region comprises, for each segment in the first region: inputting the one or more first parameter values into the first iterative algorithm to generate at least one value of the output signal, wherein the first iterative algorithm comprises iteratively updating the one or more first parameters until one or more updated first parameter values are reached for each of the one or more first parameter values.

3. The method of claim 2, wherein the one or more updated first parameter values are the one or more second parameter values.

4. The method of claim 2 or claim 3, wherein each iteration of the first iterative algorithm generates a respective value of the output signal.

5. The method of any of claims 2 to 4, wherein, for each segment, the one or more updated first parameter values are reached during a final iteration of the first iterative algorithm.

6. The method of claim 5, wherein a predetermined number of values of the output signal are generated for each segment according to a sampling rate, and the final iteration of the first iterative algorithm for each segment is reached when the predetermined number of values of the output signal have been reached.

7. The method of any preceding claim, wherein generating the at least one value of the output signal for each segment in the second region comprises, for each segment in the second region: inputting the one or more second parameter values into the second iterative algorithm to generate the at least one value of the output signal.

8. The method of any preceding claim, wherein a value of the desired signal varies with a variable parameter.

9. The method of claim 8, wherein the first region is defined between a first region starting value and a first region ending value of the variable parameter, and the second region is defined between a second region starting value and a second region ending value of the variable parameter.

10. The method of claim 9, wherein the first region ending value is equal to the second region starting value to define a symmetrical centre point halfway between the first region starting value and the second region ending value.

11. The method of any of claims 8 to 10, wherein the variable parameter is time and each segment has a length, wherein the sum of the lengths of each segment in the first region is equal to the sum of the lengths of each segment in the second region.

12. The method of any preceding claim, wherein the generated signal is used for shaping a control pulse of a quantum control system.

13. The method of claim 12, wherein the generated signal is an envelope signal, and shaping the control pulse comprises one of modulating an amplitude of the control pulse and modulating a phase envelope of the control pulse.

14. The method of any preceding claim, wherein each segment in the first region is associated with one or more polynomial coefficients and, for each segment in the first region, the one or more polynomial coefficients define an interpolating polynomial that approximates values of the desired signal within the segment.

15. The method of claim 14, wherein, for each segment in the first region, the one or more first parameter values for the segment are based on the polynomial coefficients for the segment.

16. The method of claim 14 or claim 15, the method further comprising generating the one or more first parameter values for each segment in the first region based on the polynomial coefficients.

17. The method of any of claims 14 to 16, further comprising generating the one or more polynomial coefficients for each segment in the first region using a fitting algorithm.

18. The method of any preceding claim, wherein the first iterative algorithm comprises a plurality of addition steps and the second iterative algorithm comprises a plurality of corresponding subtraction steps; or wherein the first iterative algorithm comprises a plurality of subtraction steps and the second iterative algorithm comprises a plurality of corresponding addition steps.

19. The method of claim 18, wherein the plurality of addition steps are performed in a first order, and the plurality of subtraction steps are performed in a second order, the second order being reversed relative to the first order.

20. The method of any preceding claim, wherein the sum of the number of segments in the first region and the number of segments in the second region is an even number.

21. The method of any preceding claim, further comprising segmenting the desired signal into the plurality of segments.

22. The method of any preceding claim, wherein each segment in the first region has a corresponding segment in the second region, and the one or more second parameter values for a particular segment in the second region are generated based on the one or more first parameter values from a segment in the first region which corresponds with the particular segment in the second region.

23. The method of claim 22, wherein values of the desired signal in corresponding segments are symmetric with each other.

24. The method of claim 22 or claim 23, wherein values of the desired signal in corresponding segments are equal but reversed in order relative to one another.

25. The method of any preceding claim, wherein the desired signal comprises a third and a fourth region, the third region being symmetric with the fourth region; and the method further comprises: obtaining one or more third parameter values for each segment in the third region; using the first iterative algorithm and the one or more third parameter values to generate at least one value of the output signal for each segment in the third region; and using the second iterative algorithm and one or more fourth parameter values to generate at least one value of the output signal for each segment in the fourth region, wherein the one or more fourth parameter values are generated based on the one or more third parameter values.

26. The method of any preceding claim, wherein obtaining the one or more first parameter values for each segment in the first region comprises retrieving the one or more first parameter values from one or more memory elements.

27. A computer-readable medium comprising instructions which, when executed by one or more processors, cause the one or more processors to perform the method of any preceding claim.

28. An apparatus for generating a signal for use in a quantum control system, the apparatus comprising one or more memory elements, and one or more processors configured to perform the method of any of claims 1 to 26.

29. The apparatus of claim 28, wherein the apparatus is a pulse shaper configured to shape a control pulse of the quantum control system.

30. A quantum control system comprising: a quantum computer comprising one or more qubits; a pulse generator configured to generate a control pulse for controlling a state of the one or more qubits; and a pulse shaper configured to shape the control pulse generated by the pulse generator using an output signal; the pulse shaper comprising one or more memory elements and one or more processors configured to generate the output signal by performing the method of any of claims 1 to 26.

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