Confinement rod-based spot size converter for fiber-to-chip coupling in photonic integrated circuits

Abstract

A photonic device and method are disclosed for low-loss fiber-to-chip coupling in photonic integrated circuits. A waveguide tapers near the edge, reducing its width by at least 50%, while confinement rods arranged in multiple vertical layers above and below the waveguide taper in the opposite direction. Together, they form a complementary "super-mode," ensuring a smooth transition for the optical field. This design alleviates fabrication challenges tied to extremely narrow tapers and enables a smaller footprint than conventional edge couplers. By placing the waveguide at the super-mode's center, the dielectric stack is thinner, facilitating integration with standard silicon photonics processes. The result is a robust, compact, and highly efficient solution for fiber-to-chip interconnects.

Description

[0001] CONFINEMENT ROD-BASED SPOT SIZE CONVERTER FOR FIBER-TO-CHIP COUPLING IN PHOTONIC INTEGRATED CIRCUITS

[0002] RELATED APPLICATIONS

[0003]

[0001] This application claims the benefit under 35 USC 119(e) of U.S. Provisional Application No. 63 / 558,421, filed on February 27, 2024, which is incorporated herein by reference in its entirety.

[0004] BACKGROUND OF THE INVENTION

[0005]

[0002] Photonic integrated circuits (PICs) are increasingly being developed for applications that demand compact and efficient optical functionality on a single chip. These integrated devices combine multiple optical components — such as switches, wavelength splitters, modulators, mode-size converters (also referred to as “spot size converters”), multiplexers and demultiplexers, resonators, polarizers, phase shifters, and waveguides — side- by-side with electrical signal routing and electronic components. By leveraging semiconductor fabrication methods, photonic integrated circuits can also benefit from the maturity of microelectronics manufacturing. This has led to a wider adoption of photonic chips in telecommunications, data communications, computing and sensing applications. A critical challenge in many of these applications is the efficient coupling of light between standard optical fibers and the on-chip waveguides, due to the mismatch in optical mode size and numerical aperture.

[0006]

[0003] Silicon photonics, in particular, has emerged as a leading technology for large-scale photonic integrated circuits and is well-suited for implementing spot size converters. Because silicon photonics leverages complementary metal-oxide-semiconductor (CMOS) processes, it offers economies of scale, reduced manufacturing costs, and compatibility with existing electronic device fabrication infrastructure. In data centers and other high-speed communication environments, photonic links and silicon-based optical components can replace or enhance conventional copper interconnects, reducing power consumption and latency. However, minimizing coupling losses between fibers and the tightly confined waveguide modes on silicon photonic chips remains a key hurdle.

[0004] Waveguide structures form the backbone of photonic integrated circuits by guiding light from one component to another on the chip. They typically consist of a high-refractive - index core surrounded by one or more lower-index cladding layers. The geometry, material composition, and fabrication methods used to define these waveguides strongly impact optical losses, bandwidth, and overall device performance. While the compact nature of high-index- contrast waveguides (such as silicon-on-insulator) is advantageous in most parts of the circuit, it also increases the difficulty of coupling to external components like optical fibers, which usually have a much larger mode field diameter.

[0007]

[0005] In silicon photonics, waveguides may be formed from crystalline or amorphous silicon or silicon nitride, with claddings made of silica, silicon dioxide (SiCh), or silicon oxynitride. These processes utilize lithography and etching steps to define the waveguide shape, and further deposition steps to form precise film thicknesses for optimal mode confinement often at telecommunication wavelengths, typically around 1310 nm or 1550 nm. The small cross-section of these waveguides enables tight bends and high integration density but complicates the direct coupling to standard single-mode optical fibers.

[0008]

[0006] Spot size converters (SSCs) are often employed on-chip to bridge this mode-size mismatch between the fiber’s large optical mode and the waveguide’s much smaller mode. An SSC gradually transitions between a larger cross-section waveguide at and near the chip’s edge or facet to the smaller waveguide core used internally in the chip, effectively expanding or contracting the optical mode along the propagation direction to minimize coupling loss. Despite the availability of various SSC designs, further improvements are needed to reduce complexity, enhance fabrication tolerance, and achieve lower insertion loss.

[0009] SUMMARY OF THE INVENTION

[0010]

[0007] In conventional spot size converter designs, mismatches in waveguide geometry, material index, or fabrication imperfections can still lead to notable coupling losses. Fiber-to- waveguide transitions remain a crucial performance bottleneck, especially for applications requiring high optical power efficiency, minimal insertion losses, and resilience to alignment errors. Moreover, achieving a robust lateral and vertical confinement without excessive complexity in fabrication processes can be difficult.

[0008] To address these challenges, there is a need for improved spot size converter structures that offer efficient, low-loss coupling between standard optical fibers and the on- chip waveguide modes. The present invention provides a solution through the use of confinement rod, e.g., nanorod, arrays — periodic or quasi-periodic arrangements of high-index rods or pillars integrated within or adjacent to the SSC region. These arrays can tailor the optical mode transition, enhancing mode matching and effectively reducing coupling losses. By carefully configuring rod geometry, spacing, and material composition, the invention offers a more robust and fabrication-tolerant approach to spot size conversion, thereby facilitating higher-performance fiber-to-chip interfaces in photonic integrated circuits.

[0011]

[0009] In contrast to existing approaches, the functional waveguide is integrated directly into the rod-based converter structure rather than relegating it beneath a large rod stack. Because the waveguide core typically uses a higher -refractive-index material (e.g., silicon) and maintains a certain thickness for the primary PIC functionality, combining it seamlessly with confinement rods at multiple layers is non-trivial. Achieving this uniform super-mode transition — while keeping the waveguide in its functional position — represents an evolution of previous SSC designs.

[0012]

[0010] By judiciously tailoring the thicknesses of the dielectric layers and the rod geometry, the design strikes a balance between efficient mode expansion, minimal loss, and manufacturability — traits not readily apparent from existing inverted taper or top-loaded nanorod solutions.

[0013]

[0011] By achieving low-loss edge coupling to standard fibers within a compact footprint and without necessarily resorting to thick dielectric stacks, the proposed solution can provide benefits such as lower insertion loss at the fiber-to-chip interface, reduced chip thickness and simpler integration, especially useful in multi-layer PICs where vertical dimensions are at a premium, and / or greater design flexibility to tune the super-mode shape through strategic placement and tapering of rods in multiple layers.

[0014]

[0012] Embodiments of the present invention improves upon conventional couplers by placing the functional waveguide at the center of the “super-mode” defined by the confinement rods. Rather than burying the waveguide under a thick stack, the design layers — above and below the waveguide — are possibly thinned, ensuring that the waveguide is directly integrated into the confinement rod structure.

[0015]

[0013] Structurally, this is achieved by tapering the waveguide down such that as the waveguide approaches the chip edge, its width decreases, shrinking the core size and / or tapering the confinement rods up. That is, surrounding rods — distributed in multiple layers above and below the waveguide — simultaneously broaden toward the chip edge. This arrangement gradually reshapes the optical field, transitioning from a tightly confined waveguide mode to a larger fiber-compatible mode.

[0016]

[0014] The result is a more efficient super-mode that incorporates the waveguide core and the multiple layers of confinement rods as a unified optical structure.

[0017]

[0015] The present invention provides a photonic device and fabrication method for efficiently coupling light between an on-chip waveguide and an external optical fiber (e.g., into and / or out of an on-chip waveguide). The device includes a waveguide disposed in a waveguide layer and having a tapered portion that reduces its width toward a facet of a photonic integrated circuit (PIC) chip. Surrounding the waveguide at least in one layer below and at least one layer above are confinement rods (e.g., an array of confinement rods) whose widths increase toward the facet. These features collectively create a spot size converter configured to transition the optical mode from a confined cross-section in the waveguide to a larger cross-section at the chip facet, thus optimizing fiber coupling.

[0018]

[0016] In one embodiment, the waveguide can be formed from a high-refractive-index material such as silicon or silicon nitride. The waveguide layer may be part of a silicon-on- insulator (SOI) platform, wherein the waveguide core is fashioned in the top silicon device layer of the SOI. This arrangement leverages standard microelectronics processes.

[0019]

[0017] The invention envisions multiple confinement-rod layers both below and above the waveguide, wherein at least three distinct rod layers can be used for enhanced mode control. Each rod layer may contain a plurality of rods whose widths increase as the waveguide narrows, providing a complementary tapering pattern to guide the optical mode smoothly. Optionally, the waveguide taper angle relative to its longitudinal axis falls between approximately 0.01° and 0.1°. The tapering of the confinement rods and / or the waveguide may include a change in width in the order of hundreds of nanometers over a length in the order of hundreds of nanometers, with a taper angle between approximately 0.01° and 0.1°.

[0020]

[0018] The confinement rods themselves can assume various cross-sectional shapes — rectangular rods, cylindrical rods, or rib-like rods, — and are typically formed of a dielectric material with a refractive index lower than that of the waveguide, facilitating a super-mode that spans both the waveguide and surrounding rods. To preserve the designed optical field distribution and reduce scattering, usually a cladding layer encapsulates the rods and the waveguide. In some embodiments, the confinement rods are formed of a dielectric material that is similar to a dielectric material of which the waveguide is formed.

[0021]

[0019] For further tailoring of dimensions, each confinement rod may have a thickness from about 200 nanometers to about 500 nanometers and a width from about 150 nanometers to about 600 nanometers. These ranges assist in shaping the guided mode profile and ensuring efficient coupling.

[0022]

[0020] In another embodiment, a photonic device for edge coupling comprises a base substrate with multiple dielectric layers, including a waveguide layer and at least one confinement-rod layer, plus a tapered waveguide whose width decreases toward the facet. One or more confinement rods in these layers also increase in width toward the facet. Collectively, the rods and tapered waveguide form a super-mode that transitions from the smaller on-chip waveguide to the larger fiber-compatible mode.

[0023]

[0021] The invention additionally encompasses a method of fabricating such a photonic device. The method involves providing a suitable substrate, forming a waveguide core that tapers toward the chip facet, and arranging confinement rods in layers above and below the waveguide such that each rod tapers in the opposite sense. The waveguide layer can be crystalline silicon or silicon nitride, possibly realized on an SOI wafer.

[0024]

[0022] To create the confinement rods, a rod-forming material may be deposited, lithographically patterned, and etched in at least two confinement -rod layers oriented substantially parallel to the tapered waveguide’s longitudinal axis. Fabricating the waveguide taper and the rods’ taper angles is preferably coordinated so the evolving optical mode — often termed a super-mode — encompasses both the waveguide core and rods.

[0023] In many embodiments, one or more cladding layers can be deposited to encapsulate the spot size converter region, thereby maintaining optical confinement and reducing undesired scattering. Alternative rod geometries such as rectangular, cylindrical, or rib-like can be used. Selecting precise rod dimensions helps achieve a targeted optical mode size at the facet. Finally, while forming the waveguide taper (by at least 50% width reduction), each rod width increases by at least 50% in the same direction, producing a complementary tapering profile beneficial for efficient mode conversion.

[0025]

[0024] Overall, the invention described herein provides a robust approach to reducing insertion losses at the fiber-to-chip interface by controlling both the waveguide taper and the geometry of surrounding confinement rods. The layered, tapered design forms an effective spot size converter with a comparatively small footprint and enhanced fabrication tolerance, enabling higher coupling efficiency for a variety of photonic applications.

[0026]

[0025] The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.

[0027] BRIEF DESCRIPTION OF THE DRAWINGS

[0028]

[0026] In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings:

[0029]

[0027] Fig. 1 includes a top schematic view and various cross sectional views of a photonic integrated circuit including a spot size converter according to the presently disclosed invention;

[0030]

[0028] Figs. 2A, 2B, and 2C are cross-sectional views of embodiments of a spot size converter according to the present invention; and

[0029] Figs. 3 A and 3B are plots of transmission for, respectively, a conventional spot size converter and a spot size converter according to the present invention.

[0031] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0032]

[0030] The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0033]

[0031] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Also, all conjunctions used are to be understood in the most inclusive sense possible. Thus, the word "or" should be understood as having the definition of a logical "or" rather than that of a logical "exclusive or" unless the context clearly necessitates otherwise. Further, the singular forms and the articles "a", "an" and "the" are intended to include the plural forms as well, unless expressly stated otherwise. It will be further understood that the terms: includes, comprises, including and / or comprising, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Further, it will be understood that when an element, including component or subsystem, is referred to and / or shown as being connected or coupled to another element, it can be directly connected or coupled to the other element or intervening elements may be present.

[0034]

[0032] It will be understood that although terms such as “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, an element discussed below could be termed a second element, and similarly, a second element may be termed a first element without departing from the teachings of the present invention.

[0035]

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0036]

[0034] Overall, this invention can be categorized as a structural or device-level innovation. It demonstrates a new way of arranging a spot size converter, using confinement rods in multiple vertical layers around a centrally located functional waveguide, to achieve high- efficiency fiber-to-chip coupling in a smaller footprint and with reduced complexity compared to conventional approaches.

[0037]

[0035] Fig. 1 includes a top schematic view and various cross sectional views of a photonic integrated circuit (PIC) chip 10, according to the presently disclosed invention.

[0038]

[0036] Referring to portion (A) of Fig. 1 , a top view shows an array of confinement rods. The confinement rods are arrayed around a waveguide 100 that tapers into a spot size converter (SSC) for the portion of the waveguide as it approaches the edge or facet 52 of the photonic integrated circuit (PIC) chip 10. Specifically the waveguide 100 begins with a width that is characteristic of the waveguides within the chip but as it nears the edge, the waveguide transitions to a tapered section 100T that tapers, e.g., linearly, such that its width when it reaches the edge 52 of the chip 10 is reduced by at least 50%, or possibly by 75% or even 80% or more. For example, the width of the waveguide may taper such that its width when it reaches the edge 52 of the chip 10 is reduced by 50% to 90%. At the same time, the confinement rods are tapered in the opposite way such that the confinement rods linearly increase in width moving in the direction toward the edge 52. The length of the tapered section 100T may be on the order of hundreds of micrometers (e.g., several hundreds of micrometers) and / or may be based on an operating wavelength of the PIC chip 10 (e.g., increasing with decreasing wavelength), for example, with relatively larger lengths being used for relatively shorter operating wavelengths and relatively shorter lengths being used for relatively longer operating wavelengths.

[0037] The confinement rods, in the illustrated example, are organized in several, such as three, layers below the waveguide 100 and one or more layers above the waveguide. In addition, rods can be added to the same layer as the waveguide 100.

[0039]

[0038] Specifically, in the illustrated example, in a lowest layer LayerO just above a lower cladding layer and silicon or silicon on insulator base wafer 50, there is a LayerO confinement rod 112 running parallel to and directly below the tapered section of the waveguide 100T.

[0040]

[0039] In a next higher layer Layer 1 , there are a set of several, such as four, Layer 1 confinement rods 122, 124, 126, 128 running parallel to the tapered section of the waveguide 100T.

[0041]

[0040] In a next higher layer Layer2, there are a set of several, such as four, Layer2 confinement rods 132, 134, 136, 138 running parallel to the tapered section of the waveguide 100T. The tapered section of the waveguide 100T is in LayerW that is slightly higher than Layer2. The presence of successive layers of rods in LayerO, Layer 1, and Layer2 ensures a gradual modification of the effective refractive index environment around the waveguide, promoting efficient mode transformation. Because the waveguide core is elevated relative to the lower layers of confinement rods, the rods in LayerO, Layer 1, and Layer2 primarily shape the optical field from below.

[0042]

[0041] Then above the waveguide 100T in Layer4, three Layer4 confinement rods 152, 154, 156 run parallel to the tapered section of the waveguide 100T. These rods provide an upper boundary that complements the lower confinement rods, thereby enhancing vertical and lateral optical confinement.

[0043]

[0042] Notably, in the region near the chip facet 52, the confinement rods in each layer are designed to taper in the opposite sense to the waveguide taper. As the waveguide narrows toward the edge, the confinement rods gradually increase in width (or cross-sectional dimension) in the same direction. This complementary tapering arrangement — waveguide narrowing combined with rod widening — allows for a smoother transition of the optical mode, reducing reflection and scattering losses. By tailoring the placement, spacing, and width of the rods in each layer, the spot size converter can more effectively expand or compress the guided mode for coupling to an external fiber at the chip edge. The tapering of the confinement rods and / or the waveguide 100 may include a change in width in the order of hundreds of nanometers over a length in the order of hundreds of nanometers, with a taper angle between approximately 0.01° and 0.1°.

[0044]

[0043] In general, each confinement rod has a thickness in a range of about 50 nanometers to about 150 nanometers and a width in a range of about 150 nanometers to about 600 nanometers at their widest point.

[0045]

[0044] Portion (B) of Fig. 1 presents a cross-sectional view of the photonic integrated circuit (PIC) chip 100 before the confinement rod array is introduced closer to the chip’s edge 52. In this particular cross section, the waveguide 100, located in LayerW, runs through the chip as it normally would in the interior region, without any specialized patterning around it.

[0046]

[0045] Below LayerW, three material layers — LayerO, Layer 1 , and Layer2 — are stacked atop the chip’s lowest cladding layer and base wafer 50, which may be silicon or silicon-on- insulator. In this pre-confinement section, these lower layers appear as uniform dielectric films such as SiCh, since the confinement rods have not yet started. The waveguide 100 itself, typically composed of a high-refractive-index material such as silicon or silicon nitride, is shown in cross section in LayerW. It is surrounded by standard cladding materials that help guide light within the waveguide core.

[0047]

[0046] Above the waveguide layer lies Layer4. In this cross-sectional slice, Layer4 also remains unpatterned, serving simply as another uniform dielectric film. Farther toward the chip edge, Layer4 eventually accommodates the upper confinement rods for spot size conversion. However, in Portion (B), the cross section emphasizes the baseline structure of the chip — namely, the continuous dielectric layers below and above the waveguide — prior to the transition where the confinement rods begin.

[0048]

[0047] Portion (C) of Fig. 1 provides a cross-sectional snapshot of the photonic integrated circuit (PIC) chip 10 right at its edge 52, where the waveguide 100T has fully tapered to its narrowest width in LayerW. This taper is designed to match, as closely as possible, the mode size of the external optical fiber that will couple light at the facet.

[0048] In contrast to the waveguide’s reduced cross section, the confinement rods in each of the underlying and overlying layers have broadened to their largest widths at the chip edge. Specifically, in LayerO, the single confinement rod 112 is shown at its maximum lateral extent. In Layerl, the four confinement rods (122, 124, 126, 128) also widen to provide an increasingly strong index contrast near the facet. Likewise, the four rods in Layer2 (132, 134, 136, 138) reach their maximum widths at this boundary, further assisting in effectively guiding and transitioning the optical mode to the waveguide taper. Finally, in Layer4, a set of confinement rods (152, 154, 156) appears above the waveguide at their largest widths, providing top-side confinement that complements the lower layers.

[0049]

[0049] This coordinated tapering of the waveguide core (narrowing) and the confinement rods (broadening) creates a smooth mode transition region, reducing scattering and reflection losses. As a result, the light traveling through the fully tapered waveguide 100T at the edge couples more efficiently into — or out of — an external fiber. The cross section shown in Portion (C) thus underscores how both the waveguide and rod geometries are precisely engineered to optimize edge coupling performance.

[0050]

[0050] In some embodiments, the dielectric thickness between the functional waveguide (e.g., the waveguide 100) and each confinement -rod layer is up to 500 nanometers. The dielectric thickness may increase with the operating wavelength of the PIC chip 10.

[0051]

[0051] Fig. 2A is a cross-sectional view of another embodiment of the SSC of the photonic integrated circuit (PIC) chip 10 at its edge 52. The waveguide 100T has narrowed to its smallest width. This tapering of the waveguide is designed to match the optical mode of an external fiber more closely and reduce coupling losses. Surrounding the waveguide are layers of confinement rods, each carefully configured to broaden in width at the chip edge in tandem with the waveguide’s taper.

[0052]

[0052] Beneath the waveguide, LayerO contains a single rod (112), which is shown at its maximum lateral extent at the facet. Above that, Layerl includes four rods (122, 124, 126, 128), and Layer2 has another four rods (132, 134, 136, 138). As in earlier embodiments, these rods in the lower layers collectively guide and shape the light as it transitions through the narrowing waveguide core.

[0053] However, unlike the version depicted in Portion (C) of Fig. 1 , there are four rods (152, 154, 156, 158) in Layer4 instead of three. These top-layer rods also reach their widest dimensions at the chip’s edge, providing added control over the waveguide’s vertical confinement. By spreading the optical mode between lower and upper confinement structures, the design creates a smoother transition region where the waveguide (100T) meets the external fiber.

[0053]

[0054] Overall, Fig. 2A demonstrates how including an additional rod in Layer4 can offer improved versatility in tailoring the electromagnetic field profile at the facet, making the coupling process more robust against variations in fabrication and alignment.

[0054]

[0055] Fig. 2B is a cross-sectional view of another embodiment of an SSC of the photonic integrated circuit (PIC) chip 10 at the chip edge 52. The waveguide 100T has tapered to its narrowest width. This tapering reduces the optical mode size to match more closely with an external fiber, thereby improving coupling efficiency. Surrounding the tapered waveguide is an array of confinement rods arranged in multiple layers, each designed to provide lateral and vertical mode confinement.

[0055]

[0056] Below the waveguide, LayerO contains a single confinement rod (112), which expands to its maximum width near the chip facet. Moving upward, Layer 1 features four rods (122, 124, 126, 128), all of which also reach their largest widths at the edge. In Layer2, however, the design has been simplified compared to earlier embodiments: there are now only two rods (132, 134) instead of four. These two rods still broaden as they approach the facet, guiding the light through the narrowing waveguide core.

[0056]

[0057] Above the waveguide in LayerW, Layer4 contains its own set of rods (152, 154,

[0057] 156), similarly expanding to their widest dimensions at the edge. Together, the rods above and below the waveguide work in concert to shape the optical mode through this transition region. The choice to use only two rods in Layer2 can streamline the fabrication process or adjust how the mode is confined, potentially affecting performance metrics such as insertion loss or sensitivity to alignment tolerances.

[0058] Overall, Fig. 2B demonstrates a design variant of the confinement rod arrangement in which the total number of rods in Layer2 is reduced, while still offering effective confinement and mode matching for the waveguide at the chip edge.

[0058]

[0059] Fig. 2C is a cross-sectional view of another embodiment of the SSC of the photonic integrated circuit (PIC) chip (10) at its edge (52). Again, the waveguide (100T) narrows to its smallest width for improved coupling to an external fiber. Just as in previous embodiments, the tapered waveguide is surrounded by confinement rods in multiple layers — LayerO, Layer 1, Layer2, and Layer4 — all of which reach their maximum widths at the facet.

[0059]

[0060] In this particular design, there is now an additional Layer5 above Layer4. This new layer contains three confinement rods (162, 164, 166), each positioned to help maintain tight control over the optical mode vertically and laterally as it transitions out of the narrow waveguide core. By stacking another set of rods above the topmost layer of the waveguide, the device provides an enhanced index contrast gradient, potentially reducing reflections and improving overall coupling efficiency.

[0060]

[0061] Below the waveguide, LayerO still includes the single rod (112), and Layers 1 and Layer2 each contains multiple rods (122, 124, 126, 128, and 132, 134, respectively). Above the waveguide in Layer4, rods (152, 154, 156) also maintain the broadening profile near the edge. Now, with Layer5 also contributing, the confinement rods collectively form a more comprehensive framework for guiding the optical mode.

[0061]

[0062] This additional layer highlights the flexibility designers have in tailoring rod arrangements for specific performance needs. Whether balancing fabrication complexity or optimizing optical confinement, the inclusion of Layer5 rods (162, 164, 166) illustrates how the vertical stacking of rods can be expanded to further refine edge coupling behavior.

[0062]

[0063] Fiber-to-chip optical interconnects play an essential role in integrating specialized photonic integrated circuits (PICs) into larger systems. Two principal coupling strategies are commonly employed: off-plane coupling via grating couplers and in-plane coupling via spot size converters (SSCs). While grating couplers can ease alignment, in-plane coupling remains attractive in many scenarios because of the potential for lower insertion loss — provided the on- chip waveguide mode can be expanded to match the larger mode area of an external optical fiber.

[0063]

[0064] In practice, most of a PIC’s functionality is carried out in highly confined waveguides that offer a small cross section for efficient switching, modulation, and filtering. Tightly confining the optical mode in these regions reduces chip footprint and power consumption, but when it comes to interfacing with optical fibers, such small modes lead to significant mode-size mismatches. SSCs aim to transition gradually from the tight waveguide mode on the chip to a larger mode better suited for low-loss coupling to fibers, thus driving overall insertion losses down.

[0064]

[0065] Fig. 3 A is a plot of transmission for a conventional spot size converter.

[0065]

[0066] The graph in Fig. 3A illustrates the transmission performance of a conventional spot size converter (SSC) where the waveguide is not part of the layers supporting the supermode. This configuration typically results in longer device lengths due to a more gradual mode transformation. The graph presents two transmission plots, corresponding to the transverse electric (TE) mode and the transverse magnetic (TM) mode, with transmission loss measured in decibels (dB) along the y-axis and the taper length L2 in micrometers (pm) along the x-axis.

[0066]

[0067] In the illustrated example, the TE plot represents transmission from the facet side to the waveguide side, while the TM plot represents transmission from the waveguide side to the facet side.

[0067]

[0068] The TE mode plot starts at -1.1 dB at around 800 pm and increases sharply to -0.2 dB at around 1700 pm and then continues to increase gradually, reaching approximately -0.1 dB at 3000 pm. The TM mode plot starts at -1.1 dB at approximately 500 pm, increases sharply to about -0.3 dB at around 900 pm, more gradually increases to -0.2 dB between 1100 pm and 1900 pm, and then gradually tapers back to -0.3 dB at 3000 pm.

[0068]

[0069] A vertical reference line is drawn at 1700 pm, where the TE and TM plots intersect. This suggests that a significant transmission improvement occurs at this length. Accordingly, the conventional SSC design necessitates a longer taper of 1800 pm to achieve sufficient mode conversion and low loss. The total device length required for effective mode conversion is quite large.

[0070] Fig. 3B is a plot of transmission for a spot size converter according to the present invention.

[0069]

[0071] More particularly, Fig. 3B illustrates the transmission performance of a spot size converter (SSC) according to the present invention, where the waveguide is integrated within the super-mode layers (and even positioned centrally within them). This approach results in a significantly shorter device while maintaining high transmission efficiency. The graph presents transmission results for TE mode and TM mode, with transmission measured in dB along the y-axis and the slow section length in micrometers (pm) along the x-axis. The y-axis is labeled as "Transmission (dB)", ranging from -0.5 dB to 0 dB in increments of 0.05 dB, and the x-axis is labeled as "Slow section length (pm)", ranging from 0 pm to 500 pm in increments of 50 pm.

[0070]

[0072] In the illustrated example, the TE mode plot, starts at -0.5 dB at approximately 60 pm, increases sharply to -0.025 dB at around 350 pm, slightly tapers down to -0.05 dB at approximately 500 pm. The TM mode plot starts at -0.5 dB at around 25 pm, increases sharply to -0.1 dB at about 200 pm, and remains nearly constant at -0.1 dB until 500 pm.

[0071]

[0073] A vertical reference line is drawn at 225 pm, where the TE and TM modes are both around -0.1 dB, indicating that efficient mode conversion occurs within a much shorter length (e.g., 400 pm) compared to the conventional SSC in Fig. 3 A. Thus, for example, the present invention achieves effective mode conversion in a device that is less than one-fourth the length of the conventional SSC in Fig. 3A.

[0072]

[0074] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims

CLAIMSWhat is claimed is:

1. A photonic device for coupling light into and / or out of an on-chip waveguide, comprising: a waveguide disposed in a waveguide layer, the waveguide having a tapered portion configured to reduce its width toward a facet of a photonic integrated circuit chip; an array of confinement rods arranged around the tapered portion of the waveguide in at least one layer below the waveguide layer and at least one layer above the waveguide layer, each confinement rod having a width that increases toward the facet; wherein the tapered waveguide and the confinement rods are collectively configured to form a spot size converter that transitions an optical mode from a confined cross-section within the waveguide to a larger cross-section at the facet.

2. The photonic device of claim 1, wherein the waveguide comprises a high-refractive- index material selected from the group consisting of silicon and silicon nitride.

3. The photonic device of claim 2, wherein the waveguide layer is part of a silicon-on- insulator (SOI) platform, and the waveguide is formed in a top silicon device layer of said SOI platform.

4. The photonic device of any of claims 1-3, wherein the array of confinement rods is arranged in at least three distinct confinement-rod layers located below and above the waveguide layer.

5. The photonic device of claim 4, wherein each confinement-rod layer contains a plurality of rods configured such that, as the waveguide width decreases, the widths of the rods increase to define a complementary tapering pattern.

6. The photonic device of any of claims 1-5, wherein the tapered portion of the waveguide has a taper angle between 0.01° and 0.1° relative to a longitudinal axis of the waveguide.

7. The photonic device of any of claims 1-6, wherein the confinement rods have a cross-sectional shape selected from the group consisting of rectangular rods, cylindrical rods, or rib-like rods.

8. The photonic device of claim 7, wherein the confinement rods are formed of a dielectric material having a refractive index lower than that of the waveguide material, thereby defining a super-mode that encompasses both the waveguide and the confinement rods.

9. The photonic device of any of claims 1-8, further comprising a cladding layer surrounding the waveguide and the confinement rods, such that the spot size converter region is encapsulated to preserve the designed optical field distribution.

10. The photonic integrated circuit of any of claims 1-9, wherein each confinement rod has a thickness in a range of about 50 nanometers to about 150 nanometers and a width in a range of about 150 nanometers to about 600 nanometers.

11. A photonic device for edge coupling, comprising: a base substrate; a plurality of dielectric layers formed above the base substrate, including a waveguide layer and one or more confinement-rod layers; a waveguide located in the waveguide layer, having a first width over a main portion of a photonic circuit and transitioning to a narrower width at a facet of the photonic circuit; one or more arrays of confinement rods disposed in at least two distinct confinement-rod layers, each confinement-rod layer comprising at least one confinement rod extending toward the facet, the confinement rods tapering to a wider cross-section near the facet;wherein the confinement rods and the tapered waveguide collectively define a super-mode that expands from the narrower waveguide region to a larger mode suitable for coupling to an external optical fiber.

12. A method of fabricating a photonic device for coupling light between an optical fiber and an on-chip waveguide, the method comprising: providing a substrate having at least one dielectric layer suitable for forming a waveguide layer; forming a waveguide core in the waveguide layer, wherein the waveguide core is configured to guide light along a longitudinal axis; defining a tapered portion of the waveguide core that decreases in width toward a facet of the substrate; forming an array of confinement rods in at least one layer below the waveguide layer and at least one layer above the waveguide layer, wherein each confinement rod has a width that increases toward the facet; arranging the tapered waveguide core and the array of confinement rods so as to create a spot size converter region at the facet, wherein the spot size converter is configured to transition an optical mode from the waveguide core to a larger mode suitable for coupling to the optical fiber.

13. The method of claim 12, wherein the waveguide layer comprises crystalline silicon or silicon nitride, and wherein forming the waveguide core includes lithographically patterning and etching the waveguide layer.

14. The method of claim 13, wherein providing the substrate comprises using a silicon- on-insulator (SOI) wafer such that the waveguide core is formed in a top silicon device layer of the SOI wafer, and the dielectric layer is an oxide layer.

15. The method of any of claims 12-14, wherein forming the array of confinement rods comprises: depositing a rod-forming material in at least two confinement-rod layers, patterning each confinement-rod layer using lithography, andetching the rod-forming material to create a plurality of rods oriented substantially parallel to the longitudinal axis of the tapered waveguide core.

16. The method of claim 15, wherein the step of defining the tapered portion of the waveguide core and the step of forming the array of confinement rods are coordinated such that a taper angle of the waveguide core and a corresponding taper angle of the rods collectively shape a super-mode encompassing both the waveguide core and the rods.

17. The method of any of claims 12-16, further comprising depositing one or more cladding layers over and / or under the waveguide layer and the confinement rods, thereby encapsulating the spot size converter region to maintain optical confinement and reduce scattering losses.

18. The method of any of claims 12-17, wherein the array of confinement rods is formed to have a cross-sectional shape selected from rectangular rods, cylindrical rods, or rib-like structures, and wherein the dimensions of each rod are selected to achieve a target optical mode size at the facet.

19. The method of any of claims 12-18, wherein forming the tapered portion includes reducing the waveguide core width by at least 50% from an interior region of the photonic device to the facet, and wherein forming the confinement rods includes increasing a width of each rod by at least 50% in the same direction, thereby providing complementary tapering profiles for efficient mode conversion.

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