Multilayer ceramic capacitor and method for manufacturing multilayer ceramic capacitor

Abstract

The present invention addresses the problem of suppressing concentration of residual stress caused by thermal shrinkage in a multilayer ceramic capacitor. One embodiment of the present invention relates to a multilayer ceramic capacitor comprising a main body, a first external electrode provided to the main body, and a second external electrode provided to the main body. The main body has a plurality of dielectric layers and a plurality of internal electrode layers that are stacked in a stacking direction with at least one of the plurality of dielectric layers interposed therebetween. The main body is partitioned into a central portion, a lower cover portion that is positioned below the central portion in the stacking direction, and an upper cover portion that is positioned above the central portion in the stacking direction. The main body is configured so that, from the upper end to the lower end of the central portion in the stacking direction, the area of each internal electrode layer constituting the plurality of internal electrode layers decreases with increasing proximity to the lower surface of the main body.

Description

Multilayer ceramic capacitor and method of manufacturing the same

[0001] The disclosure of this specification primarily relates to multilayer ceramic capacitors and methods for manufacturing multilayer ceramic capacitors.

[0002] Multilayer ceramic capacitors are mounted in a variety of electronic devices. A multilayer ceramic capacitor has a body in which multiple dielectric layers and multiple internal electrode layers are alternately stacked. When a voltage is applied to the internal electrode layers during use of a multilayer ceramic capacitor, capacitance is generated in the capacitance generating region where the dielectric layers and the internal electrode layers face each other.

[0003] Since the thermal shrinkage rate of the dielectric layer is different from that of the internal electrode layer, when the body of the multilayer ceramic capacitor becomes hot during manufacture or use and is then cooled, residual stress occurs in the body due to the difference between the thermal shrinkage rates of the dielectric layer and the internal electrode layer, and this residual stress may cause cracks in the body.

[0004] Japanese Patent Laid-Open Publication No. 2015-26844 describes a multilayer ceramic capacitor configured such that the width of the internal electrode layers (including the second outermost layer 4b) located near the mounting surface in the stacking direction is smaller than the width of the internal electrode layer located at the center in the stacking direction. According to the publication, this configuration can suppress residual stress caused by the difference in thermal contraction rate between the dielectric layers and the internal electrode layers, thereby suppressing the occurrence of cracks in the body.

[0005] JP 2015-26844 A

[0006] In the multilayer ceramic capacitor described in Patent Document 1, the cross-sectional shape of the capacitance generating portion differs between a region close to the mounting surface and a region distal from the mounting surface. Specifically, as shown in FIG. 3 of Patent Document 1, the outer edge of the capacitance generating portion in the region close to the mounting surface is defined by a trapezoid (a trapezoid whose lower base close to the mounting surface is shorter than its upper base distal from the mounting surface), while the cross-sectional shape of the capacitance generating portion in the region distal from the mounting surface is defined by a rectangle. Thus, in the multilayer ceramic capacitor described in Patent Document 1, in a cross section of the body cut along the lamination direction, the capacitance generating portion has a shape that combines a trapezoid and a rectangle. This means that residual stress tends to concentrate at the boundary between the trapezoidal region and the rectangular region, resulting in a problem of cracks being likely to occur near that boundary.

[0007] A multilayer ceramic capacitor that can suppress the occurrence of cracks due to residual stress not only near the bottom end of the capacitance generating region in the lamination direction but also throughout the entire capacitance generating region has not been known. Therefore, suppressing the occurrence of cracks due to residual stress throughout the entire region from the top to the bottom of the capacitance generating region remains an unsolved issue in multilayer ceramic capacitors.

[0008] One object of the invention disclosed in this specification is to suppress the concentration of residual stress due to thermal contraction in a multilayer ceramic capacitor. A more specific object of the invention disclosed in this specification is to suppress the concentration of residual stress due to thermal contraction in the entire region of a multilayer ceramic capacitor, from the upper end to the lower end of the capacitance generating region.

[0009] Objects of the present invention other than those mentioned above will become clear throughout the entire specification. The invention disclosed in this specification may solve problems that are understood from other than the description in the "Problem to be Solved by the Invention" section. When the present specification describes the effects of an embodiment, the problem of the invention corresponding to that embodiment can be understood from those effects.

[0010] The various inventions disclosed in this specification may be collectively referred to as "the present invention." A multilayer ceramic capacitor according to one aspect of the present invention includes a main body partitioned into a central portion including a capacitance generating region in which a plurality of dielectric layers and a plurality of internal electrode layers are alternately stacked in a stacking direction, a lower cover portion located below the central portion in the stacking direction, and an upper cover portion located above the central portion in the stacking direction, and external electrodes provided on the main body. The main body is configured such that, from the upper end to the lower end of the central portion in the stacking direction, the area of ​​each of the internal electrode layers constituting the plurality of internal electrode layers decreases toward the underside of the main body.

[0011] According to one embodiment of the invention disclosed in this specification, it is possible to suppress the concentration of residual stress due to thermal shrinkage.

[0012] 1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor of FIG. 1 cut along a side surface; FIG. 3 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor of FIG. 1 cut along an end surface; FIG. 4 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor according to another embodiment of the present invention cut along an end surface; FIG. 5 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor according to yet another embodiment of the present invention cut along a side surface; FIG. 6 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor according to another embodiment of the present invention cut along a side surface; FIG. 7 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor according to another embodiment of the present invention cut along a side surface; 1A and 1B are schematic diagrams illustrating a laminate sheet 104 and an unfired chip laminate 111 produced in a process for producing a multilayer ceramic capacitor according to an embodiment of the present invention;

[0013] Various embodiments of the present invention will be described below with appropriate reference to the drawings. Components common to multiple drawings are designated by the same or similar reference numerals throughout the drawings. Please note that the drawings are not necessarily drawn to scale for the sake of convenience. The embodiments described below do not necessarily limit the invention according to the claims. Elements described in the following embodiments are not necessarily essential to the solution of the invention.

[0014] For ease of explanation, each figure may include an L axis, a W axis, and a T axis that are perpendicular to each other. In this specification, the dimensions, arrangement, shape, and other features of each component of the multilayer ceramic capacitor 1 may be described with reference to the L axis, the W axis, and the T axis. 1 Multilayer Ceramic Capacitor 1 (First Embodiment) 1-1 Basic Structure of the Multilayer Ceramic Capacitor 1 The basic structure of a multilayer ceramic capacitor 1 according to one embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a perspective view of a multilayer ceramic capacitor 1 according to one embodiment. FIG. 2 is a cross-sectional view schematically showing the cross section of the multilayer ceramic capacitor 1 taken along line II. FIG. 3 is a cross-sectional view schematically showing the cross section of the multilayer ceramic capacitor 1 taken along line II-II.

[0015] The multilayer ceramic capacitor 1 includes a body 10, and a first external electrode 31 and a second external electrode 32 provided on the body 10. The first external electrode 31 is disposed spaced apart from the second external electrode 32.

[0016] The main body 10 includes a plurality of dielectric layers 11, a plurality of first internal electrode layers 21, and a plurality of second internal electrode layers 22. In this specification, when it is not necessary to distinguish between the first internal electrode layers 21 and the second internal electrode layers 22, the first internal electrode layers 21 and the second internal electrode layers 22 may be collectively referred to as "internal electrode layers." The dielectric layer 11 is disposed between adjacent internal electrode layers. For example, the first internal electrode layer 21 is disposed on the upper surface of the dielectric layer 11, and the second internal electrode layer 22 is disposed on the lower surface of the dielectric layer 11.

[0017] In the main body 10, the dielectric layers 11, the first internal electrode layers 21, and the second internal electrode layers 22 are stacked along a stacking direction (for example, the T-axis direction). The stacking direction may be along the T-axis as in the illustrated embodiment, or along the L-axis or W-axis.

[0018] The main body 10 has an upper surface 10a, a lower surface 10b, a first end surface 10c, a second end surface 10d, a first side surface 10e, and a second side surface 10f. The outer surface of the main body 10 is defined by the upper surface 10a, the lower surface 10b, the first end surface 10c, the second end surface 10d, the first side surface 10e, and the second side surface 10f.

[0019] The top surface 10a and the bottom surface 10b respectively form the surfaces at both ends of the main body 10 in the height direction (T-axis direction). The top surface 10a and the bottom surface 10b face each other in the T-axis direction. The first end surface 10c and the second end surface 10d respectively form the surfaces at both ends of the main body 10 in the length direction (L-axis direction). The first end surface 10c and the second end surface 10d face each other in the L-axis direction. The first side surface 10e and the second side surface 10f respectively form the surfaces at both ends of the main body 10 in the width direction (W-axis direction). The first side surface 10e and the second side surface 10f face each other in the W-axis direction. The top surface 10a and the bottom surface 10b are spaced apart by the height dimension of the main body 10, the first end surface 10c and the second end surface 10d are spaced apart by the length dimension of the main body 10, and the first side surface 10e and the second side surface 10f are spaced apart by the width dimension of the main body 10.

[0020] One end of the first internal electrode layer 21 is extended toward the outside of the main body 10. The first internal electrode layer 21 is connected to a first external electrode 31 provided on the surface of the main body 10. One end of the second internal electrode layer 22 is extended toward the outside of the main body 10. The second internal electrode layer 22 is connected to a second external electrode 32 provided on the surface of the main body 10. In the embodiment shown in FIG. 2 , the first internal electrode layer 21 is extended toward the outside of the main body 10 from the first end face 10c. The first internal electrode layer 21 is connected to the first external electrode 31 at one end of the main body 10 in the L-axis direction. The second internal electrode layer 22 is extended toward the outside of the main body 10 from the second end face 10d. The second internal electrode layer 22 is connected to the second external electrode 32 at the other end of the main body 10 in the L-axis direction. 2, the first internal electrode layer 21 and the second internal electrode layer 22 are respectively drawn to the opposing first end face 10c and second end face 10d, but the first internal electrode layer 21 and the second internal electrode layer 22 may be drawn from various surfaces of the main body 10 depending on the arrangement and shape of the first external electrode 31 and the second external electrode 32. For example, if the first external electrode 31 and the second external electrode 32 are both arranged on the lower surface 10b, then both the first external electrode 31 and the second external electrode 32 are drawn from the lower surface. The first external electrode 31 and the second external electrode 32 may be provided on any surface of the main body 10 as long as they are spaced apart from each other.

[0021] In one embodiment, the multilayer ceramic capacitor 1 may be configured to have a rectangular parallelepiped shape. In this specification, the terms "rectangular parallelepiped" or "rectangular parallelepiped shape" do not necessarily mean "rectangular parallelepiped" in the strict mathematical sense. As will be described later, the corners and / or sides of the main body 10 may be curved. The dimensions and shape of the main body 10 are not limited to those explicitly stated in this specification.

[0022] In one embodiment, the dimension (length dimension) of the multilayer ceramic capacitor 1 in the L-axis direction is in the range of 0.2 mm to 3.5 mm, the dimension (width dimension) in the W-axis direction is in the range of 0.1 mm to 2.5 mm, and the dimension (height dimension) in the T-axis direction is in the range of 0.1 mm to 3.0 mm. In one embodiment, the length dimension of the multilayer ceramic capacitor 1 may be greater than the width dimension. In one embodiment, the height dimension of the multilayer ceramic capacitor 1 may be greater than the width dimension. In one embodiment, the width dimension of the multilayer ceramic capacitor 1 may be greater than the length dimension.

[0023] As shown in FIG. 2 , the multilayer ceramic capacitor 1 may be mounted on an electronic circuit board 2. For simplicity of illustration, the electronic circuit board 2 is omitted from FIGS. 1 and 3 . The electronic circuit board 2 on which the multilayer ceramic capacitor 1 is mounted may be called a circuit module. Various electronic components other than the multilayer ceramic capacitor 1 may also be mounted on the circuit module. This circuit module may be mounted in various electronic devices. Electronic devices in which the circuit module may be mounted include smartphones, tablets, game consoles, automotive electrical components, servers, and various other electronic devices.

[0024] The multilayer ceramic capacitor 1 is mounted on the surface of the electronic circuit board 2 so that the lower surface 10b of the body 10 faces the surface of the electronic circuit board 2. For this reason, the lower surface 10b of the body 10 is sometimes referred to as the mounting surface (mounting surface 10b). The multilayer ceramic capacitor 1 is joined by solder to lands provided on the surface of the electronic circuit board 2. The lands are provided on the surface of the electronic circuit board 2 at positions corresponding to the first external electrode 31 and the second external electrode 32. The lands are not shown in FIG. 2 .

[0025] 1-2 Compartments of the Main Body 10 The main body 10 is compartmented into multiple regions. In the illustrated embodiment, the main body 10 is compartmented into at least a central portion R1, an upper cover portion R2 located above the central portion R1 in the stacking direction (T-axis direction), and a lower cover portion R3 located below the central portion R1 in the stacking direction. The upper cover portion R2 covers the upper end of the central portion R1. The lower cover portion R3 covers the lower end of the central portion R1.

[0026] The central portion R1 is divided into a capacitance generating region Ra and a margin region. The margin region is further divided into an end margin region and a side margin region. In the end margin region, the first internal electrode layers 21 face each other or the second internal electrode layers face each other. On the other hand, neither the first internal electrode layers 21 nor the second internal electrode layers 22 are arranged in the side margin region. In the illustrated embodiment, the end margin region is further divided into a first end margin region Rem1 and a second end margin region Rem2, and the side margin region is further divided into a first side margin region Rsm1 and a second side margin region Rsm2.

[0027] In the capacitance generating region Ra, the first internal electrode layer 21 and the second internal electrode layer 22 are arranged to face each other in the stacking direction via the dielectric layer 11. When a voltage is applied between the first external electrode 31 and the second external electrode 32, a capacitance is generated between the first internal electrode layer 21 and the second internal electrode layer 22. In other words, the capacitance generating region Ra is a region where the first internal electrode layer 21 and the second internal electrode layer 22 face each other in the stacking direction, and is a region where a capacitance is generated.

[0028] As described above, the end margin region is a region where the first internal electrode layers 21 or the second internal electrode layers face each other. The end margin region is arranged between the capacitance generating region and the surface of the main body 10. In the embodiment shown in FIG. 2 , the end margin region includes a first end margin region Rem1 and a second end margin region Rem2. The first end margin region Rem1 is a region between the capacitance generating region Ra and the first end face 10c of the main body 10. The first internal electrode layer 21 is arranged in the first end margin region Rem1, but the second internal electrode layer 22 is not arranged. The second end margin region Rem2 is a region between the capacitance generating region Ra and the second end face 10d of the main body 10. The second end margin region Rem2 is a region between the capacitance generating region Ra and the second end face 10d of the main body 10. The second internal electrode layer 22 is arranged in the second end margin region Rem2, but the first internal electrode layer 21 is not arranged.

[0029] As described above, the side margin region is a region in which no internal electrode layers are arranged. The side margin region is arranged between the capacitance generating region and the surface of the main body 10. In the embodiment shown in FIG. 3 , the side margin region includes a first side margin region Rsm1 and a second side margin region Rsm2. The first side margin region Rsm1 is a region between the capacitance generating region Ra and the first side surface 10e of the main body 10. Neither the first internal electrode layer 21 nor the second internal electrode layer 22 is arranged in the first side margin region Rsm1. The second side margin region Rsm2 is a region between the capacitance generating region Ra and the second side surface 10f of the main body 10. Neither the first internal electrode layer 21 nor the second internal electrode layer 22 is arranged in the second side margin region Rsm2. Since no internal electrode layers are arranged in the first side margin region Rsm1 and the second side margin region Rsm2, neither the first side margin region Rsm1 nor the second side margin region Rsm2 contributes to the generation of capacitance.

[0030] 1-3 Dielectric Layer 11 The dielectric layer 11 may include a ceramic material having a high dielectric constant. The dielectric layer 11 may include, for example, an oxide represented by the chemical formula ABO3 as a main component. In the chemical formula ABO3, "A" is, for example, at least one element selected from the group consisting of Ba (barium), Sr (strontium), Ca (calcium), and Mg (magnesium). In the chemical formula ABO3, "B" is, for example, at least one element selected from the group consisting of Ti (titanium), Zr (zirconium), and Hf (hafnium). Examples of oxides included as a main component in the dielectric layer 11 include BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), and MgTiO3 (magnesium titanate).

[0031] In addition to the oxide of the main component, the dielectric layer 11 may contain elements derived from known sintering aids. Examples of elements derived from known sintering aids are Mg (magnesium) and Mn (manganese).

[0032] The dielectric layer 11 may contain an additive element. In one embodiment, the additive element contained in the dielectric layer 11 is at least one element selected from the group consisting of Ni (nickel), Mo (molybdenum), Nb (niobium), Ta (tantalum), W (tungsten), V (vanadium), and Cr (chromium). The dielectric layer 11 may contain two or more types of the additive elements.

[0033] Dielectric layer 11 may contain an oxide of a rare earth element in addition to the oxide of the main component. The oxide of the rare earth element contained in dielectric layer 11 may be an oxide of at least one rare earth element selected from the group consisting of Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium). Dielectric layer 11 may contain two or more types of oxides of rare earth elements.

[0034] The dielectric layer 11 may further contain another type of oxide. For example, the dielectric layer 11 may contain an oxide of at least one element selected from the group consisting of Co (cobalt), Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon). The dielectric layer 11 may contain two or more types of oxides of these elements.

[0035] The dielectric layer 11 may contain a glass containing at least one element selected from the group consisting of Co, Ni, Li, B, Na, K, and Si.

[0036] In one embodiment, the thickness of the dielectric layer 11 (the dimension in the T-axis direction) is 0.1 to 5 μm. When the dielectric film 11 is formed by a sputtering method, the thickness of the dielectric layer 11 may be small, for example, 0.1 μm to 1 μm. When the dielectric film 11 is formed by a known method other than the sputtering method, for example, a printing method, the thickness of the dielectric layer 11 may be 0.4 μm to 3 μm.

[0037] 1-4 First Internal Electrode Layers 21 and Second Internal Electrode Layers 22 The capacitance generating region Ra includes n first internal electrode layers 21 and n or (n-1) second internal electrode layers 22. In the illustrated embodiment, n first internal electrode layers 21 and n second internal electrode layers 22 (where n is a positive integer) are stacked in the capacitance generating region Ra. When it is necessary to distinguish a specific one of the first internal electrode layers 21 from the others, each first internal electrode layer 21 is distinguished by adding a sub-number to the reference numeral indicating the first internal electrode layer 21, such that the first internal electrode layer 21 closest to the lower surface 10b of the main body 10 is referred to as the first internal electrode layer 21-1, the next closest is referred to as the first internal electrode layer 21-2, and so on. Since only n first internal electrode layers 21 are stacked, the first internal electrode layer 21-n is disposed closest to the upper surface 10a of the main body 10. Any internal electrode layer included in the first internal electrode layer 21 is represented as a first internal electrode layer 21-m (where m is a positive integer equal to or less than n). Similarly, when it is necessary to distinguish a specific one of the second internal electrode layers 22 from the others, the second internal electrode layer 22 that is closest to the lower surface 10b of the main body 10 is represented as a second internal electrode layer 22-1, the next closest one is represented as a second internal electrode layer 22-2, etc. Since n or n-1 layers of the second internal electrode layers 22 are stacked, the second internal electrode layer 22-n or the second internal electrode layer 22-(n-1) is arranged closest to the upper surface 10a of the main body 10. Any internal electrode layer included in the second internal electrode layer 22 is expressed as a second internal electrode layer 22-m (where m is a positive integer equal to or less than n when the second internal electrode layer 22-n is closest to the upper surface 10a of the main body 10, and m is a positive integer equal to or less than n-1 when the second internal electrode layer 22-(n-1) is closest to the upper surface 10a of the main body 10). The second internal electrode layer 22-m faces the first internal electrode layer 21-m via the dielectric layer 11.

[0038] 2 and 3, for the sake of simplicity, five first internal electrode layers 21 and five second internal electrode layers 22 are shown, but the multilayer ceramic capacitor 1 may have more than five first internal electrode layers 21 and second internal electrode layers 22, and may have, for example, 300 to 1000 first internal electrode layers 21 and second internal electrode layers 22. In other words, the number of stacked layers in the multilayer ceramic capacitor 1 may be 300 to 1000.

[0039] In one aspect of the present invention, each internal electrode layer constituting the capacitance generating region Ra is configured to have an area that decreases from the upper end to the lower end of the capacitance generating region Ra in the stacking direction (T-axis direction) (in other words, from the upper end to the lower end of the central portion R1 in the T-axis direction), the closer it is to the lower surface 10b of the main body 10. For example, when comparing the first internal electrode layers 21, the m-th first internal electrode layer 21-m is compared with the (m+1)-th first internal electrode layer 21-(m+1), so assuming m<n, the area of ​​the m-th first internal electrode layer 21-m is smaller than the area of ​​the (m+1)-th first internal electrode layer 21-(m+1). Also, assuming m<n-1, the area of ​​the m-th first internal electrode layer 21-m is smaller than the areas of the (m+2)-th first internal electrode layer 21-(m+2) to the n-th first internal electrode layer 21-n. This relationship in size of areas holds for any m that satisfies m<n-1. Therefore, of the n first internal electrode layers 21 included in the capacitance generating region Ra, the first first internal electrode layer 21-1 has the smallest area, and the nth first internal electrode layer 21-n has the largest area.

[0040] When comparing the areas of the second internal electrode layers 22, assuming m<n-1 to clarify the comparison, the area of ​​the m-th second internal electrode layer 22-m is smaller than the area of ​​the (m+1)-th second internal electrode layer 22-(m+1). The area of ​​the m-th second internal electrode layer 22-m is also smaller than the areas of the (m+2)-th second internal electrode layer 22-(m+2) to the n-th second internal electrode layer 22-n. This area relationship holds for any m, m<n-1. Therefore, of the second internal electrode layers 22 in the capacitance generating region Ra, the area of ​​the first-layer second internal electrode layer 22-1 is the smallest. When n second internal electrode layers 22 are included in the capacitance generating region Ra, the area of ​​the n-th second internal electrode layer 22-n is the largest. When the capacitance generating region Ra includes the (n-1)th second internal electrode layer 22, the (n-1)th second internal electrode layer 22-(n-1) has the largest area.

[0041] When comparing the areas of the internal electrode layers between the first internal electrode layer 21 and the second internal electrode layer 22, in the illustrated embodiment, the first internal electrode layer 21 is positioned closer to the lower surface 10b than the second internal electrode layer 22 at the same layer within the capacitance generating region Ra (i.e., the first internal electrode layer 21 in the mth layer is positioned closer to the lower surface 10b than the second internal electrode layer 22 in the mth layer), so the area of ​​the first internal electrode layer 21-m in the mth layer is smaller than the area of ​​the second internal electrode layer 22-m in the mth layer.

[0042] In this specification, the area of ​​the internal electrode layer means the area when viewed from the stacking direction (T-axis direction in the illustrated example). In other words, the area of ​​the internal electrode layer in this specification means the area of ​​the internal electrode layer projected onto a plane perpendicular to the stacking direction (LW plane in the illustrated example).

[0043] The first internal electrode layer 21 includes conductive electrode regions containing crystal grains of its main component metal and non-electrode regions located between the electrode regions. The non-electrode regions are regions with higher insulating properties than the electrode regions. The non-electrode regions are occupied by, for example, oxides of elements contained in the first internal electrode layer 21, parts of the dielectric layer 11, and / or voids. The non-electrode regions may be formed by evaporation of the binder resin contained in the precursor of the first internal electrode layer 21 during degreasing of the precursor of the first internal electrode layer 21, or oxidation of elements contained in the precursor of the first internal electrode layer 21 during firing. The area of ​​the first internal electrode layer 21 refers to the sum of the area of ​​the electrode regions and the area of ​​the non-electrode regions. Similar to the first internal electrode layer 21, the second internal electrode layer 22 also includes conductive electrode regions containing crystal grains of its main component metal and non-electrode regions located between the electrode regions. The area of ​​the second internal electrode layer 22 refers to the sum of the area of ​​the electrode regions and the area of ​​the non-electrode regions.

[0044] As described above, in the multilayer ceramic capacitor 1, the internal electrode layers constituting the capacitance generating region Ra have an area that decreases from the upper end to the lower end of the capacitance generating region Ra in the stacking direction (T-axis direction) toward the lower surface 10b of the body 10. Therefore, in a cross section cut along the first side surface 10e or the second side surface 10f, the outer edge of the capacitance generating region Ra has a trapezoidal shape as shown in FIG. In other words, in a cross section of the multilayer ceramic capacitor 1 cut along the first side surface 10e or the second side surface 10f, the outer edge of the capacitance generating region Ra is defined by a trapezoid having the first internal electrode layer 21-1 as a lower base, the second internal electrode layer 22-n (the first internal electrode layer 21n when the number of stacked second internal electrode layers 22 is n-1) as an upper base, one leg being an imaginary line segment connecting the ends of each first internal electrode layer 21 in the L1 direction from the negative side to the positive side of the L axis, and the other leg being an imaginary line segment connecting the ends of each second internal electrode layer 22 in the L2 direction from the positive side to the negative side of the L axis.

[0045] If the difference in area between adjacent internal electrode layers is large, stress is likely to concentrate in the region between the adjacent internal electrode layers during thermal contraction. Therefore, to prevent excessive stress concentration between adjacent internal electrode layers, it is desirable that the difference in area between adjacent internal electrode layers be small. Specifically, it is desirable that the difference in area between the upper internal electrode layer and the lower internal electrode layer among adjacent internal electrode layers be in the range of 0.001 to 1% of the area of ​​the upper internal electrode layer. For example, it is desirable that the difference in area between the m-th second internal electrode layer 22-m and the m-th first internal electrode layer 21-m be in the range of 0.001 to 1% of the area of ​​the m-th second internal electrode layer 22-m. In one aspect, the lower limit of the difference in area between the upper internal electrode layer and the lower internal electrode layer among adjacent internal electrode layers may be 0.01% of the area of ​​the upper internal electrode layer. In one aspect, the lower limit of the difference between the area of ​​an upper internal electrode layer and the area of ​​a lower internal electrode layer among adjacent internal electrode layers may be 0.1% of the area of ​​the upper internal electrode layer. It is desirable that the difference between the area of ​​the uppermost internal electrode layer (the second internal electrode layer 22-n in the example shown in FIG. 2) arranged at the uppermost side of the capacitance generating region Ra and the area of ​​the lowermost internal electrode layer (the first internal electrode layer 21-1 in the example shown in FIG. 2) be 5 to 25% of the area of ​​the uppermost internal electrode layer.

[0046] As shown in FIG. 2 , the length dimension (dimension along the L axis) of each internal electrode layer constituting the capacitance generating region Ra decreases from the upper end to the lower end of the capacitance generating region Ra in the T axis direction toward the lower surface 10b of the main body 10, and as shown in FIG. 3 , the width dimension (dimension along the W axis) of each internal electrode layer is constant. As a result, the length dimension of each internal electrode layer decreases toward the lower surface 10b of the main body 10. The difference between the length dimension of the upper internal electrode layer and the length dimension of the lower internal electrode layer among adjacent internal electrode layers is preferably within a range of 0.01 to 1% of the length dimension of the upper internal electrode layer. For example, the difference between the length dimension of the mth second internal electrode layer 22-m and the length dimension of the mth first internal electrode layer 21-m is preferably within a range of 0.01 to 1% of the length dimension of the mth second internal electrode layer 22-m. In one aspect, the lower limit of the difference between the length dimension of an upper internal electrode layer and the length dimension of a lower internal electrode layer among adjacent internal electrode layers may be 0.1% of the length dimension of the upper internal electrode layer. In one aspect, the lower limit of the difference between the length dimension of an upper internal electrode layer and the length dimension of a lower internal electrode layer among adjacent internal electrode layers may be 0.5% of the length dimension of the upper internal electrode layer. The difference between the length dimension of the uppermost internal electrode layer (in the example shown in FIG. 2, the second internal electrode layer 22-n) arranged at the uppermost side of the capacitance generating region Ra and the length dimension of the lowermost internal electrode layer (in the example shown in FIG. 2, the first internal electrode layer 21-1) arranged at the lowermost side of the capacitance generating region Ra is preferably 1 to 5% of the length dimension of the uppermost internal electrode layer. Please note that the length dimensions of the internal electrode layers shown in FIG. 2 may not be accurately represented in order to clearly illustrate the dimensional difference.

[0047] 2, the distance in the L-axis direction between the end of the first internal electrode layer 21 in the L1 direction and the second end face 10d of the main body 10 increases from the upper end to the lower end of the capacitance generating region Ra in the T-axis direction, the closer to the lower surface 10b of the main body 10. For example, the distance L1-1 between the end of the first internal electrode layer 21-1 in the L1 direction and the second end face 10d is larger than the distance between the end of each of the first internal electrode layers 21-2 to 21-n in the L1 direction and the second end face 10d of the second and subsequent layers. Thus, the distance in the L-axis direction between the end of the first internal electrode layer 21 in the L1 direction and the second end face 10d of the main body 10 increases the closer to the lower surface 10b of the main body 10, so the ends of each first internal electrode layer 21 in the L1 direction are located at different positions on the L-axis. For example, the end portion in the L1 direction of the first internal electrode layer 21-1 of the first layer is located at a position displaced in the L1 direction from the end portions in the L1 direction of each of the first internal electrode layers 21-2 to 21-n of the second and subsequent layers. More generally, the end portion in the L1 direction of the first internal electrode layer 21-m of the mth layer is located at a different position on the L axis from the end portions in the L1 direction of the first internal electrode layers of the other layers (the first layer to the (m-1)th layer and the (m+1)th layer to the nth layer).

[0048] The relationship between the end of the first internal electrode layer 21 in the L-axis direction and the second end face 10d also applies to the relationship between the end of the second internal electrode layer 22 in the L-axis direction and the first end face 10c. That is, the distance in the L-axis direction between the end of the second internal electrode layer 22 in the L2 direction and the first end face 10c of the main body 10 increases from the upper end to the lower end of the capacitance generating region Ra in the T-axis direction, the closer to the lower surface 10b of the main body 10. As such, since the distance between the end of the second internal electrode layer 22 in the L2 direction and the second end face 10d of the main body 10 increases the closer to the lower surface 10b of the main body 10, the ends of each second internal electrode layer 22 in the L2 direction are located at different positions on the L-axis. For example, the end of the first second internal electrode layer 22-1 in the L2 direction is displaced in the L1 direction from the end of each of the second internal electrode layers 22-2 to 22-n in the L2 direction. More generally, the end portion in the L2 direction of the second internal electrode layer 22-m of the mth layer is located at a different position on the L axis from the end portions in the L2 direction of the second internal electrode layers of the other layers (the 1st layer to the (m-1)th layer and the (m+1)th layer to the nth layer).

[0049] In one embodiment, the film thickness (dimension in the T-axis direction) of the first internal electrode layer 21 and the film thickness (dimension in the T-axis direction) of the second internal electrode layer 22 are both 0.1 μm or more and 2 μm or less.

[0050] In one embodiment, the first internal electrode layers 21 contain a base metal such as Ni (nickel) or Sn (tin) as a main component. Based on the total mass of the first internal electrode layers 21, a component contained in the first internal electrode layers 21 at 50 wt % or more can be the main component of the first internal electrode layers 21.

[0051] The compositions of the internal electrode layers may be the same or different. The Young's modulus of barium titanate is approximately 100 GPa, while the Young's modulus of Ni is approximately 200 GPa. Therefore, when the dielectric layer 11 contains barium titanate as a main component and each internal electrode layer contains Ni as a main component, the difference in Young's modulus between the dielectric layer 11 and the internal electrode layer becomes large. This difference in Young's modulus between the dielectric layer 11 and the internal electrode layer tends to cause large residual stress between the dielectric layer 11 and the internal electrode layer. Therefore, in one aspect of the present invention, an internal electrode layer primarily composed of Ni contains, in addition to Ni, an additive metal element having a Young's modulus smaller than that of Ni. The additive metal element is, for example, at least one of Cu (copper), Al (aluminum), and Au (gold). The Young's moduli of Cu, Al, and Au are approximately 130 GPa, 70 GPa, and 78 GPa, respectively, which are all smaller than the Young's modulus of Ni. In the internal electrode layers containing Ni and the additive metal element, the smaller the concentration of Ni, the closer the Young's modulus of the internal electrode layers can be to the Young's modulus of the dielectric layer 11 containing barium titanate as a main component.

[0052] In one aspect of the present invention, the components of the internal electrode layers are adjusted so that, from the upper end to the lower end of the capacitance generating region Ra in the stacking direction, the concentration of Ni contained in the internal electrode layers decreases toward the lower surface 10b of the main body 10, and the concentration of the additive metal element increases toward the lower surface 10b of the main body 10. As a result, by increasing the concentration of the additive metal element in the first internal electrode layer 21-1 arranged at the lower end of the capacitance generating region Ra, the Young's modulus of the first internal electrode layer 21-1 can be made closer to the Young's modulus of the dielectric layer 11, which is mainly composed of barium titanate. Therefore, by reducing the residual stress caused by the difference between the Young's modulus of the first internal electrode layer 21-1 and the Young's modulus of the dielectric layer 11 near the boundary between the lower end of the center portion R1 and the upper end of the lower cover portion R3, it is possible to suppress the occurrence of cracks due to thermal contraction.

[0053] In one embodiment, Cu is used as the added metal element, and the concentrations of Ni and the added metal element in each internal electrode layer are adjusted so that the concentration ratio of Ni to Cu contained in the internal electrode layer (internal electrode layer 21-1) located at the lower end of the capacitance generating region Ra is 1:1, and the concentration of Cu contained in the internal electrode layer (internal electrode layer 22-n) located at the upper end of the capacitance generating region Ra is substantially 0.

[0054] As the difference in Ni concentration between adjacent internal electrode layers increases, the difference in Young's modulus between the adjacent internal electrode layers also increases. If the difference in Young's modulus between adjacent internal electrode layers is large, excessive stress concentration (to the extent that it may cause cracks) may occur in the region between the internal electrode layers. In one aspect of the present invention, the difference in Ni concentration between adjacent internal electrode layers may be in the range of 0.05 to 0.1%. By making the difference in Ni concentration between adjacent internal electrode layers a very small difference of about 0.05 to 0.1%, the change in Young's modulus between adjacent internal electrode layers in the stacking direction can be made gentle, thereby preventing stress concentration due to a sudden change in Young's modulus.

[0055] 1-5 First External Electrode 31 and Second External Electrode 32 In one aspect, the first external electrode 31 and the second external electrode 32 are formed by applying a conductive paste to the main body 10 and heating the conductive paste. The conductive paste may include at least one material selected from the group consisting of Ag (silver), Pd (palladium), Au (gold), Pt (platinum), Ni (nickel), Sn (tin), Cu (copper), W (tungsten), Ti (titanium), and alloys thereof.

[0056] 1-6 Summary As described above, the main body 10 of the multilayer ceramic capacitor 1 according to one aspect of the present invention is configured such that, from the upper end to the lower end of the capacitance generating region Ra in the stacking direction, the areas of the multiple internal electrode layers decrease toward the lower surface 10b of the main body 10. Therefore, near the boundary between the lower end of the capacitance generating region Ra (i.e., the lower end of the central portion R1) and the upper end of the lower cover portion R3, the contact area between the internal electrode layer (internal electrode layer 21-1) located at the lower end of the capacitance generating region Ra and the dielectric layer 11 is small, thereby reducing residual stress generated near this boundary due to the difference in thermal contraction rate between the internal electrode layer and the dielectric layer 11. When the multilayer ceramic capacitor 1 is mounted on the electronic circuit board 2, heat from the solder is easily conducted to the region near the lower surface 10b of the main body 10, so the region of the main body 10 near the lower surface 10b is likely to become hot. As a result, significant thermal contraction is likely to occur near the boundary between the lower end of the capacitance generating region Ra and the upper end of the lower cover portion R3. By reducing the contact area between the internal electrode layer 21-1 and the dielectric layer 11 near the boundary between the lower end of the capacitance generating region Ra where large thermal contraction occurs and the upper end of the lower cover portion R3, it is possible to reduce residual stress that occurs near the boundary between the lower end of the capacitance generating region Ra where large thermal contraction occurs and the upper end of the lower cover portion R3 due to the difference in thermal contraction rate between the internal electrode layer 21-1 and the dielectric layer 11. This makes it possible to suppress the occurrence of cracks in the main body 10 near the boundary between the lower end of the capacitance generating region Ra and the upper end of the lower cover portion R3.

[0057] Near the boundary between the upper end of the capacitance generating region Ra and the upper cover portion R2, the contact area between the internal electrode layer (internal electrode layer 22-n) arranged at the upper end of the capacitance generating region Ra and the dielectric layer 11 is large, but heat from the solder is not easily conducted to the region near the upper surface 10a of the main body 10, and heat is dissipated from the upper surface 10a of the main body 10, so cracks due to thermal contraction are unlikely to occur near the boundary between the upper end of the capacitance generating region Ra and the upper cover portion R2. Therefore, by making the area of ​​the internal electrode layer arranged at the upper end of the capacitance generating region Ra larger than the areas of the other internal electrode layers, heat dissipation can be promoted without generating large residual stress.

[0058] If the capacitance generating region includes a corner, stress tends to concentrate around the corner during thermal contraction. According to one aspect of the present invention, the area of ​​the internal electrode layer is gradually changed from the upper end to the lower end of the capacitance generating region Ra in the layer direction, so that the capacitance generating region Ra has a trapezoidal shape with no corners between its upper and lower ends. Therefore, the capacitance generating region Ra of the multilayer ceramic capacitor 1 does not have any corners where residual stress can concentrate, and therefore the occurrence of cracks due to residual stress concentration can be suppressed.

[0059] According to one aspect of the present invention, the difference in area between the upper internal electrode layer and the lower internal electrode layer among adjacent internal electrode layers is in the range of 0.001 to 1% of the area of ​​the upper internal electrode layer. In this case, since the difference in area between the adjacent internal electrode layers in the stacking direction is small, it is possible to suppress the concentration of residual stress in the region between the adjacent internal electrode layers.

[0060] When the multilayer ceramic capacitor 1 is in use, the internal electrode layers generate the strongest electric field in regions near their ends in the length direction. According to one aspect of the present invention, the ends of each first internal electrode layer 21 in the L1 direction are located at different positions on the L axis, so that the electric field generated from each first internal electrode layer 21 can be prevented from being strengthened at a specific position on the L axis. This makes it possible to suppress the occurrence of dielectric breakdown in the body 10.

[0061] 2. Multilayer Ceramic Capacitor 51 (Second Embodiment) Next, a multilayer ceramic capacitor 51 according to another embodiment of the present invention will be described with reference to FIG. 4. FIG. 4 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 51 taken along a plane parallel to the WT plane (i.e., a plane parallel to the first end face 10c or the second end face 10d). The multilayer ceramic capacitor 51 differs from the multilayer ceramic capacitor 1, which has internal electrode layers whose widths (dimensions in the W-axis direction) vary depending on the position in the stacking direction. Detailed description of components of the multilayer ceramic capacitor 51 that are the same as or similar to the components of the multilayer ceramic capacitor 1 will be omitted.

[0062] As shown in FIG. 4 , the body 10 of the multilayer ceramic capacitor 51 is configured such that, from the upper end to the lower end of the central portion R1 in the lamination direction, the dimension in the width direction of each internal electrode layer decreases toward the lower surface 10b of the body 10. In the multilayer ceramic capacitor 51, the dimension in the length direction of each internal electrode layer decreases toward the lower surface 10b of the body 10, similar to the multilayer ceramic capacitor 1. The difference between the width dimension of the upper internal electrode layer and the width dimension of the lower internal electrode layer among adjacent internal electrode layers is preferably within a range of 0.01 to 1% of the width dimension of the upper internal electrode layer. For example, the difference between the width dimension of the second internal electrode layer 22-m of the mth layer and the width dimension of the first internal electrode layer 21-m of the mth layer is preferably within a range of 0.01 to 1% of the width dimension of the second internal electrode layer 22-m of the mth layer. In one aspect, the lower limit of the difference between the width dimension of an upper internal electrode layer and the width dimension of a lower internal electrode layer among adjacent internal electrode layers may be 0.1% of the width dimension of the upper internal electrode layer. In one aspect, the lower limit of the difference between the width dimension of an upper internal electrode layer and the width dimension of a lower internal electrode layer among adjacent internal electrode layers may be 0.5% of the width dimension of the upper internal electrode layer. The difference between the width dimension of the uppermost internal electrode layer (in the example shown in FIG. 2, the second internal electrode layer 22-n) arranged at the uppermost side of the capacitance generating region Ra and the width dimension of the lowermost internal electrode layer (in the example shown in FIG. 2, the first internal electrode layer 21-1) arranged at the lowermost side of the capacitance generating region Ra is preferably 1 to 5% of the width dimension of the uppermost internal electrode layer. Please note that the width dimensions of the internal electrode layers shown in FIG. 2 may not be accurately represented in order to clearly illustrate the dimensional difference.

[0063] According to the multilayer ceramic capacitor 51, the contact area between the dielectric layer 11 and the internal electrode layer (internal electrode layer 21-1) arranged at the lower end of the capacitance generating region Ra can be further reduced near the boundary between the lower end of the central portion R1 and the upper end of the lower cover portion R3. This further reduces the residual stress generated near the boundary between the lower end of the central portion R1 and the upper end of the lower cover portion R3. Also in the multilayer ceramic capacitor 51, the width direction dimension of the internal electrode layers is changed in a stepwise manner from the upper end to the lower end of the capacitance generating region Ra in the stacking direction so that there is no large change in area between adjacent internal electrode layers, thereby suppressing the concentration of residual stress in the capacitance generating region Ra.

[0064] 3 Multilayer Ceramic Capacitor 61 (Third Embodiment) Next, a multilayer ceramic capacitor 61 according to another embodiment of the present invention will be described with reference to Fig. 5 and Fig. 6. Fig. 5 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 61 cut along a plane parallel to the LT plane (i.e., a plane parallel to the first side surface 10e or the second side surface 10f), and Fig. 6 is a schematic view showing an enlarged view of a portion of the internal electrode layer included in the cross section shown in Fig. 5. Detailed description of components of the multilayer ceramic capacitor 61 that are the same as or similar to the components of the multilayer ceramic capacitor 1 will be omitted.

[0065] The multilayer ceramic capacitor 61 includes internal electrode layers whose thickness (dimension in the T-axis direction) varies depending on the position in the stacking direction. The body 10 of the multilayer ceramic capacitor 61 is configured such that, from the upper end to the lower end of the central portion R1 in the stacking direction, the thickness of each internal electrode layer decreases toward the lower surface 10b of the body 10.

[0066] The thickness dimension of each internal electrode layer will be further explained with reference to FIG. 6. As shown in FIG. 6, when comparing the first internal electrode layers 21, the mth first internal electrode layer 21-m is compared with the (m+1)th first internal electrode layer 21-(m+1), so assuming m<n, the thickness dimension T1(m) of the mth first internal electrode layer 21-m is smaller than the thickness dimension T1(m+1) of the (m+1)th first internal electrode layer 21-(m+1). This thickness dimension relationship holds for any m that satisfies m<n. Therefore, of the n first internal electrode layers 21 included in the capacitance generating region Ra, the first internal electrode layer 21-1 of the first layer is the thinnest, and the nth first internal electrode layer 21-n is the thickest.

[0067] When comparing the thicknesses of the second internal electrode layers 22 with each other, assuming that m<n, the thickness of the mth second internal electrode layer 22-m is thinner than the thickness of the (m+1)th second internal electrode layer 22-(m+1). This thickness relationship holds for any m that satisfies m<n. Therefore, of the n second internal electrode layers 22 included in the capacitance generating region Ra, the thickness of the first second internal electrode layer 22-1 is the thinnest, and the thickness of the nth second internal electrode layer 22-n is the thickest.

[0068] When comparing the thickness dimensions of the internal electrode layers between the first internal electrode layer 21 and the second internal electrode layer 22, in the illustrated embodiment, the first internal electrode layer 21 is disposed closer to the lower surface 10b than the second internal electrode layer 22 in the same layer within the capacitance generating region Ra, and therefore the thickness dimension of the first internal electrode layer 21-m in the m-th layer is smaller than the thickness dimension of the second internal electrode layer 22-m in the m-th layer. In the same layer within the capacitance generating region Ra, the second internal electrode layer 22 may be disposed closer to the lower surface 10b than the first internal electrode layer 21. In this case, the thickness dimension of the second internal electrode layer 22-m in the m-th layer is smaller than the thickness dimension of the first internal electrode layer 21-m in the m-th layer.

[0069] If the difference in thickness between adjacent internal electrode layers is large, stress is likely to concentrate in the region between the adjacent internal electrode layers during thermal contraction. Therefore, it is desirable that the difference in thickness between adjacent internal electrode layers be such that excessive stress concentration sufficient to cause cracks in the main body 10 does not occur. Specifically, it is desirable that the difference in thickness between the upper internal electrode layer and the lower internal electrode layer among adjacent internal electrode layers be in the range of 0.01 to 0.1% of the thickness of the upper internal electrode layer. For example, it is desirable that the difference in thickness between the m-th second internal electrode layer 22-m and the m-th first internal electrode layer 21-m be in the range of 0.01 to 0.1% of the thickness of the m-th second internal electrode layer 22-m. It is desirable that the difference between the thickness dimension of the uppermost internal electrode layer (in the example shown in FIG. 2, the second internal electrode layer 22-n) located at the uppermost side of the capacitance generating region Ra and the thickness dimension of the lowermost internal electrode layer (in the example shown in FIG. 2, the first internal electrode layer 21-1) located at the lowermost side of the capacitance generating region Ra is 5 to 10% of the thickness dimension of the uppermost internal electrode layer.

[0070] As described above, in the multilayer ceramic capacitor 61, from the top to the bottom in the stacking direction of the capacitance generating region Ra, the thickness of each internal electrode layer becomes thinner the closer it is to the underside 10a of the main body 10. Therefore, of the multiple internal electrode layers arranged in the capacitance generating region Ra, the internal electrode layer arranged at the bottom (internal electrode layer 21-1) has the smallest thickness, which reduces residual stress generated in the internal electrode layer 21-1 arranged near the boundary between the capacitance generating region Ra and the top end of the lower cover portion R3. This further suppresses the occurrence of cracks in the main body 10 due to thermal contraction.

[0071] In the multilayer ceramic capacitor 61, the thickness of the internal electrode layers disposed near the lower surface 10b of the body 10 is thinner than the thickness of the internal electrode layers disposed near the upper surface of the body 10, so the total thickness of the internal electrode layers can be made smaller than in an embodiment in which the internal electrode layers have a uniform thickness. For example, if the thickness of the internal electrode layers of the multilayer ceramic capacitor 1 is constant regardless of the position in the stacking direction, the thickness of the internal electrode layers disposed at the upper end of the capacitance generating region Ra in the multilayer ceramic capacitor 61 can be made equal to the thickness of the internal electrode layers of the multilayer ceramic capacitor 1, so that the total thickness of the internal electrode layers of the multilayer ceramic capacitor 61 can be made smaller than the total thickness of the internal electrode layers of the multilayer ceramic capacitor 1. In this way, the multilayer ceramic capacitor 61 can be made thinner than a multilayer ceramic capacitor having internal electrode layers with a constant thickness regardless of the position in the stacking direction.

[0072] In the multilayer ceramic capacitor 61, the internal electrode layer (in the illustrated embodiment, the second internal electrode layer 22-n) located at the upper end in the stacking direction among the multiple internal electrode layers is configured to be the thickest. This can further promote heat dissipation from the internal electrode layer located at the upper end in the stacking direction, and can prevent the multilayer ceramic capacitor 61 from becoming too hot during use.

[0073] 4. Multilayer ceramic capacitor 71 (fourth embodiment) Next, a multilayer ceramic capacitor 71 according to another embodiment of the present invention will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 71 cut along a plane parallel to the LT plane. Detailed description of components of the multilayer ceramic capacitor 71 that are the same as or similar to the components of the multilayer ceramic capacitor 1 will be omitted.

[0074] In the multilayer ceramic capacitor 71, the body 10 is configured so that the distance between the end of the first internal electrode layer 21 in the L1 direction and the second end face 10d of the body 10 is constant regardless of the position in the stacking direction, and the distance between the end of the second internal electrode layer 22 in the L2 direction and the first end face 10c of the body 10 is constant regardless of the position in the stacking direction. In other words, the body 10 of the multilayer ceramic capacitor 71 is configured so that, in a cross section cut along a plane parallel to the LT plane, the first end face 10c is parallel to one leg of a trapezoid that defines the outer edge of the capacitance generating region Ra, and the second end face 10d is parallel to one leg of the trapezoid that defines the outer edge of the capacitance generating region Ra. Therefore, the body 10 of the multilayer ceramic capacitor 71 becomes narrower in the longitudinal direction as it approaches the bottom face 10b. Therefore, the area of ​​the bottom face 10b of the body 10 of the multilayer ceramic capacitor 71 is smaller than the area of ​​the top face 10a.

[0075] FIG. 8 shows a multilayer ceramic capacitor 71 mounted on the surface of an electronic circuit board 2. The body 10 of the multilayer ceramic capacitor 71 is configured to narrow in the longitudinal direction as it approaches the lower surface 10b. Therefore, the multilayer ceramic capacitor 71 can be mounted in a smaller area on the surface of the electronic circuit board 2 than a multilayer ceramic capacitor with a rectangular parallelepiped body (e.g., the multilayer ceramic capacitor 1). In other words, the multilayer ceramic capacitor 71 can reduce the mounting area compared to a multilayer ceramic capacitor with a rectangular parallelepiped body. Furthermore, a portion of the solder 41 can be accommodated in the space defined between the first end face 10c of the body 10 and the surface of the electronic circuit board 2, and a portion of the solder 42 can be accommodated in the space defined between the second end face 10d of the body 10 and the surface of the electronic circuit board 2. This reduces the area over which the solder spreads on the surface of the electronic circuit board 2 when the multilayer ceramic capacitor 71 is mounted.

[0076] 5. Multilayer ceramic capacitor 81 (Fifth embodiment) Next, a multilayer ceramic capacitor 81 according to another embodiment of the present invention will be described with reference to Fig. 9. Fig. 9 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 91 cut along a plane parallel to the WT plane. Detailed description of components of the multilayer ceramic capacitor 81 that are the same as or similar to the components of the multilayer ceramic capacitor 1 will be omitted.

[0077] In the multilayer ceramic capacitor 81, the distance between the end of the internal electrode layer and the second side surface 10f of the body 10 in the W1 direction (from the negative side to the positive side of the W axis) is constant regardless of the position in the stacking direction. Furthermore, the distance between the end of the internal electrode layer and the first side surface 10e of the body 10 in the W2 direction (from the positive side to the negative side of the W axis) is constant regardless of the position in the stacking direction. Therefore, in a cross section cut along a plane parallel to the WT plane, the body 10 of the multilayer ceramic capacitor 81 is configured such that the first side surface 10e is parallel to one leg of a trapezoid that defines the outer edge of the capacitance generating region Ra, and the second side surface 10f is parallel to the other leg of the trapezoid that defines the outer edge of the capacitance generating region Ra. Therefore, the body 10 of the multilayer ceramic capacitor 81 becomes narrower in the width direction as it approaches the lower surface 10b. Therefore, the area of ​​the lower surface 10b of the body 10 of the multilayer ceramic capacitor 81 is smaller than the area of ​​the upper surface 10a.

[0078] Compared to a multilayer ceramic capacitor whose main body is formed in a rectangular parallelepiped shape (e.g., multilayer ceramic capacitor 1), multilayer ceramic capacitor 81 can be mounted in a smaller area on the surface of electronic circuit board 2. That is, multilayer ceramic capacitor 81 can reduce the mounting area compared to a multilayer ceramic capacitor whose main body is formed in a rectangular parallelepiped shape. Furthermore, since a portion of the solder (not shown) can be accommodated in the space defined between first side surface 10e and second side surface 10f of main body 10 and the surface of electronic circuit board 2, the area over which solder wets and spreads on the surface of electronic circuit board 2 when multilayer ceramic capacitor 81 is mounted can be reduced.

[0079] 6. Method for Manufacturing Multilayer Ceramic Capacitor Next, an overview of a method for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention will be described with reference to Fig. 10 to Fig. 14. Fig. 10 is a flow diagram showing the flow of a method for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention, and Figs. 11 to 14 are schematic diagrams showing the manufacturing process of a multilayer ceramic capacitor.

[0080] (Step S01: Preparation of Ceramic Sheets) In step S01, multiple ceramic sheets S are prepared. The ceramic sheets S are unsintered dielectric green sheets primarily composed of dielectric ceramics and serve as precursors for the dielectric layers 11. The ceramic sheets S are obtained, for example, as follows. First, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are wet-mixed with a dielectric powder to obtain a slurry. Next, this slurry is applied to a substrate film by, for example, a die coater method or a doctor blade method. The applied slurry on the substrate film is then dried to obtain a dielectric green sheet. The dielectric powder, which is the raw material powder for the dielectric green sheet, is, for example, barium titanate (BaTiO) powder. Barium titanate powder is synthesized by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate using a known method such as a solid-phase method, a sol-gel method, or a hydrothermal method. The thickness of the ceramic sheets S can be adjusted as needed.

[0081] (Step S02: Formation of Internal Electrodes) Next, in step S02, internal electrode patterns 112 are formed on the ceramic sheets S prepared in step S01 to obtain the first unit sheets 101 shown in Fig. 11. The internal electrode patterns 112 are precursors of the first internal electrode layers 21. Since the multilayer ceramic capacitor 1, which is a finished product, includes the first internal electrode layers 21-1 to 21-n, a plurality of ceramic sheets S on which internal electrode patterns 112 corresponding to the first internal electrode layers 21-1 to 21-n are formed are prepared as the first unit sheets 101.

[0082] In step S02, internal electrode patterns 113 are formed on a plurality of ceramic sheets S other than the ceramic sheet S on which the internal electrode patterns 112 are formed, to obtain the second unit sheet 102 shown in Fig. 11. The internal electrode patterns 113 are precursors of the second internal electrode layers 22. Since the multilayer ceramic capacitor 1, which is a finished product, includes the second internal electrode layers 22-1 to 22-n, a plurality of ceramic sheets S on which the internal electrode patterns 113 corresponding to the internal electrode layers 22-1 to 22-n are formed are prepared as the second unit sheet 102.

[0083] As described above, in the multilayer ceramic capacitor 1, the area of ​​the internal electrode layer decreases as it approaches the lower surface 10b of the main body 10, and therefore the internal electrode patterns 112 formed on each of the first single sheets 101 and the internal electrode patterns 113 formed on each of the second single sheets 101 also have different areas corresponding to the difference in the areas of the internal electrode layers in the finished multilayer ceramic capacitor 1.

[0084] No internal electrode pattern is formed on some of the ceramic sheets S. The ceramic sheets S on which no internal electrode pattern is formed are referred to as third unit sheets 103. In Fig. 11, the first unit sheet 101, the second unit sheet 102, and the third unit sheet 103 are each shown with cutting lines Lx and Ly indicating the cutting positions when singulating.

[0085] In step S02, the internal electrode patterns 112, 113 are formed by a vacuum film formation method such as sputtering. In the following description, it is assumed that the internal electrode patterns 112, 113 are formed by sputtering. To form the internal electrode patterns 112, 113 on the ceramic sheet S, a mask having openings corresponding to the internal electrode patterns 112, 113 is used. This mask may be formed, for example, using photoresist on the upper surface of the ceramic sheet S. A metal mask may also be used as the mask for forming the internal electrode patterns 112, 113. Since the first internal electrode layers 21-1 to 21-n and the second internal electrode layers 22-1 to 22-n have different areas, multiple masks having openings corresponding to the shapes of the first internal electrode layers 21-1 to 21-n are prepared. Multiple metal masks having openings of different sizes may be placed in a vacuum chamber of a sputtering apparatus, and the metal masks may be replaced using an autochanger.

[0086] The formation of the internal electrode patterns 112, 113 corresponding to each of the first internal electrode layers 21-1 to 21-n and the second internal electrode layers 22-1 to 22-n on the ceramic sheet S may be performed using a single metal mask. By the method described below, the internal electrode patterns 112, 113 corresponding to each of the first internal electrode layers 21-1 to 21-n and the second internal electrode layers 22-1 to 22-n can be formed using a single metal mask. First, a mask having an opening shaped to correspond to the second internal electrode layer 22-n to be arranged on the uppermost layer is prepared, and this mask is placed on the ceramic sheet S and sputtering is performed to form the internal electrode pattern 113 serving as a precursor of the second internal electrode layer 22-n on the ceramic sheet S. During this sputtering, when the internal electrode pattern serving as a precursor of the second internal electrode layer 22-n is formed on the ceramic sheet S, sputtered particles adhere not only to the ceramic sheet S but also to the upper surface of the metal mask and the side walls defining the opening. After the internal electrode pattern serving as the precursor of the second internal electrode layer 22-n is formed, the sputtered particles deposited on the upper surface of the metal mask are washed. At this time, the sputtered particles adhering to the sidewalls defining the openings of the metal mask are not washed. Next, using the metal mask whose upper surface has only been cleaned, an internal electrode pattern 112 serving as the precursor of the first internal electrode layer 21-n, which is disposed one layer below the second internal electrode layer 22-n, is formed by sputtering on another ceramic sheet S. Since the sidewalls defining the openings of the metal mask are not cleaned after the internal electrode pattern 113 serving as the precursor of the second internal electrode layer 22-n is formed, when the internal electrode pattern 112 serving as the precursor of the first internal electrode layer 21-n is formed, the openings of the metal mask are partially blocked by the sputtered particles deposited on the sidewalls defining the openings. Therefore, the internal electrode pattern 112 serving as the precursor of the first internal electrode layer 21-n has a slightly smaller area than the internal electrode pattern 113 serving as the precursor of the second internal electrode layer 22-n.Similarly, after one internal electrode pattern is formed, the upper surface is cleaned without cleaning the openings of the metal mask, and the next internal electrode pattern is formed by sputtering using this cleaned mask, thereby gradually reducing the area of ​​the formed internal electrode pattern. In the above method, the internal electrode patterns 112, 113 corresponding to each of the first internal electrode layers 21-1 to 21-n and the second internal electrode layers 22-1 to 22-n can be formed using a single metal mask. The metal mask may be cleaned each time the formation of one internal electrode pattern is completed (i.e., after each sputtering cycle), but if the sputtered particles deposited on the upper surface do not adversely affect the next sputtering cycle, cleaning may be performed once every several cycles.

[0087] To form the internal electrode pattern 112, a known sputtering apparatus having a vacuum chamber equipped with a holder and a metal target disposed opposite the holder is prepared, and the ceramic sheet S is placed on the holder in the vacuum chamber. Next, oxygen is evacuated from the vacuum chamber to create a high vacuum inside the vacuum chamber. Next, a rare gas introduced into the vacuum chamber is ionized to clean the film-forming surface (top surface) of the ceramic sheet S by reverse sputtering, and then the metal target is sputtered. By sputtering the metal target, metal atoms recoil from the metal target and deposit on the surface of the ceramic sheet S, forming the internal electrode pattern 112 on the top surface of the ceramic sheet S. The internal electrode pattern 113 is also formed in the same manner as the internal electrode pattern 112. After sputtering is completed, the mask is removed from the ceramic sheet S. By performing this sputtering process multiple times, a plurality of first unit sheets 101 are obtained on which internal electrode patterns 112 corresponding to the first internal electrode layers 21-1 to 21-n are formed, and a plurality of second unit sheets 102 are obtained on which internal electrode patterns 112 corresponding to the second internal electrode layers 22-1 to 22-n are formed.

[0088] 12, in step S03, the first single sheet 101 and the second single sheet 102 obtained in step S02 are alternately laminated, and a plurality of third single sheets 103 are laminated on each of the upper and lower surfaces in the T-axis direction of the alternately laminated first single sheet 101 and second single sheet 102 to obtain a laminate. Then, by pressing this laminate in the T-axis direction, a laminated sheet 104 in which the first single sheet 101, the second single sheet 102, and the third single sheet 103 are laminated is obtained.

[0089] (Step S04: Cutting) In step S04, laminate sheet 104 obtained in step S03 is cut along cutting lines Lx and Ly shown in Fig. 13 to produce unsintered chip stacks 111 shown in Fig. 14. For example, a press cutter blade or a rotary blade can be used to cut laminate sheet 104.

[0090] (Step S05: Firing) In step S05, the chip stack 111 obtained in step S04 is fired to produce the main body 10 of the multilayer ceramic capacitor 1. That is, in step S05, the chip stack 111 is fired to form the main body 10. The firing temperature in step S05 can be determined based on the sintering temperature of the ceramic body 111. For example, when a barium titanate (BaTiO3)-based material is used, the firing temperature can be approximately 1000 to 1300°C. Furthermore, firing can be performed, for example, in a reducing atmosphere or a low-oxygen partial pressure atmosphere.

[0091] (Step S06: Forming External Electrodes) In step S06, a first external electrode 31 is formed at one end in the L-axis direction of the main body obtained in step S05, and a second external electrode 32 is formed at the other end. In this manner, the multilayer ceramic capacitor 1 is obtained.

[0092] The multilayer ceramic capacitors 51, 61, 71, and 81 can also be manufactured in the same manner as the multilayer ceramic capacitor 1. However, when manufacturing the multilayer ceramic capacitors 51, 61, 71, and 81, appropriate modifications are made to the manufacturing method of the multilayer ceramic capacitor 1. For example, when manufacturing the multilayer ceramic capacitor 51, the thicknesses of the internal electrode patterns 112 and 113 formed on the ceramic sheet S are adjusted so that the thickness dimension of each internal electrode layer becomes smaller as it approaches the lower surface 10b of the main body 10. The thickness of the internal electrode patterns 112 and 113 can be adjusted by adjusting the film formation time during sputtering. The thickness of the internal electrode patterns 112 and 113 can be increased by extending the film formation time. For example, to manufacture the multilayer ceramic capacitor 51, the film formation time for forming the internal electrode pattern 113, which serves as a precursor of the second internal electrode layer 22-n, is set longer than the film formation time for forming the internal electrode pattern 112, which serves as a precursor of the first internal electrode layer 21-1. The thickness of the internal electrode patterns 112 and 113 may be adjusted by the bias voltage applied to the ceramic sheet S.

[0093] When forming an internal electrode layer containing multiple metal elements (e.g., Ni and an added metal element), multiple targets corresponding to the multiple metal elements are placed, and the multiple targets are sputtered simultaneously, thereby forming internal electrode patterns 112, 113 containing the multiple metal elements on the ceramic sheet S.

[0094] When manufacturing the multilayer ceramic capacitors 71 and 81, a plurality of ceramic sheets S of different sizes may be prepared, and these ceramic sheets S of different sizes may be stacked to create a laminated sheet 104 that serves as a precursor to the main body 10 of the multilayer ceramic capacitors 71 and 81.

[0095] When manufacturing the multilayer ceramic capacitors 71 and 81, a rectangular parallelepiped-shaped laminated sheet 104 may be manufactured in the same manner as in the manufacturing process of the multilayer ceramic capacitor 1, and in the cutting process of step S04, the laminated sheet 104 may be cut using a tapered blade to produce a chip laminate 111 having a trapezoidal cross-sectional shape.

[0096] 7. Note The dimensions, materials, and arrangements of the components described in the various embodiments above are not limited to those explicitly described in each embodiment, and each component can be modified to have any dimensions, materials, and arrangements that fall within the scope of the present invention.

[0097] Components not explicitly described in this specification may be added to each of the above-described embodiments, and some of the components described in each embodiment may be omitted.

[0098] The terms "first," "second," "third," and the like used in this specification are used to identify components and do not necessarily limit the number, order, or content of the components. Furthermore, numbers used to identify components are used in different contexts, and a number used in one context does not necessarily indicate the same configuration in another context. Furthermore, this does not prevent a component identified by a certain number from also serving the function of a component identified by another number.

[0099] In this specification, when a certain component is referred to as "comprising" another component, it does not mean that other components are excluded, but that other components may be further included, unless it is inconsistent with the content of the present invention.

[0100] For example, the main body 10 may be configured such that the first end face 10c and the second end face 10d are parallel to two legs of a trapezoid that defines the outer edge of the capacitance generating region Ra in the LT plane, as shown in Fig. 8, and the first side face 10e and the second side face 10f are parallel to two legs of a trapezoid that defines the outer edge of the capacitance generating region Ra in the WT plane, as shown in Fig. 9.

[0101] 8. Supplementary Notes The embodiments disclosed in this specification also include the following.

[0102] [Supplementary Note 1] A main body (10) having a plurality of dielectric layers (11) and a plurality of internal electrode layers (21, 22) stacked in a stacking direction via at least one of the plurality of dielectric layers, the main body being partitioned into a central portion (R1) including a capacitance generating region (Ra) where a plurality of first internal electrode layers of the plurality of internal electrode layers and a plurality of second internal electrode layers of the plurality of internal electrode layers are alternately stacked in the stacking direction, a lower cover portion (R3) located below the central portion in the stacking direction, and an upper cover portion (R2) located above the central portion in the stacking direction; a first external electrode (31) electrically connected to each of the plurality of first internal electrode layers and provided on the main body; and a second external electrode (32) electrically connected to each of the plurality of second internal electrode layers and provided on the main body, The main body is configured such that, from the upper end to the lower end of the central portion in the stacking direction, the area of ​​each of the plurality of internal electrode layers decreases toward the lower surface of the main body.

[0103] [Supplementary Note 2] The multilayer ceramic capacitor according to [Supplementary Note 1], wherein the body has a first end face (10c) and a second end face (10d) that face each other in a length direction perpendicular to the stacking direction, and the body is configured such that, from the upper end to the lower end of the central portion in the stacking direction, the dimension in the length direction of each of the internal electrode layers that constitutes the plurality of internal electrode layers becomes smaller toward the lower surface of the body.

[0104] [Supplementary Note 3] The multilayer ceramic capacitor according to [Supplementary Note 1] or [Supplementary Note 2], wherein the body has a first end face and a second end face that face each other in a length direction perpendicular to the stacking direction, and ends of each of the first internal electrode layers constituting the plurality of first internal electrode layers are located at different positions from each other in the length direction.

[0105] [Supplementary Note 4] The multilayer ceramic capacitor according to [Supplementary Note 3], wherein end portions of the second internal electrode layers constituting the plurality of second internal electrode layers are located at different positions from each other in the length direction.

[0106] [Supplementary Note 5] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 4], wherein the main body has a first side surface and a second side surface that face each other in a width direction perpendicular to the stacking direction and the length direction, and the main body is configured such that, from the upper end to the lower end of the central portion in the stacking direction, the dimension in the width direction of each of the first internal electrode layers that constitutes the plurality of first internal electrode layers becomes smaller the closer to the lower surface of the main body.

[0107] [Appendix 6] A multilayer ceramic capacitor according to any one of [Appendix 1] to [Appendix 5], wherein a difference between a first area indicating an area of ​​an upper internal electrode layer of an adjacent set of internal electrode layers included in the plurality of internal electrode layers and a second area indicating an area of ​​a lower internal electrode layer of the set of internal electrode layers is 0.001 to 1% of the first area.

[0108] [Supplementary Note 7] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 6], wherein the difference between the first area and the second area is 0.001 to 0.1% of the first area.

[0109] [Appendix 8] A multilayer ceramic capacitor according to any one of [Appendix 1] to [Appendix 7], wherein a difference between a third area indicating an area of ​​a top-layer internal electrode layer arranged at the uppermost side among the plurality of internal electrode layers and a fourth area indicating an area of ​​a bottom-layer internal electrode layer arranged at the lowermost side is 5 to 25% of the third area.

[0110] [Appendix 9] A multilayer ceramic capacitor according to any one of [Appendix 1] to [Appendix 8], wherein a difference between a first length indicating a length in the length direction of a top-layer internal electrode layer arranged at the uppermost side among the plurality of internal electrode layers and a second length indicating a length in the length direction of a bottom-layer internal electrode layer arranged at the lowermost side is 1 to 5% of the first length.

[0111] [Supplementary Note 10] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 9], wherein the body is configured such that the thickness of each of the plurality of internal electrode layers becomes thinner from the upper end to the lower end of the central portion in the stacking direction toward the lower surface of the body.

[0112] [Appendix 11] A difference between a first thickness indicating a thickness of an upper internal electrode layer of a set of adjacent internal electrode layers among the plurality of internal electrode layers and a second thickness indicating an area of ​​a lower internal electrode layer of the set of internal electrode layers is 0.001 to 0.5% of the first thickness. The multilayer ceramic capacitor according to [Appendix 10].

[0113] [Appendix 12] A multilayer ceramic capacitor according to [Appendix 10] or [Appendix 11], wherein a difference between a third thickness indicating a thickness of a top-layer internal electrode layer arranged at the uppermost side among the plurality of internal electrode layers and a fourth thickness indicating a thickness of a bottom-layer internal electrode layer arranged at the lowermost side is 5 to 100% of the fourth thickness.

[0114] [Supplementary Note 13] The multilayer ceramic capacitor according to [Supplementary Note 2], wherein a distance between an end of each of the plurality of first internal electrode layers and the second end face is constant in the length direction, and a distance between an end of each of the plurality of second internal electrode layers and the first end face is constant in the length direction.

[0115] [Supplementary Note 14] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 13], wherein the body has the lower surface and an upper surface opposite to the lower surface, and a lower surface area indicating an area of ​​the lower surface is smaller than an upper surface area indicating an area of ​​the upper surface.

[0116] [Appendix 15] The multilayer ceramic capacitor according to any one of [Appendix 1] to [Appendix 14], wherein the plurality of dielectric layers contain crystal grains of barium titanate, the plurality of internal electrode layers all contain Ni and an additive metal element having a Young's modulus smaller than that of Ni, and the main body is configured such that, from the top end to the bottom end of the central portion in the stacking direction, the concentration of Ni contained in the plurality of internal electrode layers decreases toward the bottom surface of the main body, and the concentration of the additive metal element increases toward the bottom surface of the main body.

[0117] [Appendix 16] A circuit board comprising the multilayer ceramic capacitor according to any one of [Appendix 1] to [Appendix 15].

[0118] [Supplementary Note 17] A method for manufacturing a multilayer ceramic capacitor, comprising: a step of forming a laminate; a step of firing the laminate to form a main body; and a step of forming external electrodes on the main body, wherein the laminate is partitioned into a central portion formed by stacking a plurality of composite sheets in a stacking direction, a lower cover portion located below the central portion in the stacking direction, and an upper cover portion located above the central portion in the stacking direction, each of the plurality of composite sheets having a dielectric sheet and an internal electrode pattern formed on the dielectric sheet by a sputtering method, and the laminate is configured such that, from an upper end to a lower end of the central portion in the stacking direction, an area of ​​each of the internal electrode patterns constituting the plurality of internal electrode patterns becomes smaller the closer to the underside of the main body.

[0119] [Supplementary Note 18] The step of forming the laminate includes: a step of preparing a first composite sheet included in the composite sheet; and a step of preparing a second composite sheet included in the composite sheet and disposed above the first composite sheet, wherein the first composite sheet has a first dielectric sheet included in the dielectric sheet and a first internal electrode pattern included in the internal electrode pattern, and the second composite sheet has a second dielectric sheet included in the dielectric sheet and a second internal electrode pattern included in the internal electrode pattern and having an area smaller than that of the first internal electrode pattern, and the step of preparing the first composite sheet includes: a step of placing a first mask on the first dielectric sheet, the first mask having a first opening in a shape corresponding to the first internal electrode pattern, and a step of forming the first internal electrode pattern by a sputtering method on the first dielectric sheet on which the first mask is placed, and and forming the second internal electrode pattern by a sputtering method on the second dielectric sheet on which the second mask is placed.

[0120] [Supplementary Note 19] The step of forming the laminate includes: a step of preparing a first composite sheet included in the composite sheet; and a step of preparing a second composite sheet included in the composite sheet after the step of preparing the first composite sheet, wherein the first composite sheet has a first dielectric sheet included in the dielectric sheet and a first internal electrode pattern included in the internal electrode pattern, and the second composite sheet has a second dielectric sheet included in the dielectric sheet and a second internal electrode pattern included in the internal electrode pattern and having an area smaller than that of the first internal electrode pattern, and the step of preparing the first composite sheet includes: a step of placing a mask on the first dielectric sheet, the mask having an upper surface, a lower surface, and an opening having a shape corresponding to the first internal electrode pattern, and a step of forming the first internal electrode pattern by a sputtering method on the first dielectric sheet on which the mask is placed, and the step of preparing the second composite sheet includes: a step of cleaning the upper surface without cleaning the opening of the mask, and a step of placing the mask cleaned in the cleaning step on the second dielectric sheet, forming the second internal electrode pattern by sputtering on the second dielectric sheet on which the mask is placed.

[0121] 1, 51, 61, 71, 81 Multilayer ceramic capacitor 10 Body 11 Dielectric layer 21 First internal electrode layer 22 Second internal electrode layer 31 First external electrode 32 Second external electrode R1 Center portion R2 Upper cover portion R3 Lower cover portion Ra Capacitance generating area

Claims

1. A multilayer ceramic capacitor having a plurality of dielectric layers and a plurality of internal electrode layers stacked in a stacking direction with at least one of the plurality of dielectric layers interposed therebetween, the multilayer ceramic capacitor being partitioned into a central portion including a capacitance generating region where a plurality of first internal electrode layers of the plurality of internal electrode layers and a plurality of second internal electrode layers of the plurality of internal electrode layers are alternately stacked in the stacking direction, a lower cover portion located below the central portion in the stacking direction, and an upper cover portion located above the central portion in the stacking direction; a first external electrode electrically connected to each of the plurality of first internal electrode layers and provided on the main body; and a second external electrode electrically connected to each of the plurality of second internal electrode layers and provided on the main body; the main body being configured such that, from the top end to the bottom end of the central portion in the stacking direction, the area of ​​each internal electrode layer constituting the plurality of internal electrode layers becomes smaller the closer it is to the underside of the main body.

2. The multilayer ceramic capacitor according to claim 1, wherein the body has a first end face and a second end face that face each other in a length direction perpendicular to the stacking direction, and the body is configured such that, from the top end to the bottom end of the central portion in the stacking direction, the dimension in the length direction of each of the internal electrode layers that make up the plurality of internal electrode layers becomes smaller the closer it is to the bottom surface of the body.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the body has a first end face and a second end face that face each other in a length direction perpendicular to the lamination direction, and ends of each of the first internal electrode layers constituting the plurality of first internal electrode layers are located at different positions in the length direction.

4. The multilayer ceramic capacitor according to claim 3, wherein the ends of the second internal electrode layers constituting the plurality of second internal electrode layers are located at different positions in the length direction.

5. A multilayer ceramic capacitor according to claim 1 or 2, wherein the main body has a first side surface and a second side surface that face each other in a width direction perpendicular to the stacking direction and the length direction, and the main body is configured such that, from the top end to the bottom end of the central portion in the stacking direction, the dimension in the width direction of each of the first internal electrode layers constituting the plurality of first internal electrode layers becomes smaller the closer it is to the bottom surface of the main body, and the dimension in the width direction of the plurality of second internal electrode layers becomes smaller the closer it is to the bottom surface of the main body.

6. The multilayer ceramic capacitor according to claim 1 or 2, wherein a difference between a first area indicating an area of ​​an upper internal electrode layer of a set of adjacent internal electrode layers included in the plurality of internal electrode layers, and a second area indicating an area of ​​a lower internal electrode layer of the set of internal electrode layers, is 0.001 to 1% of the first area.

7. The multilayer ceramic capacitor according to claim 6, wherein the difference between the first area and the second area is 0.001 to 0.1% of the first area.

8. The multilayer ceramic capacitor according to claim 1 or 2, wherein a difference between a third area indicating an area of ​​the uppermost internal electrode layer arranged on the uppermost side among the plurality of internal electrode layers and a fourth area indicating an area of ​​the lowermost internal electrode layer arranged on the lowermost side is 5 to 25% of the third area.

9. The multilayer ceramic capacitor according to claim 2, wherein a difference between a first length indicating the length in the longitudinal direction of an uppermost internal electrode layer arranged at the uppermost side among the plurality of internal electrode layers and a second length indicating the length in the longitudinal direction of a lowermost internal electrode layer arranged at the lowermost side is 1 to 5% of the first length.

10. The multilayer ceramic capacitor according to claim 1 or 2, wherein the body is configured such that the thickness of each of the plurality of internal electrode layers becomes thinner from the top end to the bottom end of the central portion in the stacking direction toward the bottom surface of the body.

11. The multilayer ceramic capacitor according to claim 10, wherein a difference between a first thickness indicating a thickness of an upper internal electrode layer of a set of adjacent internal electrode layers included in the plurality of internal electrode layers, and a second thickness indicating an area of ​​a lower internal electrode layer of the set of internal electrode layers, is 0.001 to 0.5% of the first thickness.

12. The multilayer ceramic capacitor according to claim 2, wherein a difference between a third thickness indicating the thickness of an uppermost internal electrode layer arranged at the uppermost side of the plurality of internal electrode layers and a fourth thickness indicating the thickness of a lowermost internal electrode layer arranged at the lowermost side is 5 to 100% of the fourth thickness.

13. The multilayer ceramic capacitor according to claim 2, wherein the distance between an end of each of the plurality of first internal electrode layers and the second end face is constant in the length direction, and the distance between an end of each of the plurality of second internal electrode layers and the first end face is constant in the length direction.

14. The multilayer ceramic capacitor according to claim 1 or 2, wherein the body has the lower surface and an upper surface opposite to the lower surface, and a lower surface area representing the area of ​​the lower surface is smaller than an upper surface area representing the area of ​​the upper surface.

15. A multilayer ceramic capacitor according to claim 1 or 2, wherein the plurality of dielectric layers contain crystal grains of barium titanate, the plurality of internal electrode layers all contain Ni and an additive metal element having a Young's modulus smaller than that of Ni, and the main body is configured such that, from the top to the bottom of the central portion in the stacking direction, the concentration of Ni contained in the plurality of internal electrode layers decreases the closer to the bottom surface of the main body, and the concentration of the additive metal element increases the closer to the bottom surface of the main body.

16. A circuit board comprising the multilayer ceramic capacitor according to claim 1 or 2.

17. A method for manufacturing a multilayer ceramic capacitor, comprising: a step of forming a laminate; a step of firing the laminate to form a main body; and a step of forming external electrodes on the main body, wherein the laminate is partitioned into a central portion formed by stacking a plurality of composite sheets in a stacking direction, a lower cover portion located below the central portion in the stacking direction, and an upper cover portion located above the central portion in the stacking direction, each of the plurality of composite sheets having a dielectric sheet and an internal electrode pattern formed on the dielectric sheet by a sputtering method, and the laminate is configured such that, from the upper end to the lower end of the central portion in the stacking direction, the area of ​​each of the internal electrode patterns constituting the plurality of internal electrode patterns becomes smaller the closer it is to the underside of the main body.

18. The step of forming the laminate includes: a step of preparing a first composite sheet included in the composite sheet; and a step of preparing a second composite sheet included in the composite sheet and disposed above the first composite sheet, wherein the first composite sheet has a first dielectric sheet included in the dielectric sheet and a first internal electrode pattern included in the internal electrode pattern, and the second composite sheet has a second dielectric sheet included in the dielectric sheet and a second internal electrode pattern included in the internal electrode pattern and having an area smaller than that of the first internal electrode pattern, and the step of preparing the first composite sheet includes: a step of placing a first mask on the first dielectric sheet, the first mask having a first opening in a shape corresponding to the first internal electrode pattern, and a step of forming the first internal electrode pattern by a sputtering method on the first dielectric sheet on which the first mask is placed, and the step of preparing the second composite sheet includes: a step of placing a second mask on the second dielectric sheet, the second mask having a second opening in a shape corresponding to the second internal electrode pattern, 18. The method for manufacturing a multilayer ceramic capacitor according to claim 17, further comprising: forming the second internal electrode pattern by a sputtering method on the second dielectric sheet on which the second mask is placed.

19. The step of forming the laminate includes: a step of preparing a first composite sheet included in the composite sheet; and a step of preparing a second composite sheet included in the composite sheet after the step of preparing the first composite sheet, wherein the first composite sheet has a first dielectric sheet included in the dielectric sheet and a first internal electrode pattern included in the internal electrode pattern, and the second composite sheet has a second dielectric sheet included in the dielectric sheet and a second internal electrode pattern included in the internal electrode pattern and having an area smaller than that of the first internal electrode pattern, and the step of preparing the first composite sheet includes: a step of placing a mask on the first dielectric sheet, the mask having an upper surface, a lower surface, and an opening having a shape corresponding to the first internal electrode pattern, and a step of forming the first internal electrode pattern by a sputtering method on the first dielectric sheet on which the mask is placed, and the step of preparing the second composite sheet includes: a step of cleaning the upper surface without cleaning the opening of the mask, and a step of placing the mask cleaned in the cleaning step on the second dielectric sheet.

18. The method for manufacturing a multilayer ceramic capacitor according to claim 17, further comprising: forming the second internal electrode pattern by a sputtering method on the second dielectric sheet on which the mask is placed.

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