Multilayer ceramic capacitor and method for producing multilayer ceramic capacitor

Abstract

According to the present invention, fail-open is more surely achieved in a multilayer ceramic capacitor. In this multilayer ceramic capacitor, one first internal electrode layer among a plurality of first internal electrode layers is disposed adjacent to one second internal electrode layer among a plurality of second internal electrode layers, in a first direction. The one first internal electrode layer has a first thin layer portion in a first end region that faces an end portion of the one second internal electrode layer. A first thickness that represents the dimension in the first direction of the first thin layer portion is smaller than a first average thickness that represents the average of dimensions in the first direction of the one first internal electrode layer.

Description

Multilayer ceramic capacitor and method of manufacturing the same

[0001] The disclosure of this specification primarily relates to multilayer ceramic capacitors and methods for manufacturing multilayer ceramic capacitors.

[0002] Multilayer ceramic capacitors are installed in various electronic devices. A multilayer ceramic capacitor has a body in which multiple dielectric layers and multiple internal electrode layers are alternately stacked. When a voltage is applied to the internal electrode layers during use of a multilayer ceramic capacitor, capacitance is generated in the capacitance generation region where the internal electrode layers face each other via the dielectric layer.

[0003] In recent years, dielectric layers have been made thinner to improve the capacitance of multilayer ceramic capacitors. By making the dielectric layers thinner, the spacing between internal electrode layers becomes smaller and the number of layers can be increased for a given external dimension, which allows for an efficient improvement in the capacitance of the multilayer ceramic capacitor.

[0004] As the dielectric layer becomes thinner, the insulation between the internal electrode layers decreases. This can lead to dielectric breakdown between the internal electrode layers. When dielectric breakdown occurs, the internal electrode layers short out, causing an abnormal current to flow in the circuit in which the multilayer ceramic capacitor is installed, resulting in damage to the circuit.

[0005] In order to suppress damage to the circuit in the event of a dielectric breakdown, a fuse structure that burns out due to Joule heat generated by an abnormal current that occurs in the event of a dielectric breakdown is sometimes provided in the internal electrode layer. For example, International Publication No. 2016 / 009852 (Patent Document 1) describes a multilayer ceramic capacitor in which a narrow portion that functions as a fuse is formed in the internal electrode layer. In a multilayer ceramic capacitor in which a fuse structure is provided in the internal electrode layer, it is expected that even if a dielectric breakdown occurs between the internal electrode layers, the fuse structure will burn out, thereby achieving a fail-open state.

[0006] International Publication No. 2016 / 009852

[0007] Conventionally, the placement of a fuse structure has been determined primarily from the viewpoint of suppressing a decrease in capacitance, without considering the location of dielectric breakdown. For example, Cited Document 1 states that, in order to suppress a decrease in capacitance, it is desirable to provide the fuse structure near the end face of the body (see paragraph

[0021] ). However, because a strong electric field that causes dielectric breakdown in a multilayer ceramic capacitor occurs in the region near the internal electrode layers, providing the fuse structure near the end face of the body may result in dielectric breakdown occurring at a location distant from the fuse structure. If dielectric breakdown occurs at a location distant from the fuse structure, the dielectric breakdown may spread to multiple internal electrode layers near the breakdown location before the fuse structure burns out and fails open. If dielectric breakdown occurs across multiple internal electrode layers, multiple paths for short-circuit current flow are created, making it difficult for the fuse structure to burn out, which may result in failure to achieve fail open.

[0008] Therefore, there is a need for a mechanism that can more reliably achieve fail-open when dielectric breakdown occurs between internal electrode layers. One of the objects of the invention disclosed in this specification is to provide a multilayer ceramic capacitor that can more reliably achieve fail-open.

[0009] Objects of the present invention other than those mentioned above will become clear throughout the entire specification. The inventions disclosed in this specification may solve problems that are understood from other than those described in the "Problems to be Solved by the Invention" section. When the present specification describes the effects of an embodiment, the problems of the invention corresponding to that embodiment can be understood from those effects. The various inventions disclosed in this specification may be collectively referred to as "the present invention."

[0010] The inventors of the present invention have noticed that in a multilayer ceramic capacitor, since the electric field tends to be strong in the region near the end of the internal electrode layer, breakdown between the internal electrode layers tends to occur particularly in the region near the end of the internal electrode layer. Then, they have found that when the first internal electrode layer and the second internal electrode layer are adjacent to each other in the stacking direction, by providing the fuse structure of the first internal electrode layer in the region facing the end of the second internal electrode layer, it is possible to arrange the fuse structure of the first internal electrode layer near the end of the second internal electrode layer where breakdown is likely to occur, and therefore fail-open can be more reliably achieved.

[0011] The inventors of the present application have also discovered that by forming a thin layer portion with a small thickness in the internal electrode layer, the thin layer portion can be made to function as a fuse without reducing the area of ​​the capacitance generating region.

[0012] One aspect of the present invention, which has been made based on the above findings, relates to a multilayer ceramic capacitor comprising: a body having a plurality of dielectric layers and a plurality of internal electrode layers stacked in a first direction via at least one of the plurality of dielectric layers, the body having a first surface and a second surface facing each other in a second direction perpendicular to the first direction, a first external electrode provided on the first surface of the body so as to be electrically connected to each of a plurality of first internal electrode layers of the plurality of internal electrode layers, and a second external electrode provided on the second surface of the body so as to be electrically connected to each of a plurality of second internal electrode layers of the plurality of internal electrode layers, wherein one first internal electrode layer of the plurality of first internal electrode layers is disposed adjacent to one second internal electrode layer of the plurality of second internal electrode layers in the first direction. In one aspect of the present invention, the one first internal electrode layer has a first thin layer portion in a first end region facing the end of the one second internal electrode layer in the second direction, and a first thickness representing the dimension of the first thin layer portion in the first direction is smaller than a first average thickness representing the average dimension of the one first internal electrode layer in the first direction.

[0013] According to one aspect of the invention disclosed in this specification, the first thin layer portion functioning as a fuse is provided in a region facing the end of the second internal electrode layer where dielectric breakdown is likely to occur. Therefore, the first thin layer portion is likely to be burned out by a large current generated by dielectric breakdown, so that fail-open can be more reliably achieved in the multilayer ceramic capacitor.

[0014] 1 is a perspective view schematically showing a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 2 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor of FIG. 1 taken along a side surface; FIG. 3 is an enlarged cross-sectional view schematically showing an enlarged region A1 of the cross section of FIG. 2; FIG. 4 is a cross-sectional view schematically showing a cross section of a multilayer ceramic capacitor according to another embodiment of the present invention taken along a side surface; FIG. 5 is an enlarged cross-sectional view schematically showing an enlarged region A2 of the cross section of FIG. 4; FIG. 6 is a cross-sectional view schematically showing a cross section of a multilayer ceramic capacitor according to yet another embodiment of the present invention taken along a side surface; FIG. 7 is a flow diagram showing a method for manufacturing a multilayer ceramic capacitor 1 according to an embodiment of the present invention; FIG. 8 is a schematic diagram showing sheet units U1 to U3 produced in a process for manufacturing a multilayer ceramic capacitor 1 according to an embodiment of the present invention; FIG. 9 is a schematic diagram showing a laminated sheet unit U10 produced in a process for manufacturing a multilayer ceramic capacitor 1 according to an embodiment of the present invention; FIG. 1 is a schematic diagram showing a part of the manufacturing process of sheet unit U1. FIG. 2 is a schematic diagram showing a part of the manufacturing process of sheet unit U1. FIG. 3 is a schematic diagram showing a part of the manufacturing process of sheet unit U1. FIG. 4 is a schematic diagram showing a part of the manufacturing process of sheet unit U2. FIG. 5 is a schematic diagram showing a part of the manufacturing process of sheet unit U2. FIG. 6 is a schematic diagram showing a part of the manufacturing process of sheet unit U2. FIG. 7 is a schematic diagram showing a part of the manufacturing process of sheet unit U2. FIG. 8 is a schematic diagram showing a part of the manufacturing process of sheet unit U2. FIG. 9 is a schematic diagram showing a part of the manufacturing process of sheet unit U2. FIG. 10 is a schematic diagram showing a part of the manufacturing process of sheet unit U2. FIG. 11 is a cross-sectional view schematically showing a chip laminate 90 manufactured in a process of manufacturing a multilayer ceramic capacitor 1 according to an embodiment of the present invention.1 is a cross-sectional view schematically showing a chip stack 190 produced in a process for manufacturing a multilayer ceramic capacitor 101 according to an embodiment of the present invention.

[0015] Various embodiments of the present invention will be described below with appropriate reference to the drawings. Components common to multiple drawings are designated by the same or similar reference numerals. Please note that the drawings are not necessarily drawn to scale for the sake of convenience. The embodiments described below do not necessarily limit the invention according to the claims. Elements described in the following embodiments are not necessarily essential to the solution of the invention.

[0016] For ease of explanation, each drawing may include an L-axis, a W-axis, and a T-axis that are perpendicular to each other. In this specification, the dimensions, arrangement, shape, and other characteristics of each component of the multilayer ceramic capacitor 1 may be described based on the L-axis, W-axis, and T-axis.

[0017] 1 Multilayer Ceramic Capacitor 1 (First Embodiment) 1-1 Basic Structure of Multilayer Ceramic Capacitor 1 The basic structure of a multilayer ceramic capacitor 1 according to one embodiment of the present invention will be described with reference to Figures 1 to 3. Figure 1 is a perspective view of the multilayer ceramic capacitor 1 according to one embodiment. Figure 2 is a cross-sectional view schematically showing a cross section of the multilayer ceramic capacitor 1 taken along line II. Figure 3 is an enlarged cross-sectional view schematically showing an enlarged region A1 of the cross section of the multilayer ceramic capacitor 1 shown in Figure 2.

[0018] The multilayer ceramic capacitor 1 includes a body 10, and a first external electrode 31 and a second external electrode 32 provided on the body 10. The first external electrode 31 is disposed spaced apart from the second external electrode 32.

[0019] The main body 10 includes a plurality of dielectric layers 11, a plurality of first internal electrode layers 21, and a plurality of second internal electrode layers 22. In this specification, when it is not necessary to distinguish between the first internal electrode layers 21 and the second internal electrode layers 22, the first internal electrode layers 21 and the second internal electrode layers 22 may be collectively referred to as "internal electrode layers." The dielectric layer 11 is disposed between adjacent internal electrode layers. For example, the first internal electrode layer 21 is disposed on the upper surface of the dielectric layer 11, and the second internal electrode layer 22 is disposed on the lower surface of the dielectric layer 11.

[0020] In the main body 10, the dielectric layers 11, the first internal electrode layers 21, and the second internal electrode layers 22 are stacked along a stacking direction (for example, the T-axis direction). At least one dielectric layer 11 is disposed between adjacent ones of the first internal electrode layers 21 and the second internal electrode layers 22. The stacking direction may be along the T-axis as shown in the figure, or along the L-axis or W-axis.

[0021] The main body 10 has an upper surface 10a, a lower surface 10b, a first end surface 10c, a second end surface 10d, a first side surface 10e, and a second side surface 10f. The outer surface of the main body 10 is defined by the upper surface 10a, the lower surface 10b, the first end surface 10c, the second end surface 10d, the first side surface 10e, and the second side surface 10f.

[0022] The top surface 10a and the bottom surface 10b respectively form the surfaces at both ends of the main body 10 in the height direction (T-axis direction). The top surface 10a and the bottom surface 10b face each other in the T-axis direction. The first end surface 10c and the second end surface 10d respectively form the surfaces at both ends of the main body 10 in the length direction (L-axis direction). The first end surface 10c and the second end surface 10d face each other in the L-axis direction. The first side surface 10e and the second side surface 10f respectively form the surfaces at both ends of the main body 10 in the width direction (W-axis direction). The first side surface 10e and the second side surface 10f face each other in the W-axis direction. The top surface 10a and the bottom surface 10b are spaced apart by the height dimension of the main body 10, the first end surface 10c and the second end surface 10d are spaced apart by the length dimension of the main body 10, and the first side surface 10e and the second side surface 10f are spaced apart by the width dimension of the main body 10.

[0023] One end of the first internal electrode layer 21 is extended toward the outside of the main body 10. The first internal electrode layer 21 is connected to a first external electrode 31 provided on the surface of the main body 10. One end of the second internal electrode layer 22 is extended toward the outside of the main body 10. The second internal electrode layer 22 is connected to a second external electrode 32 provided on the surface of the main body 10. In the embodiment shown in FIG. 2 , the first internal electrode layer 21 is extended toward the outside of the main body 10 from the first end face 10c. The first internal electrode layer 21 is connected to the first external electrode 31 at one end of the main body 10 in the L-axis direction. The second internal electrode layer 22 is extended toward the outside of the main body 10 from the second end face 10d. The second internal electrode layer 22 is connected to the second external electrode 32 at the other end of the main body 10 in the L-axis direction. 2, the first internal electrode layer 21 and the second internal electrode layer 22 are respectively drawn to the opposing first end face 10c and second end face 10d, but the first internal electrode layer 21 and the second internal electrode layer 22 may be drawn from various surfaces of the main body 10 depending on the arrangement and shape of the first external electrode 31 and the second external electrode 32. For example, if the first external electrode 31 and the second external electrode 32 are both arranged on the lower surface 10b, then both the first external electrode 31 and the second external electrode 32 are drawn from the lower surface. The first external electrode 31 and the second external electrode 32 may be provided on any surface of the main body 10 as long as they are spaced apart from each other.

[0024] In one embodiment, the multilayer ceramic capacitor 1 may be configured to have a rectangular parallelepiped shape. In this specification, the terms "rectangular parallelepiped" or "rectangular parallelepiped shape" do not necessarily mean "rectangular parallelepiped" in the strict mathematical sense. As will be described later, the corners and / or sides of the main body 10 may be curved. The dimensions and shape of the main body 10 are not limited to those explicitly stated in this specification.

[0025] In one embodiment, the dimension (length dimension) of the multilayer ceramic capacitor 1 in the L-axis direction is in the range of 0.1 mm to 3.5 mm, the dimension (width dimension) in the W-axis direction is in the range of 0.1 mm to 2.5 mm, and the dimension (height dimension) in the T-axis direction is in the range of 0.1 mm to 3.0 mm. In one embodiment, the length dimension of the multilayer ceramic capacitor 1 may be greater than the width dimension. In one embodiment, the height dimension of the multilayer ceramic capacitor 1 may be greater than the width dimension. In one embodiment, the width dimension of the multilayer ceramic capacitor 1 may be greater than the length dimension.

[0026] The multilayer ceramic capacitor 1 can be mounted on an electronic circuit board. An electronic circuit board on which the multilayer ceramic capacitor 1 is mounted is sometimes called a circuit module. Various electronic components other than the multilayer ceramic capacitor 1 can also be mounted on the circuit module. This circuit module can be mounted in various electronic devices. Electronic devices in which the circuit module can be mounted include smartphones, tablets, game consoles, automotive electrical components, servers, and various other electronic devices.

[0027] The multilayer ceramic capacitor 1 is mounted on the surface of the electronic circuit board so that the lower surface 10b of the body 10 faces the surface of the electronic circuit board. For this reason, the lower surface 10b of the body 10 is sometimes referred to as the mounting surface (mounting surface 10b). The multilayer ceramic capacitor 1 is joined by solder to lands provided on the surface of the electronic circuit board 2. The lands are provided on the surface of the electronic circuit board at positions corresponding to the first external electrode 31 and the second external electrode 32.

[0028] 1-2 Dielectric Layer 11 The dielectric layer 11 may include a ceramic material with a high dielectric constant. The dielectric layer 11 may include, for example, an oxide represented by the chemical formula ABO3 as a main component. In the chemical formula ABO3, "A" is, for example, at least one element selected from the group consisting of Ba (barium), Sr (strontium), Ca (calcium), and Mg (magnesium). In the chemical formula ABO3, "B" is, for example, at least one element selected from the group consisting of Ti (titanium), Zr (zirconium), and Hf (hafnium). Examples of oxides included as a main component in the dielectric layer 11 include BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), and MgTiO3 (magnesium titanate).

[0029] The dielectric layer 11 may contain an additive element. In one embodiment, the additive element contained in the dielectric layer 11 is at least one element selected from the group consisting of Ni (nickel), Mo (molybdenum), Nb (niobium), Ta (tantalum), W (tungsten), V (vanadium), and Cr (chromium). The dielectric layer 11 may contain two or more types of the additive elements.

[0030] Dielectric layer 11 may contain an oxide of a rare earth element in addition to the oxide of the main component. The oxide of the rare earth element contained in dielectric layer 11 may be an oxide of at least one rare earth element selected from the group consisting of Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium). Dielectric layer 11 may contain two or more types of oxides of rare earth elements.

[0031] The dielectric layer 11 may contain, in addition to the oxide of the main component, oxides derived from known sintering aids or elements derived from glass, as shown below.

[0032] The dielectric layer 11 may contain, for example, an oxide of at least one element selected from the group consisting of Co (cobalt), Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon). The dielectric layer 11 may contain two or more types of oxides of these elements.

[0033] The dielectric layer 11 may contain a glass containing at least one element selected from the group consisting of Co, Ni, Li, B, Na, K, and Si.

[0034] In one embodiment, the film thickness (dimension in the T-axis direction) of the dielectric layer 11 is 0.1 to 5 μm. When the dielectric film 11 is formed by sputtering, the lower limit of the film thickness of the dielectric layer 11 may be 0.1 μm, and the upper limit may be 1 μm. When the dielectric film 11 is formed by a printing method, the lower limit of the film thickness of the dielectric layer 11 may be 0.4 μm, and the upper limit may be 5 μm.

[0035] 1-3 First Internal Electrode Layer 21 and Second Internal Electrode Layer 22 In the illustrated embodiment, n layers of the first internal electrode layers 21 and the second internal electrode layers 22 are laminated (where n is a positive integer). The number of layers of the first internal electrode layers 21 and the number of layers of the second internal electrode layers 22 may be the same, or the number of layers of the first internal electrode layers 21 may be one layer more than the number of layers of the second internal electrode layers 22. When it is necessary to distinguish a specific one of the first internal electrode layers 21 from the others, each first internal electrode layer 21 is distinguished by adding a sub-number to the reference numeral indicating the first internal electrode layer 21, such that the first internal electrode layer 21 closest to the lower surface 10b of the main body 10 is referred to as the first internal electrode layer 21-1, the next closest is referred to as the first internal electrode layer 21-2, and so on. Since n layers of the first internal electrode layers 21 are laminated, the first internal electrode layer 21-n is disposed closest to the upper surface 10a of the main body 10. Similarly, when it is necessary to distinguish a particular one of the second internal electrode layers 22 from the others, the second internal electrode layer 22 that is closest to the lower surface 10b of the main body 10 is referred to as the second internal electrode layer 22-1, the next closest one is referred to as the second internal electrode layer 22-2, etc. In the illustrated embodiment, since n layers of the second internal electrode layers 22 are stacked, the second internal electrode layer 22-n (when the number of stacked second internal electrode layers 22 is n-1 layers, the second internal electrode layer 22-(n-1)) is arranged closest to the upper surface 10a of the main body 10.

[0036] 2 and 3, for the sake of simplicity, four layers of each of the first internal electrode layers 21 and the second internal electrode layers 22 are shown, but the multilayer ceramic capacitor 1 may have any number of first internal electrode layers 21 and second internal electrode layers 22 greater than four, and may have, for example, 300 to 1000 layers of the first internal electrode layers 21 and second internal electrode layers 22. In other words, the number of stacked layers in the multilayer ceramic capacitor 1 may be 300 to 1000.

[0037] In one embodiment, the film thickness (dimension in the T-axis direction) of the first internal electrode layer 21 and the film thickness (dimension in the T-axis direction) of the second internal electrode layer 22 are both 0.1 μm or more and 2 μm or less.

[0038] In one embodiment, the first internal electrode layers 21 contain, as a main component, a base metal such as Ni (nickel), Cu (copper), Sn (tin), etc. Based on the total mass of the first internal electrode layers 21, a component contained in the first internal electrode layers 21 at 50 wt % or more can be the main component of the first internal electrode layers 21.

[0039] The first internal electrode layer 21 is provided on a portion of the upper surface of the dielectric layer 11. In the illustrated embodiment, the first internal electrode layer 21 is provided on the upper surface of the dielectric layer 11 so as to be drawn out from the first end face 10c to the outside of the main body 10, and to be spaced apart from the second end face 10d, the first side face 10e, and the second side face 10f. The first internal electrode layer 21 is constructed and arranged so that its end 21a in the positive direction of the L axis (the L1 direction in FIG. 2 ) faces the second end face 10d.

[0040] The second internal electrode layer 22 is provided on a part of the upper surface of a dielectric layer 11 separate from the dielectric layer 11 on which the first internal electrode layer 21 is provided. In the illustrated embodiment, the second internal electrode layer 22 is provided on the upper surface of the dielectric layer 11 so as to be drawn out from the second end face 10d to the outside of the body 10, while being spaced apart from the first end face 10c, the first side face 10e, and the second side face 10f. The second internal electrode layer 22 is configured and arranged so that its end 22a in the negative L-axis direction (the L2 direction in FIG. 2 ) faces the first end face 10c.

[0041] In one aspect of the present invention, at least one of the plurality of first internal electrode layers 21 has a first thin layer portion 21b. Among the first internal electrode layers 21 shown in Fig. 2, each of the first internal electrode layers 21-1, 21-2, 21-(n-1), and 21-n has the first thin layer portion 21b. The first thin layer portion 21b may be provided in each of the first internal electrode layers 21 included in the main body 10.

[0042] The first thin layer portion 21b of the first internal electrode layer 21 is disposed in a first end region. The first end region refers to a region facing the end 22a of the second internal electrode layer 22 adjacent to the first internal electrode layer 21 in the T-axis direction. In other words, the first thin layer portion 21b of the first internal electrode layer 21 is provided in a region facing the end 22a in the L-axis direction of the second internal electrode layer 22 adjacent to the first internal electrode layer 21, inside the main body 10. In the example shown in Fig. 2, the first thin layer portion 21b of the first internal electrode layer 21-1 is provided at a position facing the end 22a of the second internal electrode layer 22-1 adjacent to the first internal electrode layer 21-1 in the T-axis direction. Similarly, the first thin layer portion 21b of the first internal electrode layer 21-2 is provided at a position facing the end 22a of the second internal electrode layer 22-1 and the end 22a of the second internal electrode layer 22-2 adjacent to the first internal electrode layer 21-2 in the T-axis direction. When the main body 10 is viewed from above, the first thin layer portion 21b of the first internal electrode layer 21 is provided at a position overlapping the end 22a of the second internal electrode layer 22.

[0043] The first thin portion 21b is provided at a position spaced apart from the first end surface 10c of the main body 10 in the L-axis direction. In other words, the first end region is spaced apart from the first end surface 10c in the L-axis direction.

[0044] As shown in FIG. 3 , the first thin layer portions 21b of the first internal electrode layer 21 are configured so that their thickness dimension T11 is smaller than a first average thickness T31 representing the average thickness dimension of the first internal electrode layer 21. The thickness dimension T11 of the first thin layer portions 21b means the dimension of the first thin layer portions 21b in the T-axis direction. If the thickness of the first thin layer portions 21b is not constant, the thickness of the first thin layer portions 21b can be measured at three different points in the L-axis direction, and the average of the thicknesses at the three points can be used as the thickness of the first thin layer portions 21b. The thickness dimension of the first internal electrode layer 21 means the dimension of the first internal electrode layer 21 in the T-axis direction. The first average thickness T31 of the first internal electrode layer 21 can be measured at five different points in the L-axis direction (however, these five points are selected from among the first thin layer portions 21b) and used as the average of the thickness dimensions at the five points. In one embodiment, the thickness of the first thin layer portion 21b is in the range of 10 to 90% of the first average thickness of the first internal electrode layer 21. The thickness of the first thin layer portion 21b may be in the range of 10 to 70%, 10 to 50%, or 10 to 30% of the first average thickness of the first internal electrode layer 21.

[0045] The first internal electrode layer 21 has an upper surface 21c and a lower surface 21d opposite to the upper surface 21c. As shown in FIG. 3, the first internal electrode layer 21 may be formed so that its upper surface 21c is recessed in the first end region, and this recessed portion may be the first thin layer portion 21b. The first internal electrode layer 21 may be formed so that its lower surface 21d is recessed in the first end region. The first internal electrode layer 21 may be formed so that both the upper surface 21c and the lower surface 21d are recessed in the first end region. In the embodiment shown in FIG. 3, the upper surface 21c of the first internal electrode layer 21 is recessed between one end E1 and the other end E2 in the L-axis direction. In the L-axis direction, the region between the end E1 and the end E2 is the first thin layer portion 21b.

[0046] As shown in Fig. 3, the surfaces of the ends 22a of the second internal electrode layers 22 may be inclined with respect to the T-axis. In the embodiment shown in Fig. 3, the lower surfaces 22d of the second internal electrode layers 22 extend closer to the first end face 10c than the upper surfaces 22c, and therefore the surfaces of the ends 22a connecting the ends 22c1 of the upper surfaces 22c and the ends 22d1 of the lower surfaces 22d are inclined with respect to the T-axis. In this specification, the region between the ends 22c1 of the upper surfaces 22c and the ends 22d1 of the lower surfaces 22d in the L-axis direction is defined as the ends 22a of the second internal electrode layers 22.

[0047] In one aspect, when the main body 10 is viewed in a plane through the dielectric layer 11, if at least a portion of the first thin layer portion 21b (the region between end E1 and end E2 in the L-axis direction) of the first internal electrode layer 21 overlaps with at least a portion of the end 22a of the second internal electrode layer 22, it can be determined that the first thin layer portion 21b of the first internal electrode layer 21 is located in a region facing the end 22a of the second internal electrode layer 22 adjacent to the first internal electrode layer 21. In another aspect, when the main body 10 is viewed in a plane through the dielectric layer 11, if the entire end 22a of the second internal electrode layer 22 in the L-axis direction (the entire area between the end 22c1 of the upper surface 22c and the end 22d1 of the lower surface 22d in the L-axis direction) is positioned within the area between the end E1 and the end E2 that define the first thin layer portion 21b, it can be determined that the first thin layer portion 21b of the first internal electrode layer 21 is provided in an area facing the end 22a of the second internal electrode layer 22 adjacent to the first internal electrode layer 21.

[0048] In one aspect of the present invention, at least one of the multiple second internal electrode layers 22 has a second thin layer portion 22b. In the example shown in FIG. 2, each of the second internal electrode layers 22-1, 22-2, 22-(n-1), and 22-n has a second thin layer portion 22b. The second thin layer portion 22b may be provided in each of the second internal electrode layers 22 included in the main body 10. The second thin layer portion 22b of the second internal electrode layer 22 is arranged in a second end region. The second end region refers to a region facing the end 21a of the first internal electrode layer 21 adjacent to the first internal electrode layer 22 in the T-axis direction. The second thin layer portion 22b of the second internal electrode layer 22 is provided in a region facing the end 21a of the first internal electrode layer 21 adjacent to the second internal electrode layer 22. 2, the second thin layer portion 22b of the second internal electrode layer 22-1 is provided in a region facing the end portion 21a of the first internal electrode layer 21-1 adjacent to the second internal electrode layer 22-1 from below in the T-axis direction. Furthermore, the first thin layer portion 22b of the second internal electrode layer 22-1 is provided in a region facing the end portion 22a of the first internal electrode layer 21-2 adjacent to the second internal electrode layer 22-1 from above in the T-axis direction. When the main body 10 is viewed from above, the second thin layer portion 22b of the second internal electrode layer 22 is provided at a position overlapping the end portion 21a of the first internal electrode layer 21. The second thin layer portion 22b is provided at a position spaced apart from the second end face 10d of the main body 10 in the L-axis direction.

[0049] The second thin layer portions 22b of the second internal electrode layers 22 are configured so that their thickness dimensions are smaller than a second average thickness representing the average of the thickness dimensions of the second internal electrode layers 22. The thickness dimension of the second thin layer portions 22b refers to the dimension of the second thin layer portions 22b in the T-axis direction. The thickness dimension of the second internal electrode layers 22 refers to the dimension of the second internal electrode layers 22 in the T-axis direction. The second average thickness of the second internal electrode layers 22 can be determined by measuring the thickness dimension of the second internal electrode layers 21 at five different points in the L-axis direction (however, these five points are selected from among the second thin layer portions 22b), and averaging the thickness dimensions at the five points. In one embodiment, the thickness of the second thin layer portions 22b is in the range of 10 to 90% of the second average thickness of the second internal electrode layers 22. The thickness of the second thin layer portions 22b may be in the range of 10 to 70%, 10 to 50%, or 10 to 30% of the second average thickness of the second internal electrode layers 22.

[0050] The description of the first thin portion 21b in this specification also applies to the second thin portion 22b unless a contradiction arises.

[0051] 1-4 Reverse Pattern Layers 16, 17 In this specification, the region of the upper surface of the dielectric layer 11 that is covered by either the first internal electrode layer 21 or the second internal electrode layer 22 is sometimes referred to as the electrode formation region, and the region where neither the first internal electrode layer 21 nor the second internal electrode layer 22 is formed is sometimes referred to as the margin region. The region of the margin region that exists between the electrode formation region and the first end face 10c or the second end face 10d is sometimes referred to as the end margin region, and the region of the margin region that exists between the electrode formation region and the first side face 10e or the second side face 10f is sometimes referred to as the side margin region. The reverse pattern layer 16 is provided so as to cover the margin region of the upper surface of the dielectric layer 11. Figure 2 shows the reverse pattern layer 16 formed in the end margin region. The reverse pattern layer 16 provided on the dielectric layer 11 on which the first internal electrode layer 21 is formed is provided on the upper surface of the dielectric layer 11 so as to extend between the first internal electrode layer 21 and the second end face 10d, the first side face 10e, and the second side face 10f. The reverse pattern layer 16 provided on the dielectric layer 11 on which the second internal electrode layer 22 is formed is provided on the upper surface of the dielectric layer 11 so as to extend between the second internal electrode layer 22 and the first end face 10c, the first side face 10e, and the second side face 10f.

[0052] The reverse pattern layer 17 is provided on the first thin layer portion 21b of the first internal electrode layer 21 and the second thin layer portion 22b of the second internal electrode layer 22. When the first thin layer portion 21b is formed as a recess recessed from the upper surface 21c, the reverse pattern layer 17 may be provided so as to fill the recess. Similarly, when the second thin layer portion 22b is formed as a recess recessed from the upper surface, the reverse pattern layer 17 may be provided so as to fill the recess.

[0053] The reverse pattern layers 16 and 17 are formed from a ceramic material. The reverse pattern layer 16 may be formed from the same ceramic material as the material of the dielectric layer 11.

[0054] 1-5 First External Electrode 31 and Second External Electrode 32 In one aspect, the first external electrode 31 and the second external electrode 32 are formed by applying a conductive paste to the main body 10 and heating the conductive paste. The conductive paste may include at least one material selected from the group consisting of Ag (silver), Pd (palladium), Au (gold), Pt (platinum), Ni (nickel), Sn (tin), Cu (copper), W (tungsten), Ti (titanium), and alloys thereof.

[0055] 1-6 Summary In the multilayer ceramic capacitor 1, the electric field generated from the second internal electrode layer 22 is stronger at the end 22a of the second internal electrode layer 22, and the electric field generated from the first internal electrode layer 21 is stronger at the end 21a of the first internal electrode layer 21. Therefore, in the main body 10, dielectric breakdown is more likely to occur near the end 21a of the first internal electrode layer 21 and near the end 22a of the second internal electrode layer 22 than in regions near the centers of the first internal electrode 21 and the second internal electrode 22 in the L-axis direction and W-axis direction. The first thin layer portion 21b of the first internal electrode layer 21 is provided in a region facing the end 22a of the second internal electrode layer 22 in the L-axis direction, where dielectric breakdown is more likely to occur. Therefore, a large current generated by dielectric breakdown near the end 22a of the second internal electrode layer 22 is more likely to flow to the first thin layer portion 21b, which is located near the position where dielectric breakdown occurs. Furthermore, since the second thin layer portion 22b of the second internal electrode layer 22 is provided in a region facing the end portion 21a of the first internal electrode layer 21 in the L-axis direction, where breakdown is likely to occur, a large current generated by breakdown near the end portion 21a of the first internal electrode layer 21 is likely to flow to the second thin layer portion 22b located near the location of breakdown. Therefore, when breakdown occurs, the first thin layer portion 21b and the second thin layer portion 22b are burned out by the large current generated by the breakdown. This prevents breakdown across multiple layers of the multilayer ceramic capacitor 1 in regions other than the first thin layer portion 21b and the second thin layer portion 22b that function as fuses, such as regions near the centers of the WL surfaces of the first internal electrode 21 and the second internal electrode 22, due to the large current. This allows the multilayer ceramic capacitor 1 to more reliably achieve fail-open.

[0056] In one aspect of the multilayer ceramic capacitor 1, the first thin layer portion 21b is located at a position spaced apart from the first end face 10c of the main body 10, thereby preventing a decrease in the reliability of the joint between the first internal electrode layer 21 and the first external electrode 31 due to the first thin layer portion 21b being joined to the first external electrode 31.

[0057] In one aspect of the multilayer ceramic capacitor 1, the upper surface 31c of the first external electrode 31 is recessed in the first thin layer portion 21b, and therefore an electric field tends to concentrate around the periphery of this recess (for example, at the ends E1 and E2 that define both ends of the first thin layer portion 21b in the L-axis direction). This makes it possible to more reliably guide the position at which dielectric breakdown occurs in the main body 10 to the vicinity of the first thin layer portion 21b. Therefore, when the recess formed on the surface of the first external electrode 31 is the first thin layer portion 21b, the multilayer ceramic capacitor 1 can more reliably achieve fail-open.

[0058] 2. Multilayer Ceramic Capacitor 101 (Second Embodiment) Next, a multilayer ceramic capacitor 101 according to another embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG. 4 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 101 taken along a plane parallel to the LT plane (i.e., a plane parallel to the first side surface 10e or the second side surface 10f), and FIG. 5 is an enlarged cross-sectional view schematically showing an enlarged region A2 of the cross section of the multilayer ceramic capacitor 101 shown in FIG. 4. The multilayer ceramic capacitor 101 differs from the multilayer ceramic capacitor 1 in that it includes first internal electrode layers 121 instead of the first internal electrode layers 21 and second internal electrode layers 122 instead of the second internal electrode layers 22. The multilayer ceramic capacitor 101 also differs from the multilayer ceramic capacitor 1 in that it includes reverse pattern layers 116a to 116d instead of the reverse pattern layer 16. Detailed description of components of the multilayer ceramic capacitor 101 that are the same as or similar to those of the multilayer ceramic capacitor 1 will be omitted.

[0059] 4, the multilayer ceramic capacitor 101 includes n first internal electrode layers 121-1 to 121-n and n second internal electrode layers 122-1 to 122-n. The number of second internal electrode layers 122 may be one less than the number of first internal electrode layers 121.

[0060] At least one layer of the first internal electrode layers 121-1 to 121-n has a first thin layer portion 121b. In the example shown in Fig. 4, the first internal electrode layers 121-2, 121-n each have a first thin layer portion 121b. In the embodiment shown in Fig. 4, the first thin layer portions 121b are provided in the even-numbered internal electrode layers (first internal electrode layers 121-2, 121-4, ...) counting from the bottom of the first internal electrode layers 121, and the first thin layer portions 121b are not provided in the odd-numbered internal electrode layers (first internal electrode layers 121-1, 121-3, ...) counting from the bottom. Some of the first internal electrode layers 121-1 to 121-n may not be provided with the first thin layer portions 121b. 4 is merely an example, and the first internal electrode layers 121 provided with the first thin layer portions 121b and the first internal electrode layers 121 not provided with the first thin layer portions 121b may be arranged in various ways. For example, the base 10 may include two, three, four, or more times the number of first internal electrode layers 121 provided with the first thin layer portions 121b as the number of first internal electrode layers 121 not provided with the first thin layer portions 121b. The stacking order of the first internal electrode layers 121 provided with the first thin layer portions 121b and the first internal electrode layers 121 not provided with the first thin layer portions 121b may be random. The stacking order of the first internal electrode layers 121 provided with the first thin layer portions 121b and the first internal electrode layers 121 not provided with the first thin layer portions 121b may be periodic.

[0061] The first thin layer portion 121b of the first internal electrode layer 121 is provided in a region facing, in the L-axis direction, an end portion 122a of the second internal electrode layer 122 adjacent to the first internal electrode layer 121 from below. For example, the second internal electrode layer 122-1 is adjacent to the first internal electrode layer 121-1 from below, and the first thin layer portion 121b of the first internal electrode layer 121-1 is provided in a region facing the end portion 122a of the second internal electrode layer 122-1.

[0062] The first thin layer portion 121b of the first internal electrode layer 121 will be further described with reference to FIG. 5 , taking the first thin layer portion 121b provided in the first internal electrode layer 121-2 as an example. The first internal electrode layer 121-2 extends from the first external electrode 31 in the L1 direction. The first internal electrode layer 121-2 bends upward (in the positive direction of the T axis) from below in the T axis direction at a first bend B1 located at a position overlapping or close to the position in the L axis direction of the end portion 122a of the adjacent second internal electrode layer 122-1, and bends in a direction parallel to the L axis at a first bend B2 located at a position shifted in the L1 direction from the first bend B1. The position of the first bend B2 in the L axis direction also overlaps or close to the position in the L axis direction of the end portion 122a of the second internal electrode layer 122-1. In the section from the first bent portion B2 to the end portion 121a, the first internal electrode layer 121-2 extends along the L-axis. The region extending along an extension direction inclined with respect to the L-axis direction between the first bent portion B1 and the first bent portion B2 of the first internal electrode layer 121-2 is the first thin layer portion 121b. The first thin layer portion 121b is configured so that a thickness dimension T21 indicating the dimension in a direction perpendicular to the extension direction of the first thin layer portion 121b is smaller than a first average thickness T31 indicating the average thickness dimension of the first internal electrode layer 121-2.

[0063] In one aspect, the main body 10 is configured so that the distance T41 between the first thin layer portion 121b of the first internal electrode layer 121-2 and the end portion 122a of the second internal electrode layer 122-1 is narrower than the distance T51 between a portion other than the first thin layer portion 121b of the first internal electrode layer 121-2 and a portion other than the end portion 122a of the second internal electrode layer 122-1.

[0064] The degree of bending at the first bend portions B1, B2 is determined so that the ratio (T31 / D1) of the thickness dimension T31 in the T-axis direction of the first internal electrode layer 121-2 to the distance D1 between the first bend portions B1, B2 in the T-axis direction is in the range of 0.5 to 4.0. The greater the degree of bending of the first internal electrode layer 121-2 at the first bend portions B1, B2, the thinner the thickness dimension T21 of the first thin layer portion 121b. Therefore, if the degree of bending of the first internal electrode layer 121-2 becomes too large, the first internal electrode layer 121-2 becomes more likely to break near the first bend portions B1, B2. On the other hand, if the degree of bending of the first internal electrode layer 121-2 is too small, the difference between the thickness dimension T21 of the first thin layer portion 121b and the thickness dimensions of other parts of the first internal electrode layer 121-2 becomes small, and the first thin layer portion 121b cannot function as a fuse. By setting the ratio (T31 / D1) of the thickness dimension T31 in the T-axis direction of the first internal electrode layer 121-2 to the distance D1 between the first bend portions B1 and B2 in the T-axis direction to be in the range of 0.5 to 4.0, the first thin layer portion 121b can function as a fuse and fracture of the first internal electrode layer 121-2 can be prevented.

[0065] At least one layer of the second internal electrode layers 122-1 to 122-n has a second thin layer portion 122b. In the example shown in Fig. 4, the second internal electrode layers 122-1, 122-(n-1) each have a second thin layer portion 122b. In the embodiment shown in Fig. 4, the second thin layer portions 122b are provided in the odd-numbered internal electrode layers (second internal electrode layers 122-1, 122-3, ...) counting from the bottom among the second internal electrode layers 122, and the second thin layer portions 122b are not provided in the even-numbered internal electrode layers (second internal electrode layers 122-2, 122-4, ...) counting from the bottom. Some of the second internal electrode layers 122-1 to 122-n may not be provided with the second thin layer portions 122b. The embodiment shown in FIG. 4 is merely an example, and the second internal electrode layers 122 provided with the second thin layer portions 122b and the second internal electrode layers 122 not provided with the second thin layer portions 122b can be arranged in various ways. For example, the base 10 may have two, three, four, or more times the number of second internal electrode layers 122 provided with the second thin layer portions 122b as the number of second internal electrode layers 122 not provided with the second thin layer portions 122b. The stacking order of the second internal electrode layers 122 provided with the second thin layer portions 122b and the second internal electrode layers 122 not provided with the second thin layer portions 122b may be random. The stacking order of the second internal electrode layers 122 provided with the second thin layer portions 122b and the second internal electrode layers 122 not provided with the second thin layer portions 122b may be periodic. When the stacking order is periodic, productivity can be improved compared to when the stacking order is random.

[0066] The second thin layer portion 122b of the second internal electrode layer 122 is provided in a region facing, in the L-axis direction, the end portion 121a of the first internal electrode layer 121 adjacent to the second internal electrode layer 122 from below. For example, the first internal electrode layer 121-1 is adjacent to the second internal electrode layer 122-1 from below, and the second thin layer portion 122b of the second internal electrode layer 122-1 is provided in a region facing the end portion 121a of the first internal electrode layer 121-1.

[0067] The second internal electrode layer 122 provided with the second thin layer portion 122b will be described using the second internal electrode layer 122-1 as an example. The second internal electrode layer 122-1 has a shape obtained by inverting the first internal electrode layer 121-2 in the left-right direction (L-axis direction). Specifically, the second internal electrode layer 122-1 extends from the first external electrode 31 in the L1 direction. The second internal electrode layer 122-1 bends upward (in the positive direction of the T-axis) from below in the T-axis direction at a bend located at a position overlapping or close to the position in the L-axis direction of the end 121a of the adjacent first internal electrode layer 121-1, and bends in a direction parallel to the L-axis at another bend located at a position shifted from this bend in the L2 direction. The region extending along an extension direction inclined with respect to the L-axis direction between the two bends of the second internal electrode layer 122-1 is the second thin layer portion 122b. The second thin layer portion 122b is configured so that the thickness dimension, which indicates the dimension in a direction perpendicular to the extension direction of the second thin layer portion 122b, is smaller than a second average thickness, which indicates the average thickness dimension of the second internal electrode layer 122-2.

[0068] In one aspect, the main body 10 is configured so that the distance between the second thin layer portion 122b of the second internal electrode layer 122-1 and the end portion 121a of the first internal electrode layer 121-1 is narrower than the distance between a portion other than the second thin layer portion 122 of the second internal electrode layer 122-1 and a portion other than the end portion 121a of the first internal electrode layer 121-1.

[0069] The reverse pattern layer 116a is provided on the upper surface of the dielectric layer 11 on which the first internal electrode layer 121-2 is provided, so as to cover the area not covered by the first internal electrode layer 121-2. In one aspect, the thickness dimension in the T-axis direction of each reverse pattern layer 116a is equal to the sum of the thickness dimension of the first internal electrode layer 121-1 and the thickness dimension of the first internal electrode layer 121-2. This allows the upper surface of the reverse pattern layer 116a to be flush with the upper surface of the first internal electrode layer 121-2. The reverse pattern layer 116c is provided on the dielectric layer 11 on which the first internal electrode layer 121-n is provided. The reverse pattern layer 116c has the same configuration and arrangement as the reverse pattern layer 116a.

[0070] The reverse pattern layer 116b is provided on the upper surface of the dielectric layer 11 on which the second internal electrode layer 122-2 is provided, so as to cover the area not covered by the second internal electrode layer 122-2. In one aspect, the thickness dimension in the T-axis direction of each reverse pattern layer 116b is equal to the sum of the thickness dimension of the second internal electrode layer 122-1 and the thickness dimension of the second internal electrode layer 122-2. This allows the upper surface of the reverse pattern layer 116b to be flush with the upper surface of the second internal electrode layer 122-2. The reverse pattern layer 116d is provided on the dielectric layer 11 on which the second internal electrode layer 122-n is provided. The reverse pattern layer 116d has the same configuration and arrangement as the reverse pattern layer 116b.

[0071] In the multilayer ceramic capacitor 101 shown in Figure 4, reverse pattern layers 116 are provided on some of all of the dielectric layers 11 on which internal electrode layers are provided. In contrast, in the multilayer ceramic capacitor 1, reverse pattern layers 16 are provided on all of the upper surfaces of all of the dielectric layers 11 on which internal electrode layers are provided. Therefore, in the manufacturing process of the multilayer ceramic capacitor 101, the frequency of the step of forming the reverse pattern layers can be reduced compared to the manufacturing process of the multilayer ceramic capacitor 1. Therefore, the multilayer ceramic capacitor 101 can be manufactured in a shorter time than the multilayer ceramic capacitor 1.

[0072] 5, in the multilayer ceramic capacitor 101, a distance T41 between the first thin layer portion 121b of the first internal electrode layer 121-2 and the end 122a of the second internal electrode layer 122-1 is narrower than a distance T51 between a portion of the first internal electrode layer 121-2 other than the first thin layer portion 121b and a portion of the second internal electrode layer 122-1 other than the end 122a. Furthermore, a stronger electric field is generated in the vicinity of the first bend portions B1 and B2 that define both ends of the first thin layer portion 121b in the L-axis direction in the first internal electrode layer 121-2 than in the vicinity of the flat portions of the first internal electrode 121-2 and the second internal electrode 122-1. Therefore, in the multilayer ceramic capacitor 101, breakdown between the first internal electrode layer 121-2 and the second internal electrode layer 122-1 is induced to occur in the vicinity of the first thin layer portion 121b. Therefore, a large current generated by a breakdown is likely to flow to the first thin layer portion 121b located near the location of the breakdown. Therefore, when a breakdown occurs, the large current generated by the breakdown burns out the first thin layer portion 121b located near the location of the breakdown, thereby preventing destruction across multiple layers of the multilayer ceramic capacitor 101 by the large current in areas other than the first thin layer portion 121b and the second thin layer portion 122b that function as fuses, such as areas near the centers of the WL surfaces of the first internal electrode 21 and the second internal electrode 22. This makes it possible to more reliably achieve fail-open in the multilayer ceramic capacitor 101.

[0073] 3. Multilayer Ceramic Capacitor 201 (Third Embodiment) Next, with reference to FIG. 6 , a multilayer ceramic capacitor 201 according to another embodiment of the present invention will be described. FIG. 6 is a cross-sectional view showing a cross section of the multilayer ceramic capacitor 201 cut along a plane parallel to the LT plane (i.e., a plane parallel to the first side surface 10e or the second side surface 10f). The multilayer ceramic capacitor 201 differs from the multilayer ceramic capacitor 101 in that it includes a first internal electrode layer 221 instead of the first internal electrode layer 121 and a second internal electrode layer 222 instead of the second internal electrode layer 122. The multilayer ceramic capacitor 201 also differs from the multilayer ceramic capacitor 101 in that it includes reverse pattern layers 216a to 216f instead of the reverse pattern layers 116a to 116d. Detailed descriptions of components of the multilayer ceramic capacitor 201 that are the same as or similar to the components of the multilayer ceramic capacitors 1 and 101 will be omitted.

[0074] At least one of the reverse pattern layers 216a to 216f is configured and arranged so that the position of its upper surface in the T-axis direction is offset from the position of the upper surface of the internal electrode layer provided on the same layer in the T-axis direction. In the example shown in FIG. 6, the reverse pattern layer 216a is configured and arranged so that the upper surface of the reverse pattern layer 216a is recessed relative to the upper surface of the first internal electrode layer 221-2. This arrangement is achieved, for example, by making the thickness of the reverse pattern layer 216a smaller than the sum of the thicknesses of the first internal electrode layer 221-1 and the first internal electrode layer 221-2. This forms a step between the upper surface of the pattern layer 216a and the upper surface of the first internal electrode layer 221-2. In another aspect, a step may be formed between the upper surface of the reverse pattern layer 216a and the upper surface of the first internal electrode layer 221-2 by making the thickness of the reverse pattern layer 216a larger than the sum of the thicknesses of the first internal electrode layer 221-2. The thickness of some of the reverse pattern layers included in the multilayer ceramic capacitor 201 may be different from the thickness of the other reverse pattern layers. For example, in the embodiment shown in Figure 6, the thickness of reverse pattern layer 216a is different from the thickness of reverse pattern layer 216b, and the thickness of reverse pattern layer 216f is different from the thickness of reverse pattern layer 216e.

[0075] The second internal electrode layer 222-2, which is provided on the upper surfaces of the reverse pattern layer 216a and the first internal electrode layer 221-2 via the dielectric layer 11, follows the step between the upper surface of the reverse pattern layer 216a and the upper surface of the first internal electrode layer 221-2 and bends at the position of the step in the L-axis direction. The bent portion of the second internal electrode layer 222-2 becomes the second thin layer portion 222b of the second internal electrode layer 222-2. Since the position of the step between the upper surface of the reverse pattern layer 216a and the upper surface of the first internal electrode layer 221-2 in the L-axis direction overlaps the position of the end 221a of the first internal electrode layer 221-2, the second thin layer portion 222b of the second internal electrode layer 222-2 is provided in a region facing the end 221a of the first internal electrode layer 221-2 in the L-axis direction.

[0076] 6, the reverse pattern layer 216d is configured and arranged so that the upper surface of the reverse pattern layer 216d is recessed relative to the upper surface of the second internal electrode layer 222-(n-2). The first internal electrode layer 221-(n-1), which is provided on the upper surfaces of the reverse pattern layer 216d and the second internal electrode layer 222-(n-2) via the dielectric layer 11, bends at the position of the step in the L-axis direction, following the step between the upper surface of the reverse pattern layer 216d and the upper surface of the second internal electrode layer 222-(n-2). The bent portion of the first internal electrode layer 221-(n-1) becomes the first thin layer portion 221b of the first internal electrode layer 221-(n-1). The position where there is a step between the upper surface of the reverse pattern layer 216d and the upper surface of the second internal electrode layer 222-(n-2) in the L-axis direction overlaps with the position of the end 222a of the second internal electrode layer 222-(n-2), so the first thin layer portion 221b of the first internal electrode layer 221-(n-1) is provided in an area facing the end 222a of the second internal electrode layer 222-(n-2) in the L-axis direction.

[0077] The multilayer ceramic capacitor 201 may include, in addition to the reverse pattern layer 216a and the reverse pattern layer 216d, a reverse pattern layer whose upper surface is offset from the upper surface of an internal electrode layer in the same layer.

[0078] In this way, in the multilayer ceramic capacitor 201, a step is provided between the upper surface of the reverse pattern layer 216a and the upper surface of the first internal electrode layer 221-2, so that the second internal electrode layer 222-2 can be provided with a second thin layer portion 222b in a region facing the end 221a of the first internal electrode layer 221-2 in the L-axis direction. Therefore, if a breakdown occurs near the end 221a of the first internal electrode layer 221-2, the large current generated by the breakdown is likely to flow to the second thin layer portion 222b of the second internal electrode layer 222-2, which is located near the position where the breakdown occurs. Similarly, a step is provided between the upper surface of the reverse pattern layer 216d and the upper surface of the second internal electrode layer 222-(n-2), so that the first thin layer portion 221b can be provided in the first internal electrode layer 221-(n-1) in a region facing the end 222a of the second internal electrode layer 222-(n-2) in the L-axis direction. Therefore, when a breakdown occurs near the end 222a of the second internal electrode layer 222-(n-2), the large current generated by the breakdown is likely to flow to the first thin layer portion 221b of the first internal electrode layer 221-(n-1), which is located near the location where the breakdown occurs.

[0079] In this way, in the multilayer ceramic capacitor 201, by forming a step between any of the reverse pattern layers and the upper surface of the corresponding internal electrode layer, a bent portion that becomes the first thin layer portion or the second thin layer portion can be formed in the adjacent internal electrode layer, and therefore it is possible to prevent destruction across multiple layers by a large current in areas other than the first thin layer portion 221b and the second thin layer portion 222b that should function as fuses, for example, areas near the centers of the WL surfaces of the first internal electrode 221 and the second internal electrode 222. This makes it possible to more reliably achieve fail-open in the multilayer ceramic capacitor 201 as well.

[0080] 6. Method for Manufacturing Multilayer Ceramic Capacitor Next, an overview of a method for manufacturing a multilayer ceramic capacitor 1 according to one embodiment of the present invention will be described with reference to Fig. 7 to Fig. 14. Fig. 7 is a flow diagram showing the flow of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present invention, and Figs. 8 to 14 are schematic diagrams showing the manufacturing process of a multilayer ceramic capacitor.

[0081] (Step S01: Preparation of Dielectric Green Sheets) In step S01, a plurality of dielectric green sheets 51a are prepared. The dielectric green sheets 51a are unsintered dielectric green sheets whose main component is a dielectric ceramic, and serve as precursors for the dielectric layers 11. The dielectric green sheets 51a can be obtained, for example, as follows. First, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to a dielectric powder and wet-mixed to obtain a slurry. Next, this slurry is applied to a substrate film by, for example, a die coater method or a doctor blade method. The slurry applied to the substrate film is then dried to obtain a dielectric green sheet. The dielectric powder, which is the raw material powder for the dielectric green sheets, is, for example, barium titanate (BaTiO3) powder. Barium titanate powder is synthesized by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate using a known method such as a solid-phase method, a sol-gel method, or a hydrothermal method. The thickness of the dielectric green sheet 51a can be adjusted as appropriate.

[0082] (Step S02: Formation of Sheet Units) Next, in step S02, internal electrode patterns, which are precursors of the internal electrode layers, are formed on the dielectric green sheet 51a prepared in step S01, thereby obtaining the first sheet unit U1 and the second sheet unit U2 shown in FIG. 8. For example, the first sheet unit U1 shown in FIG. 8 is obtained by forming an internal electrode pattern 60a and a dielectric pattern 71a on the dielectric green sheet 50a. The dielectric pattern 71a is a precursor of the reverse pattern layer 16. Since the multilayer ceramic capacitor 1, which is the finished product, includes first internal electrode layers 21-1 to 21-n, a plurality of dielectric green sheets 51a, on which internal electrode patterns 60a corresponding to each of these first internal electrode layers 21-1 to 21-n are formed, are prepared as the first sheet unit U1.

[0083] In step S02, the second sheet unit U2 shown in Fig. 8 is obtained by forming the internal electrode patterns 80a and the dielectric patterns 71a on a plurality of dielectric green sheets 51a other than the dielectric green sheet 51a on which the internal electrode pattern 60a is formed. The internal electrode pattern 80a is a precursor of the second internal electrode layer 22. Since the multilayer ceramic capacitor 1, which is the finished product, includes the second internal electrode layers 22-1 to 22-n, a plurality of dielectric green sheets 51a on which the internal electrode patterns 80a corresponding to the respective internal electrode layers 22-1 to 22-n are formed are prepared as the second sheet unit U2.

[0084] Some of the dielectric green sheets 51a do not have internal electrode patterns formed thereon, and the dielectric green sheets 51a on which no internal electrode patterns are formed are referred to as cover sheet units U3.

[0085] 11, cutting lines X1 and X2 are shown on the first sheet unit U1, the second sheet unit U2, and the cover sheet unit U3, respectively, to indicate the cutting positions for singulation. The cutting line X1 extends in a direction parallel to the W axis, and the cutting line X2 extends in a direction parallel to the L axis.

[0086] In step S02, the internal electrode patterns 60a, 80a are formed by using a printing method such as screen printing or a vacuum film formation method such as sputtering. The manufacturing process of the first sheet unit U1 will be further described with reference to Figures 10a to 10d and 11a to 11d. For simplicity of illustration, Figures 10a to 10d and 11a to 11d show only a region UA1 of the first sheet unit U1 that corresponds to a single chip and is surrounded by cutting lines X1 and X2.

[0087] The internal electrode pattern 60a is a laminate of a first internal electrode pattern 61a in a lower layer and a second internal electrode pattern 61b in an upper layer. To form the internal electrode pattern 60a, first, the first internal electrode pattern 61a is formed in a partial region of the upper surface of the dielectric green sheet 51a shown in Figures 10a and 11a, as shown in Figures 10b and 11b. The first internal electrode pattern 61a is formed, for example, by printing an internal electrode paste on the dielectric green sheet 51a by a known printing method such as screen printing. To form the first internal electrode pattern 61a, a mask having openings corresponding to the first internal electrode pattern 61a is used.

[0088] Next, as shown in FIGS. 10c and 11c, a second internal electrode pattern 61b is formed in a partial region of the upper surface of the first internal electrode pattern 61a. The second internal electrode pattern 61b has a recess 61c. The second internal electrode pattern 61b has the same shape as the first internal electrode pattern 61a except for the recess 61c. The recess 61c has a groove shape extending along the W-axis direction. The recess 61c extends in the L-axis direction from the cutting line X1 within a distance range of L12 to L13. Like the first internal electrode pattern 61a, the second internal electrode pattern 61b is also formed by printing an internal electrode paste by a known printing method such as screen printing. To form the second internal electrode pattern 61b, a mask having openings corresponding to the second internal electrode pattern 61b is used.

[0089] The internal electrode paste is manufactured by kneading metal powder, binder resin, and solvent using a three-roll mill. That is, the internal electrode paste is obtained by dispersing metal powder in binder resin. The metal powder contained in the internal electrode paste includes powder of base metals such as Ni, Cu, and Sn, which are the main components of the first internal electrode layers 21 and the second internal electrode layers 22. As the organic binder for the internal electrode paste, a cellulose-based resin such as ethyl cellulose or an acrylic-based resin such as butyl methacrylate can be used. The first internal electrode pattern 61a and the second internal electrode pattern 61b may be formed by a sputtering method. The method for forming the first internal electrode pattern 61a and the second internal electrode pattern 61b is not limited to the method specifically described in this specification. The internal electrode patterns may be formed by various known methods, for example, vacuum deposition, PLD (pulsed laser deposition), MO-CVD (metal-organic chemical vapor deposition), MOD (metal-organic decomposition), or CSD (chemical solution deposition).

[0090] Next, as shown in FIGS. 10d and 11d, a dielectric pattern 71a is formed on the upper surface of the dielectric green sheet 51a in areas where the internal electrode pattern 60a is not formed and in the recesses 61c of the second internal electrode pattern 61b, thereby obtaining a first sheet unit U1. The dielectric pattern 71a is formed, for example, by printing a dielectric pattern paste on the dielectric green sheet 51a using a known printing method such as screen printing. The dielectric pattern paste is obtained by wet-mixing a mixture of a dielectric powder and an Fe-containing powder with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. The Fe-containing powder is, for example, ferric oxide (FeO) powder. The mixture may be produced, for example, by mixing 100 mol of BaTiO powder with 0.6 mol to 1.8 mol of FeO powder. The mixed powder may contain at least one of magnesium oxide (MgO) powder and manganese dioxide (MnO2) powder.

[0091] 12a to 12d and 13a to 13d, the manufacturing process of the second sheet unit U2 will be further described. For simplicity of illustration, only an area UA2 of the second sheet unit U2, which corresponds to a single chip and is surrounded by cutting lines X1 and X2, is shown in FIGS.

[0092] The internal electrode pattern 80a is a laminate of a first internal electrode pattern 81a in a lower layer and a second internal electrode pattern 81b in an upper layer. To form the internal electrode pattern 80a, first, the first internal electrode pattern 81a is formed in a partial region of the upper surface of the dielectric green sheet 51a shown in Figures 12a and 13a, as shown in Figures 12b and 13b. The first internal electrode pattern 81a is formed so that one end in the L-axis direction overlaps with the cutting line X1, while the other end in the L-axis direction is spaced apart from the cutting line X1 by a distance L11, and both ends in the W-axis direction are spaced apart from the cutting line X2.

[0093] Next, as shown in Figures 12c and 13c, a second internal electrode pattern 81b is formed in a partial region of the upper surface of the first internal electrode pattern 81a. The second internal electrode pattern 81b has a recess 81c. The second internal electrode pattern 81b has the same shape as the first internal electrode pattern 81a except for the formation of the recess 81c. The recess 81c has a groove shape extending along the W-axis direction. The recess 81c extends in the L-axis direction within a distance range of L12 to L13 from the cutting line X1.

[0094] A distance L12 between one end of the recess 61c in the L-axis direction and the cutting line X1 and a distance L13 between the other end of the recess 61c in the L-axis direction and the cutting line X1 satisfy a relationship of L12<L11<L13 with respect to a distance L11 between the internal electrode pattern 80a and the cutting line X1. Furthermore, a distance L12 between one end of the recess 81c in the L-axis direction and the cutting line X1 and a distance L13 between the other end of the recess 81c in the L-axis direction and the cutting line X1 satisfy a relationship of L12<L11<L13 with respect to the distance L11 between the internal electrode pattern 60a and the cutting line X1.

[0095] The first internal electrode pattern 81a and the second internal electrode pattern 81b are formed by, for example, a printing method or a sputtering method, similarly to the first internal electrode pattern 61a and the second internal electrode pattern 61b.

[0096] Next, as shown in Figures 12d and 13d, a dielectric pattern 71a is formed on the upper surface of the dielectric green sheet 51a in areas where the internal electrode pattern 80a is not formed and in the recesses 81c of the second internal electrode pattern 81b, thereby obtaining a second sheet unit U2.

[0097] The first sheet unit U1 and the second sheet unit U2 are produced in the above manner. The first sheet unit U1 has a dielectric green sheet 51a, an internal electrode pattern 60a formed on a portion of the upper surface of the dielectric green sheet 51a, and a dielectric pattern 71a formed in an area of ​​the upper surface of the dielectric green sheet 51a not covered by the internal electrode pattern 60a and in the recesses 61c of the second internal electrode pattern 61b. The second sheet unit U2 has a dielectric green sheet 51a, an internal electrode pattern 80a formed on a portion of the upper surface of the dielectric green sheet 51a, and a dielectric pattern 71a formed in an area of ​​the upper surface of the dielectric green sheet 51a not covered by the internal electrode pattern 80a and in the recesses 81c of the second internal electrode pattern 81b.

[0098] (Step S03: Stacking) In step S03, as shown in FIG. 9 , the first sheet units U1 and second sheet units U2 obtained in step S02 are stacked in a predetermined order, and multiple cover sheet units U3 are stacked on the upper and lower surfaces of the alternating first sheet units U1 and second sheet units U2 in the T-axis direction to obtain a laminate. This laminate is then pressed in the T-axis direction to obtain a laminated sheet unit U10 in which the first sheet units U1, second sheet units U2, and cover sheet units U3 are stacked. The first sheet units U1 and second sheet units U2 are stacked such that the recess 61c on the first sheet unit U1 faces the end of the internal electrode pattern 80a on the second sheet unit U2, and the recess 81c on the second sheet unit U2 faces the end of the internal electrode pattern 60a on the first sheet unit U1.

[0099] (Step S04: Cutting) In step S04, the laminated sheet unit U10 obtained in step S03 is cut along cutting lines X1 and X2 shown in Fig. 13 to produce the unsintered chip laminate 90 shown in Fig. 14. For example, a press cutter blade or a rotary blade can be used to cut the laminated sheet unit U10.

[0100] (Step S05: Firing) In step S05, the chip stack 90 obtained in step S04 is fired to produce the main body 10 of the multilayer ceramic capacitor 1. That is, in step S05, the chip stack 90 is fired to form the main body 10. Through this firing process, the internal electrode pattern 60a becomes the first internal electrode layer 21, and the internal electrode pattern 80a becomes the second internal electrode layer 22. Furthermore, through the firing process, the dielectric pattern 71a becomes the reverse pattern layers 16 and 17. The firing temperature in step S05 can be determined based on the sintering temperature of the ceramic material constituting the dielectric layer 11. For example, when a barium titanate (BaTiO3)-based material is used as the material for the dielectric layer 11, the firing temperature can be approximately 1000 to 1300°C. Furthermore, firing can be performed, for example, in a reducing atmosphere or a low-oxygen partial pressure atmosphere.

[0101] (Step S06: Forming External Electrodes) In step S06, a first external electrode 31 is formed at one end in the L-axis direction of the main body obtained in step S05, and a second external electrode 32 is formed at the other end. The first external electrode 31 is provided on the surface of the main body 10 so as to be electrically connected to the first internal electrode layer 21. The second external electrode 32 is provided on the surface of the main body 10 so as to be electrically connected to the second internal electrode layer 22. In this manner, the multilayer ceramic capacitor 1 is obtained.

[0102] The multilayer ceramic capacitor 101 can also be fabricated in the same manner as the multilayer ceramic capacitor 1. However, the multilayer ceramic capacitor 101 differs from the multilayer ceramic capacitor 1 in the configuration and arrangement of the internal electrode layers and reverse pattern layers. For this reason, the multilayer ceramic capacitor 101 is fabricated using sheet units different from the first sheet unit U1 and second sheet unit U2 used in fabricating the multilayer ceramic capacitor 1. The sheet units used in fabricating the multilayer ceramic capacitor 101 will be described with reference to FIG. 15 .

[0103] The body 10 of the multilayer ceramic capacitor 101 is fabricated by firing a chip stack 190 shown in FIG. 15. As shown in FIG. 15, the multilayer ceramic capacitor 101 is constructed by stacking a first sheet unit U11, a second sheet unit U12, a third sheet unit U13, and a fourth sheet unit U14 in addition to cover sheet units U3 arranged at the upper and lower ends. While FIG. 15 illustrates one each of the first sheet unit U11, the second sheet unit U12, the third sheet unit U13, and the fourth sheet unit U14, the chip stack 190 is constructed by stacking multiple stacking units, each of which is constructed by stacking the first sheet unit U11, the second sheet unit U12, the third sheet unit U13, and the fourth sheet unit U14. Therefore, the chip stack 190 includes multiple stacking units each composed of the first sheet unit U11, the second sheet unit U12, the third sheet unit U13, and the fourth sheet unit U14.

[0104] The first sheet unit U11 has a dielectric green sheet 51a and an internal electrode pattern 160a. The first sheet unit U11 is obtained by forming the internal electrode pattern 160a in a partial region of the upper surface of the dielectric green sheet 51a by a printing method or a sputtering method. The first sheet unit U11 can be produced in the same manner as the first sheet unit U1, except that it does not have the dielectric pattern 71a. The internal electrode pattern 160a may have the same shape as the first internal electrode pattern 61a located in the lower layer of the internal electrode pattern 60a.

[0105] The second sheet unit U12 has a dielectric green sheet 51a and an internal electrode pattern 180a. The second sheet unit U12 is obtained by forming the internal electrode pattern 180a on a partial area of ​​the upper surface of the dielectric green sheet 51a by a printing method or a sputtering method. The second sheet unit U12 has a shape obtained by flipping the first sheet unit U11 left and right.

[0106] The third sheet unit U13 has a dielectric green sheet 51a, an internal electrode pattern 160b, and a dielectric pattern 171a. The internal electrode pattern 160b can have the same shape as the internal electrode pattern 160a. When the chip stack 190 is viewed from above through the dielectric green sheet 51a, the internal electrode pattern 160b is positioned so as to overlap the internal electrode pattern 160a. The area of ​​the dielectric green sheet 51a not covered by the internal electrode pattern 160b is covered by the dielectric pattern 171a. The dielectric pattern 171a is formed to be thicker than the internal electrode pattern 160b. The thickness of the dielectric pattern 171a may be equal to or thinner than the sum of the thicknesses of the internal electrode patterns 160a and 160b. The thickness of the dielectric pattern 171a may vary from sheet to sheet.

[0107] The fourth sheet unit U14 has a dielectric green sheet 51a, an internal electrode pattern 180b, and a dielectric pattern 171b. The internal electrode pattern 180b can have the same shape as the internal electrode pattern 180a. When the chip stack 190 is viewed from above through the dielectric green sheet 51a, the internal electrode pattern 180b is positioned so as to overlap the internal electrode pattern 180a. The area of ​​the dielectric green sheet 51a not covered by the internal electrode pattern 180b is covered by the dielectric pattern 171b. The dielectric pattern 171b is formed to be thicker than the internal electrode pattern 180b. The thickness of the dielectric pattern 171b may be equal to or thinner than the sum of the thicknesses of the internal electrode patterns 180a and 180b. The thickness of the dielectric pattern 171a may vary from sheet to sheet.

[0108] The dielectric green sheet 51a is a precursor of the dielectric layer 11, the internal electrode patterns 160a and 160b are precursors of the first internal electrode layer 121, and the internal electrode patterns 180a and 180b are precursors of the second internal electrode layer 122. Furthermore, the dielectric pattern 171a is a precursor of the reverse pattern layers 116a and 116c, and the dielectric pattern 171b is a precursor of the reverse pattern layers 116b and 116d.

[0109] The first sheet unit U11, second sheet unit U12, third sheet unit U13, and fourth sheet unit U14 configured as described above are stacked in this order along the T axis to produce a laminate, and this laminate is then pressed in the T axis direction to obtain a laminated sheet unit in which the first sheet unit U11, second sheet unit U12, third sheet unit U13, and fourth sheet unit U14 are stacked.

[0110] The first sheet unit U11 has a step between an area where the internal electrode pattern 160a is formed and an area where it is not formed. Therefore, when the laminate is pressed in the T-axis direction, the internal electrode pattern 180a of the second sheet unit U12 laminated on the first sheet unit U11 is bent at a position corresponding to the step of the first sheet unit U11. The bent portion formed in this internal electrode pattern 180a becomes the second thin layer portion 122b of the second internal electrode layer 122 in the multilayer ceramic capacitor 101, which is the finished product.

[0111] The second sheet unit U12 has a step between an area where the internal electrode pattern 180a is formed and an area where it is not formed. Therefore, when the laminate is pressed in the T-axis direction, the internal electrode pattern 180b of the third sheet unit U13 laminated on the second sheet unit U12 is bent at a position corresponding to the step of the second sheet unit U12. The bent portion formed in this internal electrode pattern 180b becomes the first thin layer portion 121b of the first internal electrode layer 121 in the multilayer ceramic capacitor 101, which is the finished product.

[0112] The laminate obtained by stacking the first sheet unit U11, the second sheet unit U12, the third sheet unit U13, and the fourth sheet unit U14 thus produced is cut into chip units to obtain the chip laminate 190. The chip laminate 190 is fired to produce the main body 10, and the first external electrode 31 and the second external electrode 32 are formed on the surface of the main body 10 to obtain the multilayer ceramic capacitor 101.

[0113] The multilayer ceramic capacitor 201 is fabricated in the same manner as the multilayer ceramic capacitor 101. When manufacturing the multilayer ceramic capacitor 201, appropriate changes are made to the first sheet unit U11, the second sheet unit U12, the third sheet unit U13, and the fourth sheet unit U14. Specifically, by making the thickness of the dielectric pattern 171a different from the sum of the thicknesses of the internal electrode patterns 160a and 160b, the step of the first sheet unit U11 is not absorbed by the thickness of the dielectric pattern 171a, and a bent portion due to the step of the first sheet unit U11 is also formed in the internal electrode patterns provided in the sheet units stacked above the fourth sheet unit U14. Similarly, by making the thickness of the dielectric pattern 171b different from the sum of the thicknesses of the internal electrode patterns 180a and 180b, the step of the second sheet unit U12 is not absorbed by the thickness of the dielectric pattern 171b, and a bent portion due to the step of the second sheet unit U12 is also formed in the internal electrode patterns provided in the sheet units stacked above the fourth sheet unit U14. The bent portion formed in the internal electrode patterns provided in the sheet units stacked above the fourth sheet unit U14 becomes, for example, the second thin layer portion 222b of the second internal electrode layer 222-2 or the first thin layer portion 221b of the first internal electrode layer 221-(n-1) in the multilayer ceramic capacitor 201, which is the finished product.

[0114] 7 may be performed to manufacture the multilayer ceramic capacitors 1, 101, and 201. For example, the multilayer ceramic capacitor 1 produced in step S06 may be subjected to a reoxidation treatment at 600°C to 1000°C in an N2 gas atmosphere. Furthermore, a plating layer of Cu, Ni, Sn, or the like may be provided on the surfaces of the first external electrode 31 and the second external electrode 32. This plating layer may be formed by electrolytic plating or electroless plating.

[0115] 7. Note The dimensions, materials, and arrangements of the components described in the various embodiments above are not limited to those explicitly described in each embodiment, and each component can be modified to have any dimensions, materials, and arrangements that fall within the scope of the present invention.

[0116] Components not explicitly described in this specification may be added to each of the above-described embodiments, and some of the components described in each embodiment may be omitted.

[0117] The terms "first," "second," "third," and the like used in this specification are used to identify components and do not necessarily limit the number, order, or content of the components. Furthermore, numbers used to identify components are used in different contexts, and a number used in one context does not necessarily indicate the same configuration in another context. Furthermore, this does not prevent a component identified by a certain number from also serving the function of a component identified by another number.

[0118] In this specification, when a certain component is referred to as "comprising" another component, it does not mean that other components are excluded, but that other components may be further included, unless it is inconsistent with the content of the present invention.

[0119] For example, the main body 10 may be configured such that the first end face 10c and the second end face 10d are parallel to two legs of a trapezoid that defines the outer edge of the capacitance generating region Ra in the LT plane, as shown in Fig. 8, and the first side face 10e and the second side face 10f are parallel to two legs of a trapezoid that defines the outer edge of the capacitance generating region Ra in the WT plane, as shown in Fig. 9.

[0120] 8. Supplementary Notes The embodiments disclosed in this specification also include the following. [Supplementary Note 1] A main body (10) having a plurality of dielectric layers (11) and a plurality of internal electrode layers (21, 22) stacked in a first direction (T) via at least one layer of the plurality of dielectric layers, and having a first surface (10c) and a second surface (10d) facing each other in a second direction (L) perpendicular to the first direction; a first external electrode (31) provided on the first surface of the main body so as to be electrically connected to each of a plurality of first internal electrode layers (21) of the plurality of internal electrode layers; and a second external electrode (32) provided on the second surface of the main body so as to be electrically connected to each of a plurality of second internal electrode layers (22) of the plurality of internal electrode layers, wherein one first internal electrode layer (21-1) of the plurality of first internal electrode layers is disposed adjacent to one second internal electrode layer (22-1) of the plurality of second internal electrode layers in the first direction, A multilayer ceramic capacitor, wherein the one first internal electrode layer has a first thin layer portion (21b) in a first end region corresponding to an end (22a) of the one second internal electrode layer in the second direction, and a first thickness (T11) representing a dimension of the first thin layer portion in the first direction is smaller than a first average thickness representing an average dimension of the one first internal electrode layer in the first direction. [Appendix 2] The multilayer ceramic capacitor according to [Appendix 1], wherein the first thickness is in a range of 10 to 90% of the first average thickness. [Appendix 3] The multilayer ceramic capacitor according to [Appendix 1] or [Appendix 2], wherein the first thin layer portion is provided at a position spaced apart from the first surface in the second direction. [Supplementary Note 4] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 3], wherein the one first internal electrode layer has a first electrode layer surface (21c) and a second electrode layer surface (21d) facing each other in the first direction, and the first electrode layer surface is recessed in the first thin layer portion. [Supplementary Note 5] The multilayer ceramic capacitor according to any one of [Supplementary Note 1] to [Supplementary Note 4], wherein the one first internal electrode layer has two first bent portions (B1, B2), and the first thin layer portion extends between the two first bent portions.[Appendix 6] The multilayer ceramic capacitor according to [Appendix 5], wherein a ratio (T31 / D1) of the first average thickness dimension (T31) of the one first internal electrode layer to the distance (D1) between the two first bend portions in the first direction is in the range of 0.5 to 4.0. [Appendix 7] The multilayer ceramic capacitor according to any one of [Appendix 1] to [Appendix 6], wherein the one second internal electrode layer has a second thin layer portion (22b) in a second end region facing an end portion (21a) of the one first internal electrode layer in the second direction, and a second thickness representing the dimension of the second thin layer portion in the first direction is smaller than a second average thickness representing the average dimension of the one second internal electrode layer in the first direction. [Appendix 8] The multilayer ceramic capacitor according to [Appendix 7], wherein the second thickness is in the range of 10 to 90% of the second average thickness. [Appendix 9] The multilayer ceramic capacitor according to [Appendix 7] or [Appendix 8], wherein the second thin layer portion is provided at a position spaced apart from the second surface in the second direction. [Appendix 10] The multilayer ceramic capacitor according to any one of [Appendix 7] to [Appendix 9], wherein the one second internal electrode layer has a third electrode layer surface and a fourth electrode layer surface facing each other in the first direction, and the third electrode layer surface is recessed in the second thin layer portion. [Appendix 11] The multilayer ceramic capacitor according to any one of [Appendix 7] to [Appendix 10], wherein the one second internal electrode layer has two second bent portions, and the second thin layer portion extends between the two second bent portions. [Appendix 12] The multilayer ceramic capacitor according to any one of [Appendix 7] to [Appendix 11], wherein the plurality of first internal electrode layers further include another first internal electrode layer (21-2) adjacent to the one second internal electrode layer, the other first internal electrode layer has a third thin layer portion (21b) in the first end region in the second direction, and a third thickness representing a dimension of the third thin layer portion in the first direction is smaller than a third average thickness representing an average dimension of the other first internal electrode layers in the first direction.[Supplementary Note 13] The multilayer ceramic capacitor according to [Supplementary Note 12], wherein the other first internal electrode layer has two third bend portions, and the third thin layer portion extends in the second direction between the two third bend portions. [Supplementary Note 14] The multilayer ceramic capacitor according to [Supplementary Note 12], comprising the steps of: preparing a first sheet unit (U11) having a first internal electrode pattern (160a) formed in a first region on an upper surface of a first dielectric green sheet (51a); preparing a second sheet unit (U12) having a second internal electrode pattern (180a) formed in a second region on an upper surface of a second dielectric green sheet; and preparing a third sheet unit (U13) having a third internal electrode pattern (160b) formed in a third region which is a part of an upper surface of a third dielectric green sheet and has the same shape as the first region in a plan view, and a first dielectric pattern (171a) having the same thickness as the sum of a thickness of the first internal electrode pattern and a thickness of the third internal electrode pattern formed in a region other than the third region on the upper surface of the third dielectric green sheet; A method for manufacturing a multilayer ceramic capacitor, comprising: a step of preparing a fourth sheet unit (U13) in which a fourth internal electrode pattern (180b) is formed in a fourth region, which is a part of an upper surface of a fourth dielectric green sheet and has the same shape as the second region in a plan view, and a second dielectric pattern (171b) is formed in a region of the upper surface of the fourth dielectric green sheet other than the fourth region; a step of stacking the first sheet unit, the second sheet unit, the third sheet unit, and the fourth sheet unit to form a laminate; and a firing step of firing the laminate.

[0121] 1, 10, 201 Multilayer ceramic capacitor 10 Main body 11 Dielectric layer 21, 121, 221 First internal electrode layer 21b, 121b, 221b First thin layer portion 22, 122, 222 Second internal electrode layer 22b, 122b, 222b Second thin layer portion 31 First external electrode 32 Second external electrode

Claims

1. A multilayer ceramic capacitor comprising: a body having a plurality of dielectric layers and a plurality of internal electrode layers stacked in a first direction via at least one of the plurality of dielectric layers, the body having a first surface and a second surface facing each other in a second direction perpendicular to the first direction; a first external electrode provided on the first surface of the body so as to electrically connect to each of a plurality of first internal electrode layers of the plurality of internal electrode layers; and a second external electrode provided on the second surface of the body so as to electrically connect to each of a plurality of second internal electrode layers of the plurality of internal electrode layers, wherein one first internal electrode layer of the plurality of first internal electrode layers is disposed adjacent to one second internal electrode layer of the plurality of second internal electrode layers in the first direction, the one first internal electrode layer having a first thin layer portion in a first end region facing an end of the one second internal electrode layer in the second direction, and a first thickness representing a dimension in the first direction of the first thin layer portion is smaller than a first average thickness representing an average dimension in the first direction of the one first internal electrode layer.

2. The multilayer ceramic capacitor according to claim 1, wherein the first thickness is in the range of 10 to 90% of the first average thickness.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the first thin layer portion is provided at a position spaced apart from the first surface in the second direction.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein the one first internal electrode layer has a first electrode layer surface and a second electrode layer surface that face each other in the first direction, and the first electrode layer surface is recessed in the first thin layer portion.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein the one first internal electrode layer has two first bent portions, and the first thin layer portion extends between the two first bent portions.

6. The multilayer ceramic capacitor according to claim 5, wherein the ratio of the first average thickness dimension of one first internal electrode layer to the distance between the two first bend portions in the first direction is in the range of 0.5 to 4.

0.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein the one second internal electrode layer has a second thin layer portion in a second end region facing an end of the one first internal electrode layer in the second direction, and a second thickness representing the dimension of the second thin layer portion in the first direction is smaller than a second average thickness representing the average dimension of the one second internal electrode layer in the first direction.

8. The multilayer ceramic capacitor according to claim 7, wherein the second thickness is in the range of 10 to 90% of the second average thickness.

9. The multilayer ceramic capacitor according to claim 7, wherein the second thin layer portion is provided at a position spaced apart from the second surface in the second direction.

10. The multilayer ceramic capacitor according to claim 7, wherein the one second internal electrode layer has a third electrode layer surface and a fourth electrode layer surface that face each other in the first direction, and the third electrode layer surface is recessed in the second thin layer portion.

11. The multilayer ceramic capacitor according to claim 7, wherein the one second internal electrode layer has two second bent portions, and the second thin layer portion extends between the two second bent portions.

12. The multilayer ceramic capacitor according to claim 7, wherein the plurality of first internal electrode layers further include another first internal electrode layer adjacent to the one second internal electrode layer, the other first internal electrode layer having a third thin layer portion in the first end region in the second direction, and a third thickness representing the dimension of the third thin layer portion in the first direction is smaller than a third average thickness representing the average of the dimensions of the other first internal electrode layers in the first direction.

13. The multilayer ceramic capacitor according to claim 11, wherein the other first internal electrode layer has two third bent portions, and the third thin layer portion extends between the two third bent portions in the second direction.

14. A method for manufacturing a multilayer ceramic capacitor, comprising: preparing a first sheet unit having a first internal electrode pattern formed in a first region on the upper surface of a first dielectric green sheet; preparing a second sheet unit having a second internal electrode pattern formed in a second region on the upper surface of a second dielectric green sheet; preparing a third sheet unit having a third internal electrode pattern formed in a third region that is a partial region on the upper surface of a third dielectric green sheet and has the same shape as the first region in a plan view, and a first dielectric pattern having a thickness equal to the sum of the thicknesses of the first and third internal electrode patterns, and the third internal electrode pattern, formed in a region on the upper surface of the third dielectric green sheet other than the third region; preparing a fourth sheet unit having a fourth internal electrode pattern formed in a fourth region that is a partial region on the upper surface of a fourth dielectric green sheet and has the same shape as the second region in a plan view, and a second dielectric pattern formed in a region on the upper surface of the fourth dielectric green sheet other than the fourth region; laminating the first, second, third, and fourth sheet units to form a laminate; and firing the laminate.

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