Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: providing a structure to be processed, said structure comprising a functional structure and a buffer structure located on the functional structure, and the functional structure comprising a first functional layer; performing planarization on said structure, the planarization causing the buffer structure to be removed and exposing a surface of the first functional layer; and performing surface treatment on the surface of the first functional layer, so that the flatness of the surface of the first functional layer is within a preset range. Thus, the yield of the semiconductor structure is increased.

Description

Method for forming semiconductor structure

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 5, 2024, with application number 2024102519327 and invention name “Method for Forming a Semiconductor Structure”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0003] A light-emitting diode (LED) is a semiconductor device that emits light using the unidirectional conductivity of a PN junction. LEDs offer advantages such as high brightness, low power consumption, and a long lifespan, making them widely used in lighting, display, and communications.

[0004] However, the process of forming light-emitting diodes still needs to be improved.

[0005] Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the yield and performance of light-emitting diodes.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a structure to be processed, wherein the structure to be processed includes a functional structure and a buffer structure located on the functional structure, and the functional structure includes a first functional layer; performing a planarization treatment on the structure to be processed, wherein the planarization treatment removes the buffer structure and exposes the surface of the first functional layer; performing a surface treatment on the surface of the first functional layer so that the flatness of the surface of the first functional layer is within a preset range.

[0008] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0009] The method for forming a semiconductor structure of the present invention first performs a planarization treatment on the structure to be processed, thereby removing the buffer structure and exposing the surface of the first functional layer. The surface of the first functional layer is then subjected to surface treatment to ensure that the surface flatness of the first functional layer is within a preset range. The combined effects of the planarization and surface treatment on the structure to be processed result in a high degree of surface flatness and good thickness uniformity on the exposed first functional layer, thereby improving the yield of the semiconductor structure.

[0010] Furthermore, the thickness of the structure to be processed removed by the planarization treatment is greater than the thickness of the structure to be processed removed by the surface treatment. The planarization treatment performs coarse etching on the structure to be processed, and the surface treatment performs fine etching on the structure to be processed. The coarse etching of the planarization treatment and the fine etching of the surface treatment act together on the structure to be processed, so that the exposed first functional layer has high surface flatness and good thickness uniformity, thereby improving the yield. When the first functional layer subsequently makes ohmic contact with the external conductive layer, good contact and low resistance can be achieved, which is conducive to improving the performance of the semiconductor structure.

[0011] Furthermore, the planarization process includes treating the structure to be processed using at least one inductively coupled plasma etching process. Using at least one inductively coupled plasma etching process to remove the buffer structure can quickly and efficiently remove thick buffer structures, thereby improving production efficiency.

[0012] Furthermore, the planarization process includes performing at least one first chemical mechanical polishing process on the structure to be processed. Removing the buffer structure using at least one first chemical mechanical polishing process can minimize defects during the removal of the thicker buffer structure. The subsequent second planarization process can easily achieve a surface flatness of the first functional layer that meets preset requirements.

[0013] Furthermore, the planarization process includes treating the structure to be processed using a hybrid process of at least one inductively coupled plasma etching process and at least one first chemical mechanical polishing process. Removing the buffer structure using a hybrid process of at least one inductively coupled plasma etching process and at least one first chemical mechanical polishing process can achieve both efficiency and quality in removing the thick buffer structure, thereby enabling the subsequent second planarization process to easily achieve the desired flatness of the surface of the first functional layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] 1 and 2 are schematic diagrams of thickness distribution of a semiconductor structure in one embodiment;

[0015] 3 and 4 are schematic diagrams of the surface state of a semiconductor structure in one embodiment;

[0016] 5 to 8 are schematic structural diagrams of a semiconductor structure forming process according to an embodiment of the present invention;

[0017] 9 is a schematic diagram of the thickness distribution of a semiconductor structure according to an embodiment of the present invention;

[0018] 10 is a schematic diagram of the surface state of a semiconductor structure according to an embodiment of the present invention;

[0019] FIG. 11 is a schematic flow chart of a semiconductor structure forming process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] As described in the background art, the process of forming light emitting diodes needs to be improved.

[0021] Specifically, the epitaxial layer of the light-emitting diode is made of gallium nitride (GaN), which enables the epitaxial layer of the light-emitting diode to have: (1) higher carrier mobility and lower leakage current density, which can achieve high-speed electron transmission and low-power operation; (2) a wider energy band gap, which can emit light within the visible spectrum; (3) better thermal conductivity and thermal stability, so that the device using the epitaxial layer of the light-emitting diode can better dissipate heat. Therefore, the gallium nitride epitaxial layer is widely used in the field of display technology.

[0022] Currently, GaN epilayers are formed by heterogeneous growth on a substrate. To reduce the effects of lattice mismatch and thermal stress on the GaN epilayer, multiple buffer layers are grown on the substrate before the functional layers are grown. After the functional layers are grown, the substrate is peeled off and the GaN epilayer is thinned to expose the polar surface of the GaN epilayer.

[0023] The process of thinning gallium nitride usually adopts the inductively coupled plasma (ICP) etching process. When the inductively coupled plasma etching process is used to process gallium nitride, various factors (pre-process contamination, gallium nitride layer abnormalities, etching process contamination, by-product generation, inductively coupled plasma etching mechanism, equipment environment, etc.) will lead to the formation of an etching mask. The etching mask will eventually lead to bump defects in the wafer, and the bump defects cannot be processed and removed.

[0024] Please refer to Figures 1 to 4. Figures 1 and 2 are schematic diagrams of the thickness distribution of the semiconductor structure in one embodiment, and Figures 3 and 4 are schematic diagrams of the surface state of the semiconductor structure in one embodiment. Figure 1 is a schematic diagram of the thickness distribution of each region before the gallium nitride is processed by the inductively coupled plasma etching process, and Figure 2 is a schematic diagram of the thickness distribution of each region after the gallium nitride is processed by the inductively coupled plasma etching process. It can be seen that the thickness of the interior of the gallium nitride is smaller before thinning, and the thickness of the periphery of the gallium nitride is larger. The range of the thickness difference between the periphery of the gallium nitride and the thickness of the interior of the gallium nitride is 0.28μm; Figures 3 and 4 are scanning electron microscope diagrams of bumps, pits and by-products generated on the surface of the gallium nitride after the gallium nitride is processed by the inductively coupled plasma etching process.

[0025] Bumps are one of the biggest obstacles to the yield of micro-LED manufacturing. To avoid the loss of product yield caused by bumps, removing bumps or suppressing their generation is an improvement solution that needs to be continuously promoted.

[0026] To address the aforementioned issues, the present invention provides a method for forming a semiconductor structure. The method first performs a planarization process on the structure to be processed, removing the buffer structure and exposing the surface of the first functional layer. The surface of the first functional layer is then subjected to surface treatment to ensure that the surface flatness of the first functional layer falls within a predetermined range. The combined effects of the planarization and surface treatment on the structure to be processed result in a highly flat surface and uniform thickness of the exposed first functional layer, thereby improving the yield of the semiconductor structure.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] 5 to 8 are schematic structural diagrams of a semiconductor structure forming process according to an embodiment of the present invention; FIG. 11 is a flow chart of a semiconductor structure forming process according to an embodiment of the present invention.

[0029] Referring to FIG. 11 , the process of forming the semiconductor structure includes:

[0030] Step S10: providing a structure to be processed, wherein the structure to be processed includes a functional structure and a buffer structure located on the functional structure, wherein the functional structure includes a first functional layer;

[0031] Step S20: performing a planarization process on the structure to be processed, wherein the planarization process removes the buffer structure and exposes the surface of the first functional layer;

[0032] Step S30: performing surface treatment on the surface of the first functional layer so that the flatness of the surface of the first functional layer is within a preset range.

[0033] The formation process of the semiconductor structure shown in FIG. 11 will now be analyzed and described in conjunction with FIG. 5 to FIG. 8 .

[0034] Please refer to FIG. 5 to perform step S10 to provide a structure to be processed. The structure to be processed includes a functional structure and a buffer structure 210 located on the functional structure 211 . The functional structure 211 includes a first functional layer 204 .

[0035] In this embodiment, the functional structure 211 also includes: a second functional layer 206 and a light-emitting quantum well layer 205, the light-emitting quantum well layer 205 is located between the second functional layer 206 and the first functional layer 204, the buffer structure 210 is connected to the first functional layer 204, and the second functional layer 206 and the first functional layer 204 have different conductivity types.

[0036] The second functional layer 206 is an N-type semiconductor layer or a P-type semiconductor layer; the first functional layer 204 is a P-type semiconductor layer or an N-type semiconductor layer.

[0037] In this embodiment, the N-type semiconductor layer includes N-type gallium nitride (GaN), and the P-type semiconductor layer includes P-type gallium nitride (GaN).

[0038] In this embodiment, the material of the light-emitting quantum well layer 205 includes gallium nitride (GaN) or indium gallium nitride (InGaN).

[0039] The buffer structure 210 includes at least one buffer layer.

[0040] In this embodiment, the buffer structure 210 includes a first buffer layer 203 , a second buffer layer 202 and a third buffer layer 201 . The second buffer layer 202 is located between the first buffer layer 203 and the third buffer layer 201 . The first buffer layer 203 is in contact with the first functional layer 204 .

[0041] In this embodiment, the material of the first buffer layer 203 includes N-type aluminum gallium nitride (AlGaN); the material of the second buffer layer 202 includes N-type gallium nitride (GaN); and the material of the third buffer layer 201 includes U-type gallium nitride (GaN).

[0042] In other embodiments, the buffer structure may also have two buffer layers, four buffer layers, etc.

[0043] 5 , the structure to be processed further includes: an underlying structure, the functional structure 211 is located on the underlying structure, and the second functional layer 206 is connected to the underlying structure.

[0044] The underlying structure includes a driving backplane 100. In this embodiment, the driving backplane 100 includes an IC driving backplane or a TFT driving backplane.

[0045] In other embodiments, other feasible driving backplanes may be used.

[0046] The method for forming the structure to be processed includes: providing a sacrificial substrate 200; epitaxially growing a buffer structure 210 on the sacrificial substrate 200; epitaxially growing a functional structure on the buffer structure 210; combining the surface of the functional structure 211 with the surface of the driving backplane 100, and electrically connecting the driving backplane 100 to the functional structure 211.

[0047] The sacrificial substrate 200 is made of silicon, silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The sacrificial substrate 200 is used to provide a reaction base for the epitaxial growth of the buffer structure and the functional structure.

[0048] The buffer structure 210 is used to perform stress transition on the functional structure 211 to prevent defects in the grown functional structure 211 due to lattice mismatch between the material of the functional structure 211 and the material of the sacrificial substrate 200 when the functional structure 211 is directly grown on the surface of the sacrificial substrate 200 .

[0049] Referring to FIG. 6 , the sacrificial substrate 200 is removed to expose the buffer structure 210 .

[0050] Please refer to FIG. 7 to execute step S20 to perform a planarization process on the structure to be processed. The planarization process removes the buffer structure 210 and exposes the surface of the first functional layer 204 .

[0051] The first functional layer 204 is N-type gallium nitride or P-type gallium nitride. The surface of the first functional layer 204 has polarity and is used for ohmic contact with the outside world.

[0052] The thickness of the structure to be processed removed by the planarization process is in the range of 0.5 microns to 4.5 microns.

[0053] In one embodiment, the planarization process includes performing at least one inductively coupled plasma etching process on the buffer structure 210. Using at least one inductively coupled plasma etching process to remove the buffer structure 210 can quickly and efficiently remove thick buffer structures 210, thereby improving production efficiency.

[0054] For example, the planarization process includes processing the buffer structure 210 using an inductively coupled plasma etching process.

[0055] The process parameters of the inductively coupled plasma etching process include: the etching gas includes a mixed gas of boron trichloride and chlorine; the upper electrode power range is 1200W to 1400W; the lower electrode power range is 400W to 600W; the chamber pressure range is 3 mTorr to 5 mTorr; the flow rate range of the boron trichloride gas is 100 sccm to 120 sccm; the flow rate range of the chlorine gas is 30 sccm to 50 sccm.

[0056] The inductively coupled plasma etching process performs physical bombardment and chemical etching on the buffer structure 210 to achieve planarization of the structure to be processed.

[0057] For example, the planarization process includes processing the buffer structure 210 using two inductively coupled plasma etching processes.

[0058] The thickness of the planarization treatment of the structure to be processed by the first inductively coupled plasma etching process is a first thickness; the thickness of the planarization treatment of the structure to be processed by the second inductively coupled plasma etching process is a second thickness.

[0059] The sum of the first thickness and the second thickness ranges from 0.5 micrometers to 4.5 micrometers.

[0060] The first thickness and the second thickness may be the same or different.

[0061] In this embodiment, the first thickness is greater than the second thickness, and the second thickness is in a range of 0.4 micrometers to 0.6 micrometers.

[0062] The process parameters of the first inductively coupled plasma etching process include: the etching gas includes a mixture of boron trichloride and chlorine; the upper electrode power range is 1200W to 1400W; the lower electrode power range is 400W to 600W; the chamber pressure range is 3 mTorr to 5 mTorr; the flow rate of the boron trichloride gas ranges from 100 sccm to 120 sccm; and the flow rate of the chlorine gas ranges from 30 sccm to 50 sccm.

[0063] The process parameters of the second inductively coupled plasma etching process include: the etching gas includes a mixture of boron trichloride and chlorine; the upper electrode power range is 400W to 500W; the lower electrode power range is 150W to 200W; the chamber pressure range is 3 mTorr to 5 mTorr; the flow rate of the boron trichloride gas ranges from 80 sccm to 90 sccm; and the flow rate of the chlorine gas ranges from 30 sccm to 50 sccm.

[0064] The first thickness is greater than the second thickness, and the purpose of the first thickness being greater than the second thickness is achieved by adjusting the upper electrode power, lower electrode power and flow rate of boron trichloride gas in the process parameters of the second inductively coupled plasma etching process.

[0065] In one embodiment, the planarization process includes performing at least one first chemical mechanical polishing process on the buffer structure 210. Removing the buffer structure 210 using at least one first chemical mechanical polishing process can remove defects as much as possible during the removal of the thicker buffer structure 210. The subsequent second planarization process can easily ensure that the surface flatness of the first functional layer meets preset requirements.

[0066] The first chemical mechanical polishing process is performed using chemical mechanical polishing equipment, which includes a carrier, a polishing pad, and a polishing head. The carrier is connected to a drive that can drive the carrier to rotate; the polishing pad is mounted on the carrier; and the polishing head is movably mounted above the polishing pad and is used to secure a semiconductor structure having a buffer structure. During the polishing process, the semiconductor structure having a buffer structure is secured to the polishing head, with the surface of the buffer structure to be subjected to the first chemical mechanical polishing process facing the polishing pad. The carrier drives the buffer structure 210 to press against the polishing pad, applying pressure to the buffer structure 210. The drive drives the carrier to rotate the polishing pad, polishing the buffer structure 210 to smooth the surface of the structure to be processed.

[0067] For example, the planarization process includes processing the buffer structure 210 using a first chemical mechanical polishing process.

[0068] The process parameters of the first chemical mechanical polishing process include: the polishing liquid includes molten sodium hydroxide, molten potassium hydroxide or a polishing liquid containing silica abrasive; the pressure range of the chemical mechanical polishing equipment on the buffer structure is 55Kg to 65Kg; the rotation speed range of the carrier is 35 rpm to 45 rpm.

[0069] For example, the planarization process includes performing two first chemical mechanical polishing processes on the buffer structure 210 .

[0070] When the polishing liquid includes molten sodium hydroxide or molten potassium hydroxide, the molten polishing liquid is provided to the polishing pad during the polishing process, which is beneficial to the corrosion of the buffer structure and thus beneficial to the polishing of the buffer structure.

[0071] When the polishing liquid includes a silica abrasive, the diameter of the silica is less than or equal to 200 nm. Using a silica polishing liquid can reduce the "glazing" phenomenon of the polishing pad, thereby improving the efficiency of the planarization process.

[0072] The thickness of the planarization treatment of the structure to be processed by the first first chemical mechanical polishing process is the third thickness; the thickness of the planarization treatment of the structure to be processed by the second first first chemical mechanical polishing process is the fourth thickness.

[0073] The sum of the third thickness and the fourth thickness ranges from 0.5 micrometers to 4.5 micrometers.

[0074] The third thickness and the fourth thickness may be the same or different.

[0075] In this embodiment, the third thickness is greater than the fourth thickness, and the fourth thickness ranges from 0.4 micrometers to 0.6 micrometers.

[0076] The process parameters of the first chemical mechanical polishing process include: the polishing liquid includes molten sodium hydroxide, molten potassium hydroxide or silicon dioxide; the pressure range of the chemical mechanical polishing equipment on the buffer structure is 55kg to 65kg; the rotation speed range of the carrier is 35 rpm to 45 rpm.

[0077] The process parameters of the second first chemical mechanical polishing process include: the polishing liquid includes molten sodium hydroxide, molten potassium hydroxide or silicon dioxide; the pressure range of the chemical mechanical polishing equipment on the buffer structure is 30kg to 40kg; the rotation speed range of the carrier is 35 rpm to 45 rpm.

[0078] In one embodiment, the planarization process includes treating the buffer structure 210 using a hybrid process of at least one inductively coupled plasma etching process and at least one first chemical mechanical polishing process. Removing the buffer structure 210 using a hybrid process of at least one inductively coupled plasma etching process and at least one first chemical mechanical polishing process can achieve both efficiency and quality during the removal of the thick buffer structure 210, thereby enabling the subsequent second planarization process to easily achieve the desired flatness of the surface of the first functional layer.

[0079] The process sequence of the inductively coupled plasma etching process and the first chemical mechanical polishing process can be adjusted according to actual needs.

[0080] The inductively coupled plasma etching process is interspersed with a first chemical mechanical polishing process, which can promptly remove defects such as bumps, pits, and reaction by-products caused by the inductively coupled plasma etching process, thereby preventing the bumps, pits, and reaction by-products from causing secondary damage and deepening of defects in subsequent process steps.

[0081] For example, the planarization process includes one inductively coupled plasma etching process and two first chemical mechanical polishing processes to process the buffer structure 210. The buffer structure 210 is first etched by the inductively coupled plasma etching process, and then the buffer structure 210 is removed by the two first chemical mechanical polishing processes.

[0082] The thickness of the planarization treatment of the structure to be processed by the inductively coupled plasma etching process is the fifth thickness; the thickness of the planarization treatment of the structure to be processed by the first first chemical mechanical polishing process is the sixth thickness; the thickness of the planarization treatment of the structure to be processed by the second first first chemical mechanical polishing process is the seventh thickness.

[0083] The sum of the fifth thickness, the sixth thickness, and the seventh thickness ranges from 0.5 micrometers to 4.5 micrometers.

[0084] The fifth thickness, the sixth thickness and the seventh thickness may be the same or different.

[0085] In this embodiment, the fifth thickness is greater than the sixth thickness, the sixth thickness is greater than the seventh thickness, and the seventh thickness ranges from 0.2 micrometers to 0.4 micrometers.

[0086] The process parameters of the inductively coupled plasma etching process include: the etching gas includes a mixed gas of boron trichloride and chlorine; the upper electrode power range is 1200W to 1400W; the lower electrode power range is 400W to 600W; the chamber pressure range is 3 mTorr to 5 mTorr; the flow rate range of the boron trichloride gas is 100 sccm to 120 sccm; the flow rate range of the chlorine gas is 30 sccm to 50 sccm.

[0087] The process parameters of the first chemical mechanical polishing process include: the polishing liquid includes molten sodium hydroxide, molten potassium hydroxide or a polishing liquid containing silica abrasive; the pressure range of the chemical mechanical polishing equipment on the buffer structure is 50kg to 65kg; the rotation speed range of the carrier is 20 revolutions per minute to 25 revolutions per minute.

[0088] The process parameters of the second first chemical mechanical polishing process include: the polishing liquid includes molten sodium hydroxide, molten potassium hydroxide or a polishing liquid containing silica abrasive; the pressure range of the chemical mechanical polishing equipment on the buffer structure is 35kg to 45kg; the rotation speed range of the carrier is 20 revolutions per minute to 25 revolutions per minute.

[0089] The sixth thickness is greater than the seventh thickness, and the purpose of the sixth thickness being greater than the seventh thickness is achieved by adjusting the pressure range in the process parameters of the second first chemical mechanical polishing process.

[0090] For example, the planarization process includes performing one inductively coupled plasma etching process and two first chemical mechanical polishing processes on the buffer structure 210. The buffer structure 210 is first removed by performing one chemical mechanical polishing process, then etched by performing an inductively coupled plasma etching process, and then removed by performing one first chemical mechanical polishing process.

[0091] For example, the planarization process includes alternating an inductively coupled plasma etching process and a first chemical mechanical polishing process.

[0092] Please refer to FIG. 8 to perform step S30 to perform surface treatment on the surface of the first functional layer 204 so that the flatness of the surface of the first functional layer 204 is within a preset range.

[0093] In this embodiment, the thickness of the structure to be processed removed by the planarization treatment is greater than the thickness of the structure to be processed removed by the surface treatment. The planarization treatment performs coarse etching on the structure to be processed, and the surface treatment performs fine etching on the structure to be processed. The coarse etching of the planarization treatment and the fine etching of the surface treatment act together on the structure to be processed, so that the exposed first functional layer 204 has high surface flatness and good thickness uniformity, thereby improving the yield. When the first functional layer 204 subsequently makes ohmic contact with the external conductive layer, good contact and low resistance can be achieved, which is conducive to improving the performance of the semiconductor structure.

[0094] In this embodiment, the flatness of the surface of the first functional layer 204 after the surface treatment is greater than or equal to the flatness of the surface of the first functional layer 204 after the planarization treatment.

[0095] In this embodiment, the surface treatment process includes a second chemical mechanical polishing process.

[0096] The process parameters of the second chemical mechanical polishing process include: the polishing liquid includes molten sodium hydroxide, molten potassium hydroxide or a polishing liquid containing silica abrasive; the pressure range of the chemical mechanical polishing equipment on the buffer structure is 35kg to 45kg; the rotation speed range of the carrier is 20 revolutions per minute to 25 revolutions per minute.

[0097] The second chemical mechanical polishing process can effectively remove defects such as bumps, by-product residues, and dirt on the surface of the first functional layer 204 after planarization treatment, improve the flatness and thickness uniformity of the surface of the first functional layer 204, and provide a good epitaxial layer for subsequent process steps of the semiconductor structure, thereby improving the yield of the semiconductor structure.

[0098] The flatness of the surface of the first functional layer after the surface treatment is greater than the flatness of the surface of the first functional layer after the planarization treatment. In this embodiment, the flatness of the surface of the first functional layer after the surface treatment includes: the absolute value range of the difference between the maximum thickness of the first functional layer and the minimum thickness of the first functional layer is less than or equal to 0.08 microns.

[0099] In other embodiments, the absolute value range of the difference between the maximum thickness of the first functional layer and the minimum thickness of the first functional layer may be other specifications.

[0100] In other embodiments, the surface treatment process includes an inductively coupled plasma etching process.

[0101] Please refer to Figures 9 and 10. Figure 10 is a schematic diagram of the surface state of the semiconductor structure in an embodiment of the present invention. Figure 9 is a schematic diagram of the thickness distribution of various parts of the semiconductor structure after flattening and surface treatment. In conjunction with Figure 1, refer to Figure 9. The maximum thickness of the thinned semiconductor structure in Figure 9 is 1.23μm, the minimum thickness of the thinned semiconductor structure is 1.15μm, and the range of the thickness of the thinned semiconductor structure is 0.08μm. The thickness range of the thinned semiconductor structure is 1.15μm to 1.23μm, of which the thickness range of the thinned semiconductor structure is between 1.20μm and 1.23μm, accounting for 53.8%, and the thickness range of the thinned semiconductor structure is between 1.15μm and 1.19μm, accounting for 46.2%. The thickness distribution of the thinned semiconductor structure is relatively uniform. The thickness distribution of the semiconductor structure before thinning in Figure 1 has no effect on the thickness distribution of the thinned semiconductor structure in Figure 9.

[0102] Figure 10 is a scanning electron microscope diagram of the surface of the first functional layer after flattening and surface treatment. The surface of the thinned semiconductor structure in Figure 10 has no bumps and only slight pits, thereby improving the yield of the semiconductor structure during the thinning process.

[0103] The method for forming a semiconductor structure according to the embodiment of the present invention can be applied in the manufacturing process of a micro display panel.

[0104] The micro display panel described above has a very small volume, with length and width dimensions ranging from 500μm to 50,000μm. The area of ​​the light-emitting region of the micro display panel is very small, such as 1mm×1mm, 2.64mm×2.02mm, 3mm×5mm, etc. The light-emitting region of the micro display panel includes a plurality of micro LED pixels arranged in an array, and the specific pixel arrangement can be one of 320×240, 640×480, 1600×1200, 1920×1080, and 2560×1440. The size of a single micro LED pixel is between 100nm and 100μm. In some embodiments, the size of a single micro LED pixel is between 150nm and 15μm. In some embodiments, the size of a single micro LED pixel can also be less than 10μm.

[0105] A driver backplane is located behind the micro-LED pixel array. It is electrically connected to the micro-LEDs within the array and receives signals such as image data from the outside world, controlling the corresponding micro-LEDs to illuminate or not illuminate. The driver backplane is typically a TFT (Thin Film Transistor) board or an IC (Integrated Circuit) board.

[0106] For example, the driving backplane of the above-mentioned micro display panel integrates a frame buffer, a column driving circuit, and a row driving circuit. The frame buffer includes a first pixel storage area, and the micro LED pixel array includes a second pixel storage area. A complete frame of pixel grayscale data from the outside world can first enter the first pixel storage area of ​​the frame buffer, and the column driving circuit can load the pixel grayscale data in the first pixel storage area of ​​the frame buffer into the second pixel storage area of ​​the micro LED pixel array. The row driving circuit can scan the pixel grayscale data in the second pixel storage area and generate a pulse modulation signal to achieve the purpose of displaying different grayscales. When driving multiple micro LED pixels in the micro LED pixel array, it is possible to adopt a single pixel independent driving method or a multiple pixel unit independent driving method. The specific driving method should not constitute a limitation to the present invention.

[0107] It should be noted that the application of the semiconductor structure forming method of the present invention in the process of manufacturing a microdisplay panel should not constitute a limitation on the application of the present invention. Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a structure to be processed, the structure to be processed comprising a functional structure and a buffer structure located on the functional structure, wherein the functional structure comprises a first functional layer; performing a planarization process on the structure to be processed, wherein the planarization process removes the buffer structure and exposes the surface of the first functional layer; The surface of the first functional layer is subjected to surface treatment so that the flatness of the surface of the first functional layer is within a preset range.

2. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the structure to be processed removed by the planarization process is greater than the thickness of the structure to be processed removed by the surface treatment.

3. The method for forming a semiconductor structure according to claim 2, wherein: The planarization process includes processing the structure to be processed by at least one inductively coupled plasma etching process.

4. The method for forming a semiconductor structure according to claim 3, wherein: The etching gas of the inductively coupled plasma etching process includes a mixed gas of boron trichloride and chlorine.

5. The method for forming a semiconductor structure according to claim 2, wherein: The planarization process includes at least once processing the structure to be processed using a first chemical mechanical polishing process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The polishing liquid of the first chemical mechanical polishing process includes molten sodium hydroxide, molten potassium hydroxide or a polishing liquid containing silicon dioxide abrasive.

7. The method for forming a semiconductor structure according to claim 2, wherein: The planarization process includes processing the structure to be processed by a mixed process of at least one inductively coupled plasma etching process and at least one first chemical mechanical polishing process.

8. The method for forming a semiconductor structure according to claim 2, wherein: The surface treatment process includes a second chemical mechanical polishing process.

9. The method for forming a semiconductor structure according to claim 2, wherein: The surface treatment process includes an inductively coupled plasma etching process.

10. The method for forming a semiconductor structure according to claim 1, wherein: The flatness of the surface of the first functional layer after the surface treatment is greater than or equal to the flatness of the surface of the first functional layer after the planarization treatment.

11. The method for forming a semiconductor structure according to claim 1, wherein: The functional structure further includes: a second functional layer and a light-emitting quantum well layer, the light-emitting quantum well layer is located between the second functional layer and the first functional layer, the buffer structure is connected to the first functional layer, and the second functional layer and the first functional layer have different conductivity types.

12. The method for forming a semiconductor structure according to claim 11, wherein: The second functional layer is an N-type semiconductor layer or a P-type semiconductor layer; the first functional layer is a P-type semiconductor layer or an N-type semiconductor layer, and the conductivity type of the second functional layer and the first functional layer is different from that of the first functional layer.

13. The method for forming a semiconductor structure according to claim 11, wherein: The structure to be processed further includes: an underlying structure, the functional structure is located on the underlying structure, and the second functional layer is connected to the underlying structure.

14. The method for forming a semiconductor structure according to claim 1, wherein: The buffer structure includes at least one buffer layer.

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