Perovskite / electron transport layer integrated film forming method and tandem cell

Abstract

The present invention provides a perovskite / electron transport layer integrated film forming method and a tandem cell. By synchronously preparing a perovskite absorption layer and an electron transport layer, the corrosion of moisture to a perovskite thin film in the process of preparing the electron transport layer through atomic deposition is avoided; and additionally, the moisture is used to help the diffusion of reactant molecules in a perovskite crystallization process, thereby improving the thoroughness of the reaction, and reducing internal defects of the thin film. A tandem solar cell prepared by the method has higher open-circuit voltage and photoelectric conversion efficiency. Additionally, the method also simplifies the manufacturing process steps of a crystalline silicon / perovskite tandem cell, thereby reducing manufacturing costs of the tandem cell.

Description

A perovskite / electron transport layer integrated film forming method and stacked battery

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on March 7, 2024, with application number 2024102581987 and invention name “A perovskite / electron transport layer integrated film forming method and stacked battery”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention mainly relates to the technical field of solar cells, and in particular to a perovskite / electron transport layer integrated film forming method and a stacked cell. Background Art

[0003] The statements herein merely provide background information related to the present application and do not necessarily constitute prior art.

[0004] Solar energy, a sought-after new clean energy source, boasts abundant resources and low costs. Converting solar energy into electricity using photovoltaic cells is currently one of the most efficient ways to utilize solar energy. Monocrystalline and polycrystalline silicon solar cells have relatively mature industrial technologies. In recent years, perovskite solar cells have garnered widespread attention from both the scientific and industrial communities due to their advantages, including adjustable band gaps, low exciton binding forces, and high photoelectric conversion efficiency.

[0005] Currently, the photoelectric conversion efficiency of crystalline silicon / perovskite tandem solar cells has reached a high of 33.9%. However, this efficiency still lags behind theoretical values, leaving significant room for improvement. Furthermore, stability issues remain a challenge that needs to be addressed. Optimizing the structure of the perovskite top cell is one of the key areas for improving the efficiency and stability of tandem solar cells.

[0006] Please refer to Figure 3. In the traditional preparation process of perovskite / crystalline silicon tandem solar cells, the metal oxide as the electron transport layer is often prepared on the perovskite film by atomic layer deposition. However, this method requires the introduction of water vapor, which will corrode the prepared perovskite film during the preparation process, destroy the perovskite crystal structure, and affect the device performance. If C 60 As an electron transport layer, although water vapor can be avoided during the preparation process to reduce the impact of water vapor on the perovskite film, C 60 The thickness is usually around 10~50nm, and its absorption rate for light in the range of 300~800nm ​​is relatively high, resulting in a film transmittance usually below 85%, causing light absorption losses in the device. Application Contents

[0007] The present invention aims to overcome the problem that the electron transport layer (ETL) produced by existing atomic layer deposition (ALD) methods can erode the crystal structure of perovskite films, resulting in decreased device performance. A method for forming an integrated perovskite / ETL film and a stacked cell are proposed. This method involves first using a two-step process to deposit two seed layers (a lead iodide film and an ammonium salt film) on a cell substrate. The cell substrate is then placed in an ALD chamber. The chamber temperature is controlled, and water vapor and an oxide material are introduced. The two seed layers are annealed to form a perovskite absorber layer, and an ETL is then formed on the perovskite absorber layer. In this method, the ETL and the ETL are formed simultaneously. During the ALD process, since the perovskite crystals are not yet fully formed, the introduction of water vapor does not erode the perovskite film structure. Instead, it accelerates interdiffusion between the two seed layers, improving the sufficiency of the perovskite reaction. The resulting integrated perovskite / ETL structure is more stable, has fewer internal defects, reduces light absorption losses in the absorber layer, and improves the device's photoelectric conversion efficiency and stability. At the same time, this method also simplifies the manufacturing process steps of crystalline silicon / perovskite tandem cells and reduces their manufacturing costs.

[0008] To achieve the above objectives, the present invention provides the following specific solutions.

[0009] In one aspect, the present invention provides a method for forming an integrated perovskite / electron transport layer film, comprising the steps of:

[0010] A textured substrate is provided, lead iodide and cesium bromide are co-evaporated on the textured substrate to form a lead iodide film, an ammonium salt solution is spin-coated on the lead iodide film to obtain an ammonium salt film, and after the spin coating is completed, the film is dried; the obtained substrate sample is placed in an ALD chamber, annealed, and water vapor and an electron transport layer material are introduced to obtain a perovskite absorption layer and an electron transport layer deposited thereon on the surface of the textured substrate.

[0011] In one embodiment, the evaporation rate of the lead iodide is controlled at 0-10 A / s, the evaporation rate of the cesium bromide is controlled at 0-10 A / s, the total evaporation time is controlled between 0 and 10,000 s, and the thickness of the formed lead iodide film is 200-800 nm.

[0012] Preferably, the evaporation rates of different materials are controlled so that the content ratio of lead iodide to cesium bromide is between 10:1 and 2:1.

[0013] The ammonium salt solution is prepared by dissolving formamidine iodide (FAI), formamidine bromide (FABr) and methylammonium chloride (MACl) in an organic solvent in a certain proportion, wherein the volume ratio of FAI and FABr is between 10:1 and 1:10; the volume ratio of MACl to the two ammonium salt additives FAI and FABr is between 0% and 50%, and the solution concentration is controlled between 0.5-2 M; the organic solvent includes at least one of ethanol, isopropanol, methanol, dimethylformamide (DMF), g-butyrolactone (GBL), dimethyl sulfoxide (DMSO) and N,N-dimethylacetamide (DMA), and the solvent volume ratio is between 0-3:10-7.

[0014] In one embodiment, the spin coating speed of the ammonium salt solution is 1200-6000 rpm, the spin coating time is 20-120 s, and after the spin coating is completed, the solution is dried at a temperature of 50-100° C. for 5-10 min to obtain the ammonium salt film with a thickness of 200-800 nm.

[0015] In one embodiment, the temperature inside the ALD chamber is 100-200°C, the temperature of the pipe entering the ALD chamber is between 50-150°C, the water vapor in the ALD chamber is controlled by a water vapor precursor bottle, and the opening parameter is 100-800 mSec per cycle. At the same time, the electron transport layer material is deposited on the ammonium salt film, and the deposition vacuum is 0-1×10 -4 Pa, total deposition time 0~120min, and control the film thickness between 5~40nm.

[0016] Specifically, the electron transport layer material is at least one of zinc oxide, tin dioxide, and titanium dioxide.

[0017] In one embodiment, the preparation of the suede substrate comprises:

[0018] A textured silicon substrate is provided, and a base passivation layer, a P-type base doping layer, and a first conductive layer are sequentially prepared on one side of the textured silicon substrate; and a base surface passivation layer, an N-type base doping layer, a tunneling layer, and a hole transport layer are sequentially prepared on the other side of the textured silicon substrate to obtain the textured substrate, wherein the perovskite absorption layer is formed on the hole transport layer.

[0019] Specifically, the first conductive layer includes a first conductive transparent layer and a first metal electrode layer sequentially formed on the P-type doped layer.

[0020] In one embodiment, the integrated film forming method further includes sequentially forming a buffer layer, a second conductive layer, and an anti-reflection layer on the surface of the electron transport layer.

[0021] Specifically, the second conductive layer includes a second conductive transparent layer and a second metal electrode layer sequentially formed on the buffer layer.

[0022] On the other hand, the present invention also provides a stacked cell prepared by the above method, comprising a velvet substrate; and a perovskite absorption layer, an electron transport layer, a buffer layer, a second conductive layer and an anti-reflection layer sequentially arranged on the surface of the velvet substrate.

[0023] Specifically, the second conductive layer includes a second conductive transparent layer and a second metal electrode layer sequentially disposed on the buffer layer.

[0024] The textured substrate includes a textured crystalline silicon layer; a tunneling layer and a hole transport layer sequentially arranged on one surface of the textured crystalline silicon layer, the perovskite absorption layer is arranged on the hole transport layer; and a first conductive layer arranged on the other surface of the textured crystalline silicon layer.

[0025] Specifically, the first conductive layer includes a first conductive transparent layer and a first metal electrode layer sequentially provided on the surface of the textured crystalline silicon layer.

[0026] Specifically, the textured crystalline silicon layer includes a textured silicon substrate; and a base passivation layer and a P-type base doping layer sequentially arranged on one surface of the textured silicon substrate, and the first conductive layer is arranged on the P-type base doping layer; and a base surface passivation layer and an N-type base doping layer sequentially prepared on the other surface of the textured silicon substrate, and the tunneling layer is arranged on the N-type base doping layer.

[0027] The present invention provides a method for forming an integrated perovskite / electron transport layer film. By simultaneously preparing the perovskite absorption layer and the electron transport layer, the method solves the problem of water vapor erosion on the perovskite film during the atomic deposition of the electron transport layer. At the same time, water vapor is used to help the diffusion of reactant molecules in the perovskite crystallization process, thereby improving the reaction efficiency and reducing internal defects in the film. The stacked solar cell prepared by this method has a higher open circuit voltage, photoelectric conversion efficiency and a lower attenuation rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG1 is a schematic diagram of the steps of a perovskite / electron transport layer integrated film forming method provided by an embodiment of the present invention.

[0029] FIG2 is a schematic diagram of a stacked battery structure provided by an embodiment of the present invention.

[0030] FIG3 is a schematic diagram of the steps of preparing a perovskite / electron transport layer in a conventional process.

[0031] 1. Velvet substrate; L1, lead iodide film; L2, ammonium salt film; 2. Perovskite absorption layer.

[0032] 10. First conductive layer; 11. Textured crystalline silicon layer; 12. Tunneling layer; 13. Hole transport layer; 21. Electron transport layer; 22. Buffer layer; 23. Second conductive layer; 24. Anti-reflection layer.

[0033] 101. First metal electrode layer; 102. First conductive transparent layer; 111. P-type base doping layer; 112. Base passivation layer; 113. Textured silicon substrate; 114. Base surface passivation layer; 115. N-type base doping layer; 231. Second metal electrode layer; 232. Second conductive transparent layer. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0035] In the description of the present invention, unless otherwise specified, "plurality" means two or more; the terms "center", "longitudinal", "lateral", "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0036] Referring to FIG. 1 , an embodiment of the present invention provides a method for forming an integrated perovskite / electron transport layer film, comprising the following steps:

[0037] A textured substrate 1 is provided, lead iodide and cesium bromide are co-evaporated on the textured substrate 1 to form a lead iodide film L1, an ammonium salt solution is spin-coated on the lead iodide film L1 to obtain an ammonium salt film L2, and after the spin coating is completed, the film is dried; the obtained substrate sample is placed in an ALD (atomic layer deposition) chamber, annealed, and water vapor and electron transport layer materials are introduced to obtain a perovskite absorption layer 2 and an electron transport layer 21 deposited thereon on the surface of the textured substrate 1.

[0038] Please refer to Figure 3. In the process of preparing the electron transport layer by the traditional atomic layer deposition method, if metal oxide is used as the material of the electron transport layer, water vapor must be introduced during the deposition process. The introduction of water vapor will destroy the annealed perovskite crystal structure and cause internal defects in the film. If C60 As the material of the electron transport layer, a layer of C is first prepared on the perovskite absorption layer. 60 The film layer can avoid the damage to the perovskite film structure caused by the introduction of water vapor, but the C 60 The thickness of the film is usually around 10~50nm, and its absorption rate for light in the range of 300~800nm ​​is high, resulting in the transmittance of the film layer usually being below 85%, which causes the loss of light absorption in the device. In order to solve the water vapor corrosion in the traditional atomic deposition method and introduce C 60 In order to solve the problem of light loss caused by the electron transport layer 21, a method for synchronously preparing the perovskite absorption layer 2 and the electron transport layer 21 is adopted in the embodiment of the present invention. First, the lead iodide film L1 and the ammonium salt film L2 are prepared in sequence on the velvet substrate 1 and placed in an atomic deposition chamber for annealing. Water vapor and metal oxide materials are introduced during annealing. Under the action of water vapor, the mutual diffusion between the lead iodide film L1 and the ammonium salt film L2 can be effectively helped, making the reaction between them more thorough and sufficient. In addition, since the electron transport layer 21 and the perovskite absorption layer 2 are formed synchronously, the contact effect between the interfaces is better, and the electrical contact and stability of the interfaces are improved. This method simplifies the traditional preparation process, reduces manufacturing costs, and improves the performance and stability of the device.

[0039] In one embodiment, the evaporation rate of the lead iodide is controlled at 0-10 A / s, the evaporation rate of the cesium bromide is controlled at 0-10 A / s, the total evaporation time is controlled between 0 and 10,000 s, and the thickness of the formed lead iodide film L1 is 200-800 nm.

[0040] Preferably, the evaporation rates of different materials are controlled so that the content ratio of lead iodide to cesium bromide is between 10:1 and 2:1.

[0041] The ammonium salt solution is prepared by dissolving formamidine iodide (FAI), formamidine bromide (FABr) and methylammonium chloride (MACl) in an organic solvent in a certain proportion, wherein the volume ratio of FAI and FABr is between 10:1 and 1:10; the volume ratio of MACl to the two ammonium salt additives FAI and FABr is between 0% and 50%, and the solution concentration is controlled between 0.5-2 M; the organic solvent includes at least one of ethanol, isopropanol, methanol, dimethylformamide (DMF), g-butyrolactone (GBL), dimethyl sulfoxide (DMSO) and N,N-dimethylacetamide (DMA), and the solvent volume ratio is between 0-3:10-7.

[0042] In one embodiment, the ammonium salt solution is spin-coated at a speed of 1200-6000 rpm for a time of 20-120 seconds. After the spin coating is completed, the solution is dried at a temperature of 50-100°C for 5-10 minutes to obtain the ammonium salt film L2 having a thickness of 200-800 nm. The drying process described in the embodiment of the present invention is primarily to remove the organic solvent in the solution, allowing the ammonium salt solution to solidify to form a thin film structure. However, at this temperature, the lead iodide film L1 and the ammonium salt film L2 are not yet sufficiently reacted to form a perovskite crystal structure.

[0043] In other embodiments, the ammonium salt film L2 can also be prepared by an evaporation method, including the steps of controlling the maximum evaporation rate of formamidine iodide (FAI) to be 0~10A / s, controlling the maximum evaporation rate of formamidine bromide (FABr) to be 0~10A / s, controlling the total evaporation time to be between 0-10000s, and forming the ammonium salt film L2 on the lead iodide film L1 with a thickness of 200-800nm.

[0044] In one embodiment, the temperature inside the ALD chamber is 100-200°C, the temperature of the pipe entering the ALD chamber is between 50-150°C, the water vapor in the ALD chamber is controlled by a water vapor precursor bottle, and the opening parameter is 100-800 mSec per cycle. At the same time, the electron transport layer material is deposited on the ammonium salt film L2, and the deposition vacuum is 0-1×10 -4 Pa, total deposition time 0~120min, and control the film thickness between 5~40nm.

[0045] Specifically, the electron transport layer material is at least one of zinc oxide (ZnO), tin dioxide (SnO2), and titanium dioxide (TiO2).

[0046] When the substrate sample is placed in the ALD chamber, the lead iodide film L1 and the ammonium salt film L2 will diffuse and react with each other, and anneal at a temperature of 100~200℃ to form a perovskite absorption layer 2, and the electron transport layer material deposited thereon forms an electron transport layer 21. The film interface contact obtained by this method is better.

[0047] In this embodiment, the velvet base 1 is a layer film with a velvet structure on the surface. In the production and application of solar cells, the irregular surface of the velvet structure can increase the number of reflections of sunlight on the surface, effectively reduce the surface reflectivity of the solar cell, and increase the light absorption coefficient of the device, thereby increasing the photoelectric conversion efficiency of the device. The velvet base 1 described in this application has a velvet structure, which can also reduce light reflection.

[0048] In one embodiment, the preparation of the velvet base 1 includes: providing a velvet silicon substrate 113, sequentially preparing a base passivation layer 112, a P-type base doping layer 111 and a first conductive layer 10 on one side of the velvet silicon substrate 113, and sequentially preparing a base surface passivation layer 114, an N-type base doping layer 115, a tunneling layer 12 and a hole transport layer 13 on the other side of the velvet silicon substrate 113 to obtain the velvet base 1, wherein the perovskite absorption layer 2 is formed on the hole transport layer 13, and the first conductive layer 10 includes a first conductive transparent layer 102 and a first metal electrode layer 101 sequentially formed on the P-type base doping layer 111.

[0049] In this embodiment, the textured silicon substrate 113 has a textured surface on its surface. On this basis, each film layer formed on the two surfaces of the textured silicon substrate 113 also has a textured structure; specifically, the textured surface of the textured silicon substrate 113 can be prepared by anisotropically etching a silicon wafer with an alkaline solution.

[0050] The base passivation layer 112 and the base surface passivation layer 114 formed on the two surfaces of the textured silicon substrate 113 are both passivation structures, which can saturate the dangling bonds at the semiconductor surface, reduce surface activity, increase the surface cleaning process, and avoid the formation of recombination centers due to the introduction of impurities in the surface layer, thereby reducing the surface recombination rate of minority carriers; specifically, the base passivation layer 112 and the base surface passivation layer 114 can be formed by methods such as vapor deposition and atomic layer deposition.

[0051] In this embodiment, the P-type base doping layer 111 and the N-type base doping layer 115 can be formed by diffusion. Specifically, a phosphorus source / nitrogen source is diffused on the textured silicon substrate 113 to form a doping structure, thereby obtaining the P-type base doping layer 111 and the N-type base doping layer 115 respectively.

[0052] The first conductive transparent layer 102 can be formed by magnetron sputtering. The substrate sample to be prepared is placed in a magnetron sputtering device, the power is controlled between 50 and 200 W, a target is set, and the first conductive transparent layer 102 is sputtered. The first metal electrode layer 101 is formed by evaporation. The substrate sample to be prepared is placed on a mask plate for evaporation. The evaporation vacuum is 5×10 -5 ~2×10 -4 Pa, the evaporation temperature is 500-2000° C., the evaporation rate is 0.1-5 Å / S, and the metal material is evaporated to form the first metal electrode layer 101.

[0053] In this embodiment, the tunneling layer 12 is prepared by atomic layer deposition, magnetron sputtering or wet chemical method, which can eliminate the electrical mismatch and device instability problems caused by direct series connection of crystalline silicon cells and perovskite cells.

[0054] In this embodiment, the hole transport layer 13 is prepared by spin coating, and the hole transport layer dispersion is evenly coated on the surface of the tunneling layer 12. The spin coating speed is 1000-5000 rpm, and the spin coating time is 10-100 s. After the spin coating is completed, an annealing operation is performed. The annealing temperature is 300-600° C. and the annealing time is 10-50 min to obtain the hole transport layer 13.

[0055] In this embodiment, the hole transport layer 13 can also be prepared by magnetron sputtering. The substrate sample to be prepared is placed in a magnetron sputtering device, and the power is controlled to be 30-90W to obtain the hole transport layer 13 by sputtering.

[0056] In one embodiment, the integrated film forming method also includes sequentially forming a buffer layer 22, a second conductive layer 23 and an anti-reflection layer 24 on the surface of the electron transport layer 21, and the second conductive layer 23 includes a second conductive transparent layer 232 and a second metal electrode layer 231 sequentially formed on the buffer layer 22.

[0057] The buffer layer 22 is prepared by atomic layer deposition. The buffer layer material is deposited on the surface of the electron transport layer 21 using an atomic layer deposition device. The deposition vacuum is 0-1×10 4 Pa, the deposition pipeline temperature is between 50 and 150° C., the deposition chamber temperature is between 40 and 150° C., and the buffer layer 22 is obtained.

[0058] The buffer layer 22 can also be prepared by evaporation, wherein the buffer layer material is evaporated onto the surface of the electron transport layer 21, and the evaporation vacuum degree is 6×10 -5 ~4×10 -4 Pa, the evaporation temperature is 100~500℃, and the evaporation rate is 0.05~1 Å / S to obtain the buffer layer 22.

[0059] In this embodiment, the second conductive layer 23 can be prepared by the same method as the first conductive layer 10. Specifically, the second conductive transparent layer 232 can be formed by magnetron sputtering. The substrate sample to be prepared is placed in a magnetron sputtering device, the power is controlled between 50 and 200 W, a target material is set, and the second conductive transparent layer 232 is sputtered. The second metal electrode layer 231 is formed by evaporation. The substrate sample to be prepared is placed on a mask plate for evaporation. The evaporation vacuum is 5×10 -5 ~2×10 -4 Pa, the evaporation temperature is 500-2000° C., the evaporation rate is 0.1-5 Å / S, and the metal material is evaporated to form the second metal electrode layer 231 .

[0060] In this embodiment, the anti-reflection layer 24 can be prepared by magnetron sputtering or evaporation, and has a thickness of 1-600 nm.

[0061] This embodiment provides a perovskite / electron transport layer integrated film formation method, which solves the problem of water vapor erosion of the perovskite film during the atomic deposition of the electron transport layer by simultaneously preparing the perovskite absorption layer 2 and the electron transport layer 21, and simultaneously uses water vapor to help the diffusion of reactant molecules in the perovskite crystallization process, thereby improving the reaction efficiency and reducing internal defects of the film, thereby improving the photoelectric conversion efficiency and stability of the device.

[0062] Please refer to Figure 2. An embodiment of the present invention also provides a stacked cell obtained by the above-mentioned multi-perovskite / electron transport layer integrated film forming method, including a suede substrate 1; and a perovskite absorption layer 2, an electron transport layer 21, a buffer layer 22, a second conductive layer 23 and an anti-reflection layer 24 arranged in sequence on the surface of the suede substrate.

[0063] Specifically, the second conductive layer 23 includes a second conductive transparent layer 232 and a second metal electrode layer 231 sequentially disposed on the buffer layer 22 .

[0064] In this embodiment, the surface of the velvet substrate 1 has a velvet structure. Therefore, the perovskite absorption layer 2, the electron transport layer 21, the buffer layer 22, the second conductive layer 23 and the anti-reflection layer 24 formed on the surface of the velvet substrate 1 are also film layers with a velvet structure. The irregular surface of the velvet structure can increase the number of reflections of sunlight on the surface, effectively reduce the surface reflectivity of the solar cell, and improve the light absorption coefficient of the device, thereby increasing the photoelectric conversion efficiency of the device.

[0065] In this embodiment, the perovskite absorption layer 2 is specifically an ABX3 structure, and the A position is an organic cation, including CH3NH3 + (MA + ), NH2CH=NH2 + (FA + ), CH3CH2NH3 + or Cs + At least one of .

[0066] The B position is a metal cation, including Pb 2+ 、Sn 2+ At least one of .

[0067] The X position is a halogen anion, including F- 、Cl - Br - , I - At least one of .

[0068] The electron transport layer 21 can effectively transport electrons and block holes. Specifically, the electron transport layer is composed of at least one of zinc oxide (ZnO), tin dioxide (SnO2), and titanium dioxide (TiO2).

[0069] The buffer layer 22 can effectively improve problems such as band mismatch between interfaces, carrier recombination and chemical reactions, thereby improving the charge separation and collection efficiency in the perovskite battery, and effectively improving interface and stability problems. Specifically, the buffer layer 22 is composed of at least one of zinc oxide (ZnO), tin dioxide (SnO2), and titanium dioxide (TiO2).

[0070] The second conductive layer 23 is composed of a second conductive transparent layer 232 and a second metal electrode layer 231, which plays the role of conducting electrons and outputting current. Specifically, the second metal electrode layer 231 is composed of at least one of silver (Ag), gold (Au), copper (Cu), aluminum (Al), and carbon (C); the second conductive transparent layer 232 is composed of at least one of indium tin oxide (ITO), indium zinc oxide (IZO), and aluminum zinc oxide (AZO).

[0071] The anti-reflection layer 24 is composed of at least one of magnesium fluoride, lithium fluoride (LiF), sodium fluoride (NaF), and silicon oxide (SiO2), which can increase the light transmittance of the device, thereby improving the light absorption efficiency of the device.

[0072] In this embodiment, the textured substrate 1 includes a textured crystalline silicon layer 11; a tunneling layer 12 and a hole transport layer 13 sequentially arranged on one surface of the textured crystalline silicon layer 11, and the perovskite absorption layer 2 is arranged on the hole transport layer 13; and a first conductive layer 10 arranged on the other surface of the textured crystalline silicon layer 11, and the first conductive layer 10 includes a first conductive transparent layer 102 and a first metal electrode layer 101 sequentially arranged on the surface of the textured crystalline silicon layer 11.

[0073] Specifically, the textured crystalline silicon layer 11 includes a textured silicon substrate 113; and a base passivation layer 112 and a P-type base doping layer 111 sequentially arranged on one surface of the textured silicon substrate 113, and the first conductive layer 10 is arranged on the P-type base doping layer 111; and a base surface passivation layer 114 and an N-type base doping layer 115 sequentially prepared on the other surface of the textured silicon substrate 113, and the tunneling layer 12 is arranged on the N-type base doping layer 115.

[0074] The tunneling layer 12 may be made of oxides such as silicon dioxide, and may generate a tunneling current at the contact position of the stacked battery to connect the two sub-batteries.

[0075] The hole transport layer 13 is made of poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), poly-3-hexylthiophene (P3HT), nickel oxide (NiO x ), molybdenum oxide (MoO x ), cuprous iodide (CuI), and cuprous thiocyanate (CuSCN), can transport holes and block electron transmission.

[0076] In this embodiment, the hole transport layer 13, perovskite absorption layer 2, and electron transport layer 21 constitute a perovskite cell; the P-type base doping layer 111, base passivation layer 112, textured silicon substrate 113, base surface passivation layer 114, and N-type base doping layer 115 constitute a textured crystalline silicon layer 11. The textured crystalline silicon layer 11 is a crystalline silicon cell, specifically, a crystalline silicon cell formed of single crystal silicon, polycrystalline silicon, or amorphous silicon semiconductor. Connecting the two cells to form a series structure through a tunneling layer 12 can achieve excellent surface passivation and selective carrier collection, thereby improving device performance.

[0077] The present invention provides a stacked cell, comprising a velvet substrate 1, a perovskite absorption layer 2, an electron transport layer 21, a buffer layer 22, a second conductive layer 23, and an anti-reflection layer 24. A method for simultaneously preparing the perovskite absorption layer 2 and the electron transport layer 21 is adopted, thereby reducing the risk of damage to the perovskite film during the preparation process, improving the film quality and interface contact performance, and thus improving the photoelectric conversion efficiency and stability of the cell device.

[0078] The following specific embodiments and comparative examples are provided to clearly and completely describe the technical solutions of the present invention. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0079] Example 1

[0080] Provided is a stacked cell, comprising a first metal electrode layer 101, a first conductive transparent layer 102, a P-type base doping layer 111, a base passivation layer 112, a textured silicon substrate 113, a base surface passivation layer 114, an N-type base doping layer 115, a tunneling layer 12, a hole transport layer 13, a perovskite absorption layer 2, an electron transport layer 21, a buffer layer 22, a second conductive transparent layer 232, a second metal electrode layer 231, and an anti-reflection layer 24, and is prepared by the following method, comprising the steps of:

[0081] Step 1: providing a textured silicon substrate 113, sequentially preparing a base passivation layer 112 and a P-type base doping layer 111 on the back side of the textured silicon substrate 113, and sequentially preparing a base surface passivation layer 114 and an N-type base doping layer 115 on the other side.

[0082] Step 2: Using magnetron sputtering, an ITO target is set, the power is controlled to 60 W, the operation time is 1.5 hours, and the first conductive transparent layer 102 is formed on the P-type base doped layer 111.

[0083] Step 3: Using the evaporation method, place the substrate sample prepared in the previous step into the evaporation chamber and wait for the evaporation vacuum to reach 2×10 -4 Pa, the evaporation voltage is adjusted to the evaporation temperature, the evaporation rate is controlled at 2.5 Å / s, and silver is evaporated to the first conductive transparent layer 102 to obtain the first metal electrode layer 101.

[0084] Step 4: Using magnetron sputtering, place the substrate sample prepared in the previous step on the mask and then place it in the magnetron sputtering equipment, control the power to 60W, run for 1 hour, and form a tunneling layer 12 on the N-type substrate doping layer 115. The tunneling layer 12 is silicon dioxide.

[0085] Step 5: Treat the substrate sample prepared in the previous step with UV-Ozone for 15 minutes, and use the spin coating method to prepare a hole transport layer dispersion. Weigh 0.05 mol NiOx powder and dissolve it in 1 ml ultrapure water, and ultrasonically vibrate for 20 minutes; evenly coat the hole transport layer dispersion on the surface of the tunneling layer 12, set the spin coating speed to 2000 rpm, the spin coating time to 40 seconds, and the solution volume to 100 ul; after the spin coating is completed, perform annealing operation at an annealing temperature of 450°C and an annealing time of 30 minutes to obtain a hole transport layer 13.

[0086] Step 6: Referring to FIG. 1 , lead iodide and cesium bromide are co-evaporated on the hole transport layer 13 to form a lead iodide thin film L1. The evaporation rate of lead iodide is controlled at 8 A / s, the evaporation rate of cesium bromide is controlled at 0.8 A / s, and the total evaporation time is controlled within 1000 s. The thickness of the formed film is 440 nm.

[0087] An ammonium salt solution is prepared by dissolving formamidine iodide (FAI), formamidine bromide (FABr), and methylammonium chloride (MACl) in an organic solvent in a certain ratio, wherein the ratio of FAI to FABr is 1:4.7, the ratio of methylammonium chloride (MACl) to the other two ammonium salt additives is 10%wt, and the solution concentration is controlled at 1M; the ammonium salt solution is spin-coated on the lead iodide film L1 at a spin-coating speed of 5000 rpm for 30 seconds to obtain an ammonium salt film L2. After the spin-coating is completed, the film is dried at a drying temperature of 100°C for 5 minutes;

[0088] The obtained substrate sample was placed in the ALD (atomic layer deposition) chamber, annealed, and water vapor and electron transport layer material (titanium oxide) were introduced. The deposition vacuum was 1×10 -4 Pa, the deposition channel temperature is 80°C, the deposition chamber temperature is 150°C, the water vapor precursor bottle opening parameter during the deposition process is 200 mSec per cycle, the total deposition time is 60 min, and the film thickness of the electron transport layer 21 is 10 nm. At the same time, the lead iodide film L1 and the ammonium salt film L2 react to obtain the perovskite absorption layer 2.

[0089] Step 7: Using atomic layer deposition, set the vacuum degree of the atomic layer deposition equipment to 0.5×10 4 Pa, the deposition pipeline temperature is 60° C., the deposition chamber temperature is 70° C., SnO 2 is evaporated onto the electron transport layer 21 to obtain the buffer layer 22 .

[0090] Step eight: using a magnetron sputtering method, setting an IZO target, controlling the power to 50 W, and operating for 1 hour, to form a second conductive transparent layer 232 on the buffer layer 22 .

[0091] Step 9: Using the evaporation method, place the substrate sample prepared in the previous step into the evaporation chamber and wait for the evaporation vacuum to reach 2×10 -4 Pa, the evaporation voltage is adjusted to the evaporation temperature, the evaporation rate is controlled at 2.5 Å / S, and silver is evaporated onto the second conductive transparent layer 232 to obtain the second metal electrode layer 231.

[0092] Step 10: Deposit magnesium fluoride on the second metal electrode layer 231 by evaporation, control the evaporation rate to 2Å / s, and the thickness to 100nm, and finally obtain a stacked battery.

[0093] Example 2

[0094] A stacked battery is provided, which has the same device structure as that of Example 1, but the difference in the preparation method from that of Example 1 is that the opening parameter of the water vapor precursor bottle in step 6 is 400 mSec per cycle.

[0095] Example 3

[0096] A stacked battery is provided, which has the same device structure as that of Example 1, but the difference in the preparation method from that of Example 1 is that the opening parameter of the water vapor precursor bottle in step 6 is 600 mSec per cycle.

[0097] Comparative Example 1

[0098] A stacked battery is provided, which has the same device structure as Example 1, wherein the electron transport layer 21 is C 60 Preparation: The preparation method does not adopt an integrated film forming method to prepare the perovskite / electron transport layer structure. Step 6 in this comparative example is:

[0099] Lead iodide and cesium bromide are co-evaporated on the hole transport layer 13 to form a lead iodide film L1, the evaporation rate of lead iodide is 8A / s, the evaporation rate of cesium bromide is controlled at 0.8A / s, the total evaporation time is controlled between 1000s, and the thickness of the formed film is 440nm; an ammonium salt solution is prepared, and formamidine iodide (FAI), formamidine bromide (FABr), and methylammonium chloride (MACl) are dissolved in an organic solvent in a certain proportion, the ratio of FAI to FABr is between 1:4.7, the ratio of methylammonium chloride (MACl) to the other two ammonium salt additives is 10%wt, and the solution concentration is controlled at 1M; the ammonium salt solution is spin-coated on the lead iodide film L1 at a spin-coating speed of 5000rpm and a spin-coating time of 30s to obtain an ammonium salt film L2. After the spin-coating is completed, annealing is performed at an annealing temperature of 150°C and a drying time of 10 min, and obtain the perovskite absorption layer 2; using the evaporation method, place the above substrate sample on the mask, put it into the evaporation chamber, and wait for the evaporation vacuum degree to be 1×10 -4 Pa, the evaporation voltage was adjusted to the evaporation temperature, and the evaporation rate was controlled at 0.1-0.15Å / S. 60 Evaporated onto the perovskite absorption layer 2 to obtain the electron transport 21 with a thickness of 20 nm.

[0100] Comparative Example 2

[0101] A stacked cell is provided. The difference from the device structure of Example 1 is that there is no electron transport layer 21. The buffer layer 22 (tin oxide) is directly prepared on the perovskite absorption layer 2 and prepared by a traditional atomic layer deposition method. It plays the role of the electron transport layer. The difference between its preparation method and that of Example 1 lies in step 6:

[0102] Lead iodide and cesium bromide are co-evaporated on the hole transport layer 13 to form a lead iodide film L1, the evaporation rate of lead iodide is 8A / s, the evaporation rate of cesium bromide is controlled at 0.8A / s, the total evaporation time is controlled between 1000s, and the thickness of the formed film is 440nm; an ammonium salt solution is prepared, and formamidine iodide (FAI), formamidine bromide (FABr), and methylammonium chloride (MACl) are dissolved in an organic solvent in a certain proportion, the ratio of FAI to FABr is between 1:4.7, the ratio of methylammonium chloride (MACl) to the other two ammonium salt additives is 10%wt, and the solution concentration is controlled at 1M; the ammonium salt solution is spin-coated on the lead iodide film L1 at a spin-coating speed of 5000rpm and a spin-coating time of 30s to obtain an ammonium salt film L2. After the spin-coating is completed, annealing is performed at an annealing temperature of 150°C and a drying time of 10 min to obtain a perovskite absorption layer 2.

[0103] A solar simulator was used to perform a standard solar intensity calibration and a 1.0 cm 2 The embodiment and comparative device were subjected to long-term IV testing, with the starting voltage set to 2.2V, the cut-off voltage set to 0V, the range set to 100 mA, and the results rounded to two decimal places. The test results are shown in the following table:

[0104] Device electron transport layer transmittance (%) Open circuit voltage (V) Short circuit current density (mA / cm 2 ) Photoelectric conversion efficiency (%) Example 1 951.98 2031.3 Example 2 952.03 20.23 3 Example 3 952.01 19.9 31.9 Comparative Example 1 891.95 19.3 28.9 Comparative Example 2 951.61 20.4 21.3

[0105] From the test data obtained in the experiment, it can be seen that in Comparative Example 1, due to the use of C 60As an electron transport layer, although it can protect the perovskite film from water vapor erosion, it will also affect the transmittance of the electron transport layer and reduce the light absorption of the absorption layer. In Comparative Example 2, although the atomic layer deposition method is directly used to prepare an oxide as an electron transport layer on the perovskite absorption layer, the light transmittance of the device can be improved. However, during the preparation of the oxide electron transport layer, water vapor will damage the perovskite film, thereby reducing the photoelectric conversion efficiency of the device. Examples 1 to 3 can maintain good electrical and optical properties of the film, and the transmittance of its electron transport layer can be guaranteed to be around 95%, which greatly increases the light absorption efficiency of the device. The use of the perovskite / electron transport layer integrated film forming method to prepare the stacked cell can well solve the problem of water vapor erosion of the perovskite film in the traditional atomic deposition method, and can use water vapor to help the reactant molecules of the perovskite reaction diffuse, thereby improving the reaction efficiency. In particular, in Example 2, the water vapor introduction is best when it is 400 mSec per cycle. This is reflected in the fact that the stacked device of Example 2 based on the optimized parameters has a higher photoelectric conversion efficiency and open circuit voltage than Examples 1 and 3.

[0106] The above embodiments are only preferred implementation modes of the present invention. It should be pointed out that for ordinary technicians in this technical field, various changes, modifications, replacements and deformations can be made to these embodiments without departing from the principles of the present invention. These technical solutions that are equivalent to the claims of the present invention all fall within the scope of protection of the present invention, and the scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A perovskite / electron transport layer integrated film forming method, characterized in that: Including steps: A textured substrate is provided, lead iodide and cesium bromide are co-evaporated on the textured substrate to form a lead iodide film, an ammonium salt solution is spin-coated on the lead iodide film to obtain an ammonium salt film, and after the spin coating is completed, the film is dried; the obtained substrate sample is placed in an ALD chamber, annealed, and water vapor and an electron transport layer material are introduced to obtain a perovskite absorption layer and an electron transport layer deposited thereon on the surface of the textured substrate.

2. The perovskite / electron transport layer integrated film forming method according to claim 1, characterized in that: The evaporation rate of the lead iodide is controlled at 0-10A / s, the evaporation rate of the cesium bromide is controlled at 0-10A / s, the total evaporation time is between 0 and 10000 s, and the thickness of the formed lead iodide film is 200-800nm.

3. The perovskite / electron transport layer integrated film forming method according to claim 1, characterized in that: The ammonium salt solution is prepared by dissolving formamidine iodide (FAI), formamidine bromide (FABr) and methylammonium chloride (MACl) in an organic solvent in a certain proportion, wherein the volume ratio of FAI and FABr is between 10:1 and 1:10; the volume ratio of MACl to the two ammonium salt additives FAI and FABr is between 0% and 50%, and the solution concentration is controlled between 0.5-2 M; the organic solvent includes at least one of ethanol, isopropanol, methanol, dimethylformamide (DMF), g-butyrolactone (GBL), dimethyl sulfoxide (DMSO) and N,N-dimethylacetamide (DMA), and the solvent volume ratio is between 0-3:10-7.

4. The perovskite / electron transport layer integrated film forming method according to claim 1, characterized in that: The spin coating speed of the ammonium salt solution is 1200-6000 rpm, the spin coating time is 20-120 s, and after the spin coating is completed, the solution is dried at a temperature of 50-100° C. for 5-10 min to obtain the ammonium salt film with a thickness of 200-800 nm.

5. The perovskite / electron transport layer integrated film forming method according to claim 1, characterized in that: The temperature inside the ALD chamber is 100-200°C, the temperature of the pipe entering the ALD chamber is between 50-150°C, the water vapor in the ALD chamber is controlled by a water vapor precursor bottle, and the opening parameter is 100-800 mSec per cycle. At the same time, the electron transport layer material is deposited on the ammonium salt film, and the deposition vacuum is 0-1×10 -4 Pa, total deposition time 0~120min, and control the film thickness between 5~40nm.

6. The perovskite / electron transport layer integrated film forming method according to claim 1, characterized in that: The electron transport layer material is at least one of zinc oxide, tin dioxide and titanium dioxide.

7. The method for forming an integrated perovskite / electron transport layer film according to claim 1, wherein: The preparation of the suede substrate comprises: A textured silicon substrate is provided, and a base passivation layer, a P-type base doping layer, and a first conductive layer are sequentially prepared on one side of the textured silicon substrate; and a base surface passivation layer, an N-type base doping layer, a tunneling layer, and a hole transport layer are sequentially prepared on the other side of the textured silicon substrate to obtain the textured substrate, wherein the perovskite absorption layer is formed on the hole transport layer.

8. The method for forming an integrated perovskite / electron transport layer according to any one of claims 1 to 7, wherein: The method further includes sequentially forming a buffer layer, a second conductive layer, and an anti-reflection layer on the surface of the electron transport layer.

9. A stacked cell, prepared by the perovskite / electron transport layer integrated film forming method according to any one of claims 1 to 8, characterized in that: The invention comprises a suede substrate; and a perovskite absorption layer, an electron transport layer, a buffer layer, a second conductive layer and an anti-reflection layer sequentially arranged on the surface of the suede substrate.

10. The stacked battery according to claim 9, characterized in that: The textured substrate includes a textured crystalline silicon layer; a tunneling layer and a hole transport layer sequentially arranged on one surface of the textured crystalline silicon layer, the perovskite absorption layer is arranged on the hole transport layer; and a first conductive layer arranged on the other surface of the textured crystalline silicon layer.

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