Imaging element and electronic device

Abstract

The present disclosure relates to an electronic device and an imaging element configured so as to be able to avoid further degradation in performance. The imaging element is provided with, for each of a plurality of pixels, a single-photon avalanche diode (SPAD) that generates avalanche multiplication as a result of the supply of a reverse bias voltage, the imaging element further comprising: a storage unit into which address information indicating an address of a defective pixel has been written; a digital processing circuit that outputs a pixel selection signal, for selecting the defective pixel, in accordance with the address information read from the storage unit; and a retention unit that is provided for each pixel and retains defect information indicating whether the pixel is a defective pixel. For each pixel, the retention unit provided in a pixel selected by the pixel selection signal output from the digital processing circuit retains defect information indicating that the pixel is defective, and outputs a control signal for blocking supply of the reverse bias voltage to the SPAD. The present technology can be applied to, for example, an imaging element in which a SPAD is used.

Description

Image sensor and electronic device

[0001] The present disclosure relates to an imaging element and an electronic device, and more particularly to an imaging element and an electronic device that are able to further avoid performance degradation.

[0002] Conventionally, imaging devices have been developed that use SPADs (Single Photon Avalanche Diodes), which have a pixel structure that utilizes avalanche multiplication to amplify electrons from a single incident photon.

[0003] For example, Japanese Patent Application Laid-Open No. 2003-144999 discloses a solid-state imaging device in which a reverse bias voltage less than the breakdown voltage of an avalanche photodiode provided in a defective pixel is applied to the avalanche photodiode.

[0004] Japanese Patent Application Laid-Open No. 2019-115032

[0005] However, in an image sensor using a SPAD, if a pixel is defective, the defective pixel can adversely affect the normal pixels around it, causing the normal pixels to be treated as defective as well, which has raised concerns that this could degrade the performance of the image sensor.

[0006] The present disclosure has been made in light of such circumstances, and aims to make it possible to further avoid degradation of performance.

[0007] An imaging element according to one aspect of the present disclosure includes a plurality of pixels each provided with a SPAD that generates avalanche multiplication when a reverse bias voltage is supplied, and control is performed to cut off the supply of the reverse bias voltage to the SPAD for each of the pixels according to address information indicating the address of a defective pixel.

[0008] An electronic device according to one aspect of the present disclosure includes an imaging element having a plurality of pixels each provided with a SPAD that generates avalanche multiplication when a reverse bias voltage is supplied, and in which control is performed to cut off the supply of the reverse bias voltage to the SPAD for each of the pixels in accordance with address information indicating the address of a defective pixel.

[0009] In one aspect of the present disclosure, a SPAD that generates avalanche multiplication when a reverse bias voltage is supplied is provided in multiple pixels, and control is performed to cut off the supply of reverse bias voltage to the SPAD for each pixel according to address information indicating the address of the defective pixel.

[0010] FIG. 1 is a block diagram showing a first configuration example of an imaging element. FIG. 2 is a timing chart illustrating a sequence for writing defect information. FIG. 3 is a block diagram showing a second configuration example of an imaging element. FIG. 4 is a timing chart illustrating a sequence for writing defect information. FIG. 5 is a block diagram showing a third configuration example of an imaging element. FIG. 6 is a diagram illustrating an address decode circuit and an electronic fuse. FIG. 7 is a block diagram showing a fourth configuration example of an imaging element. FIG. 8 is a block diagram showing a fifth configuration example of an imaging element. FIG. 9 is a diagram illustrating shifting defect information to an adjacent flip-flop. FIG. 10 is a block diagram showing a configuration example of an imaging device. FIG. 11 is a diagram illustrating an example of use in which an image sensor is used.

[0011] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

[0012] <First Configuration Example of Image Sensor> A configuration example of a first embodiment of an image sensor to which the present technology is applied will be described with reference to FIGS. 1 and 2 .

[0013] FIG. 1 shows a block diagram of an image sensor 11 as a first configuration example.

[0014] 1 is configured by stacking a sensor substrate 12 and a logic substrate 13. In the image sensor 11, a plurality of pixels 14 are arranged in an array, and each pixel 14 has a sensor unit 21 provided on the sensor substrate 12 and a pixel control unit 22 provided on the logic substrate 13. In addition, a digital processing circuit 23 and a non-volatile memory 24 are provided on the logic substrate 13.

[0015] The sensor unit 21 includes a SPAD 31 , an inverting buffer 32 , and a PMOS (P-Channel Metal-Oxide Semiconductor) transistor 33 .

[0016] When a control signal PDEF supplied from the pixel control unit 22 to the gate electrode of the PMOS transistor 33 is at a low level, the sensor unit 21 is controlled so that the PMOS transistor 33 is turned on, a reverse bias voltage HVDD is supplied to the SPAD 31, and avalanche multiplication occurs in the SPAD 31. In this case, every time a photon is incident on the SPAD 31, a large current flows in the SPAD 31 due to avalanche multiplication, causing a change in the potential of the input terminal of the inverting buffer 32, and a pulse signal whose waveform has been shaped in the inverting buffer 304 is output from the sensor unit 21.

[0017] On the other hand, in the sensor unit 21, when the control signal PDEF supplied from the pixel control unit 22 to the gate electrode of the PMOS transistor 33 is at a high level, the PMOS transistor 33 is turned off, and the reverse bias voltage HVDD is not supplied to the SPAD 31, so that avalanche multiplication does not occur in the SPAD 31.

[0018] The pixel control unit 22 includes a counter 41 , an AND circuit 42 , and a latch 43 .

[0019] The counter 41 counts the pulse signal output from the inversion buffer 32 of the sensor unit 21 to measure the number of photons incident on the SPAD 31 .

[0020] The AND circuit 42 outputs a set signal SET that sets defect information to the latch 43 in accordance with the pixel selection signal supplied from the digital processing circuit 23. For example, when the vertical selection signal VSEL and the horizontal selection signal HSEL supplied from the digital processing circuit 23 are both at a high level, the AND circuit 42 supplies a high-level set signal SET to the latch 43. On the other hand, when at least one of the vertical selection signal VSEL and the horizontal selection signal HSEL supplied from the digital processing circuit 23 is at a low level, the AND circuit 42 supplies a low-level set signal SET to the latch 43.

[0021] The latch 43 is a holding unit that holds one bit of defect information indicating whether or not the pixel 14 is defective, and in accordance with the defect information, outputs a control signal PDEF to be supplied to the gate electrode of the PMOS transistor 33. The latch 43 is reset in accordance with the reset signal Reset supplied from the digital processing circuit 23, and then holds the defect information in accordance with the set signal SET supplied from the AND circuit 42.

[0022] For example, when a high-level set signal SET is supplied from the AND circuit 42 to the latch 43, the latch 43 holds one-bit defect information indicating that the pixel 14 is defective, and supplies a high-level control signal PDEF to the gate electrode of the PMOS transistor 33. On the other hand, when a low-level set signal SET is supplied from the AND circuit 42 to the latch 43, the latch 43 holds one-bit defect information indicating that the pixel 14 is not defective, and supplies a low-level control signal PDEF to the gate electrode of the PMOS transistor 33.

[0023] The digital processing circuit 23 supplies a reset signal Reset to the latch 43 to reset the latch 43, and supplies a vertical selection signal VSEL and a horizontal selection signal HSEL, which are pixel selection signals for selecting only defective pixels 14 one by one, to the AND circuit 42. For example, after resetting the latches 43 of all pixels 14, the digital processing circuit 23 supplies a high-level vertical selection signal VSEL and a high-level horizontal selection signal HSEL to the defective pixel 14 in accordance with the address information read from the nonvolatile memory 24. In other words, the digital processing circuit 23 controls the output of the pixel selection signal so that one-bit defect information indicating that the pixel 14 is defective is written to the latch 43 of the defective pixel 14.

[0024] The nonvolatile memory 24 stores address information indicating the addresses of pixels 14 that have been detected as being defective during shipping testing of the imaging device 11, for example.

[0025] In this way, the image sensor 11 is provided with a latch 43 below each pixel 14, and one bit of defect information indicating that the pixel 14 is defective can be written to the latch 43 of the defective pixel 14 in accordance with a pixel selection signal output from the digital processing circuit 23. For example, after powering on the image sensor 11, the digital processing circuit 23 reads address information from the nonvolatile memory 24, and, in accordance with the address information, sets the vertical selection signal VSEL supplied to the row of the defective pixel 14 to a high level, and sets the horizontal selection signal HSEL supplied to the column of the defective pixel 14 to a high level.

[0026] As a result, in the image sensor 11, the latch 43 outputs a high-level control signal PDEF in the defective pixel 14, turning off the PMOS transistor 33 and cutting off the reverse bias voltage HVDD supplied to the SPAD 31. Therefore, the image sensor 11 can accurately select only the defective pixel 14 and perform control so as to prevent avalanche multiplication from occurring in the SPAD 31 of the defective pixel 14. This prevents the defective pixel 14 from adversely affecting normal pixels 14 around the defective pixel 14, and prevents the normal pixels 14 from being treated as defective, thereby preventing performance degradation due to such adverse effects.

[0027] For example, if the SPAD 31 of a certain pixel 14 is defective, a large amount of current may flow through the SPAD 31, which may adversely affect normal pixels 14 around the defective pixel 14 (e.g., IR drop or malfunction of the counter 41). The image sensor 11 can prevent such adverse effects from the defective pixel 14 by cutting off the reverse bias voltage HVDD supplied to the SPAD 31 of the defective pixel 14. Furthermore, since the defective pixel 14 cannot accurately detect photons even if the SPAD 31 is operating, the image sensor 11 can suppress unnecessary power consumption by cutting off the reverse bias voltage HVDD. Furthermore, the image sensor 11 can improve yield.

[0028] The digital processing circuit 23 can write defect information to the latch 43 for each defective pixel 14. Alternatively, the digital processing circuit 23 may write defect information to the latch 43 for multiple defective pixels 14 simultaneously (for example, by scanning the vertical selection signal VSEL one bit at a time and simultaneously switching multiple bits of the horizontal selection signal HSEL from low level to high level).

[0029] With reference to the timing chart shown in FIG. 2, a sequence for writing 1-bit defect information indicating that a pixel 14 is defective to the latch 43 of the defective pixel 14 will be described.

[0030] At timing t1, the digital processing circuit 23 outputs a reset signal that goes high with a predetermined pulse width to all the pixels 14, thereby resetting the latches 43 of all the pixels 14.

[0031] Then, at timing t2 after the reset signal Reset has gone low, the digital processing circuit 23 switches the vertical selection signal VSEL, which is output to the row in which the defective pixel 14 is located, from low to high in accordance with the address information.

[0032] After that, at timing t3, the digital processing circuit 23 switches, in accordance with the address information, the horizontal selection signal HSEL output to the column in which the defective pixel 14 is located, from low to high, thereby switching the set signal SET output from the AND circuit 42 from low to high, and one-bit defect information indicating that the pixel 14 is defective is held in the latch 43.

[0033] Then, at timing t4, the digital processing circuit 23 switches the vertical selection signal VSEL and the horizontal selection signal HSEL from high level to low level, whereby the set signal SET output from the AND circuit 42 switches from high level to low level.

[0034] In this way, one bit of defect information indicating that the pixel 14 is defective can be written to the latch 43 of the defective pixel 14 .

[0035] In the example shown in FIG. 2, the vertical selection signal VSEL is first switched from a low level to a high level, and then the horizontal selection signal HSEL is switched from a low level to a high level. However, for example, the horizontal selection signal HSEL may be first switched from a low level to a high level, and then the vertical selection signal VSEL may be switched from a low level to a high level.

[0036] <Second Configuration Example of Image Sensor> A configuration example of a second embodiment of an image sensor to which the present technology is applied will be described with reference to FIGS. 3 and 4 .

[0037] Fig. 3 shows a block diagram of an image sensor 11A as a second configuration example. In the image sensor 11A shown in Fig. 3, components common to those of the image sensor 11 in Fig. 1 are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0038] As shown in Fig. 3, the imaging element 11A is configured by stacking a sensor substrate 12 and a logic substrate 13A, and the sensor unit 21 provided on the sensor substrate 12 has a configuration common to the imaging element 11 in Fig. 1. The imaging element 11A also has a configuration common to the imaging element 11 in Fig. 1 in that it includes a non-volatile memory 24, a counter 41, and an AND circuit 42.

[0039] The imaging element 11A differs from the imaging element 11 of FIG. 1 in that it includes a digital processing circuit 23A provided on a logic board 13A, and an AND circuit 44 and a flip-flop 45 provided in a pixel control unit 22A of a pixel 14A.

[0040] The digital processing circuit 23A supplies a reset signal Reset to the flip-flop 45 for resetting the flip-flop 45, and supplies a vertical selection signal VSEL and a horizontal selection signal HSEL, which are pixel selection signals for selecting only defective pixels 14 one by one, to the AND circuit 42. Furthermore, the digital processing circuit 23A supplies a clock signal CLK to the AND circuit 44 for controlling the flip-flop 45.

[0041] The AND circuit 44 receives the set signal SET output from the AND circuit 42 and the clock signal CLK output from the digital processing circuit 23A. When the set signal SET supplied from the AND circuit 42 is at a high level, the AND circuit 44 supplies the local clock signal Local CLK in accordance with the clock signal CLK supplied from the digital processing circuit 23A to the flip-flop 45. On the other hand, when the set signal SET supplied from the AND circuit 42 is at a low level, the AND circuit 44 stops outputting the local clock signal Local CLK (always at a low level).

[0042] The flip-flop 45 is a holding unit that holds one bit of defect information indicating whether the pixel 14 is defective or not, and outputs a control signal PDEF to be supplied to the gate electrode of the PMOS transistor 33 in accordance with the defect information. The flip-flop 45 is reset in accordance with the reset signal Reset supplied from the digital processing circuit 23, and then holds the defect information in accordance with the set signal SET supplied from the AND circuit 42 and the local clock signal Local CLK supplied from the AND circuit 44.

[0043] For example, when a high-level set signal SET is supplied from the AND circuit 42, the flip-flop 45 holds one bit of defect information indicating that the pixel 14 is defective, and supplies a high-level control signal PDEF to the gate electrode of the PMOS transistor 33, at the timing when the local clock signal Local CLK supplied from the AND circuit 44 is switched from low to high. On the other hand, when the set signal SET supplied from the AND circuit 42 is low, the latch 43 holds one bit of defect information indicating that the pixel 14 is not defective, and supplies a low-level control signal PDEF to the gate electrode of the PMOS transistor 33.

[0044] In this way, the image sensor 11A is provided with a flip-flop 45 below each pixel 14A, and one bit of defect information indicating that the pixel 14A is defective can be written to the flip-flop 45 of the defective pixel 14A in accordance with a pixel selection signal output from the digital processing circuit 23A. For example, after powering on the image sensor 11A, the digital processing circuit 23A reads address information from the non-volatile memory 24, and, in accordance with the address information, sets the vertical selection signal VSEL supplied to the row of the defective pixel 14A to a high level, and sets the horizontal selection signal HSEL supplied to the column of the defective pixel 14A to a high level.

[0045] As a result, in the image sensor 11A, in the defective pixel 14A, the flip-flop 45 outputs a high-level control signal PDEF to turn off the PMOS transistor 33, thereby cutting off the reverse bias voltage HVDD supplied to the SPAD 31. Therefore, similar to the image sensor 11 in FIG. 1, the image sensor 11A can avoid degradation of performance due to adverse effects exerted by the defective pixel 14A on normal pixels 14A.

[0046] With reference to the timing chart shown in FIG. 4, a sequence for writing one bit of defect information indicating that the pixel 14A is defective to the flip-flop 45 of the defective pixel 14A will be described.

[0047] At timing t1, the digital processing circuit 23A outputs a reset signal that goes to a high level with a predetermined pulse width to all the pixels 14A, resetting the flip-flops 45 of all the pixels 14A.

[0048] Then, at timing t2 after the reset signal Reset has gone low, the digital processing circuit 23A switches, in accordance with the address information, the vertical selection signal VSEL_0 output to the row in which the defective pixel 14A is located from low to high, and switches the horizontal selection signal HSEL_0 output to the column in which the defective pixel 14 is located from low to high, thereby switching the set signal SET output from the AND circuit 42 from low to high.

[0049] Thereafter, at timing t3 when the clock signal CLK output from the digital processing circuit 23 is switched from low to high, the local clock signal Local CLK output from the AND circuit 44 is switched from low to high, causing the flip-flop 45 to hold one bit of defect information indicating that the pixel 14A is defective, and outputting a high control signal PDEF from the flip-flop 45.

[0050] At timing t4 when the clock signal CLK output from the digital processing circuit 23 is switched from high to low, the digital processing circuit 23A switches the vertical selection signal VSEL and the horizontal selection signal HSEL from high to low. Accordingly, the set signal SET output from the AND circuit 42 is switched from high to low, and the local clock signal Local CLK output from the AND circuit 44 is switched from high to low. At this time, the flip-flop 45 continues to output the control signal PDEF at high level.

[0051] In this way, one bit of defect information indicating that the pixel 14A is defective can be written to the flip-flop 45 of the defective pixel 14A.

[0052] <Third Configuration Example of Image Sensor> A configuration example of a third embodiment of an image sensor to which the present technology is applied will be described with reference to Figs. 5 and 6 .

[0053] Fig. 5 shows a block diagram of an image sensor 11B as a third example configuration. In the image sensor 11B shown in Fig. 5, components common to those of the image sensor 11 in Fig. 1 are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0054] As shown in Fig. 5, the imaging element 11B is configured by stacking a sensor substrate 12 and a logic substrate 13B, and the sensor unit 21 provided on the sensor substrate 12 has a configuration common to the imaging element 11 in Fig. 1. The imaging element 11B also has a configuration common to the imaging element 11 in Fig. 1 in that it includes a counter 41.

[0055] The imaging element 11B has a different configuration from the imaging element 11 of FIG. 1 in that it has an address decode circuit 25 and an electronic fuse 26 provided on the logic board 13B, and an AND circuit 42B provided in the pixel control unit 22B of the pixel 14B.

[0056] The address decode circuit 25 decodes the address information written in the electronic fuse 26 and supplies a vertical selection signal VSEL and a horizontal selection signal HSEL, which are pixel selection signals for selecting only the defective pixels 14B one by one, to the AND circuit 42B. For example, the address decode circuit 25 supplies a high-level vertical selection signal VSEL and a high-level horizontal selection signal HSEL to the defective pixels 14B in accordance with the address information.

[0057] The electronic fuse 26 stores, for example, address information of pixels 14B that have been detected as defective during shipping testing of the imaging device 11B (H addresses and V addresses corresponding to the number of defective pixels 14B).

[0058] 6, for example, a set of an H address and a V address for each defective pixel 14B is stored in the electronic fuse 26. After reading the H address and V address from the electronic fuse 26, the address decode circuit 25 decodes them into a vertical selection signal VSEL and a horizontal selection signal HSEL, and performs control so that defective pixels 14B can be selected one by one from among the multiple pixels 14B arranged in the pixel array section.

[0059] When the vertical selection signal VSEL and the horizontal selection signal HSEL supplied from the address decode circuit 25 are both at a high level, the AND circuit 42B supplies a high-level control signal PDEF to the gate electrode of the PMOS transistor 33. On the other hand, when at least one of the vertical selection signal VSEL and the horizontal selection signal HSEL supplied from the address decode circuit 25 is at a low level, the AND circuit 42B supplies a low-level control signal PDEF to the gate electrode of the PMOS transistor 33.

[0060] In this way, in the image sensor 11B, the address information written in the electronic fuse 26 is decoded and, in accordance with the pixel selection signal output from the address decode circuit 25, the AND circuit 42B outputs a high-level control signal PDEF in the defective pixel 14B to turn off the PMOS transistor 33 and cut off the reverse bias voltage HVDD supplied to the SPAD 31. Therefore, similar to the image sensor 11 in FIG. 1 , the image sensor 11B can avoid degradation of performance due to adverse effects exerted by the defective pixel 14B on normal pixels 14B.

[0061] <Fourth Configuration Example of Image Sensor> A configuration example of a fourth embodiment of an image sensor to which the present technology is applied will be described with reference to FIG.

[0062] Fig. 7 shows a block diagram of an image sensor 11C as a fourth configuration example. In the image sensor 11C shown in Fig. 7, components common to the image sensor 11 in Fig. 1 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0063] As shown in Fig. 7, the imaging element 11C is configured by stacking a sensor substrate 12 and a logic substrate 13C, and the sensor unit 21 provided on the sensor substrate 12 has a configuration common to the imaging element 11 in Fig. 1. The imaging element 11C also has a configuration common to the imaging element 11 in Fig. 1 in that it includes a non-volatile memory 24 and a counter 41.

[0064] The imaging device 11C differs from the imaging device 11 in FIG. 1 in that it includes a frame memory 27 provided on a logic board 13C.

[0065] The frame memory 27 has memory sections corresponding to all pixels 14C provided in the image sensor 11C, and each memory section holds one bit of defect information for each pixel 14C. The frame memory 27 is configured so that each memory section outputs a control signal PDEF to its corresponding pixel 14C. For example, after power is applied to the image sensor 11C, the frame memory 27 can read address information from the non-volatile memory 24 and write the defect information to the memory section corresponding to the address of the defective pixel 14C. As a result, the frame memory 27 outputs a high-level control signal PDEF to the defective pixel 14C, turning off the PMOS transistor 33 and cutting off the reverse bias voltage HVDD supplied to the SPAD 31.

[0066] Therefore, similar to the image sensor 11 in FIG. 1, the image sensor 11C can avoid degradation of performance due to adverse effects of defective pixels 14C on normal pixels 14C.

[0067] <Fifth Configuration Example of Image Sensor> A configuration example of a fifth embodiment of an image sensor to which the present technology is applied will be described with reference to Figs. 8 and 9 .

[0068] Fig. 8 shows a block diagram of an image sensor 11D as a fifth example configuration. In the image sensor 11D shown in Fig. 8, components common to those of the image sensor 11A in Fig. 3 are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0069] 8, pixel control units 22D provided for a plurality of pixels 14D of an image sensor 11D are illustrated as being arranged in an array, and like the pixel control unit 22A in Fig. 3, the pixel control unit 22D is configured to include a flip-flop 45 and a counter 41. Note that the sensor unit 21 and the non-volatile memory 24 are not illustrated in Fig. 8.

[0070] The image sensor 11D is configured such that horizontally adjacent flip-flops 45 are connected to each other, with the side on which the digital processing circuit 23D is provided being the upstream side, and defect information is shifted and transmitted sequentially from the upstream flip-flop 45 to the downstream flip-flop 45.

[0071] The digital processing circuit 23D outputs a reset signal Reset for resetting the flip-flops 45, a setting signal for setting defect information for the most upstream flip-flop 45, and a clock signal CLK for controlling the flip-flops 45.

[0072] The flip-flop 45 holds the defect information according to the setting signal supplied from the digital processing circuit 23D or the defect information supplied from the upstream flip-flop 45 at the timing when the clock signal CLK is switched from low level to high level. Furthermore, at this timing, the flip-flop 45 supplies the defect information that it has held up to that point to the downstream flip-flop 45. The defect information output from the flip-flop 45 downstream is the same as the control signal PDEF supplied from the flip-flop 45 to the gate electrode of the PMOS transistor 33.

[0073] Shifting of defect information to adjacent flip-flops 45 will be described with reference to FIG.

[0074] 9, pixel 14D is represented by a dashed line, and the hatched pixel 14D is assumed to be defective. That is, of the nine flip-flops 45(0,0) to 45(2,2) arranged in a 3x3 array as shown in the figure, pixel 14D that includes flip-flops 45(1,0) and 45(2,2) is defective.

[0075] Then, at timing T0 after power is applied to the image sensor 11D, the digital processing circuit 23D resets the flip-flops 45 of all pixels 14D, thereby setting the defect information held in the flip-flops 45 of all pixels 14D to 0 (=defect information indicating that none of the pixels 14D is defective).

[0076] Thereafter, at timing T1, the digital processing circuit 23D outputs 0 as a setting signal for setting the defect information to be held in the flip-flop 45(2,0), outputs 0 as a setting signal for setting the defect information to be held in the flip-flop 45(2,1), and outputs 1 as a setting signal for setting the defect information to be held in the flip-flop 45(2,2).

[0077] Then, at timing T2 when the clock signal CLK output from the digital processing circuit 23D to all pixels 14D is switched from low level to high level, in accordance with the setting signal output at timing T1, 0 is held as defect information in the flip-flop 45(0,0), 0 is held as defect information in the flip-flop 45(0,1), and 1 is held as defect information in the flip-flop 45(0,2). Furthermore, the digital processing circuit 23D outputs 1 as a setting signal for setting the defect information to be held in the flip-flop 45(1,0), outputs 0 as a setting signal for setting the defect information to be held in the flip-flop 45(1,1), and outputs 0 as a setting signal for setting the defect information to be held in the flip-flop 45(1,2).

[0078] Next, at timing T3 when the clock signal CLK output from the digital processing circuit 23D to all pixels 14D is switched from low level to high level, a 0 is transmitted as defect information from flip-flop 45(0,0) to flip-flop 45(1,0), a 0 is transmitted as defect information from flip-flop 45(0,1) to flip-flop 45(1,1), and a 1 is transmitted as defect information from flip-flop 45(0,2) to flip-flop 45(1,2), and each is held.

[0079] At the same time, in accordance with the setting signal output at timing T2, flip-flop 45(0,0) holds 1 as defect information, flip-flop 45(0,1) holds 0 as defect information, and flip-flop 45(0,2) holds 0 as defect information. Furthermore, digital processing circuit 23D outputs 0 as a setting signal for setting the defect information to be held in flip-flop 45(0,0), outputs 0 as a setting signal for setting the defect information to be held in flip-flop 45(0,1), and outputs 0 as a setting signal for setting the defect information to be held in flip-flop 45(0,2).

[0080] Then, at timing T4 when the clock signal CLK output from the digital processing circuit 23D to all pixels 14D is switched from low level to high level, a 0 is transmitted as defect information from flip-flop 45(1,0) to flip-flop 45(2,0), a 0 is transmitted as defect information from flip-flop 45(1,1) to flip-flop 45(2,1), and a 1 is transmitted as defect information from flip-flop 45(1,2) to flip-flop 45(2,2), and each is held.

[0081] At the same time, a 1 is transmitted as defect information from flip-flop 45(0,0) to flip-flop 45(1,0), a 0 is transmitted as defect information from flip-flop 45(0,1) to flip-flop 45(1,1), and a 0 is transmitted as defect information from flip-flop 45(0,2) to flip-flop 45(1,2), and these are held. Furthermore, in accordance with the setting signal output at timing T3, a 0 is held as defect information in flip-flop 45(0,0), a 0 is held as defect information in flip-flop 45(0,1), and a 0 is held as defect information in flip-flop 45(0,2).

[0082] Then, by stopping the transmission of defect information at this stage, the flip-flop 45(1,0) and the flip-flop 45(2,2) can be made to hold the defect information 1 (= defect information indicating that the pixel 14D is defective).

[0083] In this way, the image pickup device 11D can transmit defect information in sequence from the upstream flip-flop 45 to the downstream flip-flop 45, like a chain of beads.

[0084] <Configuration Example of Electronic Device> The imaging element 11 as described above can be applied to various electronic devices, such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0085] FIG. 10 is a block diagram showing an example of the configuration of an imaging device mounted on an electronic device.

[0086] As shown in FIG. 10, the imaging device 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still images and moving images.

[0087] The optical system 102 is configured to have one or more lenses, and guides image light (incident light) from a subject to the image sensor 103 , forming an image on the light receiving surface (sensor section) of the image sensor 103 .

[0088] The image sensor 103 is the image sensor 11 described above. Electrons are accumulated in the image sensor 103 for a certain period of time in accordance with an image formed on the light receiving surface via the optical system 102. A signal corresponding to the electrons accumulated in the image sensor 103 is then supplied to the signal processing circuit 104.

[0089] The signal processing circuit 104 performs various types of signal processing on the pixel signals output from the image sensor 103. The image (image data) obtained by the signal processing performed by the signal processing circuit 104 is supplied to a monitor 105 for display, or supplied to a memory 106 for storage (recording).

[0090] In the imaging device 101 configured in this manner, by applying the imaging element 11 described above, it is possible to capture high-quality images in which adverse effects from defective pixels 14 are suppressed, for example.

[0091] <Example of Use of Image Sensor> FIG. 11 is a diagram showing an example of use of the image sensor (imaging element) described above.

[0092] The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0093] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0094] <Examples of Combinations of Configurations> The present technology can also be configured as follows. (1) An imaging element including a plurality of pixels each provided with a SPAD (Single Photon Avalanche Diode) that generates avalanche multiplication when a reverse bias voltage is supplied thereto, wherein control is performed to cut off supply of the reverse bias voltage to the SPAD for each of the pixels in accordance with address information indicating an address of the defective pixel. (2) The imaging element according to (1) above further including: a storage unit that stores the address information; a digital processing circuit that outputs a pixel selection signal for selecting the defective pixel in accordance with the address information read from the storage unit; and a holding unit that is provided for each of the pixels and holds defect information indicating whether the pixel is defective, wherein the holding unit provided for the pixel selected by the pixel selection signal output from the digital processing circuit holds the defect information indicating that the pixel is defective, and outputs a control signal to cut off supply of the reverse bias voltage to the SPAD. (3) The image sensor according to (2) above, wherein the digital processing circuit controls the selection of the pixels one by one using, as the pixel selection signals, a vertical selection signal supplied to a row of the defective pixel and a horizontal selection signal supplied to a column of the defective pixel. (4) The image sensor according to (3) above, wherein the digital processing circuit controls the writing of the defect information to the holding unit in accordance with the address information read from the storage unit after the image sensor is powered on. (5) The image sensor according to (4) above, wherein the digital processing circuit writes the defect information to the holding unit one by one for each defective pixel. (6) The image sensor according to (4) above, wherein the digital processing circuit writes the defect information to the holding unit simultaneously for multiple defective pixels. (7) The image sensor according to any of (2) to (6) above, wherein the storage unit has written therein the address information of the pixel detected to be defective during shipping testing of the image sensor.(8) The image sensor according to any of (2) to (7) above, wherein the holding unit is a latch, and the digital processing circuit outputs a reset signal for resetting the latches of all the pixels, and the pixel selection signal for causing the latch of a defective pixel to hold the defect information indicating that the pixel is defective. (9) The image sensor according to any of (2) to (8) above, wherein the holding unit is a flip-flop, and the digital processing circuit outputs a reset signal for resetting the flip-flop of all the pixels, the pixel selection signal for causing the flip-flop of a defective pixel to hold the defect information indicating that the pixel is defective, and a clock signal for controlling the flip-flop. (10) The image sensor according to (1) above, further comprising: an electronic fuse in which the address information is written; and an address decode circuit that decodes the address information written in the electronic fuse and outputs a pixel selection signal for selecting only the defective pixels one by one, wherein a control signal for cutting off the supply of the reverse bias voltage to the SPAD is output at the pixel selected by the pixel selection signal. (11) The image sensor according to (1) above, further comprising: a storage unit in which the address information is written; and a frame memory having memory units corresponding to all the pixels, each memory unit holding defect information for each pixel indicating whether the pixel is defective, wherein a control signal for cutting off the supply of the reverse bias voltage to the SPAD is output from each memory unit to the corresponding pixel. (12) The image sensor according to (2) above, wherein the holding units of adjacent pixels are connected to each other, and the defect information is shifted and transmitted sequentially from the holding unit on the upstream side to the holding unit on the downstream side.(13) The image sensor according to (12), wherein the holding unit is a flip-flop, and the digital processing circuit outputs a reset signal for resetting the flip-flops of all the pixels, a setting signal for setting the defect information in the most upstream flip-flop, and a clock signal for controlling the flip-flop, and the flip-flop holds the defect information according to the setting signal supplied from the digital processing circuit or the defect information supplied from the upstream flip-flop at a timing when the clock signal is switched from a low level to a high level, and supplies the defect information held up to that point to the downstream flip-flop at this timing. (14) An electronic device comprising an image sensor having a plurality of pixels provided with SPADs (Single Photon Avalanche Diodes) that generate avalanche multiplication when a reverse bias voltage is supplied, and control is performed to cut off the supply of the reverse bias voltage to the SPAD for each of the pixels according to address information indicating the address of a defective pixel.

[0095] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0096] REFERENCE SIGNS LIST 11 imaging element, 12 sensor substrate, 13 logic substrate, 14 pixel, 21 sensor section, 22 pixel control section, 23 digital processing circuit, 24 non-volatile memory, 25 address decode circuit, 26 electronic fuse, 27 frame memory, 31 SPAD, 32 inversion buffer, 33 PMOS transistor, 41 counter, 42 AND circuit, 43 latch, 44 AND circuit, 45 flip-flop

Claims

1. An imaging device comprising a plurality of pixels each provided with a SPAD (Single Photon Avalanche Diode) that generates avalanche multiplication when a reverse bias voltage is supplied, and in which control is performed to cut off the supply of the reverse bias voltage to the SPAD for each of the pixels in accordance with address information indicating the address of a defective pixel.

2. The imaging element of claim 1, further comprising: a memory unit that stores the address information; a digital processing circuit that outputs a pixel selection signal for selecting a defective pixel in accordance with the address information read from the memory unit; and a holding unit that is provided for each pixel and holds defect information indicating whether the pixel is defective, wherein the holding unit provided for the pixel selected by the pixel selection signal output from the digital processing circuit holds the defect information indicating that the pixel is defective and outputs a control signal to cut off the supply of the reverse bias voltage to the SPAD.

3. The image sensor according to claim 2, wherein the digital processing circuit controls the selection of the pixels one by one using, as the pixel selection signals, a vertical selection signal supplied to the row of the defective pixel and a horizontal selection signal supplied to the column of the defective pixel.

4. The imaging device according to claim 3, wherein the digital processing circuit controls writing of the defect information to the holding section in accordance with the address information read from the memory section after power is applied to the imaging device.

5. The imaging device according to claim 4, wherein the digital processing circuit writes the defect information to the holding unit for each of the defective pixels.

6. The imaging device according to claim 4, wherein the digital processing circuit writes the defect information to the holding unit simultaneously for a plurality of defective pixels.

7. The imaging device according to claim 2, wherein the address information of the pixel detected as being defective during a shipping test of the imaging device is written in the memory unit.

8. The imaging element according to claim 2, wherein the holding unit is a latch, and the digital processing circuit outputs a reset signal for resetting the latches of all the pixels, and a pixel selection signal for causing the latch of a defective pixel to hold the defect information indicating that the pixel is defective.

9. The imaging element according to claim 2, wherein the holding unit is a flip-flop, and the digital processing circuit outputs a reset signal for resetting the flip-flops of all the pixels, a pixel selection signal for causing the flip-flop of a defective pixel to hold the defect information indicating that the pixel is defective, and a clock signal for controlling the flip-flop.

10. The imaging device according to claim 1, further comprising: an electronic fuse in which the address information is written; and an address decoding circuit that decodes the address information written in the electronic fuse and outputs a pixel selection signal for selecting only the defective pixels one by one, wherein a control signal for cutting off the supply of the reverse bias voltage to the SPAD is output from the pixel selected by the pixel selection signal.

11. The imaging element according to claim 1, further comprising: a storage unit in which the address information is written; and a frame memory having memory units corresponding to all of the pixels, each of which holds defect information for each pixel indicating whether the pixel is defective or not, wherein a control signal for cutting off the supply of the reverse bias voltage to the SPAD is output from each of the memory units to the corresponding pixel.

12. The image sensor according to claim 2, wherein the holding units of adjacent pixels are connected to each other, and the defect information is transmitted by shifting sequentially from the holding unit on the upstream side to the holding unit on the downstream side.

13. The image sensor according to claim 12, wherein the holding unit is a flip-flop, and the digital processing circuit outputs a reset signal for resetting the flip-flops of all the pixels, a setting signal for setting the defect information in the most upstream flip-flop, and a clock signal for controlling the flip-flop, and the flip-flop holds the defect information in accordance with the setting signal supplied from the digital processing circuit or the defect information supplied from the upstream flip-flop at the timing when the clock signal is switched from low level to high level, and at this timing supplies the defect information held up to that point to the downstream flip-flop.

14. An electronic device having an imaging element that has a plurality of pixels each provided with a SPAD (Single Photon Avalanche Diode) that generates avalanche multiplication when a reverse bias voltage is supplied, and in which control is performed to cut off the supply of the reverse bias voltage to the SPAD for each of the pixels according to address information indicating the address of a defective pixel.

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