Printer head and printer

Abstract

A printer head (12) comprises a light-emitting unit (13) having a plurality of light-emitting devices (L1i to L4i) for exposing a photosensitive drum (11). The plurality of light-emitting devices include first light-emitting devices (L1i) constituting a first row, second light-emitting devices (L2i) constituting a second row, third light-emitting devices (L3i) constituting a third row, and fourth light-emitting devices (L4i) constituting a fourth row. The first row and the second row have a first interval (Wy1). The second row and the third row have a second interval (Wy2). The third row and the fourth row have a third interval (Wy3). The second interval is greater than both the first and third intervals.

Description

Printer head and printer

[0001] The present disclosure relates to a printer head and a printer.

[0002] A technology has been developed in which a printer head having an array of light emitters is used to expose a photosensitive drum to light to form an image (see Japanese Patent Laid-Open No. 2003-222294).

[0003] Japanese Patent Application Publication No. 2014-179574

[0004] In the technology described above, the printer head has wiring for supplying current to multiple light emitters. Because multiple light emitters are arranged on the printer head, the wiring for one light emitter is located near the other light emitters. As a result, one light emitter may emit light influenced by the light emission state (current supply state) of the other light emitters, which may result in noise being mixed into the formed image.

[0005] An object of one aspect of the present disclosure is to realize a printer head and a printer that reduce interference between multiple light emitters.

[0006] A printer head according to one aspect of the present disclosure comprises a light-emitting unit having a plurality of light-emitting elements that expose a rotating photosensitive drum, and a current supply unit that supplies current to the light-emitting unit to cause the plurality of light-emitting elements to emit light, wherein the plurality of light-emitting elements include a plurality of first light-emitting elements that are arranged along a first direction and form a first row, a plurality of second light-emitting elements that are arranged along the first direction and form a second row, a plurality of third light-emitting elements that are arranged along the first direction and form a third row, and a plurality of fourth light-emitting elements that are arranged along the first direction and form a fourth row, wherein the first to fourth rows are arranged in order along a second direction that is different from the first direction, a first interval between the first row and the second row, a second interval between the second row and the third row, and a third interval between the third row and the fourth row, wherein the second interval is larger than both of the first and third intervals.

[0007] According to the present disclosure, it is possible to realize a printer head and a printer that aim to reduce interference between a plurality of light emitters.

[0008] 1 is a schematic diagram showing a printer according to an embodiment of the present disclosure; FIG. 2 is a plan view showing a printer head according to an embodiment of the present disclosure; FIG. 3 is an enlarged plan view showing an enlarged light-emitting section; FIG. 4 is a timing chart showing the timing of data signals and control signals; FIG. 5 is a circuit diagram showing an example of a pixel circuit; FIG. 6 is a schematic diagram showing pixels formed on a photosensitive drum; and FIG. 7 is a schematic diagram showing the corresponding relationship between the arrangement of light-emitting devices and pixels.

[0009] (Embodiment) A printer according to an embodiment of the present disclosure will be described below. Fig. 1 is a schematic diagram illustrating a printer 10 according to an embodiment of the present disclosure.

[0010] The printer 10 is an image forming device that forms an image on a sheet (for example, a paper surface), and includes a photosensitive drum 11 and a printer head 12 .

[0011] The photosensitive drum 11 is exposed to light by the printer head 12, and a latent image of the print data is formed on it. When the photosensitive drum 11 is charged and a photosensitive pattern corresponding to the image pattern is formed by the printer head 12, a charged pattern (latent image) is formed on the photosensitive drum 11. The photosensitive drum 11 has a rotation axis C, and is rotated around the rotation axis C by a rotation mechanism (not shown) during exposure, etc. At this time, the moving speed Vm of the rotating photosensitive drum 11 on its outer periphery can be expressed by the following formula (1): Vm = 2 x π x r x Vc Formula (1) Vm: moving speed of the photosensitive drum 11 on its outer periphery r: radius of the photosensitive drum 11 (distance from the rotation axis C to the outer periphery of the photosensitive drum 11) Vc: rotation speed of the photosensitive drum 11 [number of rotations / second]

[0012] In addition to the photosensitive drum 11 and the printer head 12, the printer 10 may also include a charging mechanism, a developing mechanism, a transfer mechanism, and a fixing mechanism. The charging mechanism charges the photosensitive drum 11. The developing mechanism develops the exposed photosensitive drum 11 with toner. That is, the developing mechanism forms a toner image by supplying toner to the exposed photosensitive drum 11. The transfer mechanism transfers the developed image on the photosensitive drum 11 onto a paper surface. The fixing mechanism fixes the toner image transferred onto the paper surface.

[0013] 2 is a plan view showing the printer head 12 according to the embodiment of the present disclosure. The printer head 12 irradiates a photosensitive drum 11 with a light pattern to form a latent image pattern on the photosensitive drum 11. The printer head 12 has a light-emitting unit 13, current supply units 14 (14a, 14b), drive units 15 (15a, 15b), a data output unit 16, a wiring switching unit 17, and a switching control unit 18.

[0014] The light-emitting unit 13 has a plurality of light emitters Li. The plurality of light emitters Li includes a plurality of first light emitters L1i, a plurality of second light emitters L2i, a plurality of third light emitters L3i, and a plurality of fourth light emitters L4i. The plurality of first to fourth light emitters L1i to L4i are all lined up along a first direction (in this example, the X-axis direction) and form first to fourth columns.

[0015] As shown in Fig. 1, light B emitted from these light emitters L1i to L4i is focused onto the photosensitive drum 11 by a lens (not shown). As a result, pixels D1i to D4i that make up the latent image are formed. In Fig. 2, for ease of understanding, the pixels D1i to D4i are shown by dotted lines superimposed on the light emitters L1i to L4i. This also applies to Fig. 3, which will be described later.

[0016] For ease of understanding, Figure 1 shows pixels D1i to D4i when light emitters L1i to L4i emit light at the same timing. In reality, the light emitters L1i and L2i and the light emitters L3i and L4i emit light at different timings, so the positional relationship of pixels D1i to D4i will differ from that shown in Figure 1. This will be described in detail later.

[0017] 3 is an enlarged plan view showing the light-emitting unit 13. The intervals Wy1 to Wy1 and Wx (Wx1 to Wx5) between the light emitters L1i to L4i will be described below with reference to FIG.

[0018] The first row (first light emitter L1i) and the second row (second light emitter L2i) of the light emitters L have a first spacing Wy1. The second row (second light emitter L2i) and the third row (third light emitter L3i) of the light emitters L have a second spacing Wy2. The third row (third light emitter L3i) and the fourth row (fourth light emitter L4i) have a third spacing Wy3.

[0019] The first interval Wy1 and the second interval Wy2 have sizes corresponding to each other. This means that the first interval Wy1 and the second interval Wy2 match each other within an error range. The error range means a level that is sufficiently smaller than the pitch (spacing) of the pixels D (for example, 1 / 10 or less), and as an example, is 1 / 10 or less of the first interval Wy1.

[0020] On the other hand, the second interval Wy2 is larger than both the first interval Wy1 and the third interval Wy3. This makes it possible to reduce interference between the first and second light emitters L1i, L2i and the third and fourth light emitters L1i, L2i. This will be described in detail later.

[0021] The first interval Wy1 and the third interval Wy3 correspond to n dots (n: an integer equal to or greater than 1) of pixels D on the photosensitive drum. On the other hand, the second interval Wy2 corresponds to less than (n+1) dots of pixels D on the photosensitive drum 11. Here, the first interval Wy1 and the third interval Wy3 correspond to 6 dots of pixels D on the photosensitive drum, and the second interval Wy2 corresponds to 6.5 (6+1 / 2) dots of pixels D on the photosensitive drum 11.

[0022] The first direction corresponds to the axial direction of the rotation axis C of the photosensitive drum 11, and the second direction corresponds to the movement direction on the circumferential surface of the rotating photosensitive drum 11. In this example, the first direction and the second direction correspond to the X-axis direction and the Y-axis direction.

[0023] The first to fourth light emitters L1i to L4i are arranged so as to be offset from one another in the first direction. Here, the first light emitter L21 in the second column is arranged offset by a distance Wx1 in the X-axis direction from the first light emitter L11 in the first column. Similarly, the light emitter L31 in the third column is arranged offset by a distance Wx2 in the X-axis direction from the light emitter L21 in the second column, and the light emitter L41 in the fourth column is arranged offset by a distance Wx3 in the X-axis direction from the light emitter L31 in the third column. Furthermore, the second light emitter L12 in the first column is arranged offset by a distance Wx4 in the X-axis direction from the first light emitter L41 in the fourth column. These distances Wx1 to Wx4 match each other within the tolerance range (Wx1, Wx2, Wx3, Wx4 = Wx).

[0024] The first to fourth light emitters L1i to L4i are arranged so as to be shifted from one another in the first direction by a distance (interval Wx) corresponding to one dot of the pixel D. In other words, the interval Wx (Wx1 to Wx4) corresponds to one dot of the pixel D.

[0025] Returning to FIG. 2 , the explanation continues. The current supply unit 14a supplies current to the plurality of first light emitters L1i and the plurality of second light emitters L2i at a first light emission timing TL1, causing them to emit light. The current supply unit 14b supplies current to the plurality of third light emitters L3i and the plurality of fourth light emitters L4i at a second light emission timing TL2, which is different from the first light emission timing TL1, causing them to emit light. The first light emission timing TL1 is represented in FIG. 4 (described later) as the timing at which the control signals Em(1) and Em(2) go low (times t6 to t13). The second light emission timing TL2 is represented in FIG. 4 as the timing at which the control signals Em(3) and Em(4) go low (times t12 to t20).

[0026] By synchronizing the light emission timing of the first light emitter L1i and the second light emitter L2i, it is possible to reduce interference caused by timing differences between the first light emitter L1i and the second light emitter L2i. Similarly, by synchronizing the light emission timing of the third light emitter L3i and the fourth light emitter L4i, it is possible to reduce interference caused by timing differences between the third light emitter L3i and the fourth light emitter L4i.

[0027] The time difference ΔT (= t12 - t6, see FIG. 4 described later) between the first and second light emission timings TL1 and TL2 corresponds to the difference ΔWy (= Wy2 - Wy1) ​​between the first and second intervals Wy1 and Wy2, converted into the moving speed Vm on the outer periphery of the rotating photosensitive drum 11. This correspondence can be expressed, for example, by the following equation (2). As a result, it is possible to align the intervals between the pixels D1i to D3i generated on the photosensitive drum 11 by the light emitters L1i to Li3 arranged at different intervals Wy1 and Wy2. This will be described in detail later. ΔWy = Wy2 - Wy1 = Vm × ΔT ... equation (2)

[0028] The current supply unit 14 has a plurality of first to fourth pixel circuits 141i to 144i that supply current to the plurality of first to fourth light emitters L1i to L4i, respectively. The first to fourth pixel circuits 141i to 144i are connected to the first to fourth light emitters L1i to L4i by current supply lines AL1 to AL4, respectively. That is, the first to fourth pixel circuits 141i to 144i supply current to the first to fourth light emitters L1i to L4i via the first to fourth current supply lines AL1 to AL4, respectively, to cause them to emit light.

[0029] The plurality of first and second pixel circuits 141i, 142i are arranged on the first column side of the light-emitting section 13, and the plurality of third and fourth pixel circuits 143i, 14i are arranged on the fourth column side of the light-emitting section 13. In other words, the first and second pixel circuits 141i, 142i and the third and fourth pixel circuits 143i, 144i are separated from each other and arranged so as to sandwich the light-emitting section 13 from the front and rear in the Y-axis direction.

[0030] As a result, the first and second current supply lines AL1 and AL2 can connect the first and second pixel circuits 141i and 142i to the first and second light emitters L1i and L2i without passing through the vicinity of the third and fourth light emitters L3i and L4i. Similarly, the third and fourth current supply lines AL3 and AL4 can connect the third and fourth pixel circuits 143i and 144i to the third and fourth light emitters L3i and L4i without passing through the vicinity of the first and second light emitters L1i and L2i. This reduces noise in the light emitted by the first to fourth light emitters L1i to L4i due to interference of the supply current between the first and second light emitters L1i and L2i and the third and fourth light emitters L3i and L4i.

[0031] Furthermore, interference between the current supply lines AL1 and AL2 can be reduced by separately arranging the first and second current supply lines AL1 and AL2 above and below the light-emitting unit 13. Similarly, interference between the current supply lines AL3 and AL4 can be reduced by separately arranging the third and fourth current supply lines AL3 and AL4 above and below the light-emitting unit 13.

[0032] The drive units 15 (15a, 15b) drive the current supply units 14 (pixel circuits 141i to 144i) using control signals Em, Dis, and Scan, causing the light-emitting units 13 (light emitters L1i to L4i) to emit light. The drive unit 15a is arranged on the side of the current supply unit 14a (pixel circuits 141i, 142i) and drives the current supply unit 14a. Similarly, the drive unit 15b is arranged on the side of the current supply unit 14b (pixel circuits 143i, 144i) and drives the current supply unit 14b.

[0033] The driver 15a drives the pixel circuit 141i with control signals Em(1), Dis(1), and Scan(1), and drives the pixel circuit 142i with control signals Em(2), Dis(2), and Scan(2). Similarly, the driver 15b drives the pixel circuit 143i with control signals Em(3), Dis(3), and Scan(3), and drives the pixel circuit 142i with control signals Em(4), Dis(4), and Scan(4). These will be described in detail later.

[0034] The data output unit 16 outputs first to fourth data signals S1 to S4 corresponding to the first to fourth pixel circuits 141i to 144i, respectively, during first to fourth output periods T1 to T4 that do not overlap with one another. In FIG. 4, the first to fourth output periods T1 to T4 are represented as periods corresponding to times t1 to t2, t2 to t7, t7 to t9, and t9 to t15, respectively. Hereinafter, the first to fourth data signals S1 to S4 may be collectively referred to as data signals S. Furthermore, the wiring that outputs the data signals S from the data output unit 16 may be referred to as output lines S.

[0035] The wiring switching unit 17 switches the connection between the data output unit 16 and the first and second data lines DLa, DLb. The wiring switching unit 17 has a plurality of wiring switches 17i. The wiring switch 17i has transistors TRa and TRb. The transistor TRa connects the output line S of the data output unit 16 to the first data line DLa when the control signal ASWa is at L level, and disconnects the output line S from the first data line DLb when the control signal ASWa is at H level. The transistor TRb connects the output line S to the second data line DLb when the control signal ASWa is at L level, and disconnects the output line S from the second data line DLb when the control signal ASWb is at H level.

[0036] The switching control unit 18 controls the wiring switching unit 17 using control signals ASWa and ASWb, as will be described in detail below.

[0037] 4 is a timing chart showing the timing of the signals on the first or second data line DLa, DLb, the data signal S, and the control signals Em, Dis, Scan, ASWa, and ASWb. As shown in FIG. 4, the data output unit 16 outputs first to fourth data signals S1 to S4 corresponding to first to fourth output periods T1 to T4. The first to fourth data signals S1 to S4 are signals that define the intensities of the light emitted by the first to fourth light emitters L1i to L4i, respectively.

[0038] The switching control unit 18 alternately outputs (1) a combination of an L-level control signal ASWa and an H-level control signal ASWb, and (2) a combination of an H-level control signal ASWa and an L-level ASWb, corresponding to the output periods T1 to T4. As a result, the output line S from the data output unit 16 is alternately connected to the first data line DLa and the second data line DLb.

[0039] The wiring switching unit 17 connects the data output unit 16 to the first data line DLa during one of the first and second output periods T1, T2 corresponding to one of the plurality of first and second pixel circuits 141i, 142i and one of the third and fourth output periods T3, T4 corresponding to one of the plurality of third and fourth pixel circuits 143i, 144i. On the other hand, the wiring switching unit 17 connects the data output unit 16 to the second data line DLb during one of the first and second output periods T1, T2 corresponding to one of the plurality of first and second pixel circuits 141i, 142i and one of the third and fourth output periods T3, T4 corresponding to one of the plurality of third and fourth pixel circuits 143i, 144i.

[0040] For example, the switching control unit 18 controls the wiring switching unit 17 to connect the output line S of the data output unit 16 to (1) the first data line DLa, (2) the second data line DLb, (3) the first data line DLa, and (4) the second data line DLb in this order so as to correspond to the first to fourth output periods T1 to T4 of the data output unit 16. For example, with the control signals ASWa and ASWb in FIG. 4, the output line S is connected to the first data line DLa during the first and third output periods T1 and T3, and the output line S is connected to the second data line DLb during the second and fourth output periods T2 and T4.

[0041] 4, the output line S may be connected to the second data line DLb during the first and third output periods T1 and T3, and the output line S may be connected to the first data line DLa during the second and fourth output periods T2 and T4. However, in this case, other control signals and wiring may need to be changed.

[0042] 5 is a circuit diagram showing an example of a pixel circuit 14j (141 to 144). The symbol j is an integer between 1 and 4. These integers 1 to 4 correspond to the pixel circuits 141 to 144, light emitters L1 to L4, data signals S1 to S4, and control signals Em(1) to Em(4), Dis(1) to Dis(4), and Scan(1) to Scan(4), respectively. The pixel circuit 14j has a capacitor Cst and transistors TR1 to TR7, and operates on a drive voltage ELVDD.

[0043] The pixel circuit 14j is connected to the data output unit 16 via the data line DLa or DLb. As described above, the pixel circuits 141i and 143i receive the data signals S1 and S3 corresponding to the light emitters L1i and L3i, respectively, via the data line DLa. The pixel circuits 142i and 144i receive the data signals S2 and S4 corresponding to the light emitters L2i and L4i, respectively, via the data line DLb.

[0044] The pixel circuit 14j outputs a light-emitting current Cj based on the data signal S. The pixel circuit 14j outputs the light-emitting current Cj based on control signals Scan(j), Dis(j), and Em(j) supplied from the drive unit 15 and a data signal Sj output from the data output unit 16. The light-emitting current Cj is supplied to the light emitter Lj via a current supply line ALj, causing the light emitter Lj to emit light. As a result, the light emitter Lj emits light with an intensity corresponding to the data signal Sj, and a pixel Dj with a density corresponding to this intensity is formed on the photosensitive drum 11.

[0045] The capacitor Cst stores a data signal supplied from the first or second data line DLa, DLb as an electric charge. The transistors TR2 to TR4 function as a data connection switching unit DSW, which switches whether the first or second data line DLa, DLb is connected to the capacitor Cst. The data connection switching unit DSW connects the data line DLa or DLb to the capacitor Cst (wiring point P1) using the transistors TR3, TR4, and TR2. The transistors TR4 to TR6 function as an emission connection switching unit LSW, which switches whether the capacitor Cst is connected to any of the first to fourth light emitters L1i to L4i. The emission connection switching unit LSW connects the capacitor Cst (wiring point P2) to the light emitter Lj (current supply line ALj) using the transistors TR5, TR4, and TR6. These will be described in detail later.

[0046] (Operation of Printer Head 12) The operation of the printer head 12 will be described below with reference to FIGS.

[0047] The current supply unit 14 (pixel circuits 141 to 144) causes each of the light emitters L1i to L4i to emit light once within a period T0 (times t1 to t15) to form pixels D1i to D4i on the photosensitive drum 11. By repeating this process, a latent image made up of a large number of pixels D1i to D4i can be formed on the photosensitive drum 11.

[0048] This period T0 can be divided into output periods T1 to T4 (times t1 to t2, t2 to t7, t7 to t9, and t9 to t15) in accordance with the switching of the data signal S. During the output periods T1 to T4, data signals S1 to S4 corresponding to the light emitters L1i to L4i are output from the data output unit 16, respectively.

[0049] During the output period T1 (times t1 to t2), the data output unit 16 outputs a data signal S1 corresponding to the light emitter L1i. At this time, the control signals ASWa and ASWb are at L level and H level, respectively, and the switching control unit 18 connects the data output unit 16 to the first data line DLa. As a result, the data signal S1 is input to the first data line DLa. This data signal S1 is held in the first data line DLa from time t2 until time t7. This is because the connection between the output line S and the first data line DLa is released at time t2. As a result, the first data line DLa holds the data signal S1 during the output periods T1 and T2 (times t1 to t7).

[0050] During the output period T1 (time t1 to t2), the control signals Em(1), Dis(1), and Scan(1) are H level, L level, and H level, respectively. The transistors TR1, TR4, and TR7 are in the ON state, and the transistors TR2, TR3, TR5, and TR6 are in the OFF state. Although the control signals Em(1), Dis(1), and Scan(1) are not input to the transistor TR4, the transistor TR1 is in the ON state, so the gate of the transistor TR4 is connected to VINI, becomes L level, and the transistor TR4 is in the ON state. During this output period T1 (time t1 to t2), the transistor TR3 is in the OFF state, so the data signal S1 is held on the first data line DLa and does not flow into the pixel circuit 141.

[0051] When the output period T1 (between times t1 and t2) transitions to time t3, the control signal Dis(1) goes high, and the transistors TR1 and TR7 are turned off. As described above, from time t1 to t3, the transistor TR3 is in the off state, and the first data signal S1 output from the data output unit 16 is held on the first data line DLa. That is, from time t1 to before time t4, the drive unit 15 holds the first data signal S1 on the first data line DLa by keeping the transistor TR3 (data connection switching unit DSW) of the pixel circuit 141 in the off state (open state).

[0052] At time t4, the control signal Scan(1) goes low, turning on transistors TR2 and TR3. As a result, the data signal S1 held on the first data line DLa flows into capacitor Cst via transistors TR3, TR4, TR2, and wiring location P1, and is stored as a charge in capacitor Cst. That is, during the second drive period t4-t5 after the first drive period (from time t2 to before time t4), the drive unit 15 closes the data connection switch unit DSW of the pixel circuit 141 (ON state) and opens the light-emission switch unit LSW (OFF state), thereby storing the first data signal S1 held on the first data line DLa as a charge in capacitor Cst.

[0053] At time t5, the control signal Scan(1) goes high, turning transistors TR2 and TR3 off. At time t6, the control signal Em(1) goes low, turning transistors TR5 and TR6 on. As a result, the signal S1 stored as a charge in the capacitor Cst is injected into the light emitter L1i as a light-emitting current Cj via the wiring point P2, transistors TR5, TR4, and TR6, and the current supply line AL1, causing the light emitter L1i to emit light at an intensity corresponding to the signal S1. This light emission begins at time t6 and can continue until time t13. That is, during the third driving period t6 to t13 following the second driving period t4 to t5, the driving unit 15 closes (turns on) the light-emitting connection switching unit LSW of the pixel circuit 141i, thereby supplying the light-emitting current Cj to the first light emitter L1i based on the charge stored in the capacitor Cst and causing the light emitter L1i to emit light.

[0054] During the output period T2 (times t2 to t7), the data output unit 16 outputs a data signal S2 corresponding to the light emitter L2i. At this time, the control signals ASWa and ASWb are at H level and L level, respectively, and the switching control unit 18 connects the data output unit 16 to the second data line DLb. As a result, the data signal S2 is input to the second data line DLb. This data signal S2 is held in the second data line DLb from time t7 until time t9. This is because the connection between the output line S and the second data line DLb is released at time t7. As a result, the second data line DLb holds the data signal S2 during the output periods T2 and T3 (times t2 to t9). That is, from time t2 to before time t4, the driving unit 15 holds the second data signal S2 on the second data line DLb by setting the transistor TR3 (data connection switching unit DSW) of the pixel circuit 142 to the OFF state (open state).

[0055] During the output period T2 (times t2 to t7), the control signals Em(2), Dis(2), and Scan(3) change over time, similar to the control signals Em(1), Dis(1), and Scan(1). As a result, at time t4, the data signal S2 held on the second data line DLb flows into the capacitor Cst in the pixel circuit 142 via the transistors TR3, TR4, and TR2 and the wiring location P1, and is stored as a charge in the capacitor Cst. That is, during the second drive period t4 to t5 after the first drive period (from time t2 to before time t4), the drive unit 15 closes the data connection switch unit DSW of the pixel circuit 142 (ON state) and opens the light-emission switch unit LSW (OFF state), thereby storing the second data signal S2 held on the second data line DLb as a charge in the capacitor Cst.

[0056] Between times t5 and t12, the signal S2 stored as a charge in the capacitor Cst is injected into the light emitter L2i as a light-emitting current Cj via the wiring point P2, transistors TR5, TR4, and TR6, and the current supply line AL2, causing the light emitter L2i to emit light with an intensity corresponding to the signal S2. This light emission begins at time t6 and can continue until time t13. That is, during the third driving period t6 to t13 after the second driving period t4 to t5, the driving unit 15 closes the light-emitting connection switching unit LSW of the pixel circuit 142 (ON state), thereby supplying a current to the second light emitter L2i based on the charge stored in the capacitor Cst and causing the second light emitter L2i to emit light.

[0057] That is, the data signals S1 and S2 are output from the data output unit 16 during different output periods T1 and T2 and are held on different data lines DLa and DLb. This holding continues from the start of the output periods T1 and T2 until just before time t4, when the flow into the capacitor Cst begins. As a result, the light emitters L1 and L2 can emit light at the same timing.

[0058] The data signals S3 and S4 are also output from the data output unit 16 during different output periods T3 and T4, and are held on different data lines DLa and DLb. This holding continues from the start of the output periods T3 and T4 until just before time t10, when the flow into the capacitor Cst begins. As a result, the light emitters L3 and L4 can emit light at the same timing.

[0059] The data signals S1 and S3 are held on the same data line DLa shared by the pixel circuits 141 and 143. However, there is no overlap in this period, so the pixel circuits 141 and 143 can obtain different data signals S1 and S3 from the same data line DLa.

[0060] Similarly, data signals S2 and S4 are held on the same data line DLb shared by pixel circuits 142 and 144. However, there is no overlap during this period, so pixel circuits 142 and 144 can obtain different data signals S2 and S4 from the same data line DLb.

[0061] As described above, the light emitters L1 and L2 emit light at the same timing (start time t6), and the light emitters L3 and L4 also emit light at the same timing (start time t12). The difference ΔT between these light emission timings is half the period T0 (ΔT = t12 - t6 = (1 / 2) × T0). Note that the time difference ΔT may be changed as appropriate to a value other than half the period T0.

[0062] As described above, the time difference ΔT (= t12 - t6) between the first and second light emission timings TL1 and TL2 corresponds to the difference ΔWy between the first and second intervals Wy1 and Wy2 when converted into the moving speed Vm on the outer periphery of the rotating photosensitive drum 11. This correspondence can be expressed, for example, by the above-described formula (2).

[0063] As described above, the drive unit 15 drives the first to fourth pixel circuits 141i to 144i in the following manner (1) to (3). As a result, a charge corresponding to the data signal S is accumulated as a charge in the capacitor Cst, and a current corresponding to this charge is supplied to the light emitters L1i and L2i, causing the light emitters L1i and L2i to emit light.

[0064] (1) The driving unit 15 causes the first and second data signals S1 and S2 output from the data output unit 16 to be held on the first and second data lines DLa and DLb, respectively, for the plurality of first and second pixel circuits 141i and 142i by setting the data connection switching unit DSW to an open state (OFF state) during the first driving period (from time t2 to before time t4).

[0065] The first drive period (from time t1 to before time t4) includes at least a part of each of the first and second output periods T1 and T2, so that the first and second data signals S1 and S2 output from the data output unit 16 can be held on the first and second data lines DLa and DLb, respectively.

[0066] (2) During the second driving period t4 to t5 after the first driving period (from time t2 to before time t4), the driving unit 15 closes the data connection switching unit DSW (ON state) and opens the light-emitting switching unit LSW (OFF state), thereby storing the first and second data signals S1 and S2 held on the first and second data lines DLa and DLb as electric charges in the capacitor Cst.

[0067] (3) During the third driving period t6 to t13 after the second driving period t4 to t5, the driving unit 15 closes the light-emitting connection switching unit LSW (ON state), thereby supplying current to the first and second light emitters L1i and L2i based on the charge accumulated in the capacitor Cst, causing them to emit light.

[0068] 6 is a schematic diagram showing a pixel D of the latent image formed on the photosensitive drum 11. For ease of understanding, this figure shows the surface of the photosensitive drum 11 as viewed from the positive direction of the Z axis, and corresponds to FIGS. 2 and 3. Below, the pixel D of the latent image formed on the photosensitive drum 11 will be described.

[0069] As the light emitters L1i to L4i emit light, pixels D1i to D4i corresponding to the light emitters L1i to L4i are formed on the photosensitive drum 11. Here, as the light emitters L1i to L4i each emit light n times, pixels D1i(1) to D1i(n), ..., D4i(1) to D4i(n) are formed.

[0070] As shown in FIG. 3 , the light emitters L1i to L4i are arranged at intervals Wx1 to Wx4 in the X direction so that the pixels D1i to D4i are adjacent to each other, and at intervals Wy1 to Wy3 in the Y direction. The intervals Wy1 to Wy3 are larger than the size of the pixels D1i to D4i, respectively. This is because, when a latent image is formed, multiple pixels D can be formed between the intervals Wy1 to Wy3. Here, the intervals Wy1 to Wy3 are set so that, when a latent image is formed, five pixels D can be formed between the pixels D1i and D2i. As a result, as shown in FIG. 6 , five pixels D11(n-1) to D11(n-5) are arranged between the pixels D11(n) and D21(n), and pixel D21(n) is located on the sixth line relative to pixel D11(n).

[0071] As described above, the light emitters L3i and L4i emit light with a time delay ΔT from the light emitters L1i and L2i. Furthermore, the distance Wy2 between the light emitters L2i and L3i is greater than the distance Wy1 between the light emitters L1i and L2i and the distance Wy3 between the light emitters L3i and L4i. The difference ΔWy between these distances is Wy2-Wy1 or Wy2-Wy3. The correspondence between this delay in light emission timing and the distance difference ΔWy results in pixels D3i and D4i being aligned in the X direction relative to pixels D1i and D2i, as shown in FIG. 6 . For example, pixels D11(1), D21(7), D31(13), and D41(19) are aligned in the X direction.

[0072] FIG. 7 is a schematic diagram showing the correspondence relationship between the arrangement of light emitters L1 to L4 and pixels D1 to D4. Let us assume that light emitters L1 to L4 emit light simultaneously. Here, let us assume that light emitters L3 and L4 emit light in synchronization with light emitters L1 and L2, rather than at their original timing, and that pixels D3f and D4f are formed by light emitters L3 and L4 at this time. These pixels D3f and D4f are virtual and may be referred to as virtual pixels hereinafter. In this case, pixels D1, D2, D3f, and D4f formed by light emitters L1 to L4 correspond to the arrangement of light emitters L1 to L4 and are arranged at intervals Wy1, Wy2, and Wy3 in the y direction.

[0073] In this embodiment, light emitters L3 and L4 emit light with a time ΔT delay from light emitters L1 and L2. During this time ΔT, the outer periphery of the photosensitive drum 11 moves in the negative Y-axis direction at a moving speed Vm. As a result, pixels D3 and D4 of light emitters L3 and L4 are shifted by Vm×ΔT in the negative Y-axis direction relative to virtual pixels D3f and D4f. In other words, by setting Vm×ΔT to correspond to the difference ΔWy (=Wy2-Wy1) between the intervals Wy2 and Wy1, it is possible to generate pixels D1 to D4 with uniform intervals from light emitters L1 to L4 that are arranged at irregular intervals. As a result, for example, pixel D31(1) in FIG. 6 is arranged side by side with pixels D11(13) and D21(7). Similarly, pixel D41(1) is arranged side by side with pixels D11(19) and D21(13). That is, the pixels D1i to D4i formed by the light emitters L1i to L4i are arranged in a straight line in the X-axis direction.

[0074] As described above, in this embodiment, the printer head (10) includes a light-emitting unit (13) having a plurality of light-emitting devices (L1i to L4i) that expose a rotating photosensitive drum, and a current supply unit that supplies current to the light-emitting unit to cause the plurality of light-emitting devices to emit light, and the plurality of light-emitting devices are arranged in a first direction (X direction) and include a plurality of first light-emitting devices (L1i) that form a first row, a plurality of second light-emitting devices (L2i) that form a second row, and a plurality of third light-emitting devices (L3i) that form a third row. and a plurality of third light emitters (L3i) arranged along the first direction and constituting a fourth row, and a plurality of fourth light emitters (L4i) arranged along the first direction and constituting a fourth row, the first to fourth rows are arranged in order along a second direction (Y direction) different from the first direction, the first row and the second row have a first interval (Wy1), the second row and the third row have a second interval (Wy2), and the third row and the fourth row have a third interval (Wy3), the second interval being larger than both the first and third intervals. This makes it possible to reduce interference between the plurality of light emitters.

[0075] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present disclosure.

[0076] 10 Printer 11 Photosensitive drum 12 Printer head 13 Light emitting section 14 Current supply section 15 Driver section 16 Data output section 17 Wiring switching section 141i to 144i Pixel circuits AL1 to AL4 Current supply line Cst Capacitor Dij Pixel DLa, DLb Data line S1 to S4 Data signal L1i, L2i, L3i, L4i Light emitter TL1, TL2 Light emission timing PO1 to PO4 Output period TR1 to TR7 Transistor Vm Moving speed Wx1 to Wx4 Spacing Wy1 to Wy3 Spacing

Claims

1. A printer head comprising: a light-emitting unit having a plurality of light-emitting devices that expose a rotating photosensitive drum; and a current supply unit that supplies current to the light-emitting unit to cause the plurality of light-emitting devices to emit light, wherein the plurality of light-emitting devices include: a plurality of first light-emitting devices that are aligned along a first direction and form a first row; a plurality of second light-emitting devices that are aligned along the first direction and form a second row; a plurality of third light-emitting devices that are aligned along the first direction and form a third row; and a plurality of fourth light-emitting devices that are aligned along the first direction and form a fourth row, wherein the first to fourth rows are aligned in order along a second direction different from the first direction, a first interval between the first row and the second row, a second interval between the second row and the third row, and a third interval between the third row and the fourth row, wherein the second interval is larger than both the first and third intervals.

2. A printer head as described in claim 1, wherein the current supply unit supplies current to the plurality of first light-emitting devices and the plurality of second light-emitting devices at a first light-emitting timing to cause them to emit light, and supplies current to the plurality of third light-emitting devices and the plurality of fourth light-emitting devices at a second light-emitting timing different from the first light-emitting timing to cause them to emit light.

3. A printer head as described in claim 2, wherein the time difference between the first and second light emission timings corresponds to the difference between the first and second intervals when converted into the moving speed of the rotating photosensitive drum on the outer periphery.

4. A printer head according to any one of claims 1 to 3, wherein the current supply unit has a plurality of first to fourth pixel circuits that supply current to the plurality of first to fourth light emitters, respectively.

5. A printer head as described in claim 4, wherein the plurality of first and second pixel circuits are arranged on the first column side of the light-emitting section, and the plurality of third and fourth pixel circuits are arranged on the fourth column side of the light-emitting section.

6. A printer head as described in claim 4 or 5, wherein the current supply section has: a plurality of first data lines that supply data signals to one of the plurality of first and second pixel circuits and one of the plurality of second and fourth pixel circuits; and a plurality of second data lines that supply data signals to the other of the plurality of first and second pixel circuits and the other of the plurality of second and fourth pixel circuits.

7. The printer head according to claim 6, wherein the current supply section has: a data output section that outputs first to fourth data signals corresponding to the plurality of first to fourth pixel circuits, respectively, during first to fourth output periods that do not overlap one another; and a connection switching section that switches the connection between the data output section and the first and second data lines, wherein the connection switching section connects the data output section to the first data line during one of the first and second output periods corresponding to one of the plurality of first and second pixel circuits and one of the third and fourth output periods corresponding to one of the plurality of third and fourth pixel circuits, and connects the data output section to the second data line during one of the first and second output periods corresponding to one of the plurality of first and second pixel circuits and one of the third and fourth output periods corresponding to one of the plurality of third and fourth pixel circuits.

8. A printer head as described in claim 6 or 7, wherein each of the plurality of first to fourth pixel circuits comprises: a capacitor that stores a data signal supplied from the first or second data line as an electric charge; a data connection switching unit that switches whether the first or second data line and the capacitor are connected; and an emission connection switching unit that switches whether the capacitor is connected to any of the first to fourth light emitters.

9. A printer head according to claim 8, further comprising a drive unit that drives the plurality of first to fourth pixel circuits, wherein the drive unit, for the plurality of first and second pixel circuits, during a first drive period, opens the data connection switching unit, thereby causing the first and second data signals output from the data output unit to be held on the first and second data lines, respectively; during a second drive period after the first drive period, closes the data connection switching unit and opens the light emission switching unit, thereby storing the first and second data signals held on the first and second data lines as charges in the capacitor; and during a third drive period after the second drive period, closes the light emission connection switching unit, thereby supplying current to the first and second light emitters, causing them to emit light, based on the charges stored in the capacitor.

10. The printer head according to claim 9, wherein the first drive period includes at least a portion of each of the first and second output periods.

11. A printer head according to any one of claims 1 to 10, wherein the first direction corresponds to the axial direction of the rotation axis of the photosensitive drum, and the second direction corresponds to the direction of movement on the circumferential surface of the rotating photosensitive drum.

12. A printer head described in any one of claims 1 to 11, wherein the first interval and the third interval correspond to n pixel dots (n: an integer equal to or greater than 1) on the photosensitive drum, and the second interval corresponds to less than (n+1) pixel dots on the photosensitive drum.

13. A printer head according to any one of claims 11 to 12, wherein the first gap and the second gap have sizes corresponding to each other.

14. The printer head according to claim 12, wherein the first to fourth light emitters are arranged so as to be offset from one another in the first direction.

15. A printer head according to claim 14, wherein the first to fourth light emitters are arranged so as to be shifted from one another in the first direction by a distance corresponding to one dot of a pixel.

16. A printer comprising a printer head according to any one of claims 1 to 15.

Images