Data carrier device, data communication system, and image forming device

Abstract

The present invention provides a data carrier device capable of increasing the current supplied thereto from a data carrier drive device as necessary. Provided is a data carrier device that operates by being powered by a data carrier drive device. A first terminal and a second terminal are connected to the data carrier drive device. An integrated circuit is connected to the first terminal and the second terminal. When the inter-terminal voltage between the first terminal and the second terminal changes in a specific pattern, the integrated circuit increases the value of the current supplied from the data carrier drive device to the data carrier device through the first terminal from a first current value to a second current value.

Description

Data carrier device, data communication system and image forming apparatus

[0001] The present invention relates to a data carrier device, a data communication system, and an image forming device.

[0002] There is a security authentication system in which a master and a slave communicate via a two-wire communication interface. In a two-wire communication interface, two signal lines are used for data transmission and reception, power supply, and synchronization signal supply. To strengthen security authentication, the integrated circuit (IC) built into the slave must operate at high speed. As a result, fluctuations in the IC's current consumption increase, making the IC's operation more susceptible to analysis (see Patent Document 1). Therefore, there is a need to stabilize the IC's current in order to safely process security data.

[0003] U.S. Patent No. 9,787,171

[0004] Increasing the operating frequency of the slave IC or operating multiple logic circuits simultaneously within the IC enables more advanced security calculations, improving security. This requires increasing the IC's internal voltage and the current required for processing. However, because the slave IC also performs other processes besides security calculations, it does not always require a high voltage or a large current.

[0005] The present invention provides, for example, a data carrier device that operates by receiving power from a data carrier driving device, the data carrier device having: a first terminal connected to the data carrier driving device; a second terminal connected to the data carrier driving device; and an integrated circuit connected to the first terminal and the second terminal, wherein the integrated circuit increases the value of the current supplied from the data carrier driving device to the data carrier device through the first terminal from a first current value to a second current value when the inter-terminal voltage between the first terminal and the second terminal changes in a specific pattern.

[0006] According to the present invention, a data carrier device is provided that can increase the current supplied from the data carrier driving device as needed.

[0007] Other features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings, in which the same or similar elements are designated by the same reference numerals.

[0008] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0009] FIG. 1 is a diagram illustrating a data communication system.

[0010] FIG.

[0011] FIG. 2 is a diagram for explaining a communication state.

[0012] FIG. 2 is a diagram for explaining a communication state.

[0013] FIG. 2 is a diagram illustrating a data carrier device.

[0014] FIG. 10 is a diagram illustrating another example of a power supply circuit.

[0015] FIG. 2 is a diagram illustrating a data carrier device.

[0016] FIG. 2 is a diagram illustrating a data carrier device.

[0017] FIG. 2 is a diagram illustrating a data carrier device.

[0018] FIG. 2 is a diagram for explaining a communication state.

[0019] FIG.

[0020] 10 is a flowchart showing a control method.

[0021] FIG. 1 is a diagram illustrating an image forming apparatus.

[0022] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0023] 1, a data communication system 100 includes a data carrier device 101 and a data carrier driving device 102. The data carrier device 101 may be called a slave device or an authenticated device. The data carrier driving device 102 may be called a master device or an authenticating device.

[0024] The data carrier driving device 102 has terminals 131A and 131B. The data carrier device 101 has contacts 132A and 132B. Contacts 132A and 132B may also be called terminals. Terminal 131A and contact 132A are connected by a first communication line 133A. Terminal 131B and contact 132B are connected by a second communication line 133B. The data carrier device 101 and the data carrier driving device 102 transmit and receive data via the first communication line 133A and the second communication line 133B. The data carrier driving device 102 supplies power to the data carrier device 101 via the first communication line 133A and the second communication line 133B.

[0025] (2) Data Carrier Driving Device The data carrier driving device 102 includes a processing unit 103, a modulation unit 105, a demodulation unit 106, a first power supply 107 that outputs voltage V1, and a second power supply 108 that outputs voltage V2. The processing unit 103 and modulation unit 105 may be integrated into an IC. The processing unit 103, modulation unit 105, and demodulation unit 106 may also be integrated into an IC. Furthermore, the data carrier driving device 102, including the first power supply 107 and the second power supply 108, may also be integrated into an IC. Voltage V2 is lower than voltage V1. The processing unit 103 creates command data to be transmitted to the data carrier device 101 and executes processing based on reply data received from the data carrier device 101. The first power supply 107 outputs voltage V1 to the demodulation unit 106. The second power supply 108 outputs voltage V2 to the conversion unit 112.

[0026] The modulation unit 105 and the conversion unit 112 execute processing for transmitting the command data generated by the processing unit 103 to the data carrier device 101. The modulation unit 105 generates a clock pulse signal in accordance with the command data generated by the processing unit 103. The setting unit 114 stores values ​​indicating two duty ratios, duty A and duty B. For example, duty A is smaller than 50%. Duty B is larger than 50%. The setting unit 114 selects duty A or duty B in accordance with the data value of the command data, and notifies the generation unit 113 of the selected duty ratio. The generation unit 113 generates a clock pulse signal including a pulse based on the duty ratio selected by the setting unit 114, and outputs the clock pulse signal to the conversion unit 112.

[0027] During a period in which the input clock pulse signal is at a low level, the conversion unit 112 outputs the voltage V2 output by the second power supply 108 to the terminal 131B. During a period in which the input clock pulse signal is at a high level, the conversion unit 112 outputs a voltage of 0 V (GND potential) to the terminal 131B. GND is an abbreviation for ground.

[0028] The demodulation unit 106 demodulates the reply data transmitted by the data carrier device 101 and outputs the demodulated reply data to the processing unit 103. The demodulation unit 106 has a detection unit 110, a setting unit 111, and a determination unit 109. The setting unit 111 generates a threshold voltage Vth from the voltage V1 output by the first power source 107 and sets the threshold voltage Vth in the determination unit 109. The detection unit 110 detects the current I flowing from the first power source 107 to the data carrier device 101 and sets an input voltage corresponding to the current I in the determination unit 109. The determination unit 109 compares the threshold voltage Vth with the input voltage and outputs the comparison result to the processing unit 103. The processing unit 103 identifies the reply data based on the comparison result input from the determination unit 109 and performs processing according to the reply data.

[0029] (3) Data Carrier Device The data carrier device 101 includes a switching unit 117, a power supply circuit 118, a processing unit 123, a clock unit 116, and a demodulation unit 122. As described above, these can be packaged as a single IC or multiple ICs.

[0030] Here, the voltage applied between contacts 132A and 132B is called inter-terminal voltage Vab. Power supply circuit 118 generates voltage VDD used in data carrier device 101 based on pulsed inter-terminal voltage Vab supplied from data carrier driving device 102. Power supply circuit 118 supplies voltage VDD to each block (processing unit 123, clock unit 116, and demodulation unit 122) of data carrier device 101.

[0031] The clock unit 116 generates an internal clock CLK having a frequency that is sufficiently higher than the frequency of the pulsed inter-terminal voltage Vab, and supplies the internal clock CLK to blocks that require the internal clock CLK (e.g., the processing unit 123 and the demodulation unit 122).

[0032] The demodulation unit 122 converts the pulsed inter-terminal voltage Vab into one of two predetermined voltages. For example, when the inter-terminal voltage Vab is at a high level, the demodulation unit 122 outputs the voltage VDD. When the inter-terminal voltage Vab is at a low level, the demodulation unit 122 outputs a reference voltage (e.g., 0 V) ​​lower than the voltage VDD. Furthermore, the demodulation unit 122 identifies the duty ratio of the pulsed inter-terminal voltage Vab, demodulates command data according to the identified duty ratio, and outputs the command data to the processing unit 123.

[0033] The processing unit 123 executes arithmetic processing or control according to the command data demodulated by the demodulation unit 122. The processing unit 123 generates reply data based on the command data and outputs the reply data to the switching unit 117. The reply data may be an ACK (acknowledgement) or NACK (negative acknowledgement) indicating the result of receiving the command data. Furthermore, the reply data may include the result of execution of the calculation corresponding to the command data. In this case, a bit string indicating data (execution result) is present after the bit string indicating ACK.

[0034] The switching unit 117 changes the load depending on the reply data, and switches the magnitude of the current I flowing from the data carrier driving device 102 to the data carrier device 101. As a result, the reply data is transmitted from the data carrier device 101 to the data carrier driving device 102.

[0035] (4) Demodulation Unit of Data Carrier Driving Device Figure 2 shows the details of the demodulation unit 106. The detection unit 110 has a current detection resistor Ri for detecting the current I. The current detection resistor Ri converts the current I into a detection voltage. The value of the current I flowing from the first power source 107 to the data carrier device 101 is defined as Ix. The voltage Va is the voltage at the contact 132A (terminal 131A) of the data carrier device 101. The voltage Va is V1-Ix x Ri. Here, the voltage Va is a voltage based on the GND potential.

[0036] The setting unit 111 has voltage-dividing resistors R1 and R2. The voltage-dividing resistors R1 and R2 divide the voltage V1 to generate a threshold voltage Vth. The determination unit 109 has a comparator 201. The comparator 201 receives the threshold voltage Vth and the voltage Va, determines which is larger between the threshold voltage Vth and the voltage Va, and outputs the determination result to the processing unit 103. In the first embodiment, the data carrier device 101 changes the current I.

[0037] (5) State Transitions FIG. 3 is a state transition diagram in the data communication system 100. As shown in FIG. 3, the data communication system 100 has a wait state, a data transmission state, an interval state, a data reply state, and a data processing state. The wait state is a state in which the system waits for the start of data communication. Note that the last pulse in the wait state indicates a transition from the wait state to the data transmission state. The data transmission state is a state in which the data carrier driving device 102 transmits data or a command to the data carrier device 101. The interval state is a state in which the data carrier device 101 analyzes the data or command received from the data carrier driving device 102. The data reply state is a state in which the data carrier device 101 returns data or a response (e.g., ACK / NACK) to the data carrier driving device 102. The data processing state is a state in which the data carrier device 101 executes calculations or control corresponding to the command data. Note that the data transmission state and the data processing state are variable in length. In the data transmission state, length information indicating the length of the data to be transmitted is also transmitted, and the end of the data state can be recognized based on the length information. The length of the data processing state varies depending on the content of the data processing. The interval state and the data reply state are basically of fixed length. The data reply state may be of variable length. In this case, length information and data are also transmitted in the data reply state. Furthermore, following the data reply state in which an ACK / NACK is returned, there may be another data reply state in which data corresponding to the command is returned. In this other data reply state, length information and data are transmitted.

[0038] As shown in Figure 3, in the standby state, data transmission state, and interval state, the data carrier device 101 controls the value of the current I to Idef. In the data reply state, the data carrier device 101 controls the value of the current I to Idef or Ix depending on the data value of the reply data. Ix is greater than Idef. Here, Idef means "1" and Ix means "0". In the following, the voltage Vab when the current I is Idef is represented as V1'. The voltage Va when the current I is Ix is represented as Vx (<V1'). Note that Vx is higher than V2.

[0039] 3 also shows the voltage V1' and the inter-terminal voltage Vab. As shown in FIG. 3, when the current I is Idef, the high level of the inter-terminal voltage Vab is approximately V1' (= V1 - Idef x Ri). The low level of the inter-terminal voltage Vab is approximately V1' - V2.

[0040] There are various commands from the data carrier driving device 102. For example, there are commands to make the data carrier device 101 execute processing, and commands to make the data carrier device 101 output the results of processing to the data carrier driving device 102.

[0041] In the data transmission state, the data carrier driving device 102 transmits command data to the data carrier device 101. For example, the data carrier driving device 102 uses the command data to instruct the data carrier device 101 to read data stored in the memory 124 of the data carrier device 101.

[0042] In the interval state, the data carrier device 101 analyzes the command received in the data transmission state. In the data reply state, the data carrier device 101 transmits an ACK or NACK to the data carrier driving device 102 in response to the received command. In this example, the ACK is represented by 8-bit (1-byte) data "00100000" (20h). Note that the NACK is expressed as "11111111" (FFh). In the data processing state, the data carrier device 101 executes the received command. For example, the processing unit 123 performs an authentication calculation on the data stored in the memory 124. Alternatively, the processing unit 123 reads the data stored in the memory 124 and uses the read data as reply data. At this point, no reply data is transmitted. When the data processing state ends, the data carrier device 101 transitions to the standby state. The standby state exists from the end of the data processing state until the data carrier driving device 102 transmits the next command data to the data carrier device 101.

[0043] In order to obtain the results processed by the data carrier device 101, the data carrier driving device 102 issues a read command to the data carrier device 101 in the data transmission state. In the interval state, the data carrier device 101 analyzes the command and determines that the command is to read predetermined information from the memory 124. In the data reply state, the data carrier device 101 replies with an ACK to the data carrier driving device 102, and then replies with reply data (data read from the memory).

[0044] When the transmission of the reply data is completed, the data carrier device 101 transitions from the data reply state to the waiting state, i.e., the data processing state is skipped.

[0045] (6) Command Data Transmission Process The modulation unit 105 of the data carrier driving device 102 transmits command data in the data transmission state. At this time, the modulation unit 105 generates a clock pulse signal modulated according to the data value of the command data. The clock pulse signal output by the generation unit 113 includes a pulse with duty A and a pulse with duty B. The current I in the data transmission state is Idef. Therefore, when the clock pulse signal is at a high level in the data transmission state, the inter-terminal voltage Vab becomes a voltage V1'. When the clock pulse signal is at a low level, the inter-terminal voltage Vab becomes a voltage (V1'-V2). In other words, the waveform of the inter-terminal voltage Vab is the same as the waveform of the clock pulse signal.

[0046] (7) Receiving process of reply data When the interval state ends, the data carrier device 101 transitions to the data reply state. In the data reply state, the switching unit 117 changes the load and switches the magnitude of the current I according to the reply data input from the processing unit 123. In this way, the data carrier device 101 transmits reply data to the data carrier driving device 102 by changing the current I flowing from the data carrier driving device 102.

[0047] The demodulation unit 106 of the data carrier driving device 102 can determine the data value of the reply data by determining the magnitude of the current I. The data value of the reply data may be "1". In this case, the data carrier device 101 sets the value of the current I to Idef both during the period when the clock pulse signal is at a high level and during the period when the clock pulse signal is at a low level. On the other hand, the data value of the reply data may be "0". In this case, the data carrier device 101 sets the value of the current I to Ix, which is larger than Idef, during the period when the clock pulse signal is at a high level. Furthermore, the data carrier device 101 maintains the value of the current I at Idef during the period when the clock pulse signal is at a low level.

[0048] The data carrier device 101 maintains the value of the current I at Idef during a period when no reply data is being transmitted. The data carrier device 101 also sets the value of the current I to Idef when transmitting reply data of "1". In other words, when transmitting reply data of the data value "0", the data carrier device 101 increases the value of the current I during a period when the clock pulse signal is at a high level compared to the value during other periods.

[0049] The voltage Va is affected by the voltage drop that occurs across the current detection resistor Ri of the detection unit 110. In other words, the voltage Va changes depending on the value of the current I. When the value of the current I is Ix, the voltage Va is Vx. When the value of the current I is Idef, the voltage Va is V1' (V1' > Vx). The threshold voltage Vth is generated to satisfy the relationship V1' > Vth > Vx. As shown in FIG. 2, the threshold voltage Vth is input to the negative terminal of the comparator 201. When the value of the current I is Ix, the voltage Vx is input to the positive terminal of the comparator 201. Therefore, the comparator 201 outputs a low-level signal. On the other hand, when the current I is Idef, the voltage V1' is input to the positive terminal of the comparator 201. Therefore, the comparator 201 outputs a high-level signal. The determination result by the comparator 201 is input to the processing unit 103.

[0050] (8) Data Processing State The processing unit 123 executes internal processing based on commands from the data carrier driving device 102. The internal processing is, for example, access to the memory 124 or arithmetic processing. Some arithmetic processing of security data requires complex cryptographic calculations. In addition, to process security data securely, it is necessary to stabilize the operating current supplied to the processing unit 123 during arithmetic processing.

[0051] The arithmetic circuit included in the processing unit 123 is designed to operate at or below a stable upper limit current value (e.g., Idef). The arithmetic circuit is also designed to be supplied with a predetermined voltage and to operate at a predetermined operating frequency. The execution time of an operation performed by the arithmetic circuit depends on the operating frequency. To shorten the execution time, it is necessary to increase the operating voltage and operating frequency supplied to the arithmetic circuit. In this case, the current consumption also increases. If the current consumption exceeds the upper limit current value, the operation of the processing unit 123 may become unstable, and the security of the security data may be compromised. Therefore, in this embodiment, the goals are to shorten the execution time of the data processing state and to safely process the security data.

[0052] As shown in FIG. 4, during execution of the data processing state, the upper limit current value is temporarily increased to Idef'. When execution of the command is completed, the processing unit 123 returns the upper limit current value from Idef' to Idef. In the data processing state, the voltage supplied from the terminal 131B of the data carrier driving device 102 is V2. Because the value of the current I is Idef' (>Idef), the value of the terminal voltage Vab becomes Vab1, which is lower than V1'-V2. This is because an increase in the current I increases the voltage drop experienced by the voltage Va. Note that the processing unit 123 has a lower limit voltage at which it can operate normally. Therefore, Idef' is designed so that the voltage Vab1 is equal to or higher than the lower limit voltage.

[0053] (9) Details of the Power Supply Circuit and Switching Unit Fig. 5 shows one configuration of the data carrier device 101. Here, the current I supplied from the data carrier driving device 102 is branched into a current Idef and a current Irsp.

[0054] The power supply circuit 118 has current sources 127a and 127b, a switch 128, and a clamp circuit 501. The current source 127b and the switch 128 are connected in series. The current source 127a is connected in parallel to the series circuit consisting of the current source 127b and the switch 128. The current source 127a supplies a current Iref. The current source 127b supplies a current Iref2. The clamp circuit 501 is a circuit that adjusts the current Iclamp so that the sum of the currents Id and Iclamp is constant. The current Id is the sum of the currents supplied to the processing unit 123, the demodulation unit 122, and the clock unit 116, which are loads. The switch 128 is, for example, a semiconductor switch that is turned on / off by a control signal (gate signal) supplied from the processing unit 123.

[0055] The switching unit 117 includes a current source 125 and a switch 126. The current source 125 generates a current Irsp.

[0056] When the inter-terminal voltage Vab reaches a certain level or higher, the power supply circuit 118 generates a power supply voltage VDD and supplies the power supply voltage VDD to the processing unit 123, the clock unit 116, and the demodulation unit 122. The total current flowing into the power supply circuit 118 is Idef. Initially, the power supply circuit 118 supplies each block (the processing unit 123, the clock unit 116, and the demodulation unit 122) with a current Id (=Iref-Iclamp). Here, Id is the current remaining after subtracting the current Iclamp flowing through the clamp circuit 501 from the current Iref generated by the current source 127a.

[0057] The clamp circuit 501 operates so that the sum of the current Id consumed inside the data carrier device 101 and the current Iclamp is constant. The clamp circuit 501 can be realized using, for example, a Zener diode.

[0058] When the processing unit 123 receives a predetermined command, it increases the current I. Specifically, when the change pattern of the inter-terminal voltage Vab in the data transmission state is a specific pattern, the current I is increased. The specific pattern corresponds to the predetermined command. For example, the received command may be a command requesting a complex calculation in the arithmetic circuit of the processing unit 123. In this case, the processing unit 123 switches the switch 128 from OFF to ON when the data reply state ends or when the processing unit 123 transitions from the data reply state to the data processing state. If the interval state and the data reply state each have a fixed time length, the processing unit 123 switches the switch 128 from OFF to ON when a predetermined time has elapsed since the data transmission state ended. When a command that does not require advanced calculation is received, the processing unit 123 may keep the switch 128 OFF. Examples of commands that do not require advanced calculation include a command to perform a simple calculation, a command to read data directly from the memory 124, and a command to write data to the memory 124.

[0059] For example, processing unit 123 may include an arithmetic circuit such as an arithmetic circuit for encryption calculation, an arithmetic circuit for authentication calculation, a basic arithmetic circuit, and a simple calculation circuit (e.g., addition, subtraction, shift). More specifically, there may be an arithmetic circuit that analyzes commands, an arithmetic circuit that reads authentication information from memory 124 and returns it, an arithmetic circuit that executes authentication calculation, an arithmetic circuit that controls switch 128, and an arithmetic circuit that controls switch 126. In this case, the process of reading authentication information from memory 124 and returning it does not require advanced calculation. The authentication calculation is an advanced calculation.

[0060] When switch 128 is turned on, the total current flowing into power supply circuit 118 increases from Idef to Idef'. Idef' is the sum of Idef and Iref2. The current supplied from power supply circuit 118 to each block also increases from Id to Id'. Here, Id' is Idef'-Iclamp. In other words, Id' is Iref+Iref2-Iclamp. Clamp circuit 501 operates so that the sum of currents Id' and Iclamp consumed inside data carrier device 101 remains constant. This stabilizes current Id'.

[0061] When the processing unit 123 completes the calculation in response to the command, the data carrier device 101 transitions from the data processing state to the standby state. At this timing, the processing unit 123 turns off the switch 128. As a result, the current I flowing into the data carrier device 101 decreases from Idef' to Idef.

[0062] During the period when the current I is increasing, the processing unit 123 increases the frequency of the internal clock CLK generated by the clock unit 116. This allows an arithmetic circuit that performs advanced calculations (such as authentication calculations) inside the processing unit 123 to operate at high speed. Note that a frequency multiplication circuit that multiplies the frequency may be implemented inside the processing unit 123.

[0063] The current consumption value of the arithmetic circuit responsible for advanced calculations within the processing unit 123 may be designed in advance to be greater than Iref. If such an arithmetic circuit were to be operated with the switch 128 turned off, the current supplied to the arithmetic circuit would be insufficient. As a result, the power supply voltage VDD would drop, and the arithmetic circuit would not be able to perform calculations correctly. In the first embodiment, the current supplied from the power supply circuit 118 to the processing unit 123 is increased, allowing the arithmetic circuit to operate stably. As a result, the arithmetic circuit operates at high speed, and the execution time in the data processing state is shortened.

[0064] When the interval state ends, the processing unit 123 transitions to a data reply state. In the data reply state, the switching unit 117 changes the load in accordance with the reply data input from the processing unit 123, and switches the magnitude of the current I flowing from the data carrier driving device 102 to the data carrier device 101.

[0065] 5, the processing unit 123 turns on and off the switch 126 according to the data value, thereby turning on and off the operation of the current source 125. When the data value is "1", the switch 126 is turned off. When the data value is "0", the switch 126 is turned on. When the current source 125 is turned on, the current I changes to a current Ix. The relationship between the data and the operation of the switch 126 is merely an example. Other relationships may also be used.

[0066] There may be cases where a command other than the command for causing the arithmetic circuit in the processing unit 123 to execute advanced calculations is received. In this case, the switch 128 is kept off. However, the processing unit 123 may turn on the switch 128 in response to all commands.

[0067] When the data processing state starts, the switch 128 is turned on. When the data processing state ends, the switch 128 is turned off. In this case, the period from when the current I increases to when the current I decreases corresponds to the period during which security data is being processed. This may be exploited in an attack by a third party.

[0068] Therefore, the period during which the current I is increased may be set to be longer than the period of the data processing state. For example, the processing unit 123 may set the period during which the switch 128 is turned on to be longer than a predetermined period. The predetermined period is longer than the period of the data processing state. Alternatively, the processing unit 123 may randomly change the predetermined period. This will result in a mismatch between the period of the data processing state and the period during which the switch 128 is turned on, making it difficult to externally identify the period during which the switch 128 is turned on. In this way, the timing of data processing may be substantially masked.

[0069] In one data processing state, multiple arithmetic operations, including security operations (encryption operations, authentication operations, etc.), may be executed. In this case, the period during which switch 128 is turned on may be longer than the period during which the security operations are executed within the data processing state. This may achieve high-speed and stable execution of the security operations and masking of the execution period of the security operations.

[0070] In the first embodiment, the current source 127b and the switch 128 are connected in parallel to the current source 127a in order to increase the current of the power supply circuit 118. However, this is only an example. More current sources and switches may be connected in parallel to the current source 127a.

[0071] For example, as shown in FIG. 6 , a current source 127z and a switch 129 may be added. The processing unit 123 may control the switches 128 and 129 to finely control the increase in current depending on the command content. The timing at which the switch 128 is turned on / off may coincide with the timing at which the switch 129 is turned on / off. The timing at which the switch 128 is turned on / off may not coincide with the timing at which the switch 129 is turned on / off. In the latter case, offsetting the timing at which the switch 128 is turned on / off from the timing at which the switch 129 is turned on / off will make the change in the current I more gradual. This will prevent malfunction of the processing unit 123.

[0072] According to the first embodiment, the data carrier device 101 switches the current supplied to the internal circuitry of the data carrier device 101 in response to a command from the data carrier driving device 102. This makes it possible to temporarily increase the power supply voltage and operating frequency of the arithmetic circuitry provided in the processing unit 123 as needed. For example, the data carrier device 101 will be able to stably (safely) execute advanced arithmetic processing, such as security data processing, in a short time.

[0073] Furthermore, in the first embodiment, when the current Id to the load increases, the clamp circuit 501 reduces the current Iclamp. When the current Id to the load decreases, the clamp circuit 501 increases the current Iclamp. This maintains the current (inter-terminal current) flowing from the terminals 131A and 131B of the data carrier driving device 102 to the contacts 132A and 123B of the data carrier device 101 at a substantially constant level. In other words, the inter-terminal current is stabilized independently of the internal state of the data carrier device 101. This makes it difficult to identify the internal state of the data carrier device 101 by externally measuring the inter-terminal current. In other words, it becomes possible to substantially mask the internal state.

[0074] Second Embodiment The following mainly describes the differences between the second embodiment and the first embodiment. The same reference numerals are used to designate the same parts, and the description thereof will be omitted.

[0075] (1) Power Supply Circuit FIG. 7 shows a data carrier device 101 according to a second embodiment. The power supply circuit 118 of the first embodiment was implemented using a clamp circuit 501 as a stabilization circuit. In the second embodiment, the clamp circuit 501 is replaced with a detector 701, an amplifier 702, and a variable current source 703. The detector 701 detects the power supply voltage VDD and outputs a detected voltage Vdd proportional to the power supply voltage VDD to the amplifier 702. In essence, the detector 701 detects a current Idef flowing into the power supply circuit 118. The amplifier 702 calculates the difference between a reference voltage Vref (target value) set by the processor 123 and the power supply voltage VDD (detected voltage Vdd) and outputs the difference to the variable current source 703. The variable current source 703 controls the current Idif to minimize the difference. This may be referred to as feedback control. As a result, the current Idef flowing into the power supply circuit 118 is controlled to a constant value.

[0076] The processing unit 123 may determine or select the reference voltage Vref in accordance with the sum of currents required by loads such as the processing unit 123, the clock unit 116, and the demodulation unit 122. For example, the processing unit 123 may detect the sum of currents required by the loads using a current detection resistor, and determine or select the reference voltage Vref in accordance with the detected sum.

[0077] As shown in FIG. 7, the sum of currents flowing into the power supply circuit 118 is Idef. The sum of currents supplied from the power supply circuit 118 to each block is Id. Id is the current Iref generated by the current source 127a minus the current Idif flowing through the variable current source 703. In other words, Id is Iref minus Idif. The variable current source 703 is controlled according to the difference output from the differential amplifier circuit (amplifier 702). In other words, Idif is controlled so that Iref remains constant (target value). In other words, the variable current source 703 is controlled. For example, when Id increases, the power supply voltage VDD is reduced. In other words, the variable current source 703 is controlled so that Idif decreases.

[0078] (2) Method for Temporarily Increasing the Upper Limit Current In the second embodiment, if the command transmitted from the data carrier driving device 102 is a predetermined command requesting advanced calculations within the processing unit 123, the current Id is increased. Specifically, the processing unit 123 analyzes the demodulated data to identify the command. If the identified command is a predetermined command, the processing unit 123 switches the switch 128 from OFF to ON at the end of the data reply state or the transition to the data processing state. If the identified command is not a predetermined command, the processing unit 123 maintains the switch 128 OFF. When the switch 128 is turned ON, the total current Idef flowing into the power supply circuit 118 is Iref+Iref2+Idif. The current Id' supplied from the power supply circuit 118 to each block increases from Iref to Iref+Iref2-Idif. The processing unit 123 changes the reference voltage from Vref to Vref'. Vref' is higher than Vref. As the reference voltage increases, the power supply voltage VDD also increases. The power supply circuit 118 increases the power supply voltage VDD while maintaining the sum of the current Id' and the current Idif' constant.

[0079] When the processing unit 123 completes the execution of the predetermined command (high-level calculation by the calculation circuit), the processing unit 123 transitions from the data processing state to the standby state. At this timing, the processing unit 123 turns off the switch 128. As a result, the current of the data carrier device 101 returns from Idef' to Idef.

[0080] 8 is a more detailed circuit diagram of the power supply circuit 118. In this example, the detection unit 701 is formed by voltage-dividing resistors R3 and R4. The amplifier 702 is realized by an operational amplifier OP1. The variable current source 703 is realized by a regulator 801 and transistors Tr1, Tr2, Tr3, Tr4, and Tr5. The transistors Tr1, Tr2, and Tr5 are N-channel MOS transistors. The transistors Tr3 and Tr4 are P-channel MOS transistors.

[0081] The regulator 801 generates a constant voltage Vreg from the inter-terminal voltage Vab. As shown in FIG. 3, the inter-terminal voltage Vab is not constant because it is modulated by data and a clock. Therefore, the regulator 801 generates a constant voltage Vreg even if the inter-terminal voltage Vab fluctuates. Note that the voltage Vreg is higher than the power supply voltage VDD.

[0082] The two transistors Tr1 and Tr2 form a current mirror circuit. That is, a current equal to the current (Iref or Iref + Iref2) flowing through transistor Tr1 flows through transistor Tr2. Furthermore, the two transistors Tr3 and Tr4 also form a current mirror circuit. A current equal to the current (Iref or Iref + Iref2) flowing through transistor Tr3 flows through transistor Tr4.

[0083] Transistor Tr5, which functions as a switch, is connected to transistor Tr4. The gate of transistor Tr5 is connected to the output terminal of operational amplifier OP1. That is, transistor Tr5 turns on and off so as to reduce the difference between the power supply voltage VDD and the target value (reference voltage Vref). As a result, transistor Tr4 is switched between a state in which the current Idif is subtracted (ON) and a state in which the current Idif is not subtracted (OFF).

[0084] Therefore, the value of the power supply voltage VDD is controlled by the processing unit 123 changing the reference voltage Vref. Also, Idif is controlled so that the current flowing into the power supply circuit 118 is kept constant.

[0085] The switch 128 is realized by an N-channel MOS transistor connected in series to the current source 127b that passes the current Iref2. The processing unit 123 controls the switch 128 to control whether or not the current Iref2 of the current source 127b is added to the current Iref. For example, when the processing unit 123 outputs a low-level gate signal to the switch 128, the current Iref2 is added to the current Iref. At the same time, the processing unit 123 switches the reference voltage from Vref to Vref', thereby increasing the power supply voltage VDD.

[0086] During the period when the current Id output from the power supply circuit 118 is increasing, each block operates as follows: The power supply circuit 118 increases the power supply voltage VDD. This increased power supply voltage VDD is supplied as the power supply voltage for each block. Alternatively, the increased power supply voltage may be supplied only to an arithmetic circuit in the processing unit 123 that executes a predetermined command.

[0087] As another method, similar to the first embodiment, the processing unit 123 may increase the frequency of the internal clock CLK supplied to the arithmetic circuit that executes the predetermined command. This may involve increasing the power supply voltage VDD, increasing the frequency of the internal clock CLK, or both. In either case, the current output by the power supply circuit 118 is increased above Iref. As a result, the arithmetic circuit that executes the predetermined command can operate quickly and stably. Furthermore, the execution time of the data processing state is shortened.

[0088] In the second embodiment, the power supply voltage VDD is detected, and the detection result is fed back to the variable current source 703. However, this is merely an example. The detection unit 701 may be replaced with a current detection circuit that detects the current Id. This may keep Idif constant.

[0089] According to the second embodiment, the current that can be supplied to the internal circuit of the data carrier device 101 is switched based on an instruction from the data carrier driving device 102. This makes it possible to temporarily increase the power supply voltage VDD and the frequency of the internal clock CLK of the processing unit 123. As a result, security data can be processed quickly and safely.

[0090] The increased reference voltage Vref' does not have to be a fixed value. For example, the processing unit 123 may determine, change, or select the value of Vref' depending on a calculation method or calculation time associated with a predetermined command.

[0091] Furthermore, the detector 701, amplifier 702, and variable current source 703 operate as a stabilization circuit. That is, the current between the terminals of the data carrier driving device 102 and the data carrier device 101 is maintained substantially constant, regardless of the internal state of the processor 123. This will improve the security performance of the data carrier device 101.

[0092] Third Embodiment The following mainly describes the differences between the second and first embodiments. The same reference numerals are used to designate the same parts, and the description thereof will be omitted.

[0093] (1) Configuration of the Power Supply Circuit Fig. 9 shows a data carrier device 101 according to the third embodiment. The power supply circuit 118 according to the third embodiment is substantially the same as the power supply circuit 118 according to the first embodiment. However, the current source 127b and the switch 128 are replaced with a current source 125 and a switch 126. As described in the first embodiment, the current source 125 and the switch 126 form the switching unit 117. In other words, in the third embodiment, the power supply circuit 118 and the switching unit 117 are integrated. This reduces the number of circuit components.

[0094] 9, a series circuit made up of a current source 125 and a switch 126 is connected in parallel to a current source 127a. The switch 126 is controlled to be turned on and off by the processing unit 123.

[0095] In the third embodiment, the current source 125 and the switch 126 have the role of increasing the current Id in the data processing state and the role of modulating the current I in the data reply state. Therefore, the roles of the current source 125 and the switch 126 are changed depending on the communication state. In other words, the processing unit 123 does not assign two roles to the current source 125 and the switch 126 at the same time.

[0096] (2) Method of Temporarily Increasing the Upper Limit Current When the processing unit 123 receives a predetermined command from the data carrier driving device 102, it increases the current Id supplied to each block from the power supply circuit 118. Specifically, when the processing unit 123 receives the predetermined command, it turns on the switch 126 when the data reply state ends or when the processing unit 123 transitions to the data processing state. When the processing unit 123 receives another command with a lighter calculation load, it keeps the switch 126 off. When the switch 126 is turned on, the total current flowing into the power supply circuit 118 increases from Idef to Idef'. Idef' is the sum of Iref and Irsp, which is equal to Ix.

[0097] The current supplied from the power supply circuit 118 to each block increases from Id (= Iref) to Id' (= Iref + Irsp - Iclamp). At this time, the clamp circuit 501 performs a clamping operation so that the sum of the current Id' and the current Iclamp remains constant. In other words, if the current required by the processing unit 123 and the like increases from Id to Id', the clamp circuit 501 reduces the current Iclamp. If the current required by the processing unit 123 and the like decreases from Id' to Id, the clamp circuit 501 increases the current Iclamp.

[0098] When the processing unit 123 completes execution of the predetermined command, the processing unit 123 transitions from the data processing state to the standby state. At this timing, the processing unit 123 turns off the switch 126. The current flowing into the data carrier device 101 returns from Idef' to Idef. The operation of each block during the period when the flowing current is increasing is the same as in the first embodiment. As a result, the arithmetic circuit within the processing unit 123 can operate at high speed, thereby shortening the processing time of the data processing state.

[0099] (3) Data Reply State In the third embodiment, the switching unit 117 is incorporated into the power supply circuit 118. The switching unit 117 changes the load in accordance with the reply data input from the processing unit 123, and switches the magnitude of the current I flowing from the data carrier driving device 102 to the data carrier device 101. The method of controlling the switch 126 is the same as in the first embodiment.

[0100] 10, the power supply circuit 118 temporarily increases the upper limit current to Idef' during the data processing state. After the execution of the predetermined command is completed, the power supply circuit 118 returns the upper limit current to Idef. The current source 125 operates as both the current source for the power supply circuit 118 and the current source for the switching unit 117. Since the current source 125 supplies the current Irsp, Ix is equal to Idef', and Idef' is equal to the sum of Idef and Irsp.

[0101] 10, in the data processing state, the potential of the terminal 131B is GND potential. Because the current I is Ix (>Idef), the inter-terminal voltage Vab in the data reply state and the inter-terminal voltage Vab in the data processing state are equivalent. In other words, both inter-terminal voltages Vab are Vx, which is lower than V1'. As in the first embodiment, the voltage of the terminal 131B is V2 in the data reply state and the data reply state.

[0102] The data carrier device 101 of the first and second embodiments was able to receive and demodulate commands and send responses to the commands even when the current was increased during the data processing state. However, if the current flowing through contacts 132A and 132B becomes Idef + Iref2 + Irsp, the demodulation unit 106 of the data carrier driving device 102 will not be able to demodulate the response data. This is because the demodulation unit 106 can only demodulate the current range from Idef to Ix.

[0103] In the third embodiment, the power supply circuit 118 and the switching unit 117 share the current source 125. Therefore, when the next command arrives from the data carrier driving device 102 in the data processing state, the data carrier device 101 may prohibit the demodulation unit 122 from demodulating the command data. Alternatively, the processing unit 123 may ignore this command. In this case, the current I does not change in the data reply state. The demodulation results of the demodulation unit 106 in the data carrier driving device 102 are all high level or low level. The data carrier device 101 and the data carrier driving device 102 may have a predetermined response rule. For example, when the processing unit 103 of the data carrier driving device 102 receives all zeros or all ones in the data reply state, it determines that the command data has not been correctly transmitted to the data carrier device 101.

[0104] The data carrier driving device 102 can transmit a command while the data carrier device 101 is in the standby state. This allows the data carrier driving device 102 to correctly acquire the data processed by the data carrier device 101.

[0105] According to the third embodiment, the current that can be supplied to the internal circuit of the data carrier device 101 is switched based on a command from the data carrier driving device 102. This increases the power supply voltage and operating frequency of the arithmetic circuit provided inside the processing unit 123. As a result, security data can be processed quickly and safely. In addition, some components (current source 125, switch 126) may be shared between multiple internal circuits provided in the data carrier device 101. This reduces the circuit size of the data carrier device 101.

[0106] 11 shows an arithmetic circuit or control circuit included in the processing unit 123. A command analysis unit 1101 analyzes data demodulated by the demodulation unit 122 to identify the command. When the received command is a predetermined command, an authentication calculation unit 1102 executes authentication calculation required for the data carrier driving device 102 to authenticate the data carrier device 101. The authentication calculation may include, for example, calculating a response by applying an authentication key or the like to a challenge provided by the data carrier driving device 102.

[0107] The memory access unit 1103 reads out the specified information from the memory 124 in accordance with a command to read out the specified information received from the data carrier driving device 102. The transmission control unit 1104 supplies the reply data created by the authentication calculation unit 1102 or the memory access unit 1103 to the switching unit 117, and causes the switching unit 117 to transmit the reply data to the data carrier driving device 102. The switching unit 117 may also be called a transmission circuit or a modulation circuit.

[0108] The state recognition unit 1105 recognizes the communication state based on the inter-terminal voltage Vab, the current I, or the execution / completion of internal processing of the processing unit 123. For example, if the inter-terminal voltage Vab is V1'-V2, the current I is Idef, and the processing unit 123 is not executing processing corresponding to a command, the communication state is determined to be a standby state. If the inter-terminal voltage Vab becomes higher than V1'-V2 in the standby state, the communication state is recognized as a data transmission state. If the inter-terminal voltage Vab has a pulse shape with a constant interval, that is, if the pulse duty ratio is constant, the communication state is determined as an interval state. If the current I varies between Idef and Ix, the communication state is determined as a data reply state. If the inter-terminal voltage Vab is V1'-V2, the current I is Idef, and the processing unit 123 is executing processing corresponding to a command, the communication state is determined as a data processing state.

[0109] When the power supply control unit 1106 receives a predetermined command, it switches the switch 128 of the power supply circuit 118 from off to on in the data processing state. As a result, the current supplied to the processing unit 123 and the like increases from Id to Id'. When another state or another command is received, the power supply control unit 1106 keeps the switch 128 off.

[0110] When a predetermined command is received, the clock control unit 1107 increases the frequency f of the internal clock CLK generated by the clock unit 116 from f1 to f2 in the data processing state. f2 is higher than f1. This enables the processing unit 123 to operate at a higher speed. When another state or another command is received, the clock control unit 1107 maintains the frequency f of the internal clock CLK generated by the clock unit 116 at f1.

[0111] 11 , a calculation circuit (e.g., authentication calculation unit 1102) that performs advanced calculations is provided inside processing unit 123. The calculation circuit (e.g., authentication calculation unit 1102) that performs advanced calculations may be provided outside processing unit 123.

[0112] Fifth Embodiment Fig. 12 is a flowchart showing a control method executed by a processing unit 123. The processing unit 123 may include a processor such as a CPU that executes a program stored in a memory 124. CPU is an abbreviation for central processing unit. Note that the initial communication state is a standby state. Fig. 12 also shows the correspondence between steps and states.

[0113] In S1201, the processing unit 123 determines whether communication has started based on the inter-terminal voltage Vab. If communication has been started by the data carrier driving device 102, the processing unit 123 proceeds from S1201 to S1202.

[0114] In S1202, the processing unit 123 receives command data from the data carrier driving device 102. The demodulation unit 122 demodulates the command data based on the duty ratio of the pulse of the inter-terminal voltage Vab.

[0115] In S1203, the processing unit 123 analyzes the demodulated command data, thereby identifying the command content from the command data.

[0116] In S1204, if the instruction data is correctly demodulated by the demodulation unit 122, the processing unit 123 generates reply data indicating ACK.

[0117] In S1205 , the processing unit 123 outputs the reply data to the switching unit 117 , thereby transmitting the reply data to the data carrier driving device 102 .

[0118] In S1206, the processing unit 123 determines whether the demodulated command is a predetermined command (e.g., altitude calculation command). If the demodulated command is an altitude calculation command, the processing unit 123 proceeds from S1206 to S1207.

[0119] In S1207, the processing unit 123 switches the switch 128 from off to on, thereby increasing the current supplied to the processing unit 123, etc. As a result, the current supplied to the processing unit 123, etc. increases from Id to Id'.

[0120] In S1208, the processing unit 123 increases the power supply voltage VDD or the operating frequency (the frequency of the internal clock CLK), thereby enabling the processing unit 123 to perform calculations at high speed and stably.

[0121] In S1209, the processing unit 123 executes a predetermined command (altitude calculation command), such as an authentication calculation.

[0122] In S1210, the processing unit 123 restores the current I, the power supply voltage VDD, and the operating frequency f to their original values.

[0123] If it is determined in S1206 that the demodulated command is not an altitude calculation command, the processing unit 123 proceeds from S1206 to S1220. In S1220, the processing unit 123 executes the demodulated command. In this case, the current supplied to the processing unit 123 is not increased.

[0124] 13 shows an electrophotographic image forming apparatus 1300, which is an example of the data communication system 100. The image forming apparatus 1300 is equipped with a detachable process cartridge 22. The process cartridge 22 has a photosensitive drum 1, a charging roller 2, a developing roller 24, a toner container 7, a cleaning member 41, and a data carrier device 101.

[0125] The engine controller 12 has a data carrier driving device 102. The engine controller 12 controls each unit constituting the image forming apparatus 1300.

[0126] The photosensitive drum 1 is an image carrier that is rotationally driven by a motor or the like. The charging roller 2 is in contact with the photosensitive drum 1 and rotates in accordance with the rotation of the photosensitive drum 1. A charging bias (e.g., a negative high voltage) is applied to the charging roller 2 from a high-voltage power supply 40. This causes a discharge between the photosensitive drum 1 and the charging roller 2, and a discharge current (charging current) flows from the photosensitive drum 1 to the charging roller 2. As a result, the surface of the photosensitive drum 1 becomes charged.

[0127] As the photosensitive drum 1 rotates, the charged surface portion is irradiated with light output from the light source 3 of the exposure device 4. As a result, the surface potential of the exposed surface portion changes to a light-area potential VL (exposure process). Furthermore, an electrostatic latent image corresponding to the image data is formed on the surface of the photosensitive drum 1 by the exposure. The light source 3 may be a semiconductor laser or a light-emitting diode such as an organic EL. EL is an abbreviation for electroluminescence.

[0128] As the photosensitive drum 1 rotates, the exposed surface portion reaches the developing roller 24. The high-voltage power supply 40 is a power supply device that applies a developing bias to the developing roller 24. As a result, the toner T in the toner container 7 adheres to the surface of the photosensitive drum 1 through the developing roller 24, and a toner image is formed (developing process).

[0129] As the photosensitive drum 1 rotates, the toner image is transported to the transfer nip. The transfer nip is formed between the transfer roller 8 and the photosensitive drum 1. The engine controller 12 controls the high-voltage power supply 40 to apply a positive transfer bias (e.g., a bias of positive polarity) to the transfer roller 8. This causes the toner image carried on the surface of the photosensitive drum 1 to be transferred to the sheet P (transfer process). The sheet P is stored in a sheet cassette 5, and is fed and conveyed by a feed roller 10.

[0130] The sheet P is transported from the transfer nip to a fixing device 19. The fixing device 19 has a cylindrical pressure roller and a cylindrical heating film. The fixing device 19 applies heat and pressure to the sheet P and the toner image, fixing the toner image onto the sheet P (fixing process). The discharge rollers 11 discharge the sheet P, which has been transported along the transport path, onto a sheet tray 17.

[0131] In this manner, the data carrier driving device 102 may be provided in the main body of the image forming apparatus 1300, and the data carrier device 101 may be provided in a replacement unit (e.g., process cartridge 22) of the image forming apparatus 1300. When the replacement unit is attached to the image forming apparatus 1300, the data carrier driving device 102 and the data carrier device 101 are connected via two communication lines 133A and 133B. The data carrier device 101 has a memory 124 that stores information about the replacement unit. This allows the engine controller 12 to acquire the information about the replacement unit stored in the memory 124. Note that the information stored in the memory 124 may be, for example, information about authentication of the replacement unit. This information may also be information about control parameters (e.g., charging voltage, developing voltage, fixing temperature, total operating time) applied to image formation performed using the replacement unit.

[0132] <Summary> Data carrier device 101 operates by receiving power from data carrier driving device 102. Contact 132A is an example of a first terminal connected to data carrier driving device 102. Contact 132B is an example of a second terminal connected to data carrier driving device 102. The IC in data carrier device 101 is an example of an integrated circuit connected to the first terminal and the second terminal. When the inter-terminal voltage between the first terminal and the second terminal changes in a specific pattern, the IC can increase the value of the current supplied from data carrier driving device 102 to data carrier device 101 through the first terminal from a first current value to a second current value.

[0133] As illustrated in FIG. 1 , when the inter-terminal voltage Vab changes according to a specific pattern, the IC increases the value of the current I supplied through the first terminal (e.g., contact 132A) from a first current value Idef to a second current value Idef'. This provides a data carrier device 101 capable of increasing the current I supplied from the data carrier driving device 102 as needed. The power supply circuit 118 generates a power supply voltage from power supplied from the first and second terminals. The clock unit 116 is an example of a clock circuit that operates on the power supply voltage supplied from the power supply circuit 118 and generates a clock signal. The demodulation unit 122 is an example of a demodulation circuit that operates on the power supply voltage supplied from the power supply circuit 118 and demodulates commands received through the first and second terminals. The processing unit 123 is an example of a processing circuit that operates by receiving the power supply voltage supplied from the power supply circuit 118 and the clock signal. According to FIG. 3 , the specific pattern is a pattern of the inter-terminal voltage that indicates that the command is a predetermined command.

[0134] When the command is a predetermined calculation command, the processing unit 123 may perform at least one of controlling the power supply circuit 118 to increase the power supply voltage and controlling the clock unit 116 to increase the frequency of the clock signal. In order to execute a high-level calculation in a short time, the frequency of the internal clock CLK may be increased. Furthermore, in order to stably execute the high-level calculation, the operating voltage of the calculation circuit that executes the calculation may be increased.

[0135] The IC may change the value of the current in a predetermined current pattern in response to the specific pattern before increasing the value of the current from the first current value to the second current value. As illustrated in Figure 4, the data processing state follows the data reply state. Therefore, the current may be increased when the data reply state ends.

[0136] The predetermined current pattern may be an acknowledgement pattern indicating that the predetermined calculation command has been successfully demodulated from the specific pattern. As shown in Fig. 4, the reply data may include an ACK. The ACK corresponds to the predetermined current pattern.

[0137] The processing unit 123 may execute a calculation corresponding to a predetermined calculation command during the period when the current value is the second current value, thereby enabling the calculation corresponding to the predetermined calculation command to be executed stably in a short time.

[0138] The processing unit 123 may increase the current value before starting a calculation corresponding to a predetermined calculation command, and decrease the current value after completing the calculation corresponding to the predetermined calculation command. As illustrated in Fig. 4, the current may be increased before starting an advanced calculation, and decreased when the advanced calculation is completed. In other words, the current may be increased at least in the data processing state.

[0139] The IC may maintain the value of the current at the second current value for at least a predetermined period of time. By increasing the current for a predetermined period of time in this manner, it may be difficult to determine when advanced operations, such as authentication operations, are being performed.

[0140] Here, the predetermined period may be longer than the time from when the predetermined calculation process corresponding to the specific pattern starts to when the predetermined calculation process ends. In this way, the period during which advanced calculations such as authentication calculations are being performed may be masked.

[0141] The IC may increase the current value stepwise from the first current value to the second current value. The power supply circuit 118 shown in Figure 5 can increase the current value stepwise. This will ensure stable operation of the data carrier device 101.

[0142] If the voltage between the terminals of the IC changes during a period when the current value is the second current value, the IC may send a negative response to the data carrier driving device by maintaining the current value at the second current value. As suggested in the third embodiment, it is difficult to correctly demodulate the command during a period when the current I is increasing. Therefore, the processing unit 123 may send reply data corresponding to a NACK.

[0143] 5 , the power supply circuit 118 may include a first current source 127a connected to the first terminal, a second current source 127b connected in parallel to the first current source, and a first switch 128 connected in parallel to the first current source and in series to the second current source, the first switch 128 being controlled by the processing unit 123. The processing unit 123 may switch the value of the current from the first current value to the second current value by switching the first switch 128 from off to on. The processing unit 123 may switch the value of the current from the second current value to the first current value by switching the first switch from on to off. In this way, a simple circuit configuration makes it possible to switch the current value in the data carrier device 101.

[0144] The power supply circuit 118 may include a stabilization circuit that stabilizes the current flowing from the data carrier driving device to the data carrier device through the first and second terminals. The clamp circuit 501, the variable current source 703, and the circuit shown in FIG. 8 are examples of a stabilization circuit. The stabilization circuit may generate a load current supplied from the power supply circuit to a load including a processing circuit by adjusting a subtraction current subtracted from the power supply current supplied from the first current source 127a and the second current source 127b. Here, Iclamp and Idif are examples of subtraction currents. Iref, or the sum of Iref and Iref2, is an example of a power supply current. In this way, the inter-terminal current flowing from the data carrier driving device 102 to the data carrier device 101 through the first and second terminals may be stabilized (e.g., made constant). In other words, the inter-terminal current may be stabilized independently of the internal state of the data carrier device 101. This makes it difficult to identify the internal state of the data carrier device 101 by measuring the inter-terminal current. In other words, it may be possible to substantially mask the internal state. In this way, the security performance of the data communication system 100 may be improved.

[0145] 5, the stabilization circuit may include a clamp circuit 501 that reduces the subtraction current when the load current increases and increases the subtraction current when the load current decreases. In this manner, the current between the terminals may be stabilized by the clamp circuit 501. This may improve the security performance of the data communication system 100.

[0146] 7, the stabilization circuit may include a detection circuit (e.g., a detection unit 701 and an amplifier 702) that detects the power supply voltage, and a variable current source 703 that generates a subtraction current so that the power supply voltage is maintained at a target value. In this manner, the current between the terminals may be stabilized by the detection unit 701, the amplifier 702, and the variable current source 703. This may improve the security performance of the data communication system 100.

[0147] 8, power supply circuit 118 may have a voltage regulator that receives a terminal voltage and generates a power supply voltage lower than the terminal voltage. Here, not only regulator 801 but also power supply circuit 118 itself is an example of a voltage regulator. Note that by employing regulator 801 and power supply circuit 118, two terminals 131A, 131B and two contacts 132A, 132B can be shared for both power supply and communication.

[0148] The power supply circuit 118 may further include a stabilization circuit that reduces current fluctuations at the output terminal of the voltage regulator that outputs the power supply voltage compared to fluctuations in current flowing into the input terminal of the voltage regulator. Here, the power supply circuit 118 may function as a stabilization circuit that reduces current fluctuations at the output terminal that outputs the power supply voltage VDD compared to fluctuations in current flowing into the input terminal.

[0149] 5, the voltage regulator may include a first current source 127a connected to the first terminal, a second current source 127b connected in parallel to the first current source, a switch 128 connected in parallel to the first current source 127a and in series to the second current source 127b and controlled by the processing unit 123, and a clamp circuit 501 connected to the first current source 127a and to the second current source 127b via the switch 128. In other words, the current sources 127a, 127b, the switch 128, and the clamp circuit 501 may function as a voltage regulator.

[0150] 7 , clamp circuit 501 may include a detection circuit (e.g., detector 701) that detects the power supply voltage and generates a detection voltage proportional to the power supply voltage, an amplifier 702 that amplifies the difference voltage between the detection voltage and a reference voltage corresponding to a target value of the power supply voltage, and an adjustment circuit (e.g., variable current source 703) that adjusts the value of a current in accordance with the output of the amplifier so that the power supply voltage approaches the target value. In other words, clamp circuit 501 may be realized by detector 701, amplifier 702, and variable current source 703.

[0151] The adjustment circuit may include a variable current source 703 that adjusts a subtraction current that is subtracted from the current flowing from the first terminal.

[0152] As illustrated in FIG. 8, the switching unit 117 is an example of a current modulator that modulates the inter-terminal current flowing between the first terminal and the second terminal in accordance with the reply data for the specific pattern.

[0153] As illustrated in FIG. 8, the current modulator may have a third current source 125 connected to the first terminal, and a second switch 126 connected between the third current source 125 and the second terminal and turned on and off in response to the return data.

[0154] 9, the current source 125 may function as a common current source, and the switch 126 may function as a common switch, thereby reducing the number of components.

[0155] When the data carrier driving device 102 modulates the inter-terminal voltage during a period in which the current value is a first current value, the switching unit 117 may modulate the inter-terminal current. When the data carrier driving device 102 modulates the inter-terminal voltage during a period in which the current value is a second current value, the switching unit 117 may not modulate the inter-terminal current even if the data carrier driving device 102 modulates the inter-terminal current. As mentioned in the third embodiment, when a command is transmitted in the data transmission state, the current is modulated in the data reply state. When a command is transmitted in the data processing state, the data carrier driving device 101 does not execute a reply. This allows the data carrier driving device 102 to recognize that transmission of the command has failed. Here, the predetermined command may include a command requesting execution of an authentication operation.

[0156] The data carrier device 101 may be an electronic module provided in a replacement part for the image forming device.

[0157] The IC may increase the value of the current from a first current value to a second current value when a predetermined time has elapsed since the inter-terminal voltage between the first terminal and the second terminal changed in a specific pattern.

[0158] The interval state and the data reply state may each have a fixed length. In this case, the start timing of the data processing state is a predetermined time after the end of transmission of a specific command in the data transmission state. Therefore, the value of the current may be changed based on the end of transmission of the specific command.

[0159] 13, the process cartridge 22 is an example of a replacement part that is involved in image formation and is replaced when worn out or broken. The data carrier device 101 may be provided as a replacement part. Note that the replacement part may also be other parts such as a toner bottle, a roller, or a belt.

[0160] The IC may have a transmission state in which the data carrier driving device 102 transmits a command to the data carrier device 101, and a processing state in which the IC executes a calculation process according to the command received in the transmission state. In the transmission state, the value of the current supplied from the data carrier driving device to the data carrier device through the first terminal may be a first current value. In the processing state, the value of the current may be a second current value, and the second current value may be greater than the first current value.

[0161] The IC may further have a reply state for executing a reply to the command. When transitioning from the reply state to the processing state, the IC may increase the value of the current from a first current value to a second current value.

[0162] The power supply circuit 118 functions as a power supply circuit that generates a power supply voltage in response to a voltage or current supplied from the first terminal and the second terminal. The clock unit 116 is an example of a clock circuit that operates using the power supply voltage supplied from the power supply circuit to generate a clock signal. The demodulation unit 122 operates using the power supply voltage supplied from the power supply circuit and functions as a demodulation circuit that demodulates commands received through the first terminal and the second terminal. The processing unit 123 is an example of a processing circuit that operates by receiving the power supply voltage and the clock signal supplied from the power supply circuit 118. Upon receiving a predetermined calculation command, the processing unit 123 controls the power supply circuit 118 to increase the power supply voltage or controls the clock unit 116 to increase the frequency of the clock signal. At this time, the power supply circuit 118 increases the value of the current supplied to the processing unit 123, the demodulation unit 122, and the clock unit 116.

[0163] The present invention can also be realized by supplying a program that realizes one or more of the functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., an ASIC) that realizes one or more of the functions.

[0164] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention.

[0165] This application claims priority based on Japanese Patent Application No. 2024-032520, filed March 4, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A data carrier device that operates by receiving power from a data carrier driving device, comprising: a first terminal connected to the data carrier driving device; a second terminal connected to the data carrier driving device; and an integrated circuit connected to the first terminal and the second terminal, wherein the integrated circuit increases the value of the current supplied from the data carrier driving device to the data carrier device through the first terminal from a first current value to a second current value when the inter-terminal voltage between the first terminal and the second terminal changes in a specific pattern.

2. The data carrier device of claim 1, wherein the integrated circuit comprises: a power supply circuit that generates a power supply voltage from power supplied from the first terminal and the second terminal; a clock circuit that operates using the power supply voltage supplied from the power supply circuit to generate a clock signal; a demodulation circuit that operates using the power supply voltage supplied from the power supply circuit and demodulates commands received through the first terminal and the second terminal; and a processing circuit that operates by receiving the power supply voltage supplied from the power supply circuit and the clock signal; and wherein the specific pattern is a pattern of the voltage between the terminals that indicates that the command is a predetermined command.

3. The data carrier device of claim 2, wherein the processing circuit, when the command is a predetermined calculation command, executes at least one of controlling the power supply circuit to increase the power supply voltage and controlling the clock circuit to increase the frequency of the clock signal.

4. The data carrier device of claim 3, wherein the integrated circuit changes the value of the current in a predetermined current pattern in response to the specific pattern before increasing the value of the current from the first current value to the second current value.

5. The data carrier device according to claim 4, wherein the predetermined current pattern is an acknowledgement pattern indicating that the predetermined operation command has been successfully demodulated from the specific pattern.

6. The data carrier device according to claim 3, wherein the processing circuit executes an operation corresponding to the predetermined operation command during a period in which the current value is the second current value.

7. The data carrier device according to claim 3, wherein the processing circuit increases the value of the current before starting an operation corresponding to the specified operation command, and decreases the value of the current after completing the operation corresponding to the specified operation command.

8. The data carrier device according to claim 7, wherein the integrated circuit maintains the value of the current at the second current value for at least a predetermined period of time.

9. The data carrier device according to claim 8, wherein the predetermined period is longer than the time from when the predetermined arithmetic processing corresponding to the specific pattern is started to when the predetermined arithmetic processing is completed.

10. A data carrier device according to any one of claims 1 to 9, wherein the integrated circuit increases the value of the current stepwise from the first current value to the second current value.

11. A data carrier device according to any one of claims 1 to 10, wherein if the inter-terminal voltage changes during a period in which the current value is the second current value, the integrated circuit sends a negative response to the data carrier driving device by maintaining the current value at the second current value.

12. A data carrier device as described in any one of claims 2 to 9, wherein the power supply circuit has: a first current source connected to the first terminal; a second current source connected in parallel to the first current source; and a first switch connected in parallel to the first current source and in series to the second current source, the first switch being controlled by the processing circuit; and wherein the processing circuit switches the value of the current from the first current value to the second current value by switching the first switch from off to on, and switches the value of the current from the second current value to the first current value by switching the first switch from on to off.

13. The data carrier device according to claim 12, wherein the power supply circuit has a stabilizing circuit that stabilizes the current flowing from the data carrier driving device to the data carrier device through the first terminal and the second terminal, and the stabilizing circuit generates a load current that is supplied from the power supply circuit to a load including the processing circuit by adjusting a subtraction current that is subtracted from the power supply current supplied from the first current source and the second current source.

14. The data carrier device according to claim 13, wherein the stabilization circuit includes a clamp circuit that reduces the subtraction current when the load current increases and increases the subtraction current when the load current decreases.

15. The data carrier device according to claim 13, wherein the stabilization circuit includes a detection circuit that detects the power supply voltage, and a variable current source that generates the subtraction current so that the power supply voltage is maintained at a target value.

16. A data carrier device according to any one of claims 2 to 9 and 12 to 15, wherein the power supply circuit has a voltage regulator that receives the inter-terminal voltage and generates the power supply voltage that is lower than the inter-terminal voltage.

17. The data carrier device according to claim 16, further comprising a stabilization circuit that reduces fluctuations in current at the output terminal of said voltage regulator that outputs said power supply voltage compared to fluctuations in current flowing into the input terminal of said voltage regulator.

18. The data carrier device of claim 16, wherein the voltage regulator comprises: a first current source connected to the first terminal; a second current source connected in parallel to the first current source; a switch connected in parallel to the first current source and in series to the second current source, the switch being controlled by the processing circuit; and a clamp circuit connected to the first current source and to the second current source via the switch.

19. The data carrier device according to claim 18, wherein the clamp circuit comprises: a detection circuit that detects the power supply voltage and generates a detection voltage proportional to the power supply voltage; an amplifier that amplifies the difference voltage between the detection voltage and a reference voltage corresponding to a target value of the power supply voltage; and an adjustment circuit that adjusts the value of the current in accordance with the output of the amplifier so that the power supply voltage approaches the target value.

20. The data carrier device according to claim 19, wherein the adjustment circuit includes a variable current source that adjusts a subtraction current that is subtracted from the current flowing from the first terminal.

21. The data carrier device according to claim 12, further comprising a current modulator that modulates an inter-terminal current flowing between said first terminal and said second terminal in accordance with reply data for said specific pattern.

22. The data carrier device according to claim 21, wherein the current modulator comprises: a third current source connected to the first terminal; and a second switch connected between the third current source and the second terminal and turned on and off in response to the reply data.

23. The data carrier device according to claim 22, wherein the second current source and the third current source are a common current source, and the first switch and the second switch are a common switch.

24. The data carrier device according to claim 21, wherein the current modulator modulates the inter-terminal current when the inter-terminal voltage is modulated by the data carrier driving device during a period when the current value is the first current value, and does not modulate the inter-terminal current during a period when the current value is the second current value, even if the inter-terminal voltage is modulated by the data carrier driving device.

25. The data carrier device according to claim 2, wherein the predetermined command includes a command to perform an authentication operation.

26. The data carrier device according to any one of claims 1 to 25, wherein the data carrier device is an electronic module provided in a replacement part for an image forming device.

27. A data carrier device according to any one of claims 1 to 26, wherein the integrated circuit increases the value of the current from the first current value to the second current value when a predetermined time has elapsed since the inter-terminal voltage between the first terminal and the second terminal changed in the specific pattern.

28. A data communication system comprising: a data carrier driving device; and a data carrier device that operates by receiving power from the data carrier driving device, wherein the data carrier device has: a first terminal connected to the data carrier driving device; a second terminal connected to the data carrier driving device; and an integrated circuit connected to the first terminal and the second terminal, wherein the integrated circuit increases the value of the current supplied from the data carrier driving device to the data carrier device through the first terminal from a first current value to a second current value when the inter-terminal voltage between the first terminal and the second terminal changes in a specific pattern.

29. An image forming apparatus comprising: a replacement part that is involved in image formation and is replaced when it wears out or breaks down; a data carrier device provided on the replacement part; and a data carrier driving device that communicates with the data carrier device, wherein the data carrier device is a data carrier device that operates by receiving power from the data carrier driving device, and has: a first terminal connected to the data carrier driving device; a second terminal connected to the data carrier driving device; and an integrated circuit connected to the first terminal and the second terminal, wherein the integrated circuit increases the value of the current supplied to the data carrier device from the data carrier driving device through the first terminal from a first current value to a second current value when the inter-terminal voltage between the first terminal and the second terminal changes in a specific pattern.

30. A data carrier device that operates by receiving power from a data carrier driving device, comprising: a first terminal connected to the data carrier driving device; a second terminal connected to the data carrier driving device; and an integrated circuit connected to the first and second terminals, wherein the integrated circuit has a transmission state in which the data carrier driving device transmits commands to the data carrier device, and a processing state in which it executes arithmetic processing in accordance with the commands received in the transmission state, wherein in the transmission state, the value of the current supplied from the data carrier driving device to the data carrier device through the first terminal is a first current value, and in the processing state, the value of the current is a second current value, and the second current value is greater than the first current value.

31. The data carrier device according to claim 30, wherein the integrated circuit further has a reply state for executing a reply to the command, and when transitioning from the reply state to the processing state, increases the value of the current from the first current value to the second current value.

32. A data carrier device that operates by receiving power from a data carrier driving device, comprising: a first terminal connected to the data carrier driving device; a second terminal connected to the data carrier driving device; a power supply circuit that generates a power supply voltage in response to the voltage or current supplied from the first terminal and the second terminal; a clock circuit that operates by the power supply voltage supplied from the power supply circuit and generates a clock signal; a demodulation circuit that operates by the power supply voltage supplied from the power supply circuit and demodulates commands received through the first terminal and the second terminal; and a processing circuit that operates by receiving the power supply voltage and the clock signal supplied from the power supply circuit, wherein when the command is a predetermined calculation command, the processing circuit increases the value of the current supplied from the data carrier driving device to the data carrier device through the first terminal from a first current value to a second current value, and controls the power supply circuit to increase the power supply voltage or controls the clock circuit to increase the frequency of the clock signal.

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