Photoelectric conversion element, imaging device, and camera system

Abstract

This photoelectric conversion element comprises: a photoelectric conversion layer (4) that contains a first donor organic semiconductor material (4A) and a first acceptor organic semiconductor material (4B) and converts light into a signal charge; a first electrode (2) that collects the signal charge; a second electrode (6) that faces the first electrode (2), with the photoelectric conversion layer (4) being interposed therebetween; and a charge injection layer (5) that is located between the second electrode (6) and the photoelectric conversion layer (4). The charge injection layer (5) is a bulk hetero layer that has a bulk heterojunction structure which contains a second donor organic semiconductor material (5A) and a second acceptor organic semiconductor material (5B). The ratio of the amount of the second acceptor organic semiconductor material (5B) to the amount of the second donor organic semiconductor material (5A) in the charge injection layer (5) is smaller than the ratio of the amount of the first acceptor organic semiconductor material (4B) to the amount of the first donor organic semiconductor material (4A) in the photoelectric conversion layer (4). The thickness of the charge injection layer (5) is smaller than the thickness of the photoelectric conversion layer (4).

Description

Photoelectric conversion element, imaging device, and camera system

[0001] The present disclosure relates to a photoelectric conversion element, an imaging device, and a camera system.

[0002] Photoelectric conversion elements using semiconductor thin films can be used as optical sensors, image pickup devices, etc. by extracting signal charges generated by light as electrical signals.

[0003] For example, Patent Document 1 discloses a solid-state imaging device that uses a photoelectric conversion element that includes a hole collecting electrode, an electron collecting electrode, a photoelectric conversion layer disposed between these electrodes, and a first charge blocking layer and a second charge blocking layer that suppress injection of charges from the hole collecting electrode or the electron collecting electrode into the photoelectric conversion layer.

[0004] JP 2009-099688 A International Publication No. 2017 / 094229

[0005] As in the photoelectric conversion element disclosed in Patent Document 1, when a layer other than the photoelectric conversion layer, such as a charge blocking layer, is formed between the photoelectric conversion layer and the electrode, the photoelectric conversion efficiency of the photoelectric conversion element is likely to decrease.

[0006] In addition, in Patent Document 1, the charge blocking layer suppresses dark current by suppressing charge injection from the electrode to the photoelectric conversion layer. On the other hand, in a photoelectric conversion element, it is sometimes useful to promote charge injection from the electrode to the photoelectric conversion layer.

[0007] Therefore, an object of the present disclosure is to provide a photoelectric conversion element and the like that can achieve both improved charge injection from an electrode to a photoelectric conversion layer and suppression of a decrease in photoelectric conversion efficiency.

[0008] A photoelectric conversion element according to one aspect of the present disclosure includes a photoelectric conversion layer containing a first donor semiconductor material and a first acceptor semiconductor material and converting light into signal charges, a first electrode collecting the signal charges, a second electrode facing the first electrode with the photoelectric conversion layer sandwiched therebetween, and a charge injection layer located between the second electrode and the photoelectric conversion layer. The charge injection layer is a bulk heterolayer having a bulk heterojunction structure containing a second donor semiconductor material and a second acceptor semiconductor material. The ratio of the amount of the second acceptor semiconductor material to the amount of the second donor semiconductor material in the charge injection layer is smaller than the ratio of the amount of the first acceptor semiconductor material to the amount of the first donor semiconductor material in the photoelectric conversion layer. The thickness of the charge injection layer is smaller than the thickness of the photoelectric conversion layer.

[0009] An imaging device according to an aspect of the present disclosure includes the photoelectric conversion element and a charge accumulation region electrically connected to the first electrode and configured to accumulate the signal charge.

[0010] A camera system according to an aspect of the present disclosure includes the imaging device.

[0011] According to the present disclosure, it is possible to improve the charge injection from the electrode to the photoelectric conversion layer while suppressing a decrease in photoelectric conversion efficiency.

[0012] FIG. 1 is a schematic cross-sectional view showing the configuration of a photoelectric conversion element according to an embodiment. FIG. 2 is a diagram showing an exemplary energy band of a photoelectric conversion element according to an embodiment. FIG. 3 is a diagram showing an exemplary energy band of a photoelectric conversion element according to an embodiment when a reverse bias voltage is applied. FIG. 4 is a diagram showing an exemplary energy band of a photoelectric conversion element according to an embodiment when a forward bias voltage is applied. FIG. 5 is a diagram showing an example of a circuit configuration of an imaging device according to an embodiment. FIG. 6 is a schematic cross-sectional view showing a device structure of a pixel in an imaging device according to an embodiment. FIG. 7 is a diagram showing a part of a schematic circuit configuration of a pixel according to an embodiment. FIG. 8 is a timing chart showing an example of a voltage supplied to an upper electrode of a photoelectric conversion unit according to an embodiment and an example of the timing of operations in each row of a pixel array of an imaging device. FIG. 9 is a timing chart showing an example of an operation of adjusting photoelectric conversion sensitivity using a pulse duty control system in an imaging device according to an embodiment. FIG. 10 is a block diagram showing an example of the configuration of a camera system according to an embodiment. FIG. 11 is a diagram showing a schematic configuration of photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3. Fig. 12 is a diagram showing the relationship between the capacitance and the voltage applied between the upper electrode and the lower electrode in the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3. Fig. 13 is a diagram showing the schematic configuration of the photoelectric conversion elements in Examples 2 and 4 to 8. Fig. 14 is a diagram showing the relationship between the thickness of the charge injection layer and the capacitance when a voltage of -2 V is applied between the upper electrode and the lower electrode in the photoelectric conversion elements in Examples 2 and 4 to 8 and Comparative Example 2.

[0013] (How One Aspect of the Present Disclosure Was Achieved) Before describing the embodiments of the present disclosure in detail, the how the inventors of the present disclosure arrived at one aspect of the present disclosure will be described.

[0014] Image capture devices typically use a rolling shutter method, in which exposure and signal charge readout are performed sequentially for each row of the pixel array. With the rolling shutter method, the timing of the start and end of exposure differs for each row of the pixel array. This can result in distorted images of fast-moving objects, or brightness differences within the image when using a flash. Given these circumstances, there is a growing demand for a global shutter function, in which exposure starts and ends at the same time for all pixels in the pixel array.

[0015] For example, Patent Document 2 discloses an imaging device including a first electrode connected to a charge accumulation region, a second electrode connected to a voltage supply circuit, and a plurality of unit pixel cells including a photoelectric conversion layer located between the first electrode and the second electrode. In the imaging device disclosed in Patent Document 2, the voltage supply circuit supplies a first voltage to the second electrode during an exposure period, and supplies a second voltage different from the first voltage to the second electrode during a non-exposure period, thereby realizing a global shutter function.

[0016] To achieve the global shutter function, the movement of signal charges from the photoelectric conversion layer to the charge accumulation region is suppressed during non-exposure periods by controlling the voltages applied to the electrodes sandwiching the photoelectric conversion layer, and the signal charges are read out. However, simply controlling the voltages applied to the electrodes sandwiching the photoelectric conversion layer may not completely eliminate the movement of signal charges from the photoelectric conversion layer to the charge accumulation region during non-exposure periods. This poses a problem in photoelectric conversion elements and imaging devices, etc., in that parasitic sensitivity, which is an unintended sensitivity caused by the movement of signal charges from the photoelectric conversion layer during signal charge readout, occurs.

[0017] Here, in order to suppress the occurrence of parasitic sensitivity, it is possible to consider a means of injecting charges of the opposite polarity to the signal charges into the photoelectric conversion layer during the non-exposure period, thereby recombining the injected charges with the signal charges remaining in the photoelectric conversion layer or newly generated in the photoelectric conversion layer. Therefore, in order to reduce parasitic sensitivity in photoelectric conversion elements, imaging devices, etc., it is effective to improve the charge injection property of charges of the opposite polarity to the signal charges from the electrodes to the photoelectric conversion layer during the non-exposure period.

[0018] However, when the photoelectric conversion layer is a mixed layer containing a donor semiconductor material such as a p-type organic semiconductor and an acceptor semiconductor material such as fullerenes, as disclosed in Patent Document 1, damage caused when forming an electrode on the photoelectric conversion layer can cause trap levels to form in the donor semiconductor material on the surface of the photoelectric conversion layer. As a result, the trap levels prevent charge injection from the electrode into the photoelectric conversion layer. Therefore, by forming a charge injection layer that does not contain a donor semiconductor material on the photoelectric conversion layer, trap levels are not generated in the charge injection layer even when the electrode is formed, and charge injection performance can be improved. On the other hand, a charge injection layer that does not contain a donor semiconductor material can absorb light incident on the photoelectric conversion element, resulting in light absorption loss in the photoelectric conversion layer. Furthermore, when the charge injection layer is formed without changing the overall thickness of the photoelectric conversion element, the thickness of the photoelectric conversion layer is reduced. Therefore, even though the charge injection performance is improved by forming the charge injection layer, the photoelectric conversion efficiency decreases.

[0019] Therefore, the present disclosure provides a photoelectric conversion element and the like that can achieve both improved charge injection from an electrode to a photoelectric conversion layer and suppression of a decrease in photoelectric conversion efficiency.

[0020] (Summary of the Present Disclosure) As an overview of one aspect of the present disclosure, examples of a photoelectric conversion element, an imaging device, and a camera system according to the present disclosure are described below.

[0021] (First Aspect) A photoelectric conversion element according to the first aspect of the present disclosure includes a photoelectric conversion layer containing a first donor semiconductor material and a first acceptor semiconductor material and converting light into signal charges, a first electrode collecting the signal charges, a second electrode facing the first electrode with the photoelectric conversion layer sandwiched therebetween, and a charge injection layer located between the second electrode and the photoelectric conversion layer. The charge injection layer is a bulk heterolayer having a bulk heterojunction structure containing a second donor semiconductor material and a second acceptor semiconductor material. The ratio of the amount of the second acceptor semiconductor material to the amount of the second donor semiconductor material in the charge injection layer is smaller than the ratio of the amount of the first acceptor semiconductor material to the amount of the first donor semiconductor material in the photoelectric conversion layer. The thickness of the charge injection layer is smaller than the thickness of the photoelectric conversion layer.

[0022] In the photoelectric conversion element according to this embodiment, the presence of the charge injection layer makes the surface of the photoelectric conversion layer less susceptible to damage during the formation of the upper electrode, which is the second electrode. On the other hand, the surface of the charge injection layer is damaged during the formation of the upper electrode. However, because the ratio of the amount of acceptor semiconductor material to the amount of donor semiconductor material in the charge injection layer is smaller than the ratio of the amount of acceptor semiconductor material to the amount of donor semiconductor material in the photoelectric conversion layer, acceptor semiconductor material with trap levels formed due to the damage is less likely to exist on the surface of the charge injection layer. Therefore, even when charges are injected from the upper electrode into the charge injection layer, the charges are less likely to be trapped, and charge injection from the upper electrode to the photoelectric conversion layer is less likely to be suppressed compared to when the charge injection layer is not present. Furthermore, although the charge injection layer contains a smaller proportion of acceptor semiconductor material with high charge transport properties than the photoelectric conversion layer, the thickness of the charge injection layer is smaller than that of the photoelectric conversion layer, making it easier for charges injected into the charge injection layer to reach the photoelectric conversion layer. As described above, the photoelectric conversion element according to this embodiment can improve the charge injection properties from the upper electrode to the photoelectric conversion layer compared to a case where the charge injection layer is not present.

[0023] Furthermore, the charge injection layer contains not only a donor semiconductor material but also an acceptor semiconductor material. Therefore, electrons and holes generated by photoelectric conversion are easily separated in the charge injection layer, and the charges generated in the charge injection layer are easily extracted as signal charges. Therefore, even when the photoelectric conversion element includes a charge injection layer, a decrease in photoelectric conversion efficiency can be suppressed.

[0024] As described above, the photoelectric conversion element according to this embodiment can improve the charge injection from the electrode to the photoelectric conversion layer while suppressing a decrease in photoelectric conversion efficiency.

[0025] (Second Aspect) Furthermore, for example, in the photoelectric conversion element according to the first aspect, the thickness of the charge injection layer may be greater than 0 nm and not greater than 50 nm.

[0026] This allows the charges injected into the charge injection layer to reach the photoelectric conversion layer more easily, further improving the charge injection properties from the upper electrode, which is the second electrode, to the photoelectric conversion layer.

[0027] (Third Aspect) Furthermore, for example, in the photoelectric conversion element according to the first or second aspect, the charge injection layer may have a thickness of 5 nm or more and 30 nm or less.

[0028] This allows the charges injected into the charge injection layer to reach the photoelectric conversion layer more easily, further improving the charge injection properties from the upper electrode, which is the second electrode, to the photoelectric conversion layer.

[0029] (Fourth Aspect) Furthermore, for example, in the photoelectric conversion element according to any one of the first to third aspects, at least one selected from the group consisting of the first acceptor semiconductor material and the second acceptor semiconductor material may be a fullerene or a fullerene derivative.

[0030] This makes it easier for electrons and holes generated by photoelectric conversion to separate, thereby improving the photoelectric conversion efficiency.

[0031] (Fifth Aspect) Furthermore, for example, the photoelectric conversion element according to any one of the first to fourth aspects may further include a charge blocking layer located between the first electrode and the photoelectric conversion layer.

[0032] This can suppress dark current and also suppress the movement of charges injected into the photoelectric conversion layer from the upper electrode (second electrode) to the lower electrode (first electrode), thereby increasing the capacitance of the photoelectric conversion element.

[0033] (Sixth Aspect) Furthermore, for example, in the photoelectric conversion element according to any one of the first to fifth aspects, the second acceptor semiconductor material may be the same as the first acceptor semiconductor material.

[0034] This makes it possible to realize a photoelectric conversion element that can improve the charge injection from the electrode to the photoelectric conversion layer while suppressing a decrease in photoelectric conversion efficiency using a small number of materials.

[0035] (Seventh Aspect) Furthermore, for example, in the photoelectric conversion element according to any one of the first to sixth aspects, the second donor semiconductor material may be the same as the first donor semiconductor material.

[0036] This makes it possible to realize a photoelectric conversion element that can improve the charge injection from the electrode to the photoelectric conversion layer while suppressing a decrease in photoelectric conversion efficiency using a small number of materials.

[0037] (Eighth Aspect) Furthermore, for example, in the photoelectric conversion element according to any one of the first to seventh aspects, the second acceptor semiconductor material may be the same as the first acceptor semiconductor material, and the second donor semiconductor material may be the same as the first donor semiconductor material.

[0038] This makes it possible to realize a photoelectric conversion element that can improve the charge injection from the electrode to the photoelectric conversion layer while suppressing a decrease in photoelectric conversion efficiency using a small number of materials.

[0039] (Ninth Aspect) An imaging device according to a ninth aspect of the present disclosure includes a photoelectric conversion element according to any one of the first to eighth aspects, and a charge accumulation region electrically connected to the first electrode and configured to accumulate the signal charge.

[0040] This makes it possible to realize an imaging device including a photoelectric conversion element that can improve the charge injection from the electrode to the photoelectric conversion layer while suppressing a decrease in photoelectric conversion efficiency.

[0041] (Tenth Aspect) Also, for example, the imaging device according to the ninth aspect may further include a voltage supply circuit electrically connected to the second electrode and applying a potential difference between the first electrode and the second electrode, and the voltage supply circuit may supply a first voltage to the second electrode in a first period, and supply a second voltage different from the first voltage in a second period different from the first period.

[0042] This allows the first and second voltages to be set to match the characteristics of the photoelectric conversion element, thereby separating the timing of photoelectric conversion from the timing of readout, and allowing charge injection from the upper electrode, which is the second electrode, to the photoelectric conversion layer at the required timing.

[0043] (Eleventh Aspect) Furthermore, for example, a camera system according to an eleventh aspect of the present disclosure includes the imaging device according to the ninth or tenth aspect.

[0044] This makes it possible to realize a camera system equipped with a photoelectric conversion element that can improve the charge injection from the electrode to the photoelectric conversion layer while suppressing a decrease in photoelectric conversion efficiency.

[0045] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0046] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0047] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0048] Furthermore, in this specification, terms indicating the relationship between elements, such as vertical, terms indicating the shape of elements, such as rectangle, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0049] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are used not only when two components are arranged with a gap between them and another component exists between them, but also when two components are arranged closely together and are in contact with each other.

[0050] In this specification, electromagnetic waves in general, including visible light, infrared light, and ultraviolet light, are referred to as "light" for convenience.

[0051] (Embodiment) Hereinafter, the present embodiment will be described.

[0052] [Photoelectric Conversion Element] First, a photoelectric conversion element according to the present embodiment will be described. The photoelectric conversion element according to the present embodiment is a charge readout type photoelectric conversion element. The photoelectric conversion element according to the present embodiment is used in, for example, an imaging device, a photosensor, or a photodetector. Fig. 1 is a schematic cross-sectional view showing the configuration of a photoelectric conversion element 10 according to the present embodiment.

[0053] As shown in FIG. 1 , photoelectric conversion element 10 is supported on support substrate 1 and includes a pair of electrodes: upper electrode 6 and lower electrode 2; photoelectric conversion layer 4 located between upper electrode 6 and lower electrode 2; charge injection layer 5 located between upper electrode 6 and photoelectric conversion layer 4; and charge blocking layer 3 located between lower electrode 2 and photoelectric conversion layer 4. In this embodiment, lower electrode 2 is an example of a first electrode that collects signal charges. Upper electrode 6 is an example of a second electrode that faces the first electrode with photoelectric conversion layer 4 interposed therebetween. Charge blocking layer 3 prevents charges of opposite polarity to the signal charges from being injected from lower electrode 2 into photoelectric conversion layer 4.

[0054] Hereinafter, each component of the photoelectric conversion element 10 according to this embodiment will be described.

[0055] The support substrate 1 may be any substrate that is commonly used to support a photoelectric conversion element, such as a glass substrate, a quartz substrate, a semiconductor substrate, or a plastic substrate.

[0056] The lower electrode 2 and the upper electrode 6 are film-like electrodes arranged opposite to each other.

[0057] The lower electrode 2 collects signal charges generated in the photoelectric conversion layer 4. The lower electrode 2 is formed from a metal, a metal nitride, a metal oxide, or polysilicon that has been given electrical conductivity. Examples of metals include aluminum, copper, titanium, and tungsten. An example of a method for giving electrical conductivity to polysilicon is doping with impurities.

[0058] The upper electrode 6 is disposed opposite the lower electrode 2 with the photoelectric conversion layer 4 interposed therebetween. The upper electrode 6 is, for example, a transparent electrode formed from a transparent conductive material. Examples of the material for the upper electrode 6 include transparent conductive oxide (TCO), indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), and SnO. ２ and TiO ２The upper electrode 6 may be made of a TCO and a metal material such as aluminum (Al) or gold (Au) alone or in combination depending on the desired transmittance.

[0059] The materials for the lower electrode 2 and the upper electrode 6 are not limited to the above-mentioned conductive materials, and other materials may be used. For example, the lower electrode 2 may be a transparent electrode.

[0060] Various methods are used to fabricate the lower electrode 2 and the upper electrode 6 depending on the materials used. For example, when ITO is used, methods such as an electron beam method, a sputtering method, a resistance heating vapor deposition method, a chemical reaction method such as a sol-gel method, or a method of applying a dispersion of indium tin oxide may be used. In this case, to fabricate the lower electrode 2 and the upper electrode 6, after forming an ITO film, UV-ozone treatment, plasma treatment, or the like may be further performed.

[0061] The photoelectric conversion layer 4 includes a donor semiconductor material and an acceptor semiconductor material. The photoelectric conversion layer 4 is made of, for example, an organic semiconductor material. The photoelectric conversion layer 4 can be made by, for example, a wet method such as a coating method using spin coating or a dry method such as a vacuum deposition method. The vacuum deposition method is a method in which a layer material is vaporized by heating under vacuum and deposited on a substrate. The charge injection layer 5 can also be made by the same method as the photoelectric conversion layer 4.

[0062] The photoelectric conversion layer 4 is, for example, a bulk heterolayer having a bulk heterojunction structure including a donor semiconductor material such as a donor organic semiconductor material and an acceptor semiconductor material such as an acceptor organic semiconductor material. When the photoelectric conversion layer 4 is prepared by a wet method, the bulk heterojunction structure can be formed, for example, by applying a solution in which the donor semiconductor material and the acceptor semiconductor material are mixed. When the photoelectric conversion layer 4 is prepared by a dry method, the bulk heterojunction structure can be formed, for example, by co-evaporating the donor semiconductor material and the acceptor semiconductor material. The photoelectric conversion layer 4 may have a stacked structure in which a layer of the donor semiconductor material and a layer of the acceptor semiconductor material are stacked.

[0063] The photoelectric conversion layer 4 can be easily formed as a thin film by including a donor organic semiconductor material and an acceptor organic semiconductor material. Specific examples of donor organic semiconductor materials and acceptor organic semiconductor materials are given below.

[0064] Examples of donor organic semiconductor materials include triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, naphthalocyanine compounds, subphthalocyanine compounds, cyanine compounds, merocyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, fused aromatic carbon ring compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives), and metal complexes having nitrogen-containing heterocyclic compounds as ligands. However, without being limited thereto, any organic compound having a smaller ionization potential than the organic compound used as the acceptor organic semiconductor material may be used as the donor organic semiconductor material.

[0065] Examples of the acceptor organic semiconductor material include fullerenes (e.g., C60 fullerene and C70 fullerene), fullerene derivatives (e.g., PCBM (phenyl C61 butyric acid methyl ester) and ICBA (indene C60 bisadduct)), fused aromatic carbocyclic compounds (e.g., naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives), 5- to 7-membered heterocyclic compounds containing nitrogen atoms, oxygen atoms, and sulfur atoms (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, Examples of suitable acceptor organic semiconductor materials include metal complexes having isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, and tribenzazepine, etc.), polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, and nitrogen-containing heterocyclic compounds as ligands. From the viewpoint of improving photoelectric conversion efficiency, the acceptor organic semiconductor material may be a fullerene or a fullerene derivative, among others. However, the acceptor organic semiconductor material is not limited thereto, and any organic compound having a higher electron affinity than the organic compound used as the donor organic semiconductor material may be used as the acceptor organic semiconductor material.

[0066] The donor organic semiconductor material and the acceptor organic semiconductor material are not limited to the above examples. Low-molecular-weight organic compounds and high-molecular-weight organic compounds may be used as the donor organic semiconductor material and the acceptor organic semiconductor material constituting the photoelectric conversion layer 4, as long as they are organic compounds that can be formed into a film as a photoelectric conversion layer by either a dry method or a wet method.

[0067] The photoelectric conversion layer 4 may also contain semiconductor materials other than those mentioned above as donor semiconductor materials and acceptor semiconductor materials. The photoelectric conversion layer 4 may also contain, as semiconductor materials, for example, silicon semiconductors, compound semiconductors, quantum dots, perovskite materials, carbon nanotubes, etc., or a mixture of two or more of these.

[0068] The charge blocking layer 3 is in contact with, for example, the lower electrode 2 and further in contact with the photoelectric conversion layer 4. The charge injection layer 5 is in contact with, for example, the upper electrode 6 and further in contact with the photoelectric conversion layer 4. Note that the photoelectric conversion element 10 does not necessarily have to include the charge blocking layer 3.

[0069] The charge injection layer 5 includes a donor semiconductor material and an acceptor semiconductor material. The charge injection layer 5 is a bulk hetero layer having a bulk heterojunction structure including a donor semiconductor material such as a donor organic semiconductor material and an acceptor semiconductor material such as an acceptor organic semiconductor material.

[0070] For the donor semiconductor material and acceptor semiconductor material contained in the charge injection layer 5, the materials exemplified as the donor semiconductor material and acceptor semiconductor material contained in the photoelectric conversion layer 4 above are used.

[0071] The ratio of the amount of the acceptor semiconductor material to the amount of the donor semiconductor material in the charge injection layer 5 is smaller than the ratio of the amount of the acceptor semiconductor material to the amount of the donor semiconductor material in the photoelectric conversion layer 4 .

[0072] Here, the ratio may be a volume ratio or a weight ratio. When the photoelectric conversion layer 4 and the charge injection layer 5 are formed by vacuum deposition, the volume ratio of the donor semiconductor material to the acceptor semiconductor material is controlled, making it easy to compare volumes. When the photoelectric conversion layer 4 and the charge injection layer 5 are formed by spin coating, the weight ratio of the donor semiconductor material to the acceptor semiconductor material is controlled, making it easy to compare weights.

[0073] The volume ratio of the acceptor semiconductor material to the donor semiconductor material in the charge injection layer 5 is, for example, not more than 2, and may be not more than 1. The volume ratio of the acceptor semiconductor material to the donor semiconductor material in the charge injection layer 5 is, for example, not less than 0.1, and may be not less than 0.3.

[0074] The donor semiconductor material contained in the charge injection layer 5 may be the same as the donor semiconductor material contained in the photoelectric conversion layer 4. Furthermore, the acceptor semiconductor material contained in the charge injection layer 5 may be the same as the acceptor semiconductor material contained in the photoelectric conversion layer 4. In this way, when the charge injection layer 5 and the photoelectric conversion layer 4 contain the same material, the photoelectric conversion element 10 can be manufactured using a smaller number of materials.

[0075] The thickness of the charge injection layer 5 is smaller than the thickness of the photoelectric conversion layer 4. The thickness of the charge injection layer 5 is, for example, 50 nm or less. The thickness of the charge injection layer 5 may be 30 nm or less, or 20 nm or less. The thickness of the charge injection layer 5 is greater than 0 nm, for example, 5 nm or more.

[0076] Here, the functions of the charge blocking layer 3, the photoelectric conversion layer 4, and the charge injection layer 5 will be described with reference to energy band diagrams. Fig. 2 is a diagram showing exemplary energy bands in the photoelectric conversion element 10 shown in Fig. 1. In Fig. 2, the energy bands of each layer are indicated by rectangles.

[0077] The photoelectric conversion layer 4 generates electron-hole pairs therein when irradiated with light. In the photoelectric conversion element 10, one of the electrons and holes in the pair is collected by the lower electrode 2 and used as a signal charge to be read out. In other words, the photoelectric conversion layer 4 converts light into a signal charge. For example, light that has passed through the upper electrode 6 and the charge injection layer 5 is incident on the photoelectric conversion layer 4. In this embodiment, the signal charge is a hole.

[0078] Electron-hole pairs generated in the photoelectric conversion layer 4 are separated into electrons and holes by the electric field applied to the photoelectric conversion layer 4. The electrons and holes move toward the lower electrode 2 or the upper electrode 6, respectively, according to the electric field. Here, among the electron-hole pairs generated by absorbing light, the semiconductor material that donates the electrons to the other material is a donor semiconductor material, and the semiconductor material that accepts the electrons is an acceptor semiconductor material. When the photoelectric conversion layer 4 is irradiated with light, for example, the donor semiconductor material generates electron-hole pairs and donates the electrons to the acceptor semiconductor material. This allows the electrons and holes to be easily separated.

[0079] FIG. 2 shows an example of energy bands when organic semiconductor materials are used as the donor semiconductor material and the acceptor semiconductor material contained in the photoelectric conversion layer 4 and the charge injection layer 5. When two different types of organic semiconductor materials are used, which one serves as the donor semiconductor material and which one serves as the acceptor semiconductor material is generally determined by the relative positions of the HOMO (Highest-Occupied-Molecular-Orbital) and LUMO (Lowest-Unoccupied-Molecular-Orbital) energy levels of each of the two types of organic semiconductor materials at the contact interface. In FIG. 2 , the top end of the rectangle representing the energy band is the LUMO energy level, and the bottom end is the HOMO energy level. The energy difference between the vacuum level and the HOMO energy level is referred to as the ionization potential. The energy difference between the vacuum level and the LUMO energy level is called the electron affinity. In this specification, in energy band diagrams such as Figure 2, the lower the position, the greater the electron affinity and ionization potential. When the semiconductor material is an inorganic semiconductor material, the explanation will be given by reading the HOMO and LUMO as the valence band and conduction band, respectively.

[0080] As shown in Figure 2, of the two types of organic semiconductor materials contained in the photoelectric conversion layer 4 and the charge injection layer 5, those with a lower LUMO energy level, i.e., a lower electron affinity, are the donor organic semiconductor material 4A and the donor organic semiconductor material 5A. Furthermore, of the two types of organic semiconductor materials contained in the photoelectric conversion layer 4 and the charge injection layer 5, those with a higher LUMO energy level, i.e., a higher electron affinity, are the acceptor organic semiconductor material 4B and the acceptor organic semiconductor material 5B. In Figure 2, the energy bands of the donor organic semiconductor material 4A and the acceptor organic semiconductor material 4B are shown slightly offset in the horizontal direction, but this is for ease of viewing and does not represent the distribution of the donor organic semiconductor material 4A and the acceptor organic semiconductor material 4B in the photoelectric conversion layer 4. Similarly, the energy bands of the donor organic semiconductor material 5A and the acceptor organic semiconductor material 5B are shown slightly offset in the horizontal direction, but this is also for ease of viewing.

[0081] The charge blocking layer 3 is provided to reduce dark current caused by charge injection from the lower electrode 2, and suppresses charge injection from the lower electrode 2 into the photoelectric conversion layer 4. This reduces noise signals that adversely affect the S / N ratio. In this embodiment, the charge blocking layer 3 is an electron blocking layer that suppresses electrons, which are charges of opposite polarity to the signal charges, from being injected from the lower electrode 2 into the photoelectric conversion layer 4. As shown in FIG. 2 , in order to suppress electrons from the lower electrode 2 from being injected into the photoelectric conversion layer 4, the electron affinity of the material of the charge blocking layer 3 is smaller than the work function of the lower electrode 2 and the electron affinity of the acceptor organic semiconductor material 4B of the photoelectric conversion layer 4.

[0082] 2 , the ionization potential of the charge blocking layer 3 is greater than the ionization potential of the donor organic semiconductor material 4A of the photoelectric conversion layer 4. The electron affinity of the charge blocking layer 3 is smaller than the electron affinity of the donor organic semiconductor material 4A of the photoelectric conversion layer 4.

[0083] The charge blocking layer 3 may be made of, for example, the semiconductor materials exemplified above as the donor semiconductor material or hole transporting organic compounds.

[0084] Here, the driving of the photoelectric conversion element 10 will be described.

[0085] 2 , when the lower electrode 2 is used in, for example, an imaging device, it is electrically connected to a charge storage node (described later). The charge storage node is a charge storage region that stores holes generated in the photoelectric conversion layer 4 and collected by the lower electrode 2.

[0086] 3 is a diagram showing an exemplary energy band in the photoelectric conversion element 10 when a reverse bias voltage is applied between the lower electrode 2 and the upper electrode 6. FIG. 4 is a diagram showing an exemplary energy band in the photoelectric conversion element 10 when a forward bias voltage is applied between the lower electrode 2 and the upper electrode 6. In this specification, when the signal charges are holes, a voltage applied between the upper electrode 6 and the lower electrode 2 such that the potential of the upper electrode 6 is higher than the potential of the lower electrode 2 is considered to be a reverse bias, or so-called reverse bias voltage. In this specification, when the signal charges are holes, a voltage applied between the upper electrode 6 and the lower electrode 2 such that the potential of the upper electrode 6 is lower than the potential of the lower electrode 2 is considered to be a forward bias, or so-called forward bias voltage.

[0087] The photoelectric conversion element 10 is driven by switching between, for example, a photoelectric conversion mode and a signal readout mode. In the photoelectric conversion mode, a reverse bias voltage as shown in FIG. 3 is applied between the upper electrode 6 and the lower electrode 2. The absolute value of this voltage is, for example, 1 V or more and 10 V or less. In the signal readout mode, a forward bias voltage as shown in FIG. 4 is applied between the upper electrode 6 and the lower electrode 2. The absolute value of this voltage is, for example, more than 0 V and 3 V or less.

[0088] For example, in the state shown in Fig. 3 as a photoelectric conversion mode, when light is incident on the photoelectric conversion layer 4, pairs of electrons and holes are generated in the photoelectric conversion layer 4, and of the generated electron-hole pairs, the holes, which are signal charges, move to the lower electrode 2, while the electrons, which are charges of the opposite polarity to the signal charges, move to the upper electrode 6. The holes that have moved to the lower electrode 2 are accumulated in, for example, a charge storage node. Thereafter, in the state shown in Fig. 4 as a signal readout mode, a signal based on the holes accumulated in the charge storage node is read out via the lower electrode 2.

[0089] In this case, when holes move from the photoelectric conversion layer 4 to the lower electrode 2 in the photoelectric conversion mode, they may not be able to move to the lower electrode 2 within the time of the photoelectric conversion mode, and the holes may remain in the photoelectric conversion layer 4 in the signal readout mode. When an organic semiconductor material is used in the photoelectric conversion layer 4, the mobility of charges is likely to be low, and holes are particularly likely to remain in the photoelectric conversion layer 4. Therefore, when the holes remaining in the photoelectric conversion layer 4 move to the lower electrode 2 after the transition from the photoelectric conversion mode to the signal readout mode, this appears as parasitic sensitivity, which is an unintended sensitivity that may cause noise.

[0090] 4 is applied in the signal readout mode, electrons are injected from the upper electrode 6 into the photoelectric conversion layer 4, and the injected electrons recombine with holes remaining in the photoelectric conversion layer 4. As a result, in the signal readout mode, the movement of holes remaining in the photoelectric conversion layer 4 to the lower electrode 2 is suppressed. The photoelectric conversion element 10 according to this embodiment is provided with the charge injection layer 5, which makes it easier to inject electrons from the upper electrode 6 into the photoelectric conversion layer 4 in the signal readout mode, thereby enabling effective reduction of parasitic sensitivity.

[0091] Here, the reason why the charge injection layer 5 improves the charge injection property of electrons from the upper electrode 6 to the photoelectric conversion layer 4 will be described.

[0092] When the charge injection layer 5 is not present, the upper electrode 6 is formed directly on the photoelectric conversion layer 4. In such a case, the surface of the photoelectric conversion layer 4 is damaged during the formation of the upper electrode 6. For example, when an ITO film is formed as the upper electrode 6 by a sputtering method or the like, trap levels are formed in the acceptor semiconductor material on the surface of the photoelectric conversion layer 4 by plasma, oxygen, and the like. The trap levels formed in the acceptor semiconductor material near the surface of the photoelectric conversion layer 4 trap electrons, thereby suppressing the injection of electrons from the upper electrode 6 into the photoelectric conversion layer 4. Therefore, when the charge injection layer 5 is not present, the charge injection of electrons from the upper electrode 6 into the photoelectric conversion layer 4 is low.

[0093] On the other hand, in the photoelectric conversion element 10, due to the presence of the charge injection layer 5, the surface of the photoelectric conversion layer 4 is less likely to be damaged during the formation of the upper electrode 6. On the other hand, the surface of the charge injection layer 5 is damaged during the formation of the upper electrode 6. However, because the ratio of the amount of acceptor semiconductor material to the amount of donor semiconductor material in the charge injection layer 5 is smaller than the ratio of the amount of acceptor semiconductor material to the amount of donor semiconductor material in the photoelectric conversion layer 4, acceptor semiconductor material with trap levels formed is less likely to be present on the surface of the charge injection layer 5. Therefore, compared to when the charge injection layer 5 is not present, the injection of electrons from the upper electrode 6 to the charge injection layer 5 is less likely to be suppressed. Furthermore, although the charge injection layer 5 has a smaller ratio of acceptor semiconductor material with high electron transport properties than the photoelectric conversion layer 4, the thickness of the charge injection layer 5 is smaller than the thickness of the photoelectric conversion layer 4, so that electrons injected into the charge injection layer 5 are more likely to reach the photoelectric conversion layer 4. From the above, the photoelectric conversion element 10 can improve the charge injection property from the upper electrode 6 to the photoelectric conversion layer 4 compared to when the charge injection layer 5 is not present. Furthermore, by making the thickness of the charge injection layer 5 50 nm or less, the charge injection property can be effectively improved compared to when the charge injection layer 5 is not present.

[0094] Furthermore, the charge injection layer 5 contains not only a donor semiconductor material but also an acceptor semiconductor material. Therefore, electrons and holes generated by photoelectric conversion are easily separated in the charge injection layer 5 as well, and in the photoelectric conversion mode, the holes, which are signal charges generated in the charge injection layer 5, are accumulated in the charge storage node. Therefore, even when the photoelectric conversion element 10 includes the charge injection layer 5, a decrease in photoelectric conversion efficiency can be suppressed.

[0095] As described above, the photoelectric conversion element 10 according to this embodiment can improve the charge injection from the upper electrode 6 to the photoelectric conversion layer 4 while suppressing a decrease in photoelectric conversion efficiency.

[0096] Next, the charge injection property of the photoelectric conversion element 10 will be described from the viewpoint of the capacitance of the photoelectric conversion element 10. In the following description, the capacitance of the photoelectric conversion element 10 is a capacitance that can be determined by measuring impedance at an AC frequency of 1 kHz using an impedance measuring instrument such as an LCR meter connected to the upper electrode 6 and the lower electrode 2 in a state where the photoelectric conversion element 10 is not irradiated with light.

[0097] In the photoelectric conversion element 10, electrons injected from the upper electrode 6 reach the interface between the charge blocking layer 3 and the photoelectric conversion layer 4, and their movement is restricted by the charge blocking layer 3, so that they are observed as capacitance of a capacitor with the charge blocking layer 3 as a dielectric. Therefore, the higher the charge injection property of electrons from the upper electrode 6 to the photoelectric conversion layer 4 in the charge readout mode, the larger the capacitance. Therefore, in the photoelectric conversion element 10, when the capacitance increases in the charge readout mode, it means that electron injection is promoted, and therefore recombination of the injected electrons with holes remaining in the photoelectric conversion layer 4 is promoted, thereby suppressing the occurrence of parasitic sensitivity.

[0098] Here, the voltage applied between the upper electrode 6 and the lower electrode 2 in the photoelectric conversion mode is referred to as a first bias voltage, and the voltage applied between the upper electrode 6 and the lower electrode 2 in the signal readout mode is referred to as a second bias voltage. From the viewpoint of suppressing the occurrence of parasitic sensitivity, the capacitance of the photoelectric conversion element 10 when the second bias voltage is applied is, for example, 1.5 times or more the capacitance of the photoelectric conversion element 10 when the first bias voltage is applied. The capacitance of the photoelectric conversion element 10 when the second bias voltage is applied may be, for example, twice or more the capacitance of the photoelectric conversion element 10 when the first bias voltage is applied. Furthermore, the capacitance of the photoelectric conversion element 10 when the second bias voltage is applied is, for example, 20 times or less the capacitance of the photoelectric conversion element 10 when the first bias voltage is applied. When the reverse bias voltage is a positive voltage and the forward bias voltage is a negative voltage, for example, the first bias voltage is 5 V or 10 V, and the second bias voltage is −2 V.

[0099] [Imaging Device] Next, an imaging device using the photoelectric conversion element according to this embodiment will be described with reference to Figures 5 and 6. Figure 5 is a diagram showing an example of the circuit configuration of an imaging device 100 that implements a photoelectric conversion unit 10A using the photoelectric conversion element 10 shown in Figure 1. Figure 6 is a schematic cross-sectional view showing an example of the device structure of a pixel 24 in the imaging device 100 according to this embodiment. Figure 5 representatively shows the lower electrode 2 and upper electrode 6 of the configuration of the photoelectric conversion unit 10A, and omits the charge blocking layer 3, photoelectric conversion layer 4, and charge injection layer 5.

[0100] As shown in FIGS. 5 and 6 , the imaging device 100 according to the present embodiment includes (i) a semiconductor substrate 40, and (ii) a plurality of pixels 24, each including a charge detection circuit 35 provided on the semiconductor substrate 40, a photoelectric conversion unit 10A provided on the semiconductor substrate 40, and a charge storage node 34 electrically connected to the charge detection circuit 35 and the photoelectric conversion unit 10A. The photoelectric conversion unit 10A of the plurality of pixels 24 is formed by the photoelectric conversion element 10 described above. That is, each of the plurality of pixels 24 includes a photoelectric conversion unit 10A including an upper electrode 6, a lower electrode 2, a photoelectric conversion layer 4, a charge injection layer 5, and a charge blocking layer 3. The upper electrode 6, the charge injection layer 5, the photoelectric conversion layer 4, the charge blocking layer 3, and the lower electrode 2 are arranged, for example, in this order from the light incident side. The light incident side is also the side farthest from the semiconductor substrate 40. In the present embodiment, the charge storage node 34 is an example of a charge storage region. In the following, a case will be described in which the photoelectric conversion section 10A has the same configuration as the photoelectric conversion element 10 and the signal charges are holes.

[0101] The charge accumulation node 34 accumulates the signal charge generated by the photoelectric conversion unit 10A, and the charge detection circuit 35 detects the signal charge accumulated in the charge accumulation node 34. The charge detection circuit 35 provided on the semiconductor substrate 40 may be provided on the semiconductor substrate 40 or may be provided directly in the semiconductor substrate 40.

[0102] As shown in Fig. 5, the imaging device 100 includes a plurality of pixels 24 and peripheral circuits. The imaging device 100 is an image sensor realized by a single-chip integrated circuit, and includes a pixel array PA including a plurality of pixels 24 arranged two-dimensionally. The imaging device 100 is, for example, an imaging device that operates using a global shutter system in which the exposure periods of all of the plurality of pixels 24 are unified. In other words, the imaging device 100 has a global shutter function. Details of the exposure period will be described later.

[0103] A plurality of pixels 24 are arranged two-dimensionally, i.e., in row and column directions, on the semiconductor substrate 40 to form a photosensitive region, which is a pixel region. FIG. 5 shows an example in which the pixels 24 are arranged in a two-row, two-column matrix. For convenience of illustration, FIG. 5 does not show a circuit (e.g., a pixel electrode control circuit) for individually setting the sensitivity of the pixels 24. The imaging device 100 may also be a line sensor. In this case, the plurality of pixels 24 may be arranged one-dimensionally. In this specification, the row direction and column direction refer to the direction in which the rows and columns extend, and the horizontal direction refers to the row direction.

[0104] 5 and 6 , each pixel 24 includes a photoelectric conversion unit 10A, a charge detection circuit 35, and a charge storage node 34 electrically connected to the photoelectric conversion unit 10A and the charge detection circuit 35. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23.

[0105] The photoelectric conversion unit 10A includes a lower electrode 2 provided as a pixel electrode and an upper electrode 6 provided as a counter electrode facing the pixel electrode. A voltage for applying a predetermined bias voltage is supplied to the upper electrode 6 via a counter electrode signal line 26.

[0106] The lower electrode 2 is connected to the gate electrode 21G of the amplification transistor 21, and the signal charges collected by the lower electrode 2 are stored in a charge storage node 34 located between the lower electrode 2 and the gate electrode 21G of the amplification transistor 21. The charge storage node 34 is electrically connected to the lower electrode 2 and stores holes, which are signal charges generated in the photoelectric conversion layer 4.

[0107] A voltage corresponding to the amount of signal charge stored in the charge storage node 34 is applied to the gate electrode 21G of the amplifier transistor 21. The amplifier transistor 21 amplifies this voltage, and the amplified voltage is selectively read out as a signal voltage by the address transistor 23. The reset transistor 22 has its source electrode or drain electrode connected to the lower electrode 2 via the charge storage node 34, and resets the signal charge stored in the charge storage node 34. In other words, the reset transistor 22 resets the potentials of the gate electrode 21G and the lower electrode 2 of the amplifier transistor 21.

[0108] In order to selectively perform the above-described operations in the plurality of pixels 24, the imaging device 100 has a power supply wiring 31, a vertical signal line 27, an address signal line 36, and a reset signal line 37, which are connected to each pixel 24. Specifically, the power supply wiring 31 is connected to the source electrode or drain electrode of the amplification transistor 21, and the vertical signal line 27 is connected to the source electrode or drain electrode of the address transistor 23. The address signal line 36 is connected to the gate electrode 23G of the address transistor 23. Furthermore, the reset signal line 37 is connected to the gate electrode 22G of the reset transistor 22.

[0109] The peripheral circuits include a voltage supply circuit 19 , a vertical scanning circuit 25 , a horizontal signal readout circuit 20 , a plurality of column signal processing circuits 29 , a plurality of load circuits 28 , and a plurality of differential amplifiers 32 .

[0110] The voltage supply circuit 19 is electrically connected to the upper electrode 6 via a counter electrode signal line 26. The voltage supply circuit 19 applies a voltage to the upper electrode 6, thereby creating a potential difference between the upper electrode 6 and the lower electrode 2. For example, the voltage supply circuit 19 supplies a first voltage to the upper electrode 6 during a first period such as an exposure period described below, and supplies a second voltage different from the first voltage during a second period such as a non-exposure period different from the first period.

[0111] The vertical scanning circuit 25 is connected to address signal lines 36 and reset signal lines 37, and selects the multiple pixels 24 arranged in each row on a row-by-row basis to read out the signal voltage and reset the potential of the lower electrode 2. A power supply wiring 31, which is a source follower power supply, supplies a predetermined power supply voltage to each pixel 24. The horizontal signal readout circuit 20 is electrically connected to multiple column signal processing circuits 29. The column signal processing circuits 29 are electrically connected to the pixels 24 arranged in each column via vertical signal lines 27 corresponding to each column. A load circuit 28 is electrically connected to each vertical signal line 27. The load circuit 28 and the amplification transistor 21 form a source follower circuit.

[0112] A plurality of differential amplifiers 32 are provided corresponding to each column. The negative input terminals of the differential amplifiers 32 are connected to the corresponding vertical signal lines 27. The output terminals of the differential amplifiers 32 are connected to the pixels 24 via feedback lines 33 corresponding to each column.

[0113] The vertical scanning circuit 25 applies a row selection signal, which controls the on / off of the address transistor 23, to the gate electrode 23G of the address transistor 23 via the address signal line 36. This scans and selects the row to be read out. A signal voltage is read out from the pixels 24 in the selected row to the vertical signal line 27. The vertical scanning circuit 25 also applies a reset signal, which controls the on / off of the reset transistor 22, to the gate electrode 22G of the reset transistor 22 via the reset signal line 37. This selects the row of pixels 24 to be subjected to the reset operation. The vertical signal line 27 transmits the signal voltage read out from the pixel 24 selected by the vertical scanning circuit 25 to the column signal processing circuit 29.

[0114] The column signal processing circuit 29 performs noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion).

[0115] The horizontal signal readout circuit 20 sequentially reads out signals from the plurality of column signal processing circuits 29 to a horizontal common signal line.

[0116] The differential amplifier 32 is connected to the drain electrode of the reset transistor 22 via a feedback line 33. Therefore, the differential amplifier 32 receives the output value of the address transistor 23 at its negative terminal. The differential amplifier 32 performs a feedback operation so that the gate potential of the amplifying transistor 21 becomes a predetermined feedback voltage. At this time, the output voltage value of the differential amplifier 32 is 0 V or a positive voltage close to 0 V. The feedback voltage means the output voltage of the differential amplifier 32.

[0117] As shown in FIG. 6, the pixel 24 is formed on a semiconductor substrate 40, and includes a charge detection circuit 35, a photoelectric conversion unit 10A, and a charge storage node 34 (see FIG. 5).

[0118] The semiconductor substrate 40 may be an insulating substrate or the like having a semiconductor layer provided on the surface on which the photosensitive region is formed. The semiconductor substrate 40 is, for example, a p-type silicon substrate. The semiconductor substrate 40 has impurity regions 21D, 21S, 22D, 22S, and 23S and an element isolation region 41 for electrical isolation between the pixels 24. The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, n-type regions. Here, the element isolation region 41 is provided between the impurity region 21D and the impurity region 22D. This suppresses leakage of signal charge accumulated in the charge storage node 34. The element isolation region 41 is formed, for example, by implanting acceptor ions under predetermined implantation conditions.

[0119] The charge detection circuit 35 detects the signal charge collected by the lower electrode 2 and outputs a signal voltage. The charge detection circuit 35 includes an amplification transistor 21, a reset transistor 22, and an address transistor 23, and is formed on a semiconductor substrate 40.

[0120] The impurity regions 21D, 21S, 22D, 22S, and 23S are, for example, diffusion regions formed in the semiconductor substrate 40.

[0121] 6, the amplifier transistor 21 includes an impurity region 21S and an impurity region 21D, a gate insulating layer 21X formed on a semiconductor substrate 40, and a gate electrode 21G formed on the gate insulating layer 21X. The impurity region 21S and the impurity region 21D function as, for example, a source region and a drain region, respectively, of the amplifier transistor 21. A channel region of the amplifier transistor 21 is formed between the impurity region 21S and the impurity region 21D.

[0122] The address transistor 23 includes an impurity region 23S and an impurity region 21S, a gate insulating layer 23X formed on the semiconductor substrate 40, and a gate electrode 23G formed on the gate insulating layer 23X and connected to an address signal line 36. In this example, the amplifier transistor 21 and the address transistor 23 are electrically connected to each other by sharing the impurity region 21S. The impurity region 23S functions as, for example, a source region of the address transistor 23. The impurity region 23S is connected to a vertical signal line 27 shown in FIG. 5 .

[0123] The reset transistor 22 includes impurity regions 22D and 22S, a gate insulating layer 22X formed on the semiconductor substrate 40, and a gate electrode 22G formed on the gate insulating layer 22X and connected to a reset signal line 37. The impurity region 22S functions as, for example, a source region of the reset transistor 22. The impurity region 22S is connected to a feedback line 33 shown in FIG.

[0124] An interlayer insulating layer 50 is stacked on the semiconductor substrate 40 so as to cover the amplifier transistor 21, the address transistor 23, and the reset transistor 22. For ease of viewing, hatching indicating a cross section of the interlayer insulating layer 50 is omitted in FIG.

[0125] Furthermore, a wiring layer (not shown) may be disposed in the interlayer insulating layer 50. The wiring layer may be formed of a metal such as copper, and may include, as a part thereof, wiring such as the above-mentioned vertical signal line 27. The number of insulating layers in the interlayer insulating layer 50 and the number of wiring layers disposed in the interlayer insulating layer 50 may be set arbitrarily.

[0126] 6 , the contact plugs 51, 53, 54, 52, 52a, 52b, 52c, 52d, 52e, 52f, 52f, 52f, 52g, 52h, 52h, 52f ...

[0127] The above-described photoelectric conversion unit 10A is disposed on the interlayer insulating layer 50. In other words, in this embodiment, a plurality of pixels 24 constituting the pixel array PA are formed on a semiconductor substrate 40. The plurality of pixels 24 arranged two-dimensionally on the semiconductor substrate 40 form a photosensitive region. The distance between two adjacent pixels 24 (i.e., pixel pitch) may be, for example, approximately 2 μm.

[0128] A color filter 60 is formed above the photoelectric conversion unit 10A, and a microlens 61 is formed above the color filter 60. The color filter 60 is formed as an on-chip color filter by patterning, for example. The color filter 60 is made of a material such as a photosensitive resin in which a dye or a pigment is dispersed. The microlens 61 is formed as an on-chip microlens, for example. The microlens 61 is made of a material such as an ultraviolet-sensitive material.

[0129] A general semiconductor manufacturing process can be used to manufacture the imaging device 100. In particular, when a silicon substrate is used as the semiconductor substrate 40, the imaging device 100 can be manufactured by utilizing various silicon semiconductor processes.

[0130] [Operation of the Imaging Device] Next, the operation of the imaging device 100 will be described with reference to Fig. 7 and Fig. 8. Here, the operation of the imaging device 100 when holes are used as signal charges as described above will be described.

[0131] 7 is a diagram showing a part of a schematic circuit configuration of a pixel 24. For ease of explanation, one end of the charge storage node 34 is grounded and the potential is zero. This state corresponds to the case where the feedback line 33 shown in FIG. 5 is set to 0 V, for example. In this state, if the voltage of the charge storage node 34 is Vc, then Vc is zero.

[0132] The voltage supply circuit 19 shown in FIG. 5 supplies different voltages to the upper electrode 6 via the counter electrode signal line 26 between an exposure period, which is an example of a first period, and a non-exposure period, which is an example of a second period. In this specification, the term "exposure period" refers to a period during which either electrons or holes generated by photoelectric conversion are accumulated as signal charge in the charge accumulation node 34. That is, the "exposure period" may also be referred to as a "charge accumulation period." Furthermore, in this specification, a period other than the exposure period during operation of the imaging device 100 is referred to as a "non-exposure period." The "non-exposure period" may be a period during which light is blocked from entering the photoelectric conversion unit 10A, or a period during which light is irradiated onto the photoelectric conversion unit 10A but charge is not substantially accumulated in the charge accumulation node 34.

[0133] For example, when the imaging device 100 is driven, a bias voltage in a first voltage range or a second voltage range is applied to the photoelectric conversion unit 10A.

[0134] The first voltage range is a voltage range in which the dependency of the current change in the photoelectric conversion layer 4 on the bias voltage applied between the lower electrode 2 and the upper electrode 6 and on the amount of light incident on the photoelectric conversion layer 4 is smaller than that in the second voltage range. That is, in the first voltage range, it can be considered that the difference between the current value that flows when light is incident on the photoelectric conversion layer 4 and the current value that flows when no light is incident is small. In the first voltage range, even if hole-electron pairs are generated by the incidence of light on the photoelectric conversion layer 4, the absolute value of the voltage applied between the lower electrode 2 and the upper electrode 6 is not large, so that the holes and electrons are likely to recombine before they separate. The first voltage range includes, for example, a forward bias voltage range.

[0135] The second voltage range is a reverse bias voltage range in which the current value increases as the amount of light incident on the photoelectric conversion layer 4 and the bias voltage applied between the lower electrode 2 and the upper electrode 6 increase.

[0136] In the initial state, the potential difference between the lower electrode 2 and the upper electrode 6 of the photoelectric conversion unit 10A, i.e., the bias voltage applied to the photoelectric conversion layer 4, the charge blocking layer 3, and the charge injection layer 5, is set to a value within a first voltage range. For example, the voltage supply circuit 19 supplies a voltage equal to the voltage of the lower electrode 2 to the upper electrode 6 using the counter electrode signal line 26. Here, let V2 be the voltage supplied to the upper electrode 6, and V2 be the reference voltage Vref. In this case, let Vo be the bias voltage applied to the photoelectric conversion unit 10A, and therefore Vo=V2-Vc, and therefore Vo=0.

[0137] Next, the operation during the exposure period will be described. Driving the imaging device 100 during the exposure period corresponds to the photoelectric conversion mode in driving the photoelectric conversion element 10 described above. At the start of the exposure period, the voltage supply circuit 19 supplies a voltage V2 to the upper electrode 6 via the counter electrode signal line 26 so that a bias voltage within the second voltage range, i.e., a reverse bias voltage, is applied to the photoelectric conversion unit 10A. That is, during the exposure period, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage V2 that generates photoelectric conversion sensitivity in the photoelectric conversion layer 4. The voltage V2 supplied by the voltage supply circuit 19 during the exposure period is an example of a first voltage. For example, when the photoelectric conversion layer 4 is made of an organic semiconductor material, the voltage V2 is a voltage of several volts to approximately 10 volts. As a result, holes are accumulated as signal charges in the charge storage node 34 of each pixel 24, in an amount corresponding to the amount of light incident on the photoelectric conversion layer 4.

[0138] Next, the operation during the non-exposure period will be described. Driving the imaging device 100 during the non-exposure period corresponds to the signal readout mode in driving the photoelectric conversion element 10 described above. After the exposure period ends, the voltage supply circuit 19 supplies a voltage V2 to the upper electrode 6 via the counter electrode signal line 26 so that a voltage within the first voltage range is applied to the photoelectric conversion unit 10A. That is, during the non-exposure period, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage V2 that recombines electrons and holes in the photoelectric conversion layer 4. The voltage V2 supplied by the voltage supply circuit 19 during the non-exposure period is an example of a second voltage. For example, the voltage V2 supplied to the upper electrode 6 is set to a reference voltage Vref. Holes corresponding to the amount of light incident on the photoelectric conversion layer 4 during the exposure period are accumulated in the charge storage node 34 of each pixel 24, and the value of Vc differs depending on the pixel 24. Since Vo = V2 - Vc, Vo also becomes zero for pixels 24 that are not exposed and whose Vc remains unchanged. However, in the pixel 24 where Vc has changed, Vo does not become zero, but becomes a forward bias voltage.

[0139] When the voltage V2 in the first voltage range is supplied to the upper electrode 6, holes are less likely to move to the charge storage node 34 even when light is incident on the pixel 24. In other words, the voltage supply circuit 19 supplies a voltage to the upper electrode 6 so that the photoelectric conversion efficiency of the plurality of pixels 24, specifically the photoelectric conversion unit 10A, differs between the exposure period and the non-exposure period. Furthermore, when the voltage V2 in the first voltage range is supplied to the upper electrode 6, holes stored in the charge storage node 34 are less likely to be discharged to the lower electrode 2, and charges supplied from the voltage supply circuit 19 via the lower electrode 2 are less likely to flow into the charge storage node 34.

[0140] Therefore, the holes accumulated in the charge storage node 34 of each pixel 24 are maintained at an amount corresponding to the amount of light incident on the photoelectric conversion layer 4. In other words, the holes accumulated in the charge storage node 34 of each pixel 24 can be maintained even if light is again incident on the photoelectric conversion layer 4, as long as the holes in the charge storage node 34 are not reset. Therefore, even when a readout operation is performed sequentially for each row during a non-exposure period, new holes are unlikely to accumulate in the charge storage node 34 during the readout operation. Therefore, for example, a global shutter function can be realized with a simple pixel circuit such as the pixel 24 without including a transfer transistor and an additional storage capacitor. Therefore, for example, rolling distortion, which occurs in a rolling shutter, does not occur. Furthermore, because the pixel circuit is simple, the pixel 24 can be advantageously miniaturized in the imaging device 100. Furthermore, since the imaging device 100 includes the charge injection layer 5, as described above, the charge injection of electrons into the photoelectric conversion layer 4 is high. Therefore, even if holes generated in the photoelectric conversion layer 4 during the exposure period remain during the non-exposure period, the recombination of the remaining holes with the injected electrons is promoted, and the occurrence of parasitic sensitivity can also be suppressed.

[0141] 8 is a timing chart showing an example of the voltage V2 supplied to the upper electrode 6 of the photoelectric conversion unit 10A and the timing of operations in each row of the pixel array PA of the image pickup device 100. For ease of understanding, FIG. 8 only shows the change in voltage V2 and the timing of exposure and signal readout for each row of the pixel array PA indicated by R0 to R7. In the image pickup device 100, during the non-exposure period N, the voltage supply circuit 19 supplies the upper electrode 6 with a voltage Vb as the voltage V2 that causes the bias voltage Vo to fall within a first voltage range, and during the exposure period E, it supplies a voltage Va as the voltage V2 that causes the bias voltage Vo to fall within a second voltage range.

[0142] As shown in FIG. 8 , during the non-exposure period N, signal readout R of the pixels 24 in each row R0 to R7 is performed sequentially. As described above, during the non-exposure period N, the bias voltage Vo is in the first voltage range, making it difficult for new holes to accumulate in the charge storage node 34 during the readout operation. Furthermore, the presence of the charge injection layer 5 promotes recombination of remaining holes and electrons, thereby suppressing the occurrence of parasitic sensitivity. Furthermore, the start and end timings of the exposure period E are consistent for the pixels 24 in all rows R0 to R7. In other words, the imaging device 100 realizes a global shutter function in which all rows of the pixel array PA are simultaneously exposed while sequentially reading out signals from the pixels 24 in each row.

[0143] The operation of the imaging device 100 is not limited to the above example, and for example, the imaging device 100 may perform an operation that realizes an electronic ND (Neutral Density) filter function that adjusts the sensitivity of photoelectric conversion.

[0144] For example, during the exposure period E in Figure 8, the voltage supply circuit 19 supplies, as voltage V2, instead of voltage Va, to the upper electrode 6 a voltage equivalent to an ND value, which is a predetermined magnification of the sensitivity reduction, based on the relationship between the bias voltage and the current value at that voltage (i.e., the amount of holes generated in the photoelectric conversion layer 4 that are extracted), thereby realizing the electronic ND filter function of the imaging device 100.

[0145] FIG. 9 is a timing chart showing an example of an operation of adjusting the photoelectric conversion sensitivity using a pulse duty control method in the imaging device 100. As shown in FIG. 9 , the voltage supply circuit 19 supplies a pulsed voltage that alternates between the voltages Va and Vb during the exposure period E, for example. Thus, the first period during which the voltage supply circuit 19 supplies the voltage Va, which is an example of the first voltage, and the second period during which the voltage supply circuit 19 supplies the voltage Vb, which is an example of the second voltage, may be included in the exposure period E within the same frame. In this case, the voltage supply circuit 19 supplies a voltage to the upper electrode 6 with a duty ratio of the pulsed voltage that alternates between the voltages Va and Vb that corresponds to a predetermined ND value. This also enables the imaging device 100 to achieve its electronic ND filter function. In this case, during the second period during the exposure period E during which the voltage Vb is applied to the upper electrode 6, parasitic sensitivity is reduced, similar to the non-exposure period N, making it easier to accurately achieve the set ND value.

[0146] In this way, even if the imaging device 100 has an electronic ND filter function, the parasitic sensitivity of the imaging device 100 is reduced as described above, and therefore the imaging device 100 can achieve imaging with less noise.

[0147] [Camera System] Next, a camera system including the imaging device according to this embodiment will be described.

[0148] FIG. 10 is a block diagram showing an example of the configuration of a camera system 400 according to this embodiment.

[0149] 10, camera system 400 according to this embodiment includes lens optical system 601, imaging device 602, system controller 603, and camera signal processing circuit 604. Camera system 400 may be, for example, a smartphone, a digital camera, a video camera, or an in-vehicle camera.

[0150] The lens optical system 601 focuses light onto an imaging surface of the imaging device 602. The lens optical system 601 may include, for example, a lens group including an autofocus lens and a zoom lens, and an aperture. As the imaging device 602, for example, the imaging device 100 described above is used.

[0151] The system controller 603 controls the entire camera system 400. The system controller 603 is, for example, a semiconductor integrated circuit, and a specific example is a CPU (Central Processing Unit).

[0152] The camera signal processing circuit 604 has a function of processing an output signal from the image capture device 602. The camera signal processing circuit 604 receives output data from the image capture device 602 and performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing circuit 604 is, for example, a DSP (Digital Signal Processor). The image capture device 602 and the camera signal processing circuit 604 may be implemented as a single semiconductor device. The semiconductor device may be, for example, a so-called SoC (System on a Chip). This configuration allows for further miniaturization of electronic devices that include the image capture device 602 as a part thereof.

[0153] The photoelectric conversion element according to the present disclosure will be specifically described below in examples, but the present disclosure is not limited to the following examples. In detail, a photoelectric conversion element according to an embodiment of the present disclosure and a photoelectric conversion element for comparison of characteristics were fabricated, and the photoelectric conversion elements were evaluated.

[0154] (Preparation of Photoelectric Conversion Element 1) Photoelectric conversion elements were prepared in Examples 1 to 3 and Comparative Examples 1 to 3. The schematic configurations of the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3 are shown in FIG. 11. In Examples 1 to 3 and Comparative Examples 1 to 3, the photoelectric conversion elements were prepared by varying the volume ratio ("1:X" in FIG. 11) of the donor organic semiconductor material ("D" in FIG. 11) to the acceptor organic semiconductor material ("A" in FIG. 11) in the charge injection layer.

[0155] Example 1: A silicon (Si) substrate was used as a support substrate, with a titanium nitride (TiN) film formed as a lower electrode. A charge-blocking layer was formed on the TiN film as the lower electrode by vacuum deposition of 9,9'-[1,1'-biphenyl]-4,4'-diylbis[3,6-bis(1,1-dimethylethyl)]-9H-carbazole (tBu-CBP).

[0156] Next, a photoelectric conversion layer was formed on the charge blocking layer by co-depositing a donor organic semiconductor material, subphthalocyanine, and an acceptor organic semiconductor material, C60 fullerene, at a volume ratio D:A of 1:3 by vacuum deposition. The resulting photoelectric conversion layer had a thickness of 400 nm. The subphthalocyanine used was boron subphthalocyanine chloride (SubPc), which has boron (B) as the central metal and a chloride ion coordinated to B as a ligand.

[0157] Next, on the photoelectric conversion layer, a charge injection layer was formed by co-depositing, through a metal shadow mask, subphthalocyanine, a donor organic semiconductor material, and C60 fullerene, an acceptor organic semiconductor material, at a volume ratio D:A of 1:0.5 by vacuum deposition. The thickness of the charge injection layer obtained was 10 nm.

[0158] Next, an ITO film was formed as an upper electrode on the charge injection layer by sputtering to a thickness of 30 nm, and then an Al film was formed as a sealing film. ２ O ３ The film was formed on the upper electrode by atomic layer deposition, thereby obtaining the photoelectric conversion element of Example 1.

[0159] [Example 2] A photoelectric conversion element in Example 2 was produced in the same manner as in Example 1, except that a charge injection layer was formed by co-depositing subphthalocyanine and C60 fullerene by vacuum deposition so that the volume ratio D:A was 1:1.

[0160] [Example 3] A photoelectric conversion element in Example 3 was produced in the same manner as in Example 1, except that a charge injection layer was formed by co-depositing subphthalocyanine and C60 fullerene by vacuum deposition so that the volume ratio D:A was 1:2.

[0161] Comparative Example 1 A photoelectric conversion element in Comparative Example 1 was produced in the same manner as in Example 1, except that the charge injection layer was formed by depositing subphthalocyanine and C60 fullerene at a volume ratio D:A = 1:0, that is, by vacuum deposition using only subphthalocyanine, which is a donor organic semiconductor material, as the material for the charge injection layer.

[0162] Comparative Example 2 A photoelectric conversion element was produced in the same manner as in Example 1, except that a charge injection layer was formed by co-depositing subphthalocyanine and C60 fullerene by vacuum deposition so that the volume ratio D:A was 1:3, thereby obtaining a photoelectric conversion element in Comparative Example 2. In Comparative Example 2, the volume ratio D:A of the photoelectric conversion layer and the charge injection layer is the same, and therefore the photoelectric conversion element in Comparative Example 2 corresponds to a photoelectric conversion element not provided with a charge injection layer.

[0163] Comparative Example 3 A photoelectric conversion element in Comparative Example 3 was produced in the same manner as in Example 1, except that a charge injection layer was formed by co-depositing subphthalocyanine and C60 fullerene by vacuum deposition so that the volume ratio D:A was 1:5.

[0164] (Evaluation 1 of Photoelectric Conversion Element) Evaluations were performed on the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3. Specifically, the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3 were subjected to measurement of capacitance as an evaluation of charge injection property, and measurement of external quantum efficiency as an evaluation of photoelectric conversion efficiency.

[0165] [Capacitance Measurement] The capacitance was measured for the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3. Specifically, the impedance of the photoelectric conversion element at an AC frequency of 1 kHz was measured using an LCR meter (E4980A, manufactured by Keysight Technologies) connected to the upper electrode and the lower electrode without allowing light to be incident on the photoelectric conversion element, and the capacitance value was determined. The capacitance was measured by varying the voltage applied between the upper electrode and the lower electrode in the range of -3 V to 6 V. Note that the voltage applied between the upper electrode and the lower electrode was defined as a "positive" value when the potential of the upper electrode was higher than the potential of the lower electrode.

[0166] [Measurement of External Quantum Efficiency] The external quantum efficiency was measured for the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3. Specifically, the external quantum efficiency was measured for light of 540 nm under the condition of applying a voltage of 10 V using a spectral response measurement device (manufactured by Bunkoukeiki Co., Ltd.). In addition, in measuring the external quantum efficiency, a voltage was applied so that the potential of the upper electrode was higher than the potential of the lower electrode. In other words, the external quantum efficiency was measured under the condition that electrons moved to the upper electrode and holes moved to the lower electrode. Then, the relative quantum efficiency, which is the ratio of the external quantum efficiency to that of Comparative Example 1, was calculated using the following formula.

[0167] Relative quantum efficiency (%)=(external quantum efficiency of photoelectric conversion element / external quantum efficiency of Comparative Example 1)×100

[0168] [Evaluation Results] Table 1 shows the measurement results of the capacitance and external quantum efficiency of the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3. Table 1 shows the capacitance and relative quantum efficiency when the volume ratio D:A of subphthalocyanine to C60 fullerene in the charge injection layer is changed and a voltage of -2 V is applied between the upper electrode and the lower electrode. FIG. 12 also shows the relationship between the capacitance and the voltage applied between the upper electrode and the lower electrode in the photoelectric conversion elements in Examples 1 to 3 and Comparative Examples 1 to 3.

[0169]

[0170] 12 , it can be seen that a smaller ratio of the amount of acceptor-type organic semiconductor material to the amount of donor-type organic semiconductor material in the charge injection layer increases the capacitance when a voltage of −2 V is applied between the upper electrode and the lower electrode. Therefore, in Examples 1 to 3, in which the ratio of the amount of acceptor-type organic semiconductor material to the amount of donor-type organic semiconductor material in the charge injection layer is smaller than the ratio of the amount of acceptor-type organic semiconductor material to the amount of donor-type organic semiconductor material in the photoelectric conversion layer, the capacitance is larger than in Comparative Example 2, which has the same ratio. In other words, it can be said that the photoelectric conversion elements in Examples 1 to 3 have improved charge injection properties compared to the photoelectric conversion element in Comparative Example 2, which does not have a charge injection layer.

[0171] Furthermore, as shown in Table 1, Examples 1 to 3 in which the charge injection layer contains not only a donor organic semiconductor material but also an acceptor organic semiconductor material have higher relative quantum efficiency than Comparative Example 1 in which the charge injection layer does not contain an acceptor organic semiconductor material. Therefore, even when the photoelectric conversion element includes a charge injection layer, the decrease in photoelectric conversion efficiency can be suppressed by having the charge injection layer contain an acceptor organic semiconductor material.

[0172] (Fabrication of Photoelectric Conversion Element 2) Next, photoelectric conversion elements in Examples 4 to 8 were fabricated. The schematic configurations of the photoelectric conversion elements in Examples 2 and 4 to 8 are shown in FIG. 13. In Examples 4 to 8, the photoelectric conversion elements were fabricated by changing the thickness of the charge injection layer ("Y" in FIG. 13) without changing the total thickness of the charge injection layer and the photoelectric conversion layer and the volume ratio D:A = 1:1 in the charge injection layer from Example 2. Note that in all of the photoelectric conversion elements in Examples 2 and 4 to 8, the thickness of the charge injection layer was smaller than the thickness of the photoelectric conversion layer.

[0173] Example 4 A photoelectric conversion element in Example 4 was obtained by fabricating a photoelectric conversion element in the same manner as in Example 2, except that the thickness of the photoelectric conversion layer was set to 405 nm and the thickness of the charge injection layer was set to 5 nm.

[0174] Example 5 A photoelectric conversion element in Example 5 was obtained by fabricating a photoelectric conversion element in the same manner as in Example 2, except that the thickness of the photoelectric conversion layer was set to 390 nm and the thickness of the charge injection layer was set to 20 nm.

[0175] Example 6 A photoelectric conversion element in Example 6 was obtained by fabricating a photoelectric conversion element in the same manner as in Example 2, except that the thickness of the photoelectric conversion layer was 380 nm and the thickness of the charge injection layer was 30 nm.

[0176] Example 7 A photoelectric conversion element in Example 7 was obtained by fabricating a photoelectric conversion element in the same manner as in Example 2, except that the thickness of the photoelectric conversion layer was 360 nm and the thickness of the charge injection layer was 50 nm.

[0177] Example 8 A photoelectric conversion element in Example 8 was produced in the same manner as in Example 2, except that the thickness of the photoelectric conversion layer was 210 nm and the thickness of the charge injection layer was 200 nm.

[0178] (Evaluation 2 of Photoelectric Conversion Element) Evaluations were carried out on the photoelectric conversion elements in Examples 2 and 4 to 8 and Comparative Example 2. Specifically, capacitance was measured to evaluate the charge injection properties of the photoelectric conversion elements in Examples 2 and 4 to 8 and Comparative Example 2. The capacitance was measured in the same manner as in "Evaluation 1 of Photoelectric Conversion Element" above.

[0179] [Evaluation Results] Table 2 shows the measurement results of the capacitance of the photoelectric conversion elements in Examples 2 and 4 to 8 and Comparative Example 2. Table 2 shows the thickness of the charge injection layer and the capacitance when a voltage of -2 V is applied between the upper electrode and the lower electrode. FIG. 14 also shows the relationship between the thickness of the charge injection layer in the photoelectric conversion elements in Examples 2 and 4 to 8 and Comparative Example 2 and the capacitance when a voltage of -2 V is applied between the upper electrode and the lower electrode. In Table 2 and FIG. 14, the photoelectric conversion element in Comparative Example 2 corresponds to a photoelectric conversion element that does not have a charge injection layer as described above, and therefore the thickness of the charge injection layer is set to 0.

[0180]

[0181] As shown in Table 2 and FIG. 14 , in Examples 2 and 4 to 8, in which the thickness of the charge injection layer is smaller than the thickness of the photoelectric conversion layer, the capacitance is larger than that of Comparative Example 2, which does not include a charge injection layer. In other words, the photoelectric conversion elements in Examples 2 and 4 to 8 have improved charge injection properties compared to the photoelectric conversion element in Comparative Example 2, which does not include a charge injection layer. In Examples 2 and 4 to 7, in which the thickness of the charge injection layer is 50 nm or less, the capacitance is 1.5 times or more that of Comparative Example 2, and the charge injection properties of the photoelectric conversion elements are particularly improved. Furthermore, in Examples 2 and 4 to 6, in which the thickness of the charge injection layer is 30 nm or less, the capacitance is equivalent to that of Comparative Example 1, in which the charge injection layer does not include an acceptor semiconductor material, and the charge injection properties of the photoelectric conversion elements are significantly improved.

[0182] As described above, from the evaluation results of the photoelectric conversion elements in Examples 1 to 8 and Comparative Examples 1 to 3, it can be seen that the ratio of the amount of acceptor organic semiconductor material to the amount of donor organic semiconductor material in the charge injection layer is smaller than the ratio of the amount of acceptor organic semiconductor material to the amount of donor organic semiconductor material in the photoelectric conversion layer, and that the thickness of the charge injection layer is smaller than the thickness of the photoelectric conversion layer, thereby achieving both improved charge injection from the electrode to the photoelectric conversion layer in the photoelectric conversion element and suppressing a decrease in photoelectric conversion efficiency.

[0183] (Other) While the photoelectric conversion element, imaging device, and camera system according to the present disclosure have been described above based on embodiments and examples, the present disclosure is not limited to these embodiments and examples. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the embodiments and examples, as well as other forms constructed by combining some of the components of the embodiments and examples, are also included within the scope of the present disclosure.

[0184] For example, in the above embodiment, the case where holes are used as signal charges has been described, but the signal charges may also be electrons.

[0185] The photoelectric conversion element according to the present disclosure can be applied to imaging devices, optical sensors, photodetectors, etc. Furthermore, the imaging device according to the present disclosure can be applied to various camera systems and sensor systems, such as medical cameras, surveillance cameras, vehicle-mounted cameras, distance measuring cameras, microscope cameras, drone cameras, and robot cameras.

[0186] REFERENCE SIGNS LIST 1 Support substrate 2 Lower electrode 3 Charge blocking layer 4 Photoelectric conversion layer 4A, 5A Donor organic semiconductor material 4B, 5B Acceptor organic semiconductor material 5 Charge injection layer 6 Upper electrode 10 Photoelectric conversion element 10A Photoelectric conversion section 19 Voltage supply circuit 20 Horizontal signal readout circuit 21 Amplifying transistor 22 Reset transistor 23 Address transistor 21D, 21S, 22D, 22S, 23S Impurity region 21G, 22G, 23G Gate electrode 21X, 22X, 23X Gate insulating layer 24 Pixel 25 Vertical scanning circuit 26 Counter electrode signal line 27 Vertical signal line 28 Load circuit 29 Column signal processing circuit 31 Power supply wiring 32 Differential amplifier 33 Feedback line 34 Charge storage node 35 Charge detection circuit 36 ​​Address signal line 37 REFRESHING SIGNS 40: Semiconductor substrate 41: Element isolation region 50: Interlayer insulating layer 51, 53, 54: Contact plug 52: Wiring 60: Color filter 61: Microlens 100, 602: Image pickup device 400: Camera system 601: Lens optical system 603: System controller 604: Camera signal processing circuit

Claims

1. A photoelectric conversion element comprising: a photoelectric conversion layer containing a first donor semiconductor material and a first acceptor semiconductor material and converting light into signal charges; a first electrode collecting the signal charges; a second electrode facing the first electrode with the photoelectric conversion layer sandwiched therebetween; and a charge injection layer located between the second electrode and the photoelectric conversion layer, wherein the charge injection layer is a bulk hetero layer having a bulk heterojunction structure containing a second donor semiconductor material and a second acceptor semiconductor material, the ratio of the amount of the second acceptor semiconductor material to the amount of the second donor semiconductor material in the charge injection layer is smaller than the ratio of the amount of the first acceptor semiconductor material to the amount of the first donor semiconductor material in the photoelectric conversion layer, and the thickness of the charge injection layer is smaller than the thickness of the photoelectric conversion layer.

2. The photoelectric conversion element according to claim 1, wherein the thickness of the charge injection layer is greater than 0 nm and not greater than 50 nm.

3. The photoelectric conversion element according to claim 2, wherein the charge injection layer has a thickness of 5 nm to 30 nm.

4. The photoelectric conversion element according to claim 1, wherein at least one selected from the group consisting of the first acceptor semiconductor material and the second acceptor semiconductor material is a fullerene or a fullerene derivative.

5. The photoelectric conversion element according to claim 1, further comprising a charge blocking layer located between the first electrode and the photoelectric conversion layer.

6. The photoelectric conversion element according to claim 1, wherein the second acceptor semiconductor material is the same as the first acceptor semiconductor material.

7. The photoelectric conversion element according to claim 1, wherein the second donor semiconductor material is the same as the first donor semiconductor material.

8. The photoelectric conversion element according to claim 1, wherein the second acceptor semiconductor material is the same as the first acceptor semiconductor material, and the second donor semiconductor material is the same as the first donor semiconductor material.

9. An imaging device comprising: a photoelectric conversion element according to any one of claims 1 to 8; and a charge accumulation region electrically connected to the first electrode and configured to accumulate the signal charge.

10. The imaging device according to claim 9, further comprising a voltage supply circuit electrically connected to the second electrode and applying a potential difference between the first electrode and the second electrode, wherein the voltage supply circuit supplies a first voltage to the second electrode during a first period, and supplies a second voltage different from the first voltage during a second period different from the first period.

11. A camera system comprising the imaging device according to claim 9.

Images