Plasma processing device, bias power supply system, and plasma processing method

Abstract

This disclosed plasma processing device comprises a substrate support unit in a chamber and a bias power supply system. In the substrate support unit, a first electrode is disposed below a substrate support surface and electrically coupled to a substrate, and a second electrode is disposed below a ring support surface and electrically coupled to an edge ring. The bias power supply system is configured to periodically apply a first voltage pulse to the first electrode and periodically apply a second voltage pulse to the second electrode. The bias power supply system is configured to be capable of variably adjusting the time difference between a start timing of the application of the first voltage pulse to the first electrode and a start timing of the application of the second voltage pulse to the second electrode.

Description

Plasma processing apparatus, bias power supply system, and plasma processing method

[0001] SUMMARY Exemplary embodiments of the present disclosure relate to a plasma processing apparatus, a bias power supply system, and a plasma processing method.

[0002] A plasma processing apparatus is used for plasma processing of a substrate. The plasma processing apparatus includes a chamber and a substrate support. The substrate support is provided in the chamber. The plasma processing apparatus described in Patent Document 1 listed below is configured to supply bias power separately to an electrode in the substrate support below the substrate and an electrode in the substrate support below the edge ring.

[0003] Japanese Patent Application Laid-Open No. 2020-205379

[0004] The present disclosure provides techniques for extending the replacement life of edge rings.

[0005] In one exemplary embodiment, a plasma processing apparatus is provided. The plasma processing apparatus includes a chamber, a substrate support, a plasma generation unit, and a bias power system. The substrate support is disposed within the chamber. The substrate support includes a substrate support surface on which a substrate is placed, a ring support surface on which an edge ring is placed, a first electrode, and a second electrode. The first electrode is disposed below the substrate support surface and electrically coupled to the substrate. The second electrode is disposed below the ring support surface and electrically coupled to the edge ring. The plasma generation unit is configured to generate a plasma from a gas within the chamber. The bias power system is electrically coupled to the first electrode and the second electrode to attract ions from the plasma to the substrate and the edge ring. The bias power system is configured to periodically apply a first voltage pulse to the first electrode and a second voltage pulse to the second electrode such that the application periods of the first voltage pulse and the second voltage pulse overlap in time. The bias power supply system is configured to variably adjust a start time difference, which is a time difference between a first start timing of application of a first voltage pulse at the first electrode and a second start timing of application of a second voltage pulse at the second electrode, within a range between a time difference at which the second start timing precedes the first start timing and zero.

[0006] According to one exemplary embodiment, a technique is provided for increasing the replacement life of an edge ring.

[0007] FIG. 10 is a diagram for explaining an example configuration of a plasma processing system. FIG. 10 is a diagram for explaining an example configuration of a capacitively coupled plasma processing apparatus. FIG. 10 is a diagram showing a substrate support and a power supply in a plasma processing apparatus according to an exemplary embodiment. FIG. 10 is a diagram showing a bias power supply system according to an exemplary embodiment. FIG. 10 is a timing chart related to a bias power supply system according to an exemplary embodiment. FIG. 10 is a timing chart related to a bias power supply system according to an exemplary embodiment. FIG. 10 is a timing chart related to a bias power supply system according to an exemplary embodiment. FIG. 10 is a timing chart related to a bias power supply system according to an exemplary embodiment. FIG. 10 is a timing chart related to a bias power supply system according to an exemplary embodiment. FIG. 10 is a timing chart related to a bias power supply system according to an exemplary embodiment. FIG. 10 is a flowchart showing a plasma processing method according to an exemplary embodiment. FIG. 10 is a block diagram of a processing circuit for performing the operations described herein on a computer.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0009] FIG. 1 is a diagram illustrating an exemplary configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), or surface wave plasma (SWP). Various types of plasma generators may be used, including alternating current (AC) plasma generators and direct current (DC) plasma generators. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Thus, AC signals include radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0012] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram for explaining a configuration example of a capacitively coupled plasma processing apparatus.

[0013] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0014] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0017] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0018] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0020] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0022] The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0024] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0025] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0026]

[0033] Hereinafter, reference will be made to Fig. 3. Fig. 3 is a diagram showing a substrate support and a power supply in a plasma processing apparatus according to one exemplary embodiment. The substrate support 11, the power supply, and the configuration related to the power supply shown in Fig. 3 can be employed in the plasma processing apparatus 1.

[0027] As described above, the substrate support 11 includes the base 1110 and the electrostatic chuck 1111. The first RF generator 31a may be electrically connected to the base 1110 via a matching unit 31am.

[0028] The substrate support 11 includes a first region R1 and a second region R2. In FIG. 3 , the boundary between the first region R1 and the second region R2 is indicated by a dashed line. The first region R1 is a region that intersects with the axis AX and has a generally disk shape. The axis AX is the central axis of the substrate support 11 and may coincide with the central axis of the chamber 10. The first region R1 includes the above-mentioned substrate support surface 111a as its upper surface. The substrate W is placed on the substrate support surface 111a and supported on the first region R1. The second region R2 extends to surround the first region R1. The second region R2 is an annular region around the axis AX. The second region R2 includes the above-mentioned ring support surface 111b as its upper surface. The edge ring ER included in the ring assembly 112 is placed on the ring support surface 111b and supported on the second region R2. The substrate W is placed within the region surrounded by the edge ring ER.

[0029] The substrate support 11 includes a first electrode BE1 and a second electrode BE2. The first electrode BE1 extends below the substrate support surface 111a and is disposed within the first region R1. The first electrode BE1 may be a film formed from a conductive material. The first electrode BE1 may have a substantially circular planar shape. The first electrode BE1 may be disposed such that its center is located on the axis AX.

[0030] The second electrode BE2 extends below the ring support surface 111b and is disposed within the second region R2. The second electrode BE2 may be a film formed from a conductive material. The second electrode BE2 may have a substantially annular planar shape. The second electrode BE2 may be disposed such that its center is located on the axis AX.

[0031] 3, the electrostatic chuck 1111 may include a dielectric portion 1111d. The dielectric portion 1111d may be the ceramic member 1111a described above. A central portion of the dielectric portion 1111d may form a first region R1 and may have the substrate support surface 111a as its upper surface. A peripheral portion of the dielectric portion 1111d may form a second region R2 and may have the ring support surface 111b as its upper surface.

[0032] The electrostatic chuck 1111 may include a chuck electrode CE1 as part of the electrostatic electrode 1111b. The chuck electrode CE1 is disposed within the dielectric portion 1111d and within the first region R1. The chuck electrode CE1 may be a film formed of a conductive material. The chuck electrode CE1 may have a substantially circular planar shape. The chuck electrode CE1 may be disposed such that its center is located on the axis AX. The chuck electrode CE1 may extend between the substrate support surface 111a and the first electrode BE1.

[0033] The electrostatic chuck 1111 may also include chuck electrodes CE2 and CE3 as separate parts of the electrostatic electrode 1111b. Each of the chuck electrodes CE2 and CE3 is disposed within the dielectric portion 1111d and the second region R2. Each of the chuck electrodes CE2 and CE3 may be a film formed of a conductive material. Each of the chuck electrodes CE2 and CE3 may extend circumferentially around the axis AX or have a substantially annular planar shape. The chuck electrode CE2 is disposed inward relative to the chuck electrode CE3. That is, the radial distance between the chuck electrode CE2 and the axis AX is smaller than the radial distance between the chuck electrode CE3 and the axis AX. Each of the chuck electrodes CE2 and CE3 may also extend between the ring support surface 111b and the second electrode BE2.

[0034] The plasma processing apparatus 1 may further include a DC power supply 41p. The DC power supply 41p is electrically connected to the chuck electrode CE1 via a switch 41s. A filter 41f may further be connected between the DC power supply 41p and the chuck electrode CE1. The filter 41f is a low-pass filter configured to block or attenuate RF signals such as source RF signals. When a voltage from the DC power supply 41p is applied to the chuck electrode CE1, an electrostatic attraction force is generated between the electrostatic chuck 1111 and the substrate W. The generated electrostatic attraction force attracts the substrate W to the first region R1 and holds the substrate W in the first region R1.

[0035] The plasma processing apparatus 1 may further include DC power supplies 42p and 43p. The DC power supply 42p is electrically connected to the chuck electrode CE2 via a switch 42s. A filter 42f may be further connected between the DC power supply 42p and the chuck electrode CE2. The filter 42f is a low-pass filter configured to block or attenuate RF signals such as source RF signals. The DC power supply 43p is electrically connected to the chuck electrode CE3 via a switch 43s. A filter 43f may be further connected between the DC power supply 43p and the chuck electrode CE3. The filter 43f is a low-pass filter configured to block or attenuate RF signals such as source RF signals. When voltages from the DC power supplies 42p and 43p are applied to the chuck electrodes CE2 and CE3, electrostatic attraction is generated between the electrostatic chuck 1111 and the edge ring ER. The edge ring ER is attracted to the second region R2 by the generated electrostatic force and held by the second region R2. Note that a voltage may be applied to the chuck electrodes CE2 and CE3 so as to generate a potential difference therebetween. That is, the second region R2 may constitute a bipolar electrostatic chuck.

[0036] The plasma processing apparatus 1 further includes a bias power supply system 50 as a bias power supply system including the above-described first DC generating unit 32a. The bias power supply system 50 is electrically coupled to the first electrode BE1 and the second electrode BE2.

[0037] The bias power supply system 50 is configured to periodically apply a first voltage pulse VP1 to the first electrode BE1. The bias power supply system 50 is also configured to periodically apply a second voltage pulse VP2 to the second electrode BE2. Each of the first voltage pulse VP1 and the second voltage pulse VP2 is periodically applied at a time interval equal to the time length of its period (waveform period). A bias frequency, which is the reciprocal of the time length of each of the periods (waveform periods) of the first voltage pulse VP1 and the second voltage pulse VP2, is lower than the frequency of the source RF signal and may be a frequency in the range of 100 kHz to 50 MHz. The bias frequency is, for example, 400 kHz. The bias power supply system 50 is configured to generate the first voltage pulse VP1 and the second voltage pulse VP2 such that the application periods of the first voltage pulse VP1 and the second voltage pulse VP2 at least partially overlap each other within a waveform period.

[0038] The first voltage pulse VP1 is applied to the substrate W via the first electrode BE1. The second voltage pulse VP2 is applied to the edge ring ER via the second electrode BE2. The bias power supply system 50 starts the bias voltage pulse VP1 at a start timing t Ｓ１ (first start timing) and start timing t Ｓ２ (second start timing) Ｓ As shown in FIGS. 7 to 9, the start timing t Ｓ１ is the start timing of application of the first voltage pulse VP1 to the first electrode BE1 or the substrate W. In these figures, the voltage V １Ｗ indicates the voltage waveform of the first voltage pulse VP1 applied to the first electrode BE1 or the substrate W. Also, as shown in FIGS. 7 to 9, the start timing t Ｓ２ indicates the start timing of application of the second voltage pulse VP2 to the second electrode BE2 or the edge ring ER. ２Ｅ1 shows a voltage waveform at the second electrode BE2 or the edge ring ER of the second voltage pulse VP2 applied to the second electrode BE2. The bias power supply system 50 starts the bias voltage pulse VP2 at least from the start timing t Ｓ２ is the start timing t Ｓ１ time difference d within the range between the preceding time difference and zero Ｓ is configured to be variably adjustable.

[0039] In one embodiment, the bias power supply system 50 may include a first DC power supply 51, a second DC power supply 52, a first switching circuit 61, a second switching circuit 62, and a pulse control unit 70, as shown in FIG.

[0040] Each of the first DC power supply 51 and the second DC power supply 52 may be a variable DC power supply. The first switching circuit 61 is electrically connected between the first DC power supply 51 and the first electrode BE1. The first switching circuit 61 is configured to alternately connect the negative and positive poles of the first DC power supply 51 to the first electrode BE1 to periodically apply a first voltage pulse VP1 to the first electrode BE1. The second switching circuit 62 is electrically connected between the second DC power supply 52 and the second electrode BE2. The second switching circuit 62 is configured to alternately connect the negative and positive poles of the second DC power supply 52 to the second electrode BE2 to periodically apply a second voltage pulse VP2 to the second electrode BE2.

[0041] The pulse control unit 70 is configured to control the first switching circuit 61 and the second switching circuit 62. In one embodiment, the pulse control unit 70 may be configured to control the first switching circuit 61 and the second switching circuit 62 by a first pulse control signal, a first inverted signal, a second pulse control signal, and a second inverted signal, which will be described later. The pulse control unit 70 controls the first switching circuit 61 and the second switching circuit 62 to set the time difference d Ｓ is configured to variably adjust

[0042] Reference will now be made to FIG. 4, which is a diagram illustrating a bias power supply system according to an exemplary embodiment. In one embodiment, the bias power supply system 50 may have the configuration shown in FIG. 4. That is, the first switching circuit 61 may include a first switching element 611 and a second switching element 612. The second switching circuit 62 may include a third switching element 623 and a fourth switching element 624. Each of the first switching element 611, the second switching element 612, the third switching element 623, and the fourth switching element 624 may be composed of a transistor such as an FET.

[0043] The first switching element 611 includes a control terminal 611c. The first switching element 611 further includes a first terminal and a second terminal. The control terminal 611c is connected to the pulse control unit 70. In one embodiment, the first switching element 611 is configured to switch between open and closed states in response to a first pulse control signal provided to the control terminal 611c from the pulse control unit 70. That is, the first switching element 611 is configured to switch between conduction and disconnection between its first terminal and second terminal in response to the first pulse control signal provided to the control terminal 611c.

[0044] The first switching element 611 is connected between the negative electrode of the first DC power supply 51 and a node 61na. A first terminal of the first switching element 611 is connected to the negative electrode of the first DC power supply 51, and a second terminal of the first switching element 611 is connected to the node 61na. The node 61na is connected to a node 61nb. The node 61nb is connected to an output 61o of the first switching circuit 61. The output 61o is an output for a first voltage pulse VP1 and is electrically connected to the first electrode BE1.

[0045] The second switching element 612 includes a control terminal 612c. The second switching element 612 further includes a first terminal and a second terminal. The control terminal 612c is connected to the pulse control unit 70. In one embodiment, the second switching element 612 is configured to switch between open and closed states in response to a first inverted signal provided to the control terminal 612c. That is, the second switching element 612 is configured to switch between conduction and disconnection between its first and second terminals in response to the first inverted signal provided to the control terminal 612c. Note that the first inverted signal is an inverted signal of the first pulse control signal.

[0046] The second switching element 612 is connected between the positive electrode of the first DC power supply 51 and a node 61na. A first terminal of the second switching element 612 is connected to the node 61na, and a second terminal of the second switching element 612 is connected to the positive electrode of the first DC power supply 51. The positive electrode of the first DC power supply 51 is connected to ground. Note that the positive electrode of the first DC power supply 51 may be connected to a reference potential line other than ground.

[0047] The first switching circuit 61 may further include a diode 61da and a diode 61db. The anode of the diode 61da is connected to the negative electrode of the first DC power supply 51 and the first terminal of the first switching element 611. The cathode of the diode 61da is connected to a node 61nb. The anode of the diode 61db is connected to the node 61nb. The cathode of the diode 61db is connected to the positive electrode of the first DC power supply 51 and the second terminal of the second switching element 612.

[0048] The first switching circuit 61 may further include an inductor 61i and a resistor 61r. The inductor 61i and the resistor 61r may be connected in series between the node 61nb and the output 61o. The output 61o may be connected to the first electrode BE1 through a filter 61f. The filter 61f is a low-pass filter that blocks or attenuates RF signals, such as a source RF signal.

[0049] The third switching element 623 includes a control terminal 623c. The third switching element 623 further includes a first terminal and a second terminal. The control terminal 623c is connected to the pulse control unit 70. In one embodiment, the third switching element 623 is configured to switch between open and closed states in response to a second pulse control signal provided to the control terminal 623c from the pulse control unit 70. That is, the third switching element 623 is configured to switch between conduction and disconnection between its first terminal and its second terminal in response to the second pulse control signal provided to the control terminal 623c.

[0050] The third switching element 623 is connected between the negative electrode of the second DC power supply 52 and a node 62na. A first terminal of the third switching element 623 is connected to the negative electrode of the second DC power supply 52, and a second terminal of the third switching element 623 is connected to the node 62na. The node 62na is connected to a node 62nb. The node 62nb is connected to an output 62o of the second switching circuit 62. The output 62o is an output for a second voltage pulse VP2 and is electrically connected to the second electrode BE2.

[0051] The fourth switching element 624 includes a control terminal 624c. The fourth switching element 624 further includes a first terminal and a second terminal. The control terminal 624c is connected to the pulse control unit 70. In one embodiment, the fourth switching element 624 is configured to switch between open and closed states in response to a second inverted signal provided to the control terminal 624c by the pulse control unit 70. That is, the fourth switching element 624 is configured to switch between conduction and disconnection between its first terminal and its second terminal in response to the second inverted signal provided to the control terminal 624c. Note that the second inverted signal is an inverted signal of the second pulse control signal.

[0052] The fourth switching element 624 is connected between the positive electrode of the second DC power supply 52 and the node 62na. A first terminal of the fourth switching element 624 is connected to the node 62na, and a second terminal of the fourth switching element 624 is connected to the positive electrode of the second DC power supply 52. ​​In one embodiment, the positive electrode of the second DC power supply 52 may be electrically connected to the output 61o of the first switching circuit 61.

[0053] The second switching circuit 62 may further include a diode 62da and a diode 62db. The anode of the diode 62da is connected to the negative electrode of the second DC power supply 52 and the first terminal of the third switching element 623. The cathode of the diode 62da is connected to a node 62nb. The anode of the diode 62db is connected to the node 62nb. The cathode of the diode 62db is connected to the positive electrode of the second DC power supply 52 and the second terminal of the fourth switching element 624.

[0054] The second switching circuit 62 may further include an inductor 62i and a resistor 62r. ​​The inductor 62i and the resistor 62r may be connected in series between the node 62nb and the output 62o. The output 62o may be connected to the second electrode BE2 through a filter 62f. The filter 62f is a low-pass filter that blocks or attenuates RF signals, such as a source RF signal.

[0055] Reference is now made to Figures 5 and 6, each of which is a timing chart associated with a bias power supply system according to an exemplary embodiment. Figure 5 illustrates the level of a first pulse control signal, the level of a first inverted signal, and the states of the first and second switching elements. Figure 6 illustrates the level of a second pulse control signal, the level of a second inverted signal, and the states of the third and fourth switching elements.

[0056] As shown in Fig. 5, the pulse control unit 70 may generate the first pulse control signal and the first inverted signal such that the first pulse control signal and the first inverted signal alternate between a first level L1 and a second level L2. As shown in Fig. 6, the pulse control unit 70 may generate the second pulse control signal and the second inverted signal such that the second pulse control signal and the second inverted signal alternate between a first level L1 and a second level L2. The first levels of the first pulse control signal, the first inverted signal, the second pulse control signal, and the second inverted signal may be different from each other. The second levels of the first pulse control signal, the first inverted signal, the second pulse control signal, and the second inverted signal may be different from each other.

[0057] 5 , when the first pulse control signal has a first level L1, the first inverted signal has a second level L2, the first switching element 611 is in a closed state (conducting state), and the second switching element 612 is in an open state (disconnecting state). At this time, the output 61o is connected to the negative electrode of the first DC power supply 51. In one embodiment, at this time, the potential of the positive electrode of the second DC power supply 52 becomes the same as the potential of the negative electrode of the first DC power supply 51.

[0058] On the other hand, when the first pulse control signal has the second level L2, the first inverted signal has the first level L1, the first switching element 611 is in the open state (disconnected state), and the second switching element 612 is in the closed state (conducting state). At this time, the output 61o is connected to the positive electrode of the first DC power supply 51. In one embodiment, at this time, the potential of the positive electrode of the second DC power supply 52 becomes the same as the potential of the positive electrode of the first DC power supply 51.

[0059] 6 , when the second pulse control signal has a first level L1, the second inverted signal has a second level L2, the third switching element 623 is in a closed state (conducting state), and the fourth switching element 624 is in an open state (disconnecting state). At this time, the output 62o is connected to the negative electrode of the second DC power supply 52. ​​In one embodiment, when the positive electrode of the second DC power supply 52 is connected to the positive electrode of the first DC power supply 51, the potential of the output 62o at this time is the potential of the negative electrode of the second DC power supply 52 relative to the potential of the positive electrode of the first DC power supply 51. Furthermore, when the positive electrode of the second DC power supply 52 is connected to the negative electrode of the first DC power supply 51, the potential of the output 62o at this time is the potential of the negative electrode of the second DC power supply 52 relative to the potential of the negative electrode of the first DC power supply 51. That is, in this case, the potential of the output 62 o has a value equal to the sum of the potential of the negative electrode of the first DC power supply 51 and the potential of the negative electrode of the second DC power supply 52 .

[0060] On the other hand, when the second pulse control signal has the second level L2, the second inverted signal has the first level L1, the third switching element 623 is in an open state (disconnected state), and the fourth switching element 624 is in a closed state (conducting state). At this time, the output 62o is connected to the positive electrode of the second DC power supply 52. ​​In one embodiment, when the positive electrode of the second DC power supply 52 is connected to the positive electrode of the first DC power supply 51, the potential of the output 62o at this time becomes the potential of the positive electrode of the first DC power supply 51. Furthermore, when the positive electrode of the second DC power supply 52 is connected to the negative electrode of the first DC power supply 51, the potential of the output 62o at this time becomes the potential of the negative electrode of the first DC power supply 51.

[0061] 7 to 9 are referenced below. Each of FIGS. 7 to 9 is a timing chart related to a bias power supply system according to an exemplary embodiment. FIGS. 7 to 9 show timing charts of the first voltage pulse VP1, the second voltage pulse VP2, and the differential voltage ΔV therebetween in the first to third modes. The differential voltage ΔV is zero when the output 62o is connected to the positive terminal of the second DC power supply 52, and has the level of the potential difference between the positive terminal and the negative terminal of the second DC power supply 52 when the output 62o is connected to the negative terminal of the second DC power supply 52.

[0062] The pulse control unit 70 controls the application period of the first voltage pulse VP1, the application period of the second voltage pulse VP2, and the generation period of the differential voltage ΔV in each of the first to third modes. The application period of the first voltage pulse VP1, the application period of the second voltage pulse VP2, and the generation period of the differential voltage ΔV can be controlled by the above-mentioned first pulse control signal, first inversion signal, second pulse control signal, and second inversion signal. Furthermore, in each of the first to third modes, the voltage levels of the first voltage pulse VP1 and the second voltage pulse VP2 are set so that the upper end position of the plasma sheath over the substrate W on the substrate support 11 substantially coincides with the upper end position of the plasma sheath over the edge ring ER on the substrate support 11.

[0063] The first mode can be applied when a new edge ring ER is used. A new edge ring ER is an edge ring that has never been used or is considered to be in a state where its wear is not advanced. The new edge ring ER has a thickness such that the upper end position of the plasma sheath on the edge ring ER mounted on the substrate support 11 is substantially the same as the upper end position of the plasma sheath on the substrate W mounted on the substrate support 11 in the first mode. For example, the upper surface of the substrate W mounted on the substrate support 11 and the upper surface of the new edge ring ER may be positioned approximately the same in the height direction.

[0064] As shown in FIG. 7, the pulse control unit 70 controls the time difference d Ｓ At the start timing t Ｓ１ Start timing t Ｓ２ In the first mode, the pulse control unit 70 may increase the absolute value of the voltage level of the second voltage pulse VP2 in accordance with an increase in the amount of wear (amount of reduction in thickness) of the edge ring ER.

[0065] In one embodiment, the pulse control unit 70 sets the end timing t Ｅ１ and end timing t Ｅ２ The end timing t Ｅ１is the end timing of the application of the first voltage pulse VP1 to the first electrode BE1 or the substrate W. Ｅ２ is the end timing of the application of the second voltage pulse VP2 to the second electrode BE2 or the edge ring ER. In the first mode, the pulse control unit 70 determines the end timing t ＥΔ At the end timing t Ｅ２ It can be put ahead of

[0066] The second mode can be applied when the edge ring ER is worn out more than in the state of the edge ring ER in the first mode. As shown in FIG. 8, in the second mode, the pulse control unit 70 Ｓ is set to substantially zero. In the second mode, the pulse control unit 70 may also increase the absolute value of the voltage level of the second voltage pulse VP2 in accordance with an increase in the amount of wear of the edge ring ER. Note that the voltage level of the second voltage pulse VP2 at the end of the period in which the first mode is applied and the voltage level of the second voltage pulse VP2 at the start of the period in which the second mode is applied may or may not be the same.

[0067] In one embodiment, the pulse control unit 70 sets the end timing t Ｅ１ and end timing t Ｅ２ In the second mode, the pulse control unit 70 adjusts the end timing t ＥΔ The end timing t Ｅ２ The end timing t in the second mode can be set to precede the end timing t ＥΔ and end timing t Ｅ２ The time difference between the end timing t ＥΔ and end timing t Ｅ２ may be smaller than the time difference between

[0068] The third mode can be applied when the edge ring ER is worn out more than in the state of the edge ring ER in the second mode. As shown in FIG. 9, in the third mode, the pulse control unit 70Ｓ is set to substantially zero. In addition, in the third mode, the pulse control unit 70 may increase the absolute value of the voltage level of the second voltage pulse VP2 in accordance with an increase in the amount of wear of the edge ring ER. Note that the voltage level of the second voltage pulse VP2 at the end of the period in which the second mode is applied and the voltage level of the second voltage pulse VP2 at the start of the period in which the third mode is applied may or may not be the same.

[0069] In the third mode, the pulse control unit 70 determines the end timing t ＥΔ The end timings t of the first mode and the second mode are ＥΔ That is, in the third mode, the pulse control unit 70 delays the end timing t ＥΔ and end timing t Ｅ２ The time difference between the end timing t ＥΔ and end timing t Ｅ２ In other words, in the third mode, the pulse control unit 70 extends the period during which there is a difference between the voltage level of the first voltage pulse VP1 and the voltage level of the second voltage pulse VP2 compared to the first and second modes. Specifically, in the third mode, the pulse control unit 70 delays the timing at which the electrode of the second DC power supply 52 to which the second electrode BE2 is connected is switched from negative to positive, compared to the timing at which the electrode of the second DC power supply 52 to which the second electrode BE2 is connected is switched from negative to positive in each of the first and second modes. Note that in the third mode, the pulse control unit 70 delays the end timing t ＥΔ End timing t Ｅ２ may be substantially the same as

[0070] Here, reference is made to Figures 10(a) and 10(b). Figure 10(a) is a diagram showing the state of the plasma sheath when the first start timing and the second start timing are simultaneous, and Figure 10(b) is a diagram showing the state of the plasma sheath in the first mode. Figures 10(a) and 10(b) show the behavior of the plasma sheath SH and ions when a new edge ring ER is used.

[0071] Here, even at the start of use of a brand new edge ring ER, the absolute value of the voltage level of the second voltage pulse VP2 is higher than the absolute value of the voltage level of the first voltage pulse VP1. Ｓ１ and start timing t Ｓ２ When these are aligned, as shown in (a) of Figure 10, the upper end position of the plasma sheath SH on the edge ring ER becomes higher than the upper end position of the plasma sheath SH on the substrate W, and the direction of ion travel from the plasma toward the edge of the substrate W is tilted outward relative to the vertical direction, as shown by the arrow in the figure.

[0072] On the other hand, the above-mentioned time difference d Ｓ 10B, the direction of ion travel toward the edge of the substrate W is corrected inward, and as a result, in the first mode, the angular difference between the direction of ion travel toward the edge of the substrate W and the vertical direction is reduced or eliminated, as shown by the arrow in FIG.

[0073] In the first mode, the absolute value of the voltage level of the second voltage pulse VP2 can be increased in accordance with the wear of the edge ring ER, so that in the first mode, even if the edge ring ER is worn out, the angular difference between the traveling direction of ions toward the edge of the substrate W and the vertical direction is reduced or eliminated.

[0074] In the second mode, the time difference d Ｓis set to approximately zero. In the second mode, the absolute value of the voltage level of the second voltage pulse VP2 can be further increased in accordance with the wear of the edge ring ER. Therefore, in the second mode, even if the edge ring ER is further worn, the angular difference between the traveling direction of ions toward the edge of the substrate W and the vertical direction is reduced or eliminated.

[0075] In the third mode, the time difference d Ｓ is set to approximately zero. In the third mode, the end timing t ＥΔ is the end timing t of each of the first mode and the second mode. ＥΔ In the third mode, the absolute value of the voltage level of the second voltage pulse VP2 can be further increased in accordance with the wear of the edge ring ER. Therefore, in the third mode, even if the edge ring ER is further worn, the angular difference between the traveling direction of the ions toward the edge of the substrate W and the vertical direction is reduced or eliminated.

[0076] According to the plasma processing apparatus 1 described above, the time difference d Ｓ Since is variable, it is possible to extend the replacement life of the edge ring ER.

[0077] A plasma processing method according to one exemplary embodiment will be described below with reference to Fig. 11. The plasma processing method shown in Fig. 11 (hereinafter referred to as "method MT") can be applied to a plasma processing apparatus 1. In method MT, each part of the plasma processing apparatus 1 can be controlled by a controller 2.

[0078] The method MT starts with step STa. In step STa, a substrate W is placed on the substrate support surface 111a. The substrate W is disposed on the electrostatic chuck 1111 within a region surrounded by the edge ring ER. The substrate W is held by the electrostatic chuck 1111.

[0079] In process STb, plasma is generated in the chamber 10. In process STb, gas is supplied from the gas supply unit 20 into the chamber 10. In process STb, the pressure in the chamber 10 is reduced to a specified pressure by the exhaust system 40. In process STb, plasma is generated from the gas in the chamber 10 by the plasma generating unit 12. In one embodiment, a source RF signal is supplied from the first RF generating unit 31 a to generate plasma from the gas in the chamber 10.

[0080] In step STc, a first voltage pulse VP1 is periodically applied to the first electrode BE1 to attract ions from the plasma generated in step STb to the substrate W. The first voltage pulse VP1 is applied to the substrate W via the first electrode BE1.

[0081] In step STd, in order to attract ions from the plasma generated in step STb into the edge ring ER, a second voltage pulse VP2 is applied to the second electrode BE2 so that the application of the first voltage pulse VP1 and the application of the second voltage pulse VP2 overlap in time. The second voltage pulse VP2 is applied to the edge ring ER via the second electrode BE2.

[0082] In the step STe, the second voltage pulse VP2 is adjusted in accordance with the amount of wear of the edge ring ER. Ｓ The process STe includes adjusting the temperature as described above. The process STe is performed while the processes STa to STd are repeated. During the repetition of the processes STa to STd, the operations (processing) of the first to third modes described above can be performed in order in the process STe.

[0083] The following describes examples of processing circuits that can be used as one or more processing circuits in the plasma processing apparatus 1, such as the control unit 2 and / or the pulse control unit 70. FIG. 12 is a block diagram of a processing circuit for implementing the operations described herein on a computer. FIG. 12 illustrates a processing circuit 130 that can be used to control a control process on any computer. The descriptions or blocks in the flowcharts represent modules, segments, or portions of code that include one or more executable instructions for implementing specific logical functions or steps of the process. As will be understood by those skilled in the art, other examples having functions that can be performed in a different order than that shown or described, such as substantially concurrently or in reverse order, depending on the functionality involved, are included within the scope of exemplary embodiments of the present disclosure. The various elements, features, and processes described herein may be used independently of each other or combined in various ways. All conceivable combinations and subcombinations are within the scope of the present disclosure.

[0084] In Figure 12, processing circuitry 130 includes a CPU 1200 that performs one or more of the control processes described above and / or below. Process data and instructions may be stored in memory 1202. These process data and instructions may be stored on a storage medium disk 1204, such as a hard disk drive (HDD) or a portable storage medium, or may be stored remotely. Furthermore, the claimed disclosure is not limited by the form of computer-readable medium on which instructions for processes according to the present invention are stored. For example, these instructions may be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device, such as a server and / or computer, with which processing circuitry 130 communicates.

[0085] Furthermore, the claimed disclosure may be provided as a utility application, a background daemon, a component of an operating system, or a combination thereof, and may execute in conjunction with CPU 1200 and an operating system known to those skilled in the art, such as Microsoft Windows®, UNIX®, Solaris®, LINUX®, Apple MAC-OS, etc.

[0086] The hardware elements making up the processing circuit 130 can be realized by various circuit elements. Furthermore, each function of the above-described embodiments can be implemented by a circuit including one or more processing circuits. As shown in FIG. 12, the processing circuit includes a specifically programmed processing unit, such as a processing unit (CPU) 1200. The processing circuit also includes devices such as application specific integrated circuits (ASICs) or conventional circuit components configured to perform the described functions.

[0087] 12, processing circuitry 130 includes a CPU 1200 that performs the above-described processing. Processing circuitry 130 may be a general-purpose computer or a specialized machine. In one embodiment, processing circuitry 130 functions as a specialized machine when processing device 1200 is programmed to control plasma generation unit 12 and gas supply unit 20 and / or to control bias power supply system 50.

[0088] Alternatively or additionally, CPU 1200 may be implemented on an FPGA, ASIC, PLD, or using discrete logic circuitry, as will be appreciated by those skilled in the art. Furthermore, CPU 1200 may be implemented as multiple processing units cooperating to perform in parallel the instructions of the processes of the present invention described above.

[0089] The processing circuitry 130 of FIG. 12 also includes a network controller 1206, such as an Intel Ethernet PRO network interface card from Intel Corporation of America, for interfacing with a network 1228. As can be appreciated, the network 1228 may be a public network such as the Internet, a private network such as a LAN or WAN, or any combination thereof, and may also include sub-networks such as PSTN or ISDN. The network 1228 may also be wired, such as an Ethernet network, or wireless, such as a cellular network including EDGE, 3G, and 4G wireless cellular systems. The wireless network may also be Wi-Fi, Bluetooth, or any other known form of wireless communication.

[0090] The processing circuitry 130 further includes a display device controller 1208, such as a graphics card or graphics adapter, for interfacing with a display device 1210, such as a monitor. A general-purpose I / O interface 1212 interfaces with a keyboard and / or mouse 1214 and a touch panel 1216, which may be integral with or separate from the display device 1210. The general-purpose I / O interface also connects to various peripheral devices 1218, such as printers and scanners.

[0091] The storage controller 1224 is connected to the storage media disk 1204 via a communication bus 1226, such as ISA, EISA, VESA, PCI, etc., and all components of the processing circuit 130 are connected to each other. The display device 1210, keyboard and / or mouse 1214, and the general features and functions of the display device controller 1208, storage controller 1224, network controller 1206, audio controller 1220, and general purpose I / O interface 1212 are not described herein for the sake of brevity, as they are well known.

[0092] The exemplary circuit elements described in this disclosure may be substituted with other elements and may have different structures than the examples described herein. Furthermore, circuits configured to implement the features described herein may be implemented in multiple circuit units (e.g., chips), or these features may be combined into the circuitry of a single chipset.

[0093] The functions and features described herein may also be performed by various distributed components on a system. For example, one or more processing devices may perform the functions of these systems, where the processing devices are distributed across multiple components communicating within a network. Distributed components may include various human interface and communication devices (e.g., display monitors, smartphones, tablets, personal digital assistants (PDAs)), as well as one or more client and server machines that can share processing. The network may be a private network, such as a LAN or WAN, or a public network, such as the Internet. Input to the system may be received directly by a user or remotely in real time or as a batch process. Furthermore, portions of the embodiments may be implemented on modules or hardware other than those described above. Accordingly, other embodiments are within the scope of the claims.

[0094] Although various exemplary embodiments have been described above, the present invention is not limited to the above-described exemplary embodiments, and various additions, omissions, substitutions, and modifications may be made. Furthermore, elements in different embodiments may be combined to form other embodiments.

[0095] Various exemplary embodiments included in the present disclosure are now described in [E1] to [E22] below.

[0096] [E1] A method for manufacturing a semiconductor device comprising: a chamber; a substrate support disposed within the chamber, the substrate support having a substrate support surface on which a substrate is placed, a ring support surface on which an edge ring is placed, a first electrode disposed below the substrate support surface and electrically coupled to the substrate, and a second electrode disposed below the ring support surface and electrically coupled to the edge ring; a plasma generation unit configured to generate plasma from a gas within the chamber; and a bias power supply system electrically coupled to the first electrode and the second electrode to attract ions from the plasma to the substrate and the edge ring, wherein the bias power supply system periodically applies a first voltage pulse to the first electrode and a second voltage pulse to the second electrode such that an application period of a first voltage pulse and an application period of a second voltage pulse overlap in time; a start time difference, which is a time difference between a first start timing of application of the first voltage pulse at the first electrode and a second start timing of application of the second voltage pulse at the second electrode, is variably adjustable within a range between a time difference in which the second start timing precedes the first start timing and zero.

[0097] [E2] The plasma processing apparatus according to E1, wherein the bias power supply system includes: a first DC power supply; a first switching circuit configured to alternately connect a negative pole and a positive pole of the first DC power supply to the first electrode and periodically apply the first voltage pulse to the first electrode; a second DC power supply; a second switching circuit configured to alternately connect a negative pole and a positive pole of the second DC power supply to the second electrode and periodically apply the second voltage pulse to the second electrode; and a pulse control unit configured to control the first switching circuit and the second switching circuit to variably adjust the start time difference.

[0098] [E3] The plasma processing apparatus according to E2, wherein the first switching circuit includes: a first switching element having a control terminal connected to the pulse control unit and electrically connected between the first electrode and the negative electrode of the first DC power supply; and a second switching element having a control terminal connected to the pulse control unit and electrically connected between the first electrode and each of the first switching elements and the positive electrode of the first DC power supply; and the second switching circuit includes: a third switching element having a control terminal connected to the pulse control unit and electrically connected between the second electrode and the negative electrode of the second DC power supply; and a fourth switching element having a control terminal connected to the pulse control unit and electrically connected between the second electrode and each of the third switching elements and the positive electrode of the second DC power supply.

[0099] [E4] The plasma processing apparatus according to E3, wherein the positive electrode of the second DC power supply is electrically connected to an output for the first voltage pulse of the first switching circuit.

[0100] [E5] The plasma processing apparatus according to E4, wherein the positive electrode of the first DC power supply is connected to ground.

[0101] [E6] The plasma processing apparatus according to any one of E2 to E5, wherein the pulse control unit is configured, in a first mode, to set the start time difference to a time difference in which the second start timing precedes the first start timing, and to increase the absolute value of the voltage level of the second voltage pulse in accordance with an increase in wear of the edge ring.

[0102] [E7] The plasma processing apparatus according to E6, wherein the pulse control unit is configured to substantially coincide, in the first mode, with an end timing of the application of the first voltage pulse to the first electrode and an end timing of the application of the second voltage pulse to the second electrode.

[0103] [E8] The plasma processing apparatus according to E6 or E7, wherein the pulse control unit is configured to set the start time difference to substantially zero in a second mode that is applied when wear of the edge ring is more advanced than the state of the edge ring in the first mode, and to increase the absolute value of the voltage level of the second voltage pulse in accordance with an increase in wear of the edge ring.

[0104] [E9] The plasma processing apparatus according to E8, wherein the pulse control unit is configured to substantially coincide, in the second mode, with an end timing of application of the first voltage pulse to the first electrode and an end timing of application of the second voltage pulse to the second electrode.

[0105] [E10] The plasma processing apparatus according to E8 or E9, wherein the pulse control unit is configured to: in a third mode applied when wear of the edge ring is more advanced than a state of the edge ring in the second mode, set the start time difference to substantially zero and increase an absolute value of a voltage level of the second voltage pulse according to an increase in an amount of wear of the edge ring; and delay a timing at which an electrode of the second DC power supply to which the second electrode is connected is switched from the negative pole of the second DC power supply to the positive pole of the second DC power supply in the third mode relative to a timing at which the electrode of the second DC power supply to which the second electrode is connected is switched from the negative pole of the second DC power supply to the positive pole of the second DC power supply in the first mode and the second mode.

[0106] [E11] The plasma processing apparatus according to any one of E2 to E5, wherein the pulse control unit is configured to set the start time difference to a time difference in which the second start timing precedes the first start timing.

[0107] [E12] The plasma processing apparatus according to any one of E2 to E5, wherein the pulse control unit is configured to: set the start time difference to substantially zero; and set the timing at which the difference between the voltage level of the first voltage pulse at the first electrode and the voltage level of the second voltage pulse at the second electrode becomes zero to a timing before the end timing of application of the second voltage pulse at the second electrode or a timing substantially identical to the end timing.

[0108] [E13] A first DC power supply; and a first switching circuit configured to alternately connect a negative pole and a positive pole of the first DC power supply to a first electrode to periodically apply a first voltage pulse to the first electrode, in order to attract ions from plasma in a chamber of a plasma processing apparatus to a substrate placed on a substrate support surface of a substrate support part disposed in the chamber, the first electrode being disposed within the substrate support part and below the substrate support surface and electrically coupled to the substrate on the substrate support surface; a second DC power supply; and a second switching circuit configured to alternately connect a negative pole and a positive pole of the second DC power supply to a second electrode to periodically apply a second voltage pulse to the second electrode, in order to attract ions from the plasma to an edge ring placed on a ring support surface of the substrate support part, the second electrode being disposed within the substrate support part and below the ring support surface and electrically coupled to the edge ring on the ring support surface; a pulse control unit configured to control the first switching circuit and the second switching circuit to temporally overlap an application period of the first voltage pulse and an application period of the second voltage pulse, and to variably adjust a start time difference, which is a time difference between a first start timing of application of the first voltage pulse at the first electrode and a second start timing of application of the second voltage pulse at the second electrode, within a range between a time difference at which the second start timing precedes the first start timing and zero.

[0109] [E14] The bias power supply system according to E13, wherein the first switching circuit includes: a first switching element having a control terminal connected to the pulse control unit, and electrically connected between the first electrode and the negative electrode of the first DC power supply; and a second switching element having a control terminal connected to the pulse control unit, and electrically connected between the first electrode and each of the first switching elements and the positive electrode of the first DC power supply; and the second switching circuit includes: a third switching element having a control terminal connected to the pulse control unit, and electrically connected between the second electrode and the negative electrode of the second DC power supply; and a fourth switching element having a control terminal connected to the pulse control unit, and electrically connected between the second electrode and each of the third switching elements and the positive electrode of the second DC power supply.

[0110] [E15] The bias power supply system according to E14, wherein the positive electrode of the second DC power supply is electrically connected to an output for the first voltage pulse of the first switching circuit.

[0111] [E16] The bias power supply system according to E15, wherein the positive electrode of the first DC power supply is connected to ground.

[0112] [E17] (a) preparing a substrate, the substrate being placed on a substrate support surface of a substrate support part disposed in a chamber of a plasma processing apparatus and within a region surrounded by an edge ring on a ring support surface of the substrate support part; (b) generating plasma in the chamber; (c) periodically applying a first voltage pulse to a first electrode to attract ions into the substrate, the first electrode being disposed within the substrate support part and below the substrate support surface and electrically coupled to the substrate on the substrate support surface; (d) applying a second voltage pulse to a second electrode in (c) so that application of the first voltage pulse and application of the second voltage pulse overlap in time to attract ions into the edge ring, the second electrode being disposed within the substrate support part and below the ring support surface and electrically coupled to the edge ring on the ring support surface; (e) adjusting, in accordance with an amount of wear of the edge ring, a start time difference between a first start timing of application of the first voltage pulse to the first electrode in (c) and a second start timing of application of the second voltage pulse to the second electrode in (d), within a range between a time difference by which the second start timing precedes the first start timing and zero.

[0113] [E18] The plasma processing method according to E17, wherein (e) includes, in a first mode, setting the start time difference to a time difference in which the second start timing precedes the first start timing, and increasing the absolute value of the voltage level of the second voltage pulse of (d) in accordance with an increase in wear of the edge ring.

[0114] [E19] The plasma processing method according to E18, wherein (e) includes, in the first mode, substantially matching an end timing of the application of the first voltage pulse to the first electrode with an end timing of the application of the second voltage pulse to the second electrode.

[0115] [E20] The plasma processing method according to E18 or E19, wherein (e) includes, in a second mode applied when wear of the edge ring is more advanced than the state of the edge ring in the first mode, setting the start time difference to substantially zero and increasing an absolute value of a voltage level of the second voltage pulse in accordance with an increase in an amount of wear of the edge ring.

[0116] [E21] The plasma processing method according to E20, wherein (e) includes, in the second mode, substantially matching an end timing of the application of the first voltage pulse to the first electrode with an end timing of the application of the second voltage pulse to the second electrode.

[0117] [E22] The plasma processing method according to E20 or E21, wherein (e) includes, in a third mode applied when wear of the edge ring is more advanced than the state of the edge ring in the second mode, setting the start time difference to substantially zero and increasing the absolute value of the voltage level of the second voltage pulse in accordance with an increase in the amount of wear of the edge ring, and extending a period during which a difference occurs between the voltage level of the first voltage pulse and the voltage level of the second voltage pulse with respect to the first mode and the second mode.

[0118] From the foregoing, it will be understood that various embodiments of the present disclosure have been described herein for purposes of illustration, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

[0119] 1...plasma processing apparatus, 10...chamber, 11...substrate support portion, 111a...substrate support surface, 111b...ring support surface, BE1...first electrode, BE2...second electrode, 12...plasma generation portion, 50...bias power supply system, 51...first DC power supply, 52...second DC power supply, 61...first switching circuit, 62...second switching circuit, 70...pulse control portion.

Claims

1. A method for manufacturing a semiconductor device comprising: a chamber; a substrate support disposed within the chamber, the substrate support having a substrate support surface on which a substrate is placed, a ring support surface on which an edge ring is placed, a first electrode disposed below the substrate support surface and electrically coupled to the substrate, and a second electrode disposed below the ring support surface and electrically coupled to the edge ring; a plasma generation unit configured to generate a plasma from a gas within the chamber; and a bias power supply system electrically coupled to the first electrode and the second electrode to attract ions from the plasma to the substrate and the edge ring, wherein the bias power supply system periodically applies a first voltage pulse to the first electrode and a second voltage pulse to the second electrode such that a period of application of the first voltage pulse and a period of application of the second voltage pulse overlap in time; a start time difference, which is a time difference between a first start timing of application of the first voltage pulse at the first electrode and a second start timing of application of the second voltage pulse at the second electrode, is variably adjustable within a range between a time difference in which the second start timing precedes the first start timing and zero.

2. The plasma processing apparatus according to claim 1, wherein the bias power supply system includes: a first DC power supply; a first switching circuit configured to alternately connect a negative pole and a positive pole of the first DC power supply to the first electrode and periodically apply the first voltage pulse to the first electrode; a second DC power supply; a second switching circuit configured to alternately connect a negative pole and a positive pole of the second DC power supply to the second electrode and periodically apply the second voltage pulse to the second electrode; and a pulse control unit configured to control the first switching circuit and the second switching circuit to variably adjust the start time difference.

3. The plasma processing apparatus according to claim 2, wherein the first switching circuit includes: a first switching element having a control terminal connected to the pulse control unit and electrically connected between the first electrode and the negative electrode of the first DC power supply; a second switching element having a control terminal connected to the pulse control unit and electrically connected between the first electrode and each of the first switching elements and the positive electrode of the first DC power supply; and the second switching circuit includes: a third switching element having a control terminal connected to the pulse control unit and electrically connected between the second electrode and the negative electrode of the second DC power supply; and a fourth switching element having a control terminal connected to the pulse control unit and electrically connected between the second electrode and each of the third switching elements and the positive electrode of the second DC power supply.

4. The plasma processing apparatus according to claim 3, wherein the positive electrode of the second DC power supply is electrically connected to an output for the first voltage pulse of the first switching circuit.

5. The plasma processing apparatus according to claim 4, wherein the positive electrode of the first DC power supply is connected to ground.

6. A plasma processing apparatus according to any one of claims 2 to 5, wherein the pulse control unit is configured, in the first mode, to set the start time difference to a time difference in which the second start timing precedes the first start timing, and to increase the absolute value of the voltage level of the second voltage pulse in accordance with an increase in the amount of wear of the edge ring.

7. The plasma processing apparatus of claim 6, wherein the pulse control unit is configured to substantially coincide the end timing of application of the first voltage pulse to the first electrode with the end timing of application of the second voltage pulse to the second electrode in the first mode.

8. The plasma processing apparatus of claim 6, wherein the pulse control unit is configured to set the start time difference to substantially zero in a second mode that is applied when wear of the edge ring is more advanced than the state of the edge ring in the first mode, and to increase the absolute value of the voltage level of the second voltage pulse in accordance with an increase in the amount of wear of the edge ring.

9. The plasma processing apparatus of claim 8, wherein the pulse control unit is configured to substantially coincide the end timing of application of the first voltage pulse to the first electrode with the end timing of application of the second voltage pulse to the second electrode in the second mode.

10. The plasma processing apparatus according to claim 8, wherein the pulse control unit is configured to: in a third mode applied when wear of the edge ring is more advanced than the state of the edge ring in the second mode, set the start time difference to substantially zero, and increase the absolute value of the voltage level of the second voltage pulse in accordance with an increase in the amount of wear of the edge ring; and delay the timing at which the electrode of the second DC power supply to which the second electrode is connected in the third mode is switched from the negative pole of the second DC power supply to the positive pole of the second DC power supply relative to the timing at which the electrode of the second DC power supply to which the second electrode is connected is switched from the negative pole of the second DC power supply to the positive pole of the second DC power supply in the first mode and the second mode.

11. A plasma processing apparatus according to any one of claims 2 to 5, wherein the pulse control unit is configured to set the start time difference to a time difference in which the second start timing precedes the first start timing.

12. A plasma processing apparatus as described in any one of claims 2 to 5, wherein the pulse control unit is configured to set the start time difference to substantially zero, and to set the timing at which the difference between the voltage level of the first voltage pulse at the first electrode and the voltage level of the second voltage pulse at the second electrode becomes zero to a timing before the end timing of application of the second voltage pulse at the second electrode or a timing substantially the same as the end timing.

13. A plasma processing apparatus comprising: a first DC power supply; and a first switching circuit configured to alternately connect a negative pole and a positive pole of the first DC power supply to a first electrode to periodically apply a first voltage pulse to the first electrode, in order to attract ions from a plasma in a chamber of the plasma processing apparatus to a substrate placed on a substrate support surface of a substrate support member disposed in the chamber, the first electrode being disposed within the substrate support member and below the substrate support surface and electrically coupled to the substrate on the substrate support surface; a second DC power supply; and a second switching circuit configured to alternately connect a negative pole and a positive pole of the second DC power supply to a second electrode to periodically apply a second voltage pulse to the second electrode, in order to attract ions from the plasma to an edge ring placed on a ring support surface of the substrate support member, the second electrode being disposed within the substrate support member and below the ring support surface and electrically coupled to the edge ring on the ring support surface; a pulse control unit configured to control the first switching circuit and the second switching circuit to temporally overlap an application period of the first voltage pulse and an application period of the second voltage pulse, and to variably adjust a start time difference, which is a time difference between a first start timing of application of the first voltage pulse at the first electrode and a second start timing of application of the second voltage pulse at the second electrode, within a range between a time difference at which the second start timing precedes the first start timing and zero.

14. The bias power supply system of claim 13, wherein the first switching circuit includes: a first switching element having a control terminal connected to the pulse control unit, and electrically connected between the first electrode and the negative electrode of the first DC power supply; a second switching element having a control terminal connected to the pulse control unit, and electrically connected between the first electrode and each of the first switching elements and the positive electrode of the first DC power supply; and the second switching circuit includes: a third switching element having a control terminal connected to the pulse control unit, and electrically connected between the second electrode and the negative electrode of the second DC power supply; and a fourth switching element having a control terminal connected to the pulse control unit, and electrically connected between the second electrode and each of the third switching elements and the positive electrode of the second DC power supply.

15. The bias power supply system of claim 14, wherein the positive pole of the second DC power supply is electrically connected to an output for the first voltage pulse of the first switching circuit.

16. The bias power supply system of claim 15, wherein the positive terminal of the first DC power supply is connected to ground.

17. (a) preparing a substrate, the substrate being disposed on a substrate support surface of a substrate support disposed in a chamber of a plasma processing apparatus and within a region surrounded by an edge ring on a ring support surface of the substrate support; (b) generating plasma in the chamber; (c) periodically applying a first voltage pulse to a first electrode to attract ions into the substrate, the first electrode being disposed within the substrate support and below the substrate support surface and electrically coupled to the substrate on the substrate support surface; (d) applying a second voltage pulse to a second electrode such that application of the first voltage pulse and application of the second voltage pulse in (c) overlap in time to attract ions into the edge ring, the second electrode being disposed within the substrate support and below the ring support surface and electrically coupled to the edge ring on the ring support surface; (e) adjusting, in accordance with an amount of wear of the edge ring, a start time difference between a first start timing of application of the first voltage pulse to the first electrode in (c) and a second start timing of application of the second voltage pulse to the second electrode in (d), within a range between a time difference by which the second start timing precedes the first start timing and zero.

18. The plasma processing method of claim 17, wherein (e) includes, in a first mode, setting the start time difference to a time difference in which the second start timing precedes the first start timing, and increasing the absolute value of the voltage level of the second voltage pulse of (d) in accordance with an increase in the amount of wear of the edge ring.

19. The plasma processing method according to claim 18, wherein (e) includes, in the first mode, substantially matching the end timing of the application of the first voltage pulse to the first electrode with the end timing of the application of the second voltage pulse to the second electrode.

20. The plasma processing method of claim 18, wherein (e) includes, in a second mode applied when wear of the edge ring is more advanced than the state of the edge ring in the first mode, setting the start time difference to substantially zero and increasing the absolute value of the voltage level of the second voltage pulse in accordance with an increase in the amount of wear of the edge ring.

21. The plasma processing method according to claim 20, wherein (e) includes, in the second mode, substantially matching the end timing of the application of the first voltage pulse to the first electrode with the end timing of the application of the second voltage pulse to the second electrode.

22. The plasma processing method according to claim 20 or 21, wherein (e) includes, in a third mode applied when wear of the edge ring is more advanced than the state of the edge ring in the second mode, setting the start time difference to substantially zero, and increasing the absolute value of the voltage level of the second voltage pulse in accordance with an increase in the amount of wear of the edge ring, and extending a period during which a difference occurs between the voltage level of the first voltage pulse and the voltage level of the second voltage pulse with respect to the first mode and the second mode.

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