Preparation method for semiconductor chip, and wafer structure and semiconductor chip

Abstract

A preparation method for a semiconductor chip with backside metallization, and a semiconductor chip, which are applied to the technical field of semiconductor device preparation. The method comprises: providing, on the front surface of a wafer, functional structures corresponding to individual chips, wherein a front dicing lane is provided between the functional structures of adjacent chips; thinning the back surface of the wafer where the functional structures are provided; on the basis of the thinned back surface of the wafer, locating the functional structures; on the basis of the located positions, providing a backside metallization array on the back surface of the wafer, wherein the backside metallization array comprises a plurality of backside metallization modules, a back dicing lane is formed between adjacent backside metallization modules, and the back dicing lanes and the front dicing lanes are mutually aligned; and dicing the wafer on the basis of the front dicing lanes and the back dicing lanes, so as to prepare semiconductor chips. A back metallization array is provided on the back surface of a wafer by means of a patterning process, such that back dicing lanes and front dicing lanes are aligned with each other; thus, there is no need to dice backside metal, and high-quality semiconductor chips with backside metallization are thus prepared.

Description

Semiconductor chip preparation method, wafer structure and semiconductor chip

[0001] This application claims priority to the Chinese patent application filed with the Patent Office of China on March 19, 2024, with application number 202410315997.3 and invention name “A method for preparing a semiconductor chip, a wafer structure and a semiconductor chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present invention relates to the technical field of semiconductor device preparation, and in particular to a method for preparing a semiconductor chip with a gold back, a wafer structure, and a semiconductor chip with a gold back. Background Art

[0003] Back-gold deposition is a process that deposits metal on the backside of a wafer. Currently, many semiconductor chips require a metal backside as a grounding layer. For thick back-gold products, a layer of 15μm to 30μm thick, primarily copper, is deposited on the backside of the wafer to achieve this desired effect.

[0004] However, for products with thick back-gold, the products formed after slicing the wafer may suffer from back-gold delamination, hidden silicon cracks on the back of the chip, and severe back-gold curling. Therefore, how to provide a method for preparing semiconductor chips with high-quality back-gold is an urgent problem for those skilled in the art.

[0005] Summary of the Invention

[0006] The object of the present invention is to provide a method for preparing a semiconductor chip with back gold, which can produce high-quality semiconductor chips with back gold; another object of the present invention is to provide a wafer structure and a semiconductor chip with back gold, which have higher quality.

[0007] To solve the above technical problems, the present invention provides a method for preparing a semiconductor chip with a back-gold coating, comprising:

[0008] Functional structures corresponding to each chip are arranged on the front side of the wafer; front dicing lanes are provided between the functional structures of adjacent chips;

[0009] thinning the back side of the wafer provided with the functional structure;

[0010] Positioning the functional structure based on the thinned back side of the wafer;

[0011] A back-gold array is provided on the back side of the wafer based on the positioning position; the back-gold array includes a plurality of back-gold modules, and back-side cutting paths are formed between adjacent back-gold modules, and the back-side cutting paths are aligned with the front-side cutting paths;

[0012] The wafer is cut based on the front scribe lines and the back scribe lines to produce the semiconductor chips.

[0013] Optionally, before thinning the back side of the wafer provided with the functional structure, the method further includes:

[0014] The front side of the wafer is packaged.

[0015] Optionally, after packaging the front side of the wafer, the process further includes:

[0016] A substrate is bonded to the front side of the wafer.

[0017] Optionally, providing a back-gold array on the back side of the wafer based on the positioning position includes:

[0018] providing a seed layer on the back side of the wafer;

[0019] Based on the positioned position, an isolation layer corresponding to the backside cutting path is provided on the surface of the seed layer;

[0020] Plate a back-gold module on the area of ​​the seed layer surface not shielded by the isolation layer to form a back-gold array;

[0021] After forming the back gold array, the isolation layer is removed to expose the backside cutting lanes.

[0022] Optionally, based on the positioning position, providing an isolation layer corresponding to the backside cutting line on the surface of the seed layer includes:

[0023] Based on the positioned position, a photoresist layer corresponding to the backside scribing line is provided on the surface of the seed layer;

[0024] The step of removing the isolation layer after forming the back-gold array comprises:

[0025] After the gold back array is formed, the photoresist layer is removed by wet stripping.

[0026] Optionally, the thickness of the gold-backed module is not less than 5 μm.

[0027] Optionally, before thinning the back side of the wafer provided with the functional structure, the method further includes:

[0028] An alignment point of a preset depth is etched in a non-functional area on the front side of the wafer; the distance between the bottom surface of the alignment point and the back side of the wafer is less than the thinning thickness of the back side of the wafer; the position of the functional structure is aligned with the position of the alignment point;

[0029] Thinning the back side of the wafer provided with the functional structure includes:

[0030] thinning the back side of the wafer provided with the functional structure to expose the alignment points on the back side of the wafer;

[0031] Positioning the functional structure based on the thinned back side of the wafer includes:

[0032] The functional structure is positioned based on the exposed alignment sites.

[0033] Optionally, etching alignment points of a preset depth on the front side of the wafer includes:

[0034] Setting photoresist on the front side of the wafer and exposing it to expose the preset alignment point position;

[0035] An alignment point of a preset depth is etched at the alignment point position on the front side of the wafer by a plasma etching process.

[0036] Optionally, positioning the functional structure based on the thinned back side of the wafer includes:

[0037] Infrared rays are emitted from the back side of the thinned wafer, and the functional structure is positioned through the thinned wafer based on infrared ray detection.

[0038] The present invention also provides a wafer structure, wherein the front surface of the wafer is provided with functional structures corresponding to respective chips; and a front cutting path is provided between the functional structures of adjacent chips;

[0039] A back-gold array is provided on the back side of the wafer; the back-gold array includes a plurality of back-gold modules, and back-side cutting paths are formed between adjacent back-gold modules, and the back-side cutting paths are aligned with the front-side cutting paths.

[0040] Optionally, the non-functional area of ​​the wafer is provided with an alignment point extending from the front side to the back side, and the distance between the bottom surface of the alignment point and the initial back side of the wafer is less than the thinning thickness of the back side of the wafer; the front cutting road and the alignment point are aligned with each other, and the back cutting road and the alignment point are aligned with each other.

[0041] Optionally, the wafer is provided with a plurality of alignment points.

[0042] The present invention also provides a semiconductor chip with back gold, including a substrate, a functional structure and a back gold module separated from a wafer, the functional structure and the back gold module are aligned with each other, and when cutting the wafer, the cutting is performed based on the mutually aligned front cutting path and the back cutting path, and the front cutting path and the back cutting path are aligned with each other.

[0043] Optionally, a step structure is formed between an edge of the back-gold module and an edge of the substrate, and the step structure is a step structure formed by cutting the wafer based on the back-side cutting path.

[0044] The present invention provides a method for preparing a semiconductor chip with back gold, comprising: arranging functional structures corresponding to respective chips on the front side of a wafer; providing front cutting paths between the functional structures of adjacent chips; thinning the back side of the wafer provided with the functional structures; positioning the functional structures based on the thinned back side of the wafer; arranging a back gold array on the back side of the wafer based on the positioned positions; the back gold array comprising a plurality of back gold modules, with back cutting paths formed between adjacent back gold modules, the back cutting paths and the front cutting paths being aligned with each other; and cutting the wafer based on the front cutting paths and the back cutting paths to produce semiconductor chips.

[0045] When applying back-metal, a patterning process creates a back-metal array on the backside of the wafer. The back-metal modules in this array correspond to the back-metal on the backsides of each chip after dicing. Back-metal scribe lines are formed between the modules. By aligning the functional structures on the front side of the wafer from the backside, the back-metal scribe lines can be aligned with the front-metal scribe lines. This eliminates the need to cut the back-metal when the wafers are finally separated along the scribe lines, resulting in high-quality semiconductor chips with back-metal.

[0046] The present invention also provides a wafer structure and a semiconductor chip with back-gold coating, which also have the above-mentioned beneficial effects and will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] 1 to 5 are process flow charts of a method for preparing a semiconductor chip with a gold back surface provided by an embodiment of the present invention;

[0049] 6 to 12 are process flow charts of a first specific method for preparing a semiconductor chip with a gold back surface provided by an embodiment of the present invention;

[0050] 13 to 15 are process flow charts of a second specific method for preparing a semiconductor chip with a gold back surface provided by an embodiment of the present invention;

[0051] FIG16 is a process flow chart of a third specific method for preparing a semiconductor chip with a gold back surface provided by an embodiment of the present invention.

[0052] In the figure: 1. Wafer, 2. Functional structure, 21. Front cutting line, 3. Back-gold array, 31. Back-gold module, 32. Back cutting line, 4. Packaging layer, 5. Substrate, 6. Seed layer, 7. Isolation layer, 8. Alignment point. DETAILED DESCRIPTION

[0053] The core of the present invention is a method for preparing semiconductor chips with back-gold coatings. In the prior art, a full layer of back-gold coating is typically applied to the back of a wafer, typically with a thickness of 15 to 30 μm. This back-gold coating is not partitioned, requiring the back-gold coating to be cut when the wafer is diced.

[0054] Current packaging processes utilize two cutting methods. The first utilizes traditional mechanical cutting, using a diamond-grained blade to cut silicon and thick back-metallic components. This method relies solely on physical friction, generating significant stress and heat during the cutting process, leading to back-metallic delamination, hidden cracks in the silicon on the back of the chip, and severe back-metallic edge curling.

[0055] The second method uses laser cutting, but laser cutting has a significant thermal effect and can cause metal buildup on the chip sidewalls. The current mature process is to cut back-metal layers below 30µm. Laser cutting efficiency and quality deteriorate beyond 30µm.

[0056] The present invention provides a method for preparing a semiconductor chip with back gold, which includes: arranging functional structures corresponding to each chip on the front side of a wafer; having a front cutting path between the functional structures of adjacent chips; thinning the back side of the wafer provided with the functional structure; positioning the functional structure based on the thinned back side of the wafer; arranging a back gold array on the back side of the wafer based on the positioned position; the back gold array includes multiple back gold modules, back cutting paths are formed between adjacent back gold modules, and the back cutting paths and the front cutting paths are aligned with each other; cutting the wafer based on the front cutting paths and the back cutting paths to form a semiconductor chip.

[0057] When applying back-metal, a patterning process creates a back-metal array on the backside of the wafer. The back-metal modules in this array correspond to the back-metal on the backsides of each chip after dicing. Back-metal scribe lines are formed between the modules. By aligning the functional structures on the front side of the wafer from the backside, the back-metal scribe lines can be aligned with the front-metal scribe lines. This eliminates the need to cut the back-metal when the wafers are finally separated along the scribe lines, resulting in high-quality semiconductor chips with back-metal.

[0058] In order to enable those skilled in the art to better understand the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0059] Please refer to FIG. 1 to FIG. 5 , which are process flow charts of a method for preparing a semiconductor chip with a gold back surface provided by an embodiment of the present invention.

[0060] 1 , in an embodiment of the present invention, a method for preparing a semiconductor chip with a gold back surface includes:

[0061] S101: Arrange functional structures corresponding to each chip on the front side of the wafer.

[0062] Referring to Figure 2, in an embodiment of the present invention, there is a front cutting road 21 between the functional structures 2 of adjacent chips. The specific content of the above-mentioned functional structure 2 can be set according to actual conditions and is not specifically limited here. It can be a HEMT (high electron mobility transistor) structure, an infrared detection structure, etc. The functional structure 2 is specifically arranged on the front side of the wafer 1. Usually, the entire wafer 1 will be divided into multiple chips, and each chip surface has a functional structure 2, so that what is specifically prepared on the front side of the wafer 1 is a functional structure array, and a front cutting road 21 is set between adjacent functional structures 2. The so-called cutting road is the position where the wafer 1 is cut when the wafer 1 is divided. Usually, there is no film layer or only a small amount of film layer is set in the cutting road of the wafer 1 to facilitate cutting the wafer 1 from the cutting road. The above-mentioned cutting road set on the front side of the wafer 1 is the front cutting road 21, and the front cutting road 21 usually forms a mesh-like structural distribution.

[0063] This step usually corresponds to the FAB (semiconductor manufacturing) process, and its specific content needs to be set according to actual conditions and is not specifically limited here.

[0064] S102: Thinning the back side of the wafer provided with the functional structure.

[0065] Referring to FIG3 , after the above-mentioned FAB process is performed, the back side of the wafer 1 is thinned in this step to reduce the overall thickness of the wafer 1 from the back side of the wafer 1, so as to facilitate alignment in subsequent steps. The specific process of thinning the wafer 1 can be referred to the prior art and will not be described in detail here. It should be noted that in this embodiment, the subsequent steps of achieving alignment of the front and back side structures of the wafer 1 need to be implemented on the basis of thinning the wafer 1 in this step.

[0066] S103: Positioning the functional structure based on the thinned back side of the wafer.

[0067] This step specifically requires positioning the structure provided on the front side of the wafer 1 from the back side of the wafer 1 based on the thinned wafer 1. The positioning process will be described in detail in the following embodiments of the invention and will not be described in detail here.

[0068] S104: Setting a back-gold array on the back side of the wafer based on the positioned position.

[0069] Referring to Figure 4, in this embodiment, the back gold array 3 includes a plurality of back gold modules 31, and a back cutting path 32 is formed between adjacent back gold modules 31, and the back cutting path 32 is aligned with the front cutting path 21. The specific preparation process for the back gold array 3 will be described in detail in the following invention embodiments and will not be described in detail here. The back gold array 3 is equivalent to the patterned back gold, and the thickness of the back gold module 31 is usually not less than 5μm, and can specifically be 15μm, 30μm, 50 microns, etc. Of course, in this embodiment, the thickness of the back gold module 31 is not specifically limited, and the preparation method provided in this embodiment is applicable to a technical solution with any back gold thickness.

[0070] The above-mentioned back-gold array 3 includes a plurality of back-gold modules 31, and the back-gold module 31 will be located on the back of the chip as a back-gold structure after the wafer 1 is divided to form a chip. A cutting path located on the back of the wafer 1 is formed between the above-mentioned back-gold modules 31, namely a back-gold cutting path 32. The back-gold cutting path 32 is aligned with the above-mentioned front-gold cutting path 21, which specifically needs to be achieved on the basis of positioning the functional structure 2 set on the front of the wafer 1 from the back in S103. On the basis of achieving the front and back alignment of the wafer 1, the functional structure 2 on the front of the wafer 1 and the back-gold array 3 on the back of the wafer 1 can be aligned with each other. Since the above-mentioned back-gold cutting path 32 and the front-gold cutting path 21 are aligned with each other, when cutting the wafer 1, the wafer 1 can be directly cut based on the front-gold cutting path 21 and the back-gold cutting path 32 without cutting the back-gold, so as to ensure the quality of the chip.

[0071] It should be emphasized that the backside photomask used to prepare the gold backside array 3 is the same as the layout of the wafer when it is flipped 180° in its normal state, with the backside facing up. In other words, the backside photomask design needs to be flipped 180° to achieve the front and back side alignment of the wafer 1.

[0072] S105: Cutting the wafer based on the front scribe lines and the back scribe lines to produce semiconductor chips.

[0073] Referring to Figure 5, in this step, the wafer 1 will be cut along the front cutting path 21 and the back cutting path 32. The specific cutting process can be performed by using a traditional diamond particle knife to cut along the cutting path, or by using laser cutting to cut along the cutting path, or by using other methods, such as half cutting, etc. The specific content can be referred to the existing technology and will not be described in detail here. It should be noted that before cutting the wafer 1, it is usually necessary to peel off the substrate 5 and then cut the wafer 1.

[0074] An embodiment of the present invention provides a method for preparing semiconductor chips with back-gold coatings. When applying the back-gold coating, a back-gold coating array 3 is formed on the back side of a wafer 1 through a patterning process. The back-gold coating modules 31 in the back-gold coating array 3 correspond to the back-gold coating on the back sides of each chip after dicing. Back-gold coating streets 32 are formed between the back-gold coating modules 31. By positioning the functional structures 2 provided on the front side of the wafer 1 from the back side, the back-gold coating streets 32 and the front-gold coating streets 21 are aligned with each other. This eliminates the need to cut the back-gold coating when the wafer 1 is finally separated along the coating streets, thereby producing high-quality semiconductor chips with back-gold coatings.

[0075] The specific content of the method for preparing a semiconductor chip with a gold back surface provided by the present invention will be described in detail in the following invention embodiments.

[0076] Please refer to FIG. 6 to FIG. 12 , which are process flow charts of a first specific method for preparing a semiconductor chip with a gold-backed substrate provided by an embodiment of the present invention.

[0077] 6 , in an embodiment of the present invention, a method for preparing a semiconductor chip with a back-gold coating includes:

[0078] S201: Arrange functional structures corresponding to each chip on the front side of the wafer.

[0079] This step is basically the same as S101 in the above-mentioned embodiment of the invention. Please refer to the above-mentioned embodiment of the invention for details, and will not be described again here.

[0080] S202: packaging the front side of the wafer.

[0081] Referring to Figure 7, the packaging layer 4 formed by the packaging can protect the above-mentioned functional structure 2. In this step, the front side of the wafer 1 can be packaged specifically through the wafer-level advanced packaging process. Part of the process of the wafer-level advanced packaging usually includes: filling PI (polyimide) glue on the front side of the wafer 1; immersing gold on the front side of the wafer 1 based on the ENIG (chemical nickel-gold plating) process. The PI glue is a material composed of polyimide resin and filler. In this step, the non-metallic structure in the functional structure 2 is usually covered with PI glue first, and then the metal nickel and metal mixture are electroplated to the metal structure on the front side of the wafer 1 through the ENIG (chemical nickel-gold plating) process to form the packaging layer 4. For the specific content of PI (polyimide) glue and ENIG (chemical nickel-gold plating) process, please refer to the existing technology and will not be repeated here.

[0082] S203: Bonding a substrate to the front side of the wafer.

[0083] Referring to Figure 8 , in this step, a substrate 5 is bonded to the front side of the packaged wafer 1. This substrate 5 can be used to provide support for the wafer 1 during subsequent thinning of the back side of the wafer 1. The specific material and thickness of the substrate 5 can be determined based on actual conditions and are not specifically limited here. The above bonding process can be achieved through direct bonding or bonding via an adhesive layer such as solder, both of which are not specifically limited here.

[0084] S204: Thinning the back side of the wafer provided with the functional structure.

[0085] S205: Positioning the functional structure based on the thinned back side of the wafer.

[0086] The above S204 to S205 are basically the same as S102 to S103 in the above invention embodiment. Please refer to the above invention embodiment for details, and no further details will be given here.

[0087] S206: Setting a seed layer on the back side of the wafer.

[0088] Referring to FIG9 , in this step, a full layer of seed layer 6 is specifically provided on the back side of the wafer 1, so that the back-gold module 31 is subsequently electroplated based on this seed layer 6. Since the thickness of the seed layer 6 is generally very thin, even if a full layer is provided on the back side of the wafer 1, the seed layer 6 will be cut during subsequent cutting without affecting the morphology of the edge of the final chip. The material of the seed layer 6 needs to correspond to the material of the back-gold array 3, and is not specifically limited here.

[0089] S207: Based on the positioned position, an isolation layer corresponding to the backside cutting line is provided on the surface of the seed layer.

[0090] Referring to FIG10 , based on the positioning of the functional structure 2 from the back, an isolation layer 7 corresponding to the backside cut street 32 ​​is provided on the surface of the seed layer 6 in this step. Obviously, the isolation layer 7 is a patterned isolation layer 7, and the isolation layer 7 is generally distributed in a mesh pattern. Specifically, in this step, a photoresist can be used as the isolation layer 7. Accordingly, this step can specifically include: based on the positioning position, providing a photoresist layer corresponding to the backside cut street 32 ​​on the surface of the seed layer 6. Specifically, the photoresist can be exposed and developed to provide a photoresist layer that only covers the area where the backside cut street 32 ​​is located.

[0091] S208: Plating a back-gold module on the surface of the seed layer in the area not shielded by the isolation layer to form a back-gold array.

[0092] Referring to Figure 11, due to the setting of the above-mentioned isolation layer 7, back gold will not be electroplated in the area shielded by the isolation layer 7 during the electroplating process, that is, the back gold module 31 will not be plated at the position of the seed layer 6 corresponding to the above-mentioned back cutting road 32, but the back gold module 31 will only be formed in the area not shielded by the isolation layer 7, and at the same time, the back gold cutting road 32 will be formed between the back gold modules 31 to finally form the above-mentioned back gold array 3.

[0093] S209: After forming the back gold array, the isolation layer is removed to expose the back cutting path.

[0094] Referring to FIG12 , in this step, the isolation layer 7 needs to be removed to expose the backside cut lanes 32. Specifically, when a photoresist layer is used as the isolation layer 7, this step may specifically include: after forming the backside gold array 3, removing the photoresist layer by wet stripping. By removing the photoresist layer by the stripping process, the backside cut lanes 32 can be exposed. Of course, depending on the material of the isolation layer 7, this step may also be performed by other methods to remove the isolation layer 7, which is not specifically limited here.

[0095] S210: Cutting the wafer based on the front scribe lines and the back scribe lines to produce semiconductor chips.

[0096] This step is basically the same as S105 in the above-mentioned embodiment of the invention. Please refer to the above-mentioned embodiment of the invention for details, and no further details will be given here.

[0097] An embodiment of the present invention provides a method for preparing semiconductor chips with back-gold coatings. When applying the back-gold coating, a back-gold coating array 3 is formed on the back side of a wafer 1 through a patterning process. The back-gold coating modules 31 in the back-gold coating array 3 correspond to the back-gold coating on the back sides of each chip after dicing. Back-gold coating streets 32 are formed between the back-gold coating modules 31. By positioning the functional structures 2 provided on the front side of the wafer 1 from the back side, the back-gold coating streets 32 and the front-gold coating streets 21 are aligned with each other. This eliminates the need to cut the back-gold coating when the wafer 1 is finally separated along the coating streets, thereby producing high-quality semiconductor chips with back-gold coatings.

[0098] The specific content of the method for preparing a semiconductor chip with a gold back surface provided by the present invention will be described in detail in the following invention embodiments.

[0099] Please refer to FIG. 13 to FIG. 15 , which are process flow charts of a second specific method for preparing a semiconductor chip with a gold-backed surface provided by an embodiment of the present invention.

[0100] 13 , in an embodiment of the present invention, a method for preparing a semiconductor chip with a gold back surface includes:

[0101] S301: Arrange functional structures corresponding to each chip on the front side of the wafer.

[0102] S302: Thinning the back side of the wafer provided with the functional structure.

[0103] The above steps S301 to S302 are substantially identical to the steps S101 to S102 in the above-mentioned embodiment of the invention. For details, please refer to the above-mentioned embodiment of the invention and will not be described in detail here. In this embodiment, the front surface of the wafer 1 is divided into a functional area and a non-functional area. The functional area is an area used to form various functional structures required for semiconductor devices such as chips or discrete devices, i.e., an area subsequently used for patterning. The non-functional area is an area such as a saw path, a PCM (process control monitor) area, etc. that does not affect the function of the semiconductor device, i.e., an area that does not require patterning.

[0104] S303: etching an alignment point of a preset depth in a non-functional area on the front side of the wafer.

[0105] Referring to Figure 14, in an embodiment of the present invention, the alignment point is specifically set in the non-functional area, and the distance between the bottom surface of the alignment point 8 and the back side of the wafer 1 is less than the thinning thickness of the back side of the wafer 1; the position of the functional structure 2 and the position of the alignment point 8 are aligned with each other.

[0106] This step is specifically performed after the functional structure 2 is prepared on the front side of the wafer 1, that is, after the FAB (semiconductor manufacturing) process is completed. This step will etch a preset depth of alignment point 8 on the front side of the wafer 1. First, the alignment point 8 will be exposed on the front side of the wafer 1. Secondly, the alignment point 8 needs to have a certain depth so that the distance between the bottom surface of the alignment point 8 and the back side of the wafer 1 that has not been thinned at this time is less than the thinning thickness of the back side of the wafer 1. That is, it is necessary to ensure that the alignment point 8 can be exposed after the back side of the wafer 1 is thinned.

[0107] After the alignment point 8 is set, the entire functional structure 2 and the position of the alignment point 8 will have a fixed corresponding relationship. At this time, the position of the functional structure 2 will be aligned with the position of the alignment point 8.

[0108] Specifically, in this embodiment, two alignment points 8 are typically provided on a wafer 1. Therefore, this step may specifically include etching two alignment points 8 of a predetermined depth on the front surface of the wafer 1 where the functional structure 2 is provided. A line can be formed between the two alignment points 8. Compared to providing only one alignment point 8, the line formed by the two alignment points 8 can more accurately reflect information such as the position and orientation of the functional structure 2, thereby enabling more accurate alignment of the back-metal array 3 with the functional structure 2.

[0109] Obviously, in this embodiment, the farther the distance between the two alignment points 8, that is, the longer the distance between the two alignment points 8, the more accurate the position information reflected by the connecting line is, and the higher the precision is. Therefore, in this embodiment, it is usually necessary to ensure that the distance between the two alignment points 8 is not less than the radius of the wafer 1 to ensure the alignment accuracy. Of course, in this embodiment, only one alignment point 8 or more alignment points 8 can be set. The more alignment points 8 are set, the higher the alignment accuracy is, but it will occupy more area of ​​the wafer 1 and increase the preparation cost.

[0110] In this embodiment, the shape of the alignment point 8 is generally not specifically limited. The alignment point 8 can be circular, rectangular, cross-shaped, or any polygonal shape. The alignment point 8 is set at a predetermined position, for example, the alignment point 8 is specifically set in the front cutting path 21 to prevent the alignment point 8 from damaging the functional structure 2.

[0111] Typically, this step specifically includes: setting a photoresist on the front side of the wafer 1 and exposing it to expose the preset alignment point 8 position; etching the alignment point 8 at a preset depth at the alignment point 8 position on the front side of the wafer 1 through a plasma etching process.

[0112] The specific type of photoresist and the specific morphology of the photoresist layer formed in this embodiment can be determined based on actual conditions and are not specifically limited here. In this embodiment, the alignment points 8 are etched on the front surface of the wafer 1 using a dry etching process, specifically a plasma etching process. Compared to wet etching, dry etching has a stronger anisotropy, allowing alignment points 8 to be etched in a very small area to meet the depth requirements, thereby avoiding extensive damage to the functional structures 2 already provided on the front surface of the wafer 1.

[0113] It should also be noted that when packaging is required on the front side of the wafer 1 , the alignment point 8 will be set after the functional structure 2 is set and before packaging.

[0114] S304: thinning the back side of the wafer provided with the functional structure to expose alignment points on the back side of the wafer.

[0115] 15 , since the distance between the bottom surface of the alignment point 8 and the back surface of the wafer 1 before thinning is less than the thinning thickness of the back surface of the wafer 1 in the above step, the alignment point 8 can be exposed on the back surface of the wafer 1 after this step.

[0116] S305: Positioning the functional structure based on the exposed alignment sites.

[0117] Since the position of the alignment point 8 is fixed, and the position of the functional structure 2 is aligned with the position of the alignment point 8, the functional structure 2 on the front side of the wafer 1 can be positioned based on the alignment point 8 exposed from the back side of the wafer 1, and finally the alignment of the functional structure 2 on the front and back sides of the wafer 1 can be achieved.

[0118] S306: Setting a back-gold array on the back side of the wafer based on the positioned position.

[0119] S307: Cutting the wafer based on the front scribe lines and the back scribe lines to produce semiconductor chips.

[0120] The above S306 to S307 are basically the same as S104 to S105 in the above invention embodiment. Please refer to the above invention embodiment for details, and no further details will be given here.

[0121] An embodiment of the present invention provides a method for preparing a semiconductor chip with back gold. By setting an alignment point 8, after the wafer 1 is thinned, the functional structure 2 on the front side of the wafer 1 can be positioned on the back side of the wafer 1, so that a back gold array 3 aligned with the functional structure 2 can be prepared when the back gold is set. As a result, when the wafer 1 is finally separated along the cutting path, the back gold does not need to be cut, thereby producing a high-quality semiconductor chip with back gold.

[0122] The specific content of the method for preparing a semiconductor chip with a gold back surface provided by the present invention will be described in detail in the following invention embodiments.

[0123] Please refer to FIG. 16 , which is a process flow chart of a third specific method for preparing a semiconductor chip with a gold-backed surface provided by an embodiment of the present invention.

[0124] 16 , in an embodiment of the present invention, a method for preparing a semiconductor chip with a gold back surface includes:

[0125] S401: Arrange functional structures corresponding to each chip on the front side of the wafer.

[0126] S402: Thinning the back side of the wafer provided with the functional structure.

[0127] The above S401 to S402 are basically the same as S101 to S102 in the above invention embodiment. Please refer to the above invention embodiment for details, and no further details will be given here.

[0128] S403: Emitting infrared rays from the back side of the thinned wafer, and locating the functional structure through the thinned wafer based on infrared detection.

[0129] In this step, infrared light is scanned from the back of the wafer 1. Since the wafer 1 is thin after thinning, infrared light can penetrate the wafer 1 and scan the functional structure 2 provided on the front of the wafer 1. Therefore, in this step, infrared light is emitted from the back of the thinned wafer 1 to locate the functional structure 2 through the thinned wafer 1.

[0130] S404: Setting a back-gold array on the back side of the wafer based on the positioned position.

[0131] S405: Cutting the wafer based on the front scribe lines and the back scribe lines to produce semiconductor chips.

[0132] The above S401 to S402 are basically the same as S101 to S102 in the above invention embodiment. Please refer to the above invention embodiment for details, and no further details will be given here.

[0133] A method for preparing a semiconductor chip with back gold provided by an embodiment of the present invention can, through infrared detection, locate the functional structure 2 on the front side of the wafer 1 directly through the back side through the wafer 1 after thinning the wafer 1, so that a back gold array 3 aligned with the functional structure 2 can be prepared when setting the back gold, so that when the wafer 1 is finally separated along the cutting path, the back gold does not need to be cut, thereby producing a high-quality semiconductor chip with back gold.

[0134] The present invention also provides a wafer structure, in which the front side of the wafer 1 is provided with functional structures 2 corresponding to each chip; a front cutting path 21 is provided between the functional structures 2 of adjacent chips; a back gold array 3 is provided on the back side of the wafer 1; the back gold array 3 includes multiple back gold modules 31, and a back cutting path 32 is formed between adjacent back gold modules 31, and the back cutting path 32 is aligned with the front cutting path 21.

[0135] The wafer structure disclosed in this embodiment is the overall structure of wafer 1 before dicing. Functional structures 2 are provided on the front side of wafer 1, and a back-metal array 3 is provided on the back side of wafer 1. The specific structures of front functional structures 2 and back-metal array 3 have been described in detail in the above-mentioned embodiments of the invention and will not be repeated here.

[0136] Specifically, the front cutting road 21 and the back cutting road 2 in this embodiment can be aligned with each other based on the alignment point 8. At this time, in this embodiment, the non-functional area of ​​the wafer 1 is provided with an alignment point 8 extending from the front to the back, and the distance between the bottom surface of the alignment point 8 and the initial back of the wafer is less than the thinning thickness of the back of the wafer 1; the front cutting road 21 and the alignment point 8 are aligned with each other, and the back cutting road 32 and the alignment point 8 are aligned with each other.

[0137] The initial back side of the wafer mentioned above is the back surface before the back side of the wafer 1 is thinned, that is, the opening of the alignment point 8 on the back side of the wafer 1 can be exposed by thinning the back side of the wafer 1. For the specific content of the alignment point 8, please refer to the above-mentioned invention embodiment and will not be repeated here. In this embodiment, the front cutting road 21 can be aligned with the alignment point 8, and the back cutting road 32 can also be aligned with the alignment point 8, that is, the front cutting road 21 and the back cutting road 32 are aligned with each other through the same alignment point 8. Specifically, a plurality of the above-mentioned alignment points 8 can be provided in the wafer 1 to improve the alignment accuracy between the front cutting road 21 and the back cutting road 32.

[0138] The present invention provides a wafer structure that, when applying back-gold, employs a patterning process to form a back-gold array 3 on the back side of the wafer. Back-gold modules 31 within this array correspond to the back-gold on the back sides of each chip after dicing. Back-gold scribe lines 32 are formed between the back-gold modules 3. By positioning the functional structures 2 provided on the front side of the wafer 1 from the back side, the back-gold scribe lines 32 and the front-gold scribe lines 21 can be aligned. This eliminates the need to further cut the back-gold when the wafer 1 is finally separated along the scribe lines, resulting in high-quality semiconductor chips with back-gold.

[0139] The present invention further provides a semiconductor chip with a gold back, which is specifically a semiconductor chip prepared by the method for preparing a semiconductor chip with a gold back provided by any of the above-mentioned embodiments of the invention.

[0140] Specifically, in this embodiment, the semiconductor chip with back gold includes a substrate, a functional structure 2 and a back gold module 31 separated from a wafer 1. The functional structure 2 and the back gold module 31 are aligned with each other. When cutting the wafer 1, the cutting is performed based on the mutually aligned front cutting road 21 and the back cutting road 32. The front cutting road 21 and the back cutting road 32 are aligned with each other.

[0141] The device structure formed after the semiconductor chip is cut and separated from the wafer 1 disclosed in this embodiment has a functional structure 2 provided on the front side of the substrate and a back-gold module 31 provided on the back side of the substrate, and the functional structure 2 and the back-gold module 31 are aligned with each other. In this embodiment, when cutting the wafer 1, the front cutting path 21 and the back cutting path 32 are cut simultaneously, so the front cutting path 21 and the back cutting path 32 need to be aligned with each other. For the specific content of the functional structure 2 and the back-gold module 31, please refer to the above-mentioned invention embodiment and will not be repeated here.

[0142] Specifically, in this embodiment, a step structure is formed between the edge of the back-gold module 31 and the edge of the substrate. The step structure is formed by cutting the wafer 1 based on the back-side dicing street 32 ​​.

[0143] Since the back-gold modules 31 in this embodiment are patterned back-gold, back-side cutting paths 32 are formed between the back-gold modules 31. Accordingly, when the wafer 1 is divided, the cutting is specifically performed along the back-side cutting paths 32. Obviously, the width of the back-side cutting paths 32 usually needs to be greater than the width of the cutting tool. Therefore, after cutting, a step structure will be formed between the edge of the back-gold module 31 and the edge of the substrate. This step structure is formed because the back-side cutting paths 32 are formed at the same time as the back-gold array 3 is patterned, and the wafer 1 is cut along the back-side cutting paths 32. The back-side cutting paths 32 are specifically aligned with the front-side cutting paths 21 on the front of the wafer 1, that is, aligned with the non-functional area on the front of the wafer 1.

[0144] Similarly, in this embodiment, a step structure is generally formed between the edge of the functional structure 2 and the edge of the substrate. The step structure is formed by cutting the wafer 1 based on the front cutting street 21 formed on the front side of the wafer 1 .

[0145] Because the semiconductor chip with a gold back surface provided by the embodiment of the present invention is manufactured using the above-described preparation method, the semiconductor chip has high quality and is free from problems such as gold back surface delamination, hidden silicon cracks on the back surface of the chip, and severe gold back surface curling. The remaining structure of the semiconductor chip can be referred to in the prior art and will not be described in detail here.

[0146] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0147] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0148] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0149] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0150] The above is a detailed introduction to a method for preparing a semiconductor chip with a gold back, a wafer structure, and a semiconductor chip provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a semiconductor chip with a gold back surface, characterized in that: include: The functional structures corresponding to each chip are set on the front side of the wafer; There are front-side cutting paths between the functional structures of adjacent chips; thinning the back side of the wafer provided with the functional structure; Positioning the functional structure based on the thinned back side of the wafer; Disposing a back-gold array on the back side of the wafer based on the positioned position; The back-gold array includes a plurality of back-gold modules, and back-side cutting paths are formed between adjacent back-gold modules, and the back-side cutting paths are aligned with the front-side cutting paths; The wafer is cut based on the front scribe lines and the back scribe lines to produce the semiconductor chips.

2. The method according to claim 1, characterized in that Before thinning the back side of the wafer provided with the functional structure, the method further includes: The front side of the wafer is packaged.

3. The method according to claim 2, characterized in that After packaging the front side of the wafer, it also includes: A substrate is bonded to the front side of the wafer.

4. The method according to claim 1, wherein Providing a back-gold array on the back side of the wafer based on the positioning position includes: providing a seed layer on the back side of the wafer; Based on the positioned position, an isolation layer corresponding to the backside cutting path is provided on the surface of the seed layer; Plate a back-gold module on the area of ​​the seed layer surface not shielded by the isolation layer to form a back-gold array; After forming the back gold array, the isolation layer is removed to expose the backside cutting lanes.

5. The method according to claim 4, characterized in that Based on the positioning position, providing an isolation layer corresponding to the backside cutting street on the surface of the seed layer includes: Based on the positioned position, a photoresist layer corresponding to the backside scribing line is provided on the surface of the seed layer; The step of removing the isolation layer after forming the back-gold array comprises: After the gold back array is formed, the photoresist layer is removed by wet stripping.

6. The method according to claim 1, characterized in that The thickness of the gold-backed module is not less than 5 μm.

7. The method according to any one of claims 1 to 6, characterized in that Before thinning the back side of the wafer provided with the functional structure, the method further includes: An alignment point of a preset depth is etched in a non-functional area on the front side of the wafer; the distance between the bottom surface of the alignment point and the back side of the wafer is less than the thinning thickness of the back side of the wafer; the position of the functional structure is aligned with the position of the alignment point; Thinning the back side of the wafer provided with the functional structure includes: thinning the back side of the wafer provided with the functional structure to expose the alignment points on the back side of the wafer; Positioning the functional structure based on the thinned back side of the wafer includes: The functional structure is positioned based on the exposed alignment sites.

8. The method according to claim 7, characterized in that The alignment points etched to a predetermined depth on the front side of the wafer include: Setting photoresist on the front side of the wafer and exposing it to expose the preset alignment point position; An alignment point of a preset depth is etched at the alignment point position on the front side of the wafer by a plasma etching process.

9. The method according to any one of claims 1 to 6, characterized in that Positioning the functional structure based on the thinned back side of the wafer includes: Infrared rays are emitted from the back side of the thinned wafer, and the functional structure is positioned through the thinned wafer based on infrared ray detection.

10. A wafer structure, characterized in that: The front side of the wafer is provided with functional structures corresponding to the respective chips; and there are front dicing lanes between the functional structures of adjacent chips; A back-gold array is provided on the back of the wafer; The back-gold array includes a plurality of back-gold modules. Back-side cutting paths are formed between adjacent back-gold modules, and the back-side cutting paths are aligned with the front-side cutting paths.

11. The wafer structure according to claim 10, wherein: The non-functional area of ​​the wafer is provided with an alignment point extending from the front side to the back side, and the distance between the bottom surface of the alignment point and the initial back side of the wafer is less than the thinning thickness of the back side of the wafer; the front cutting road and the alignment point are aligned with each other, and the back cutting road and the alignment point are aligned with each other.

12. The wafer structure according to claim 11, wherein: The wafer is provided with a plurality of alignment points.

13. A semiconductor chip with a gold back, characterized in that: It includes a substrate, a functional structure and a back-gold module separated from a wafer. The functional structure and the back-gold module are aligned with each other. When cutting the wafer, cutting is performed based on the aligned front cutting path and the back cutting path. The front cutting path and the back cutting path are aligned with each other.

14. The semiconductor chip with gold backing according to claim 13, characterized in that: A step structure is formed between an edge of the back-gold module and an edge of the substrate, and the step structure is a step structure formed by cutting the wafer based on the back-side dicing street.

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