Resonator and preparation method therefor, filter, and electronic device

Abstract

The embodiments of the present application relate to the technical field of resonators, and provide a resonator and a preparation method therefor, a filter, and an electronic device, aiming to improve the in-plane yield of the resonator. The resonator comprises: a substrate; a dielectric layer, which is arranged on the substrate, wherein a cavity is formed in the dielectric layer; a piezoelectric layer, which is arranged on the dielectric layer, wherein bonding material is disposed between the dielectric layer and the piezoelectric layer and around the cavity; and a via hole, which passes through the bonding material and the piezoelectric layer and is in communication with the cavity.

Description

Resonator and preparation method thereof, filter, and electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 21, 2024, with application number 202410345005.1 and application name “Resonator and its preparation method, filter, and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of communication technology, and in particular to a resonator and a preparation method thereof, a filter, and an electronic device. Background Art

[0003] With the development of communication technology, the bandwidth of communication channels is increasing, and the frequency of communication bands is also increasing. The filters in current communication systems typically include acoustic wave resonators, such as horizontally-excited bulk acoustic resonators (XBARs), vertically-excited bulk acoustic resonators (YBARs), and film bulk acoustic resonators (FBARs).

[0004] XBARs have high electromechanical coupling and high-frequency capabilities, making them suitable for use in filters in communication bands above 3 GHz. However, XBARs suffer from low yield and high cost. Summary of the Invention

[0005] Embodiments of the present application provide a resonator and a method for manufacturing the same, a filter, and an electronic device, for improving the interface yield of the resonator without sacrificing the performance of the resonator.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a resonator is provided. The resonator includes: a substrate; a dielectric layer disposed on the substrate and having a cavity disposed therein; a piezoelectric layer disposed on the dielectric layer; a bonding material disposed between the dielectric layer and the piezoelectric layer and around the cavity; and a via hole extending through the bonding material and the piezoelectric layer and communicating with the cavity.

[0008] The resonator provided in an embodiment of the present application includes a dielectric layer, a bonding material, and a piezoelectric layer stacked on a substrate. The bonding material covers the dielectric layer, and a portion of the bonding material extends into the dielectric layer to contact the substrate. Therefore, the interface bonded to the piezoelectric layer only includes the bonding material, reducing bonding failures caused by differences in thermal expansion coefficients of different materials and improving the interface yield of the resonator without sacrificing resonator performance.

[0009] In a possible implementation, the resonator further includes a plurality of first electrodes, which are arranged side by side on the piezoelectric layer along the first direction.

[0010] In this embodiment, by applying an alternating voltage of a certain frequency to the first electrodes, an electric field is generated between the multiple first electrodes along the extension direction of the piezoelectric layer. The piezoelectric layer uses the electric field to form a piezoelectric effect, thereby generating conversion between electrical energy and mechanical energy.

[0011] In a possible embodiment, the resonator further includes: a first bus bar and a second bus bar; one of every two adjacent first electrodes among the multiple first electrodes is a first interdigitated electrode, and the other is a second interdigitated electrode; the first interdigitated electrodes and the second interdigitated electrodes are spaced apart in the first direction; multiple first interdigitated electrodes among the multiple first electrodes are connected by the first bus bar, and multiple second interdigitated electrodes among the multiple first electrodes are connected by the second bus bar.

[0012] In this embodiment, the first bus bar can serve as an input terminal, and the second bus bar can serve as an output terminal. For example, an alternating voltage within a certain frequency range can be input to the plurality of first interdigital electrodes via the first bus bar, and the plurality of second interdigital electrodes can output an alternating voltage signal processed by the resonator via the second bus bar.

[0013] In a possible implementation, the bonding material on a side close to the piezoelectric layer includes at least one or a combination of the following: argon, oxide, silicon oxide, silicon dioxide, silicon nitride, and aluminum oxide.

[0014] In a possible implementation, the material of the piezoelectric layer includes at least one or more of the following combinations: lithium niobate, lithium tantalate, lanthanum gallium silicate, gallium nitride, or aluminum nitride.

[0015] In a possible implementation, the thickness of the piezoelectric layer is 50 nm-5 um.

[0016] In one possible embodiment, the height difference of the interface of the bonding material near the piezoelectric layer within 1 mm is less than 30 nm. This can improve the bonding strength and stability between the piezoelectric layer and the bonding material, and improve the device interface yield.

[0017] In a possible implementation manner, the thickness of the substrate is 500-1000 um.

[0018] In a second aspect, a method for preparing a resonator is provided, which includes: forming a dielectric layer on a substrate; covering the dielectric layer with a bonding material and filling the bonding material between the dielectric layers; flattening the bonding material; bonding the piezoelectric layer to the bonding material; forming a via hole passing through the piezoelectric layer and the bonding material, and forming a cavity in the dielectric layer, the formed cavity is filled with bonding material around and connected to the via hole.

[0019] In a possible implementation, planarizing the bonding material includes: performing a first planarization on the bonding material through a first planarization process; and performing a second planarization on the bonding material through a second planarization process, wherein the accuracy of the second planarization process is greater than that of the first planarization process.

[0020] In a possible implementation, the first planarization process is a chemical mechanical polishing process, and the second planarization process is a plasma planarization process.

[0021] In one possible embodiment, forming the dielectric layer includes: forming an insulating layer on a substrate; forming a patterned photoresist layer on the insulating layer; using the patterned photoresist layer as a mask, forming a plurality of grooves penetrating the insulating layer in the insulating layer, and the remaining insulating layer constitutes the dielectric layer.

[0022] In a third aspect, a filter is provided, comprising a plurality of cascaded resonators, wherein at least one of the plurality of resonators is the resonator provided in the first aspect and any possible embodiment thereof.

[0023] In a fourth aspect, an electronic device is provided, comprising: a control circuit; and the filter provided in the third aspect, the filter being electrically connected to the control circuit.

[0024] Among them, the technical effects brought about by any possible implementation of the second to fourth aspects can refer to the technical effects brought about by different implementations of the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic diagram of a partial structure of an electronic device provided in an embodiment of the present application;

[0026] FIG2 is a schematic diagram of a partial structure of an electronic device provided in an embodiment of the present application;

[0027] FIG3 is a schematic diagram of a partial structure of a filter in an electronic device provided in an embodiment of the present application;

[0028] FIG4 is a schematic structural diagram of a resonator provided in an embodiment of the present application;

[0029] FIG5 is a schematic structural diagram of a resonator provided in another embodiment of the present application;

[0030] FIG6 is a schematic diagram of the bonding interface height of a resonator provided in an embodiment of the present application;

[0031] FIG7 is a schematic structural diagram of a resonator provided in another embodiment of the present application;

[0032] FIG8 is a schematic flow chart of a method for preparing a resonator according to an embodiment of the present application;

[0033] 9 to 12 are schematic diagrams of the structure of the resonator provided in the embodiments of the present application at various stages of the preparation process;

[0034] FIG13 is a schematic diagram of wafer interface height during a resonator manufacturing process according to an embodiment of the present application;

[0035] FIG14 is a schematic structural diagram of a resonator during the preparation process provided in an embodiment of the present application;

[0036] FIG15 is a schematic diagram of structural measurement results of a resonator during the preparation process provided by an embodiment of the present application;

[0037] FIG16 is a schematic diagram of a piezoelectric layer of a resonator provided in an embodiment of the present application after bonding;

[0038] FIG17 is a schematic structural diagram of a resonator during the preparation process provided in an embodiment of the present application;

[0039] FIG18 is a top view of a first electrode provided in an embodiment of the present application.

[0040] FIG19 is a schematic structural diagram of a resonator during the preparation process provided in an embodiment of the present application;

[0041] FIG20 is a top view of a resonator provided in an embodiment of the present application;

[0042] FIG21 is a top view of a filter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0044] In the following, the terms "first," "second," etc., are used for descriptive convenience only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0045] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0046] The present application provides an electronic device, including but not limited to products such as a radio frequency front end and a filter amplifier module, and may also include terminal devices such as mobile phones, tablet computers (pads), smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, drones, or other devices, or may also be base stations, televisions, routers, automobiles, and other devices. The present application does not impose any particular restrictions on the specific form of the electronic device.

[0047] In an electronic device such as the one described above, as shown in FIG1 , the electronic device 100 may include a control circuit 110 and a filter 200 . The control circuit 110 is connected to the filter 200 and is used to control the filter 200 to effectively filter out a specific frequency point in the signal or frequencies other than the frequency point, thereby obtaining a signal of a specific frequency or eliminating a signal of a specific frequency, so as to improve the working performance of the electronic device 100 .

[0048] FIG2 shows a partial circuit diagram of some electronic devices 100. As shown in FIG2 , the electronic device 100 includes a receiver 600, a transmitter 700, an antenna 500, and a baseband chip 800. The antenna 500 is electrically connected to the receiver 600 and the transmitter 700 via a switch 900, respectively. Furthermore, the receiver 600 and the transmitter 700 are electrically connected to the baseband chip 800.

[0049] Receiver 600 shown in FIG2 includes filter 60a and filter 60c. A low-noise amplifier 60b is electrically connected between filter 60a and filter 60c. Filter 60c is electrically connected to buffer 60e via mixer 60d, and buffer 60e is electrically connected to voltage-controlled oscillator 60f. FIG2 is merely an exemplary receiver; electronic components may be added or reduced based on this circuit structure.

[0050] The transmitter 700 shown in FIG2 includes a power amplifier (PA) 70b, which is electrically connected to a filter 70a and a driver 70c, respectively. The driver 70c is electrically connected to a voltage-controlled oscillator 70d. Similarly, FIG2 is merely an exemplary transmitter, and electronic components may be added or reduced based on this circuit structure.

[0051] For example, in the transmitter 700 shown in FIG2 , the filter can effectively filter out a specific frequency point or frequencies other than the specific frequency point after the power amplifier amplifies the signal, or the filter can filter out noise signals of the low noise amplifier.

[0052] As shown in FIG3 , the filter 200 may include a plurality of cascaded resonators, for example, a plurality of series resonators 300 a , or a plurality of parallel resonators 300 b , or a plurality of series resonators 300 a and a plurality of parallel resonators 300 b .

[0053] At least one of the plurality of resonators included in the filter 200 may be the resonator shown in FIG. 4 .

[0054] As shown in Figure 4, Figure 4 shows a portion of a process structure diagram of a resonator provided in an embodiment of the present application. The resonator includes a substrate 10, and a dielectric layer 20, a piezoelectric layer 30, and a plurality of first electrodes 40 sequentially disposed on the substrate 10. The plurality of first electrodes 40 are arranged side by side in a first direction. The resonator also includes a cavity 21 that extends through the substrate 10 and the dielectric layer 20.

[0055] In the resonator illustrated in FIG4 , the plurality of first electrodes 40 are arranged along a first direction, which can be understood as a direction perpendicular to or nearly perpendicular to the extension direction of the first electrodes 40. In one embodiment, the first direction is parallel to the extension direction of the piezoelectric layer 30; in other words, the first direction is perpendicular to the stacking direction of the substrate 10, the dielectric layer 20, the piezoelectric layer 30, and the first electrodes 40.

[0056] The example structure in Figure 4 can be used in a bulk acoustic wave resonator (BAW). The main working principle of a BAW resonator is to utilize the piezoelectric effect of piezoelectric materials. Using input and output transducers, the input radio wave signal is converted into mechanical energy. After processing, the mechanical energy is converted back into an electrical signal to filter out unnecessary signals and noise, thereby improving reception quality.

[0057] During operation, the resonator shown in Figure 4 applies an alternating voltage of a certain frequency to the first electrodes 40, generating an electric field E between the plurality of first electrodes 40 along the extension direction of the piezoelectric layer 30. The piezoelectric layer 30 utilizes this electric field to produce a piezoelectric effect. The example shown in Figure 4 utilizes a horizontal electric field E to excite the piezoelectric layer 30 to resonate, thereby converting electrical energy into mechanical energy.

[0058] The resonator shown in FIG4 is excited to resonate along the extension direction of the piezoelectric layer 30. In one embodiment, it can be referred to as a horizontally-excited bulk acoustic resonator (XBAR). The horizontal direction of the piezoelectric layer 30 here can be understood as the direction perpendicular to the stacking direction of the multiple membrane layers (substrate 10, dielectric layer 20, piezoelectric layer 30).

[0059] In this embodiment, when preparing the resonator, it is necessary to first form a stacked substrate 10, dielectric layer 20, piezoelectric layer 30, and first electrode 40. Then, a back-side cavity 21 process is used to form a cavity 21 on the back side of the substrate 10 that penetrates the substrate 10 and the dielectric layer 20, thereby leaving part of the piezoelectric layer 30 suspended. Under the action of the electric field, the suspended piezoelectric layer 30 deforms, thereby generating a conversion between electrical energy and mechanical energy. However, this cavity 21 also reduces the mechanical reliability and yield of the resonator.

[0060] At least one of the multiple resonators included in the filter 200 may also be the resonator shown in FIG. 5 .

[0061] As shown in Figure 5, (a) in Figure 5 shows part of a process structure diagram of a resonator provided in an embodiment of the present application. The resonator includes a substrate 10, and a dielectric layer 20 and a filling layer 23 arranged on the substrate 10, and the dielectric layer 20 and the filling layer 23 are arranged at intervals. The piezoelectric layer 30 covers the dielectric layer 20 and the filling layer 23, and a plurality of first electrodes 40 are arranged on the piezoelectric layer 30. The plurality of first electrodes 40 are arranged side by side in the first direction. A cavity 21 is also provided in the dielectric layer 20, which penetrates the dielectric layer 20.

[0062] In the resonator of the example (I) in FIG. 5 , the plurality of first electrodes 40 are arranged along a first direction, and the first direction can be understood as a direction perpendicular to or nearly perpendicular to the extension direction of the first electrodes 40. In one embodiment, the first direction is parallel to the extension direction of the piezoelectric layer 30; in other words, the first direction is perpendicular to the stacking direction of the substrate 10, the dielectric layer 20, the piezoelectric layer 30, and the first electrodes 40.

[0063] In an optional example, when preparing a resonator, it is necessary to first form a stacked substrate 10 and an insulating layer, and then form a plurality of grooves in the insulating layer to divide the insulating layer into a plurality of parts, and the remaining insulating layer constitutes the dielectric layer 20. Next, a filling layer 23 covering the dielectric layer 20 is formed, and the filling layer 23 is flattened by a flattening process until the surface of the dielectric layer 20 is exposed, so that the dielectric layer 20 and the filling layer 23 can be spaced apart in the same layer. The piezoelectric layer 30 is then bonded to the dielectric layer 20 and the filling layer 23, and a first electrode 40 arranged side by side along a first direction is formed on the piezoelectric layer 30. Finally, part of the dielectric layer 20 is removed to form a cavity 21 in the dielectric layer 20, so that part of the piezoelectric layer 30 is suspended. Under the action of the electric field, the suspended piezoelectric layer 30 is deformed, thereby generating a conversion between electrical energy and mechanical energy.

[0064] However, as shown in (2) of FIG5 , when the filling layer 23 is flattened, the different etching rates of the filling layer 23 and the dielectric layer 20 cause the surfaces of the filling layer 23 and the dielectric layer 20 to be uneven. Referring to FIG6 , which shows a schematic diagram of the bonding interface height of the resonator provided by (2) of FIG5 , a phenomenon in which the central area of ​​the filling layer 23 is convex and the surrounding area is concave is generated, and a portion of the two sides of the dielectric layer 20 are etched away, i.e., a shoulder loss is generated. This will cause an uneven interface for bonding with the piezoelectric layer 30. During the bonding process, the piezoelectric layer 30 will have a small contact area with the dielectric layer 20 and the filling layer 23, resulting in a low bonding yield. At the same time, since the piezoelectric layer 30 and the filling layer 23 are made of different materials and the two substances appear alternately, there is a large difference in the thermal expansion coefficient, which can easily cause bubbles, striping, and cracking, further reducing the bonding yield of the piezoelectric layer 30 with the dielectric layer 20 and the filling layer 23.

[0065] In an optional embodiment, at least one of the multiple resonators included in the filter 200 may also be the resonator shown in Figure 7. As shown in Figure 7, Figure 7 shows a portion of a process structure diagram of a resonator provided in an embodiment of the present application. The resonator includes: a substrate 10; a dielectric layer 20, the dielectric layer 20 is arranged on the substrate 10, and a cavity 21 is provided in the dielectric layer 20; a piezoelectric layer 30, the piezoelectric layer 30 is arranged on the dielectric layer 20; wherein a bonding material 50 is provided between the dielectric layer 20 and the piezoelectric layer 30, and a bonding material 50 is also provided around the cavity 21; a via 31; the via 31 passes through the bonding material 50 and the piezoelectric layer 30, and is connected to the cavity 21.

[0066] In a specific embodiment, as shown in FIG8 , the process of forming the above-mentioned resonator includes: S1: forming a dielectric layer 20 on a substrate 10; S2: covering the dielectric layer 20 with a bonding material 50 and filling the bonding material 50 between the dielectric layers 20; S3: flattening the bonding material 50; S4: bonding the piezoelectric layer 30 to the bonding material 50; S5: forming a via 31 penetrating the piezoelectric layer 30 and the bonding material 50, and forming a cavity 21 in the dielectric layer 20, wherein the formed cavity 21 is connected to the outside through the via 31.

[0067] The resonator provided in an embodiment of the present application includes a dielectric layer 20, a bonding material 50, a piezoelectric layer 30, and a first electrode 40 stacked on a substrate 10. The bonding material 50 covers the dielectric layer 20, and a portion of the bonding material 50 extends into the dielectric layer 20 to contact the substrate 10. Therefore, the interface bonded to the piezoelectric layer 30 only includes the material of the bonding material 50, reducing bonding failures caused by differences in thermal expansion coefficients of different materials and improving the interface yield of the resonator without sacrificing resonator performance.

[0068] In an optional embodiment, the manufacturing process of the resonator and the device structure formed during the manufacturing process are described in detail below.

[0069] S1: forming a dielectric layer 20 on a substrate 10 .

[0070] Substrate 10 can be made of silicon or other semiconductor materials. Alternatively or additionally, substrate 10 can include other elemental semiconductor materials such as silicon or germanium. In some embodiments, substrate 10 is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 10 is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. Exemplarily, the thickness of the substrate is 500-1000 μm. Thus, substrate 10 can provide sufficient support and improve the mechanical reliability of the device.

[0071] Furthermore, forming the dielectric layer 20 includes the following steps:

[0072] S11 : forming an insulating layer 22 on the substrate 10 .

[0073] As shown in FIG. 9 , the insulating layer 22 is formed by a deposition process, such as chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDPCVD), spin coating, furnace coating, sputtering, or other suitable processes.

[0074] S12 : forming a patterned photoresist layer 25 on the insulating layer 22 .

[0075] As shown in FIG10 , a patterned photoresist layer 25 can be formed by a patterning process. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, and drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process.

[0076] S13 : using the patterned photoresist layer 25 as a mask, a plurality of grooves penetrating the insulating layer are formed in the insulating layer 22 , and the remaining insulating layer 22 constitutes the dielectric layer 20 .

[0077] It is understandable that after the dielectric layer 20 is formed, the photoresist layer 25 may be dissolved by a stripping solution to remove the photoresist layer 25 , or the photoresist layer 25 may be stripped by a stripping device.

[0078] S2 : Covering the dielectric layer 20 with the bonding material 50 and filling the gaps between the dielectric layers 20 with the bonding material 50 .

[0079] In this embodiment, as shown in FIG11 , a bonding material 50 may be formed on the dielectric layer 20 by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0080] S3: planarizing the bonding material 50 .

[0081] Referring to the structural schematic diagram of the resonator shown in FIG11 , due to the presence of a groove in the dielectric layer 20, the bonding material 50 formed by the deposition process has different thicknesses at different positions. For example, the thickness of the bonding material 50 near the groove position is 2.102 μm, the thickness of the bonding material 50 near the dielectric layer 20 is 2.177 μm, or the thickness of the bonding material 50 near the dielectric layer 20 is 2.191 μm, and the thickness of the dielectric layer 20 is 1.119 μm. Then, the total thickness of the bonding material 50 near the dielectric layer 20 and the dielectric layer 20 is 3.296 μm, while the thickness of the bonding material 50 near the groove position is 2.102 μm, that is, the bonding material 50 has an uneven surface. This will reduce the bonding yield with the piezoelectric layer 30. In order to improve the bonding yield between the bonding material 50 and the piezoelectric layer 30, the bonding material 50 needs to be flattened. In an optional embodiment, the above S3 further includes:

[0082] S31 : performing a first planarization process on the bonding material 50 .

[0083] In some embodiments, the first planarization process may be chemical mechanical polishing (CMP). The basic principle of CMP is to simultaneously utilize chemical reactions and mechanical abrasion to remove unevenness on the material surface. For example, chemical substances (such as acids, bases, oxidants, etc.) contained in the grinding liquid can react chemically with the materials in the bonding material 50. The grinding liquid also includes abrasive particles. Under the action of the liquid, these abrasive particles rub against the surface of the bonding material 50, thereby removing material from the surface of the bonding material 50 and achieving planarization. At the same time, the chemical reaction causes the material on the surface of the bonding material 50 away from the substrate 10 to dissolve or oxidize, further promoting planarization. Schematic diagrams of the resonator structure after the first planarization are shown in Figures 12 and 13. Figure 13 shows a schematic diagram of the height of the bonding material after the first planarization. As can be seen, the surface of the bonding material after the first planarization is flat at the μm level. However, due to the limitations of the CMP process precision, the reaction rates between the grinding liquid and different materials are different, resulting in unevenness in the bonding material 50 at the mm level after the first planarization. For example, the height of the bonding material 50 on one side of the wafer edge is 3 μm, and the height of the middle region of the wafer is 4.5 μm.

[0084] S32 : performing a second planarization process on the bonding material 50 , wherein the precision of the second planarization process is greater than the precision of the first planarization process.

[0085] As shown in (I) in Figure 14, in order to further improve the consistency of the thickness of the bonding material 50 surface within the wafer surface, it is necessary to flatten the bonding material 50 for a second time through a second flattening process. The second flattening process can be a plasma trimming process, which can eliminate the unevenness of the center or edge of the wafer surface. Referring to the height schematic diagram of the bonding material after the second flattening shown in Figure 13, the height difference of the bonding material 50 close to the interface of the piezoelectric layer 30 within 1 mm is less than 30 nm after the second flattening. At the same time, since there is no need to expose the surface of the dielectric layer 20, the bonding material 50 can serve as a protective layer to reduce the loss of the dielectric layer 20, thereby avoiding the shoulder loss phenomenon.

[0086] Because the bonding material undergoes multiple planarization processes, the side of the bonding material near the piezoelectric layer may contain chemicals required for the previous planarization process. Therefore, in an optional embodiment, the side of the bonding material 50 facing away from the substrate 10 includes at least one or a combination of the following: argon, oxygen, and nitrogen. Exemplarily, the side of the bonding material 50 facing away from the substrate 10 includes at least one or a combination of the following: argon, oxide, silicon oxide, silicon dioxide, silicon nitride, and aluminum oxide.

[0087] In an optional embodiment, after the bonding material 50 is planarized for the second time, the above S3 further includes:

[0088] S33 : performing a third planarization process on the bonding material 50 .

[0089] Because the surface roughness of the bonding material 50 will also affect the quality and stability of the bonding interface. When the surface roughness is high, defects such as cracks and bubbles are prone to occur at the bonding interface, thereby affecting the quality and stability of the bonding. Therefore, in this embodiment, as shown in (ii) in Figure 14, it is also necessary to reduce the roughness of the surface of the bonding material 50 by a third planarization process. Exemplarily, the third planarization process can be a chemical polishing process, for example, it can be chemical mechanical polishing (CMP). Thus, referring to the schematic diagram of the bonding material height after the third planarization shown in Figure 15, the roughness of the bonding material 50 can be further reduced by the third planarization process, and the roughness of the surface of the bonding material 50 is less than 0.3nm, thereby improving the flatness of the bonding material 50, which is conducive to improving the bonding strength and stability of the subsequent piezoelectric layer 30 and the bonding material 50.

[0090] It can be understood that, in this embodiment, the surface of the bonding material 50 and the bonding interface both refer to the surface of the bonding material 50 away from the substrate 10 .

[0091] S4: Bonding the piezoelectric layer 30 to the bonding material 50 .

[0092] In an optional example, as shown in FIG16 , the piezoelectric layer 30 can be brought into contact with the bonding material 50, and sufficient pressure can be applied to bring them into contact and form a connection due to intermolecular forces, thereby bonding the piezoelectric layer 30 to the bonding material 50. Through the planarization process in the aforementioned embodiment, the yield rate of the bonding interface between the piezoelectric layer 30 and the bonding material 50 is increased from 10% to over 80%.

[0093] Exemplarily, the thickness of the piezoelectric layer 30 is between 50 nm and 5 μm. The material of the piezoelectric layer 30 includes at least one of niobium, a combination of lithium and oxygen, and tantalum, and a combination of lithium and oxygen. For example, the material of the piezoelectric layer 30 includes any one of lithium niobate (LiNbO3), lithium tantalate (LiTaO3), aluminum nitride (AlN), zinc oxide (ZnO), or a combination thereof.

[0094] S41 : forming a plurality of first electrodes 40 on the piezoelectric layer 30 .

[0095] The first electrode 40 can be made of any possible conductive metal (including but not limited to Al, Cu, W, Mo, Ru, Pt, etc.), or a conductive metal with high acoustic impedance (including but not limited to W, Ru, Mo, Pt, etc.) can be selected. These metals with high acoustic impedance help to increase the electromechanical coupling coefficient and improve the quality factor Q, thereby further improving the performance of the resonator.

[0096] In an optional embodiment, in conjunction with Figures 17 and 18, Figure 17 shows a process structure diagram of a filter, and Figure 18 shows the first electrode 40 in Figure 17. A plurality of first electrodes 40 are provided on a side of the piezoelectric layer 30 in Figure 17 away from the bonding material 50. The plurality of first electrodes 40 include a plurality of first interdigital electrodes 401 and a plurality of second interdigital electrodes 402. For example, along a direction perpendicular to the extension direction of the first interdigital electrodes 401, the plurality of first interdigital electrodes 401 and the plurality of second interdigital electrodes 402 can be arranged side by side, or the plurality of first interdigital electrodes 401 and the plurality of second interdigital electrodes 402 can be arranged in an alternating pattern, that is, a second interdigital electrode 402 can be provided between two adjacent first interdigital electrodes 401. Alternatively, the first interdigital electrodes 401 and the second interdigital electrodes 402 are spaced apart in the first direction, and the extension direction of the first interdigital electrodes 401 and / or the second interdigital electrodes 402 is perpendicular to the first direction.

[0097] The plurality of first interdigital electrodes 401 are connected via a first bus bar 601, and the plurality of second interdigital electrodes 402 are connected via a second bus bar 602. For example, the first bus bar 601 and the second bus bar 602 are arranged in parallel, and both the first bus bar 601 and the second bus bar 602 extend in a direction perpendicular to the direction in which the first interdigital electrodes 401 or the second interdigital electrodes 402 extend. As shown in FIG18 , the first bus bar 601 and the second bus bar 602 extend in a first direction.

[0098] The first bus bar 601 can serve as an input terminal, and the second bus bar 602 can serve as an output terminal. For example, an alternating voltage within a certain frequency range can be input to the plurality of first interdigital electrodes 401 via the first bus bar 601, and an alternating voltage signal processed by the resonator can be output to the plurality of second interdigital electrodes 402 via the second bus bar 602.

[0099] S5 : forming a via hole 31 penetrating the piezoelectric layer 30 and the bonding material 50 , and forming a cavity 21 in the dielectric layer 20 . The formed cavity 21 is filled with the bonding material and communicates with the via hole 31 .

[0100] In this embodiment, as shown in (1) of FIG19 , a via hole 31 can be first formed through the piezoelectric layer 30 and the bonding material 50, thereby exposing a portion of the upper surface of the dielectric layer 20, that is, the bottom of the via hole 31 is the dielectric layer 20. Then, as shown in (2) of FIG19 , the dielectric layer 20 exposed by the via hole 31 is removed to form a cavity 21 in the dielectric layer 20. For example, a first etching process is used to remove a portion of the piezoelectric layer 30 and the bonding material 50 to form the via hole 31, and a second etching process is used to remove the dielectric layer 20 near the via hole 31, so that the cavity 21 can be formed in the dielectric layer 20, thereby connecting the cavity 21 to the outside world through the via hole 31. In some embodiments, the first etching process is a dry etching process, and the second etching process is a wet etching process or a dry etching process. In some embodiments, the dry etching process includes using an etching gas such as carbon tetrafluoride (CF4), argon (Ar), nitrogen trifluoride (NF3), chlorine (Cl2), helium (He), hydrogen bromide (HBr), oxygen (O2), nitrogen (N2), fluoromethane (CH3F), methane (CH4), difluoromethane (CH2F2), or a combination thereof.

[0101] It can be understood that the embodiment of the present application does not limit the formation position of the via 31. As shown in (1) of Figure 20, the via 31 can be located between two adjacent first electrodes 40, or, as shown in (2) of Figure 20, the via 31 can also be located at both ends of the first electrode 40.

[0102] In a feasible process structure, multiple resonators provided by embodiments of the present application can be integrated on the same substrate 10 to form a filter. For example, as shown in FIG21 , resonators 301, 302, and 303 connected in series are integrated on substrate 10, with resonators 301 and 302 electrically connected via a conductive connection layer 130, and resonators 302 and 303 electrically connected via a conductive connection layer 140. It will be appreciated that the conductive connection layer 130 or the conductive connection layer 140 can have a variety of feasible structures.

[0103] The filters involved in the above-mentioned embodiments of the present application can also be used in a duplexer or a multiplexer. In a duplexer, a transmit channel filter and a receive channel filter are included, and at least one of the transmit channel filter and the receive channel filter can be filtered using the above-mentioned filter. In a multiplexer, multiple transmit channel filters and multiple receive channel filters are included, wherein at least one of the multiple transmit channel filters or at least one of the multiple receive channel filters can use the filter involved in the embodiments of the present application.

[0104] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0105] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A resonator, characterized in that include: substrate; a dielectric layer, the dielectric layer being disposed on the substrate and having a cavity therein; a piezoelectric layer, the piezoelectric layer being disposed on the dielectric layer; Wherein, bonding material is provided between the dielectric layer and the piezoelectric layer, and around the cavity; The via hole passes through the bonding material and the piezoelectric layer and communicates with the cavity.

2. The resonator according to claim 1, characterized in that The resonator further includes a plurality of first electrodes arranged side by side on the piezoelectric layer along a first direction.

3. The resonator according to claim 2, characterized in that The resonator further includes: a first bus bar and a second bus bar; Among every two adjacent first electrodes in the plurality of first electrodes, one is a first interdigital electrode and the other is a second interdigital electrode; the first interdigital electrodes and the second interdigital electrodes are spaced apart in the first direction; A plurality of the first interdigital electrodes among the plurality of first electrodes are connected through the first bus bar, and a plurality of the second interdigital electrodes among the plurality of first electrodes are connected through the second bus bar.

4. The resonator according to any one of claims 1 to 3, characterized in that The bonding material on a side close to the piezoelectric layer includes at least one or more of the following combinations: argon, oxide, silicon oxide, silicon dioxide, silicon nitride, and aluminum oxide.

5. The resonator according to any one of claims 1 to 4, characterized in that: The material of the piezoelectric layer includes at least one or more of the following combinations: lithium niobate, lithium tantalate, lanthanum gallium silicate, gallium nitride or aluminum nitride.

6. The resonator according to any one of claims 1 to 5, characterized in that: The thickness of the piezoelectric layer is 50nm-5um.

7. The resonator according to any one of claims 1 to 6, characterized in that: The height difference of the interface of the bonding material close to the piezoelectric layer within 1 mm is less than 30 nm.

8. The resonator according to any one of claims 1 to 7, characterized in that: The thickness of the substrate is 500-1000um.

9. A method for preparing a resonator, characterized in that: include: forming a dielectric layer on the substrate; Covering the dielectric layer with a bonding material, and filling the dielectric layer with a bonding material; planarizing the bonding material; bonding the piezoelectric layer to the bonding material; A via hole is formed through the piezoelectric layer and the bonding material, and a cavity is formed in the dielectric layer. The cavity is filled with bonding material and communicates with the via hole.

10. The method according to claim 9, characterized in that Planarizing the bonding material includes: performing a first planarization on the bonding material through a first planarization process; The bonding material is planarized for a second time through a second planarization process, and the accuracy of the second planarization process is greater than the accuracy of the first planarization process.

11. The method according to claim 10, characterized in that The first planarization process is chemical mechanical polishing, and the second planarization process is a plasma planarization process.

12. The method according to any one of claims 10-11, characterized in that Forming the dielectric layer includes: forming an insulating layer on the substrate; forming a patterned photoresist layer on the insulating layer; Using the patterned photoresist layer as a mask, a plurality of grooves penetrating the insulating layer are formed in the insulating layer, and the remaining insulating layer constitutes a dielectric layer.

13. A filter, characterized in that: The invention comprises a plurality of cascaded resonators; wherein at least one of the plurality of resonators is a resonator according to any one of claims 1 to 8.

14. An electronic device, characterized in that: include: control circuit; The filter according to claim 13, wherein the filter is electrically connected to the control circuit.

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