Light-emitting diode chip and chip group thereof, and display module

Abstract

A light-emitting diode chip and a chip group thereof, and a display module, which relate to the technical field of semiconductors. The light-emitting diode chip comprises an N-type electrode, a P-type electrode and a light-emitting layer. The light-emitting layer comprises a first light-emitting layer having a first light-emission wavelength and a second light-emitting layer having a second light-emission wavelength, wherein the first light-emission wavelength is less than the second light-emission wavelength; and at least part of the first light-emitting layer and at least part of the second light-emitting layer are arranged in a stacked manner, the first light-emitting layer is located on the side of the second light-emitting layer that is close to the P-type electrode, and light emitted by the first light-emitting layer is used for exciting the second light-emitting layer to emit light.

Description

Light-emitting diode chip and chipset, display module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 20, 2024, with application number 202410326712.6, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of semiconductor technology, for example, to a light emitting diode chip and its chipset, and a display module. Background Art

[0003] In semiconductor lighting technology, light emitting diodes (LEDs), as light-emitting devices that convert electrical energy into light energy, have the advantages of energy saving and environmental protection, long service life and high luminous efficiency. They are widely used in many fields such as indication, display, decoration, and lighting.

[0004] In the display field, ultra-high-density display products based on micro-LEDs (micro LEDs) typically use three independent chips to form a pixel unit, that is, three single-chip, single-color sub-pixels to form a pixel unit. The large number of chips in micro LEDs and their small size require a mass transfer process in the micro LED manufacturing process.

[0005] However, the above-mentioned micro LED manufacturing process has problems such as high process difficulty, low yield rate and high cost. Summary of the Invention

[0006] The present application provides a light-emitting diode chip, a chipset thereof, and a display module, which can flexibly adjust the size of the light-emitting diode chip and the full-color chipset, reduce the number of transfers and the difficulty of transfers in mass transfer, and thus overcome the process, yield and cost problems represented by mass transfer in ultra-high-density pixel display products.

[0007] In a first aspect, the present application provides a light-emitting diode chip, comprising an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer is electrically connected to the N-type electrode and the P-type electrode, respectively.

[0008] The light-emitting layer includes a first light-emitting layer having a first light-emitting wavelength and a second light-emitting layer having a second light-emitting wavelength, wherein the first light-emitting wavelength is smaller than the second light-emitting wavelength; along the thickness direction of the light-emitting diode chip, at least part of the first light-emitting layer and at least part of the second light-emitting layer are stacked; in the stacked first light-emitting layer and the second light-emitting layer, the first light-emitting layer is located on a side of the second light-emitting layer close to the P-type electrode, and the light emitted by the first light-emitting layer is used to excite the second light-emitting layer to emit light.

[0009] The first light emitting layer and the second light emitting layer are configured to form at least two sub-pixels arranged side by side, and the at least two sub-pixels include a first sub-pixel having a first light emitting wavelength and a second sub-pixel having a second light emitting wavelength.

[0010] In a second aspect, the present application provides a light-emitting diode chip set, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array;

[0011] The two adjacent LED chips include a first LED chip and a second LED chip. Part of the sub-pixels of the first LED chip and part of the sub-pixels of the second LED chip together form a pixel unit.

[0012] In a third aspect, the present application provides a display module, including a display module, a driving backplane and the above-mentioned light-emitting diode chipset, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG1 is a top view of a first light-emitting diode chip provided in an embodiment of the present application;

[0014] FIG2 is a cross-sectional view of a first light-emitting diode chip provided in an embodiment of the present application;

[0015] FIG3 is a top view of a second light-emitting diode chip provided in an embodiment of the present application;

[0016] FIG4 is a cross-sectional view of a second light-emitting diode chip provided in an embodiment of the present application;

[0017] FIG5 is a top view of a third light-emitting diode chip provided in an embodiment of the present application;

[0018] FIG6 is a cross-sectional view of a third light-emitting diode chip provided in an embodiment of the present application;

[0019] FIG7 is a top view of a fourth light-emitting diode chip provided in an embodiment of the present application;

[0020] FIG8 is a cross-sectional view of a fourth light-emitting diode chip provided in an embodiment of the present application;

[0021] FIG9 is a cross-sectional view of a first light-emitting diode chip provided in an embodiment of the present application, in which a reflective layer, a hole blocking layer, and a light-blocking member are provided;

[0022] FIG10 is a cross-sectional view of a fifth light-emitting diode chip provided in an embodiment of the present application;

[0023] FIG10( a ) is a cross-sectional view of the fifth light-emitting diode chip provided in an embodiment of the present application without the second filter layer;

[0024] FIG11 is a cross-sectional view of a sixth light-emitting diode chip provided in an embodiment of the present application;

[0025] FIG11( a ) is a cross-sectional view of a sixth light-emitting diode chip provided in an embodiment of the present application without the second filter layer;

[0026] FIG12 is a cross-sectional view of a seventh light-emitting diode chip provided in an embodiment of the present application;

[0027] FIG12( a ) is a cross-sectional view of a seventh light-emitting diode chip provided in an embodiment of the present application without the second filter layer;

[0028] 13 is a cross-sectional view of a fifth light-emitting diode chip provided in an embodiment of the present application, in which a reflective layer, a hole blocking layer, and a light-blocking member are provided;

[0029] FIG14 is a top view of an eighth light-emitting diode chip provided in an embodiment of the present application;

[0030] FIG15 is a cross-sectional view of an eighth light-emitting diode chip provided in an embodiment of the present application;

[0031] FIG16 is a cross-sectional view of a ninth light-emitting diode chip provided in an embodiment of the present application;

[0032] FIG17 is a top view of a tenth light-emitting diode chip provided in an embodiment of the present application;

[0033] FIG18 is a cross-sectional view of a tenth light-emitting diode chip provided in an embodiment of the present application;

[0034] FIG19 is a cross-sectional view of an eleventh light-emitting diode chip provided in an embodiment of the present application;

[0035] FIG20 is a top view of a twelfth light-emitting diode chip provided in an embodiment of the present application;

[0036] FIG21 is a cross-sectional view of a twelfth light-emitting diode chip provided in an embodiment of the present application;

[0037] FIG22 is a cross-sectional view of an eighth light-emitting diode chip provided in an embodiment of the present application, in which a reflective layer, a hole blocking layer, and a light-blocking member are provided;

[0038] FIG23 is a cross-sectional view of a thirteenth light-emitting diode chip provided in an embodiment of the present application;

[0039] FIG24 is a cross-sectional view of a fourteenth light-emitting diode chip provided in an embodiment of the present application;

[0040] FIG25 is a cross-sectional view of a fifteenth light-emitting diode chip provided in an embodiment of the present application;

[0041] FIG26 is a cross-sectional view of a thirteenth light-emitting diode chip provided in an embodiment of the present application, in which a reflective layer, a hole blocking layer, and a light-blocking member are provided;

[0042] FIG27 is a top view of a sixteenth light-emitting diode chip provided in an embodiment of the present application;

[0043] FIG28 is a top view of a seventeenth light-emitting diode chip provided in an embodiment of the present application;

[0044] FIG29 is a top view of an eighteenth light-emitting diode chip provided in an embodiment of the present application;

[0045] FIG30 is a top view of a nineteenth light-emitting diode chip provided in an embodiment of the present application;

[0046] FIG31 is a top view of the twentieth light-emitting diode chip provided in an embodiment of the present application;

[0047] FIG32 is a top view of a twenty-first light-emitting diode chip provided in an embodiment of the present application;

[0048] FIG33 is a cross-sectional view of a twenty-first light-emitting diode chip provided in an embodiment of the present application;

[0049] FIG34 is a top view of a twenty-second light-emitting diode chip provided in an embodiment of the present application;

[0050] FIG35 is a top view of a twenty-third light-emitting diode chip provided in an embodiment of the present application;

[0051] FIG36 is a top view of a twenty-fourth light-emitting diode chip provided in an embodiment of the present application;

[0052] FIG37 is a schematic diagram of a first package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0053] FIG38 is a schematic diagram of a second package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0054] FIG39 is a schematic diagram of a third package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0055] FIG40 is a schematic diagram of a fourth package structure of a light-emitting diode chip provided in an embodiment of the present application;

[0056] FIG41 is a structural flow chart of a first method for preparing a light-emitting diode chip provided in an embodiment of the present application;

[0057] FIG42 is a structural flow chart of a second method for preparing a light-emitting diode chip provided in an embodiment of the present application;

[0058] FIG43 is a structural flow chart of a third method for manufacturing a light-emitting diode chip provided in an embodiment of the present application;

[0059] FIG44 is a structural flow chart of a fourth method for manufacturing a light-emitting diode chip provided in an embodiment of the present application;

[0060] FIG45 is a schematic diagram showing a structure of a light-emitting diode chip provided in an embodiment of the present application and provided with a light conversion layer;

[0061] FIG46 is a schematic diagram of a first structure of a light-emitting diode chipset provided in an embodiment of the present application;

[0062] FIG47 is a schematic diagram of a second structure of a light-emitting diode chipset provided in an embodiment of the present application;

[0063] FIG48 is a schematic diagram of a third structure of a light-emitting diode chipset provided in an embodiment of the present application;

[0064] FIG49 is a schematic diagram of a fourth structure of a light-emitting diode chipset provided in an embodiment of the present application;

[0065] FIG50 is a schematic diagram of a fifth structure of a light-emitting diode chipset provided in an embodiment of the present application;

[0066] FIG51 is a sixth structural diagram of a light-emitting diode chipset provided in an embodiment of the present application;

[0067] FIG52 is a schematic diagram of a seventh structure of a light-emitting diode chipset provided in an embodiment of the present application;

[0068] FIG53 is a schematic diagram of an eighth structural embodiment of the light-emitting diode chipset provided in the present application;

[0069] FIG54 is a ninth structural diagram of a light-emitting diode chip set provided in an embodiment of the present application;

[0070] FIG55 is a schematic diagram of the tenth structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0071] FIG56 is a schematic diagram of the eleventh structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0072] FIG57 is a schematic diagram of a twelfth structure of a light-emitting diode chipset provided in an embodiment of the present application;

[0073] FIG58 is a schematic diagram of the thirteenth structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0074] FIG59 is a schematic diagram of the fourteenth structure of the light-emitting diode chip group provided in an embodiment of the present application;

[0075] FIG60 is a schematic diagram of the fifteenth structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0076] FIG61 is a schematic diagram of the sixteenth structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0077] FIG62 is a schematic diagram of the seventeenth structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0078] FIG63 is a diagram showing a first dimension of a light-emitting diode chip set provided in an embodiment of the present application;

[0079] FIG63( a ) is a diagram showing the dimensions of a plurality of sub-pixels of a light-emitting diode chip set provided in an embodiment of the present application along a first direction;

[0080] FIG64 is a second dimension diagram of the light-emitting diode chipset provided in an embodiment of the present application;

[0081] FIG65 is a diagram showing a third dimension of a light-emitting diode chipset provided in an embodiment of the present application;

[0082] FIG66 is a diagram showing a fourth dimension of a light-emitting diode chipset provided in an embodiment of the present application;

[0083] FIG67 is a fifth dimension diagram of the light-emitting diode chipset provided in an embodiment of the present application;

[0084] FIG68 is a schematic diagram of the eighteenth structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0085] FIG69 is a schematic diagram of the nineteenth structure of the light-emitting diode chipset provided in an embodiment of the present application;

[0086] FIG70 is a schematic diagram of a first structure of a display module provided in an embodiment of the present application;

[0087] Figure 71 is a second structural schematic diagram of the display module provided in an embodiment of the present application.

[0088] Explanation of the accompanying drawings: 100, substrate; 101, buffer layer; 102, N-type electrode; 103, N-type semiconductor layer; 104, P-type electrode; 105, P-type semiconductor layer; 106, current spreading layer; 107, reflective layer; 108, first insulating layer; 109, second insulating layer; 110, bonding substrate; 111, binding layer; 112, color conversion layer; 114, first filter layer; 115, second filter layer; 116, isolation material; 117, hole blocking layer; 118, light blocking layer; 119a, first light-emitting layer; 119b, second light-emitting layer; 119c, third light-emitting layer; 200, driving backplane; 201, driving substrate; 202, driving unit. DETAILED DESCRIPTION

[0089] In LED display products, three single-core monochrome single-pixel chips are usually used to form a pixel unit. The size of a single chip in ultra-high-density display products represented by micro LED is relatively small, and the number of chips that make up the display product is relatively large. In the manufacturing process of display products, micro LED chips need to be grown on wafers, and then transferred to a specific substrate through mass transfer technology to complete the binding assembly. In the mass transfer process, due to the small size and large number of chips, the transfer operation is more difficult, the number of operations is numerous, and the operation alignment requirements on the substrate are high. As a result, the manufacturing process of micro LED display products is more difficult, the yield is lower, the production cycle is longer, and the cost is higher.

[0090] In related technologies, in LED display products, several chips are packaged together through the MIP (Micro LED in Package) packaging process to form an integrated chipset that can emit multiple wavelengths. The traditional MIP packaging process is suitable for LED display products with pixel sizes greater than 0.3 mm. Due to the limitations of mass transfer technology, the MIP packaging process requires the use of single-core monochrome single-sub-pixel chips to be larger, that is, the sub-pixel size must be larger. A single chipset is usually an RGB pixel unit, and a large number of chips and chipsets are used in the application end.

[0091] The light-emitting diode chip and its chipset and display module provided by the present application are characterized by placing a light-emitting layer between an N-type electrode and a P-type electrode and electrically connecting the two, so that the electrons provided by the N-type electrode and the holes provided by the P-type electrode are combined in the light-emitting layer, and the light-emitting material in the light-emitting layer is excited to emit light. The light-emitting layer includes a first light-emitting layer having a first light-emitting wavelength and a second light-emitting layer having a second light-emitting wavelength. The first light-emitting wavelength is smaller than the second light-emitting wavelength. In the stacked first light-emitting layer and at least part of the second light-emitting layer, the first light-emitting layer is located on the side of the second light-emitting layer close to the P-type electrode. The light emitted by the first light-emitting layer is used to excite the second light-emitting layer to emit light, so that the light-emitting diode chip of the present application has both electroluminescence and photoluminescence mechanisms. The present application adopts a single-core dual-color multi-sub-pixel arrangement, that is, at least two sub-pixels are used to form a pixel subgroup, and a full-color pixel unit is formed by the arrangement of the pixel subgroup, thereby forming a full-color chip group. This application can flexibly adjust the size of the light-emitting diode chip and the full-color chipset, reduce the difficulty of the transfer operation in the mass transfer process, and reduce the number of mass transfers, thereby overcoming the process, yield and cost problems represented by mass transfer in ultra-high-density pixel display products.

[0092] Compared to the related art, which integrates several chips together to form an integrated chipset that emits multiple wavelengths, the related art needs to overcome the process difficulties of integrating multiple chips, resulting in greater process difficulty, lower yield, and higher cost. This application directly obtains dual-color multiple sub-pixels in a single LED chip, which is simpler in process, less technically difficult, and lower in cost.

[0093] The LED chip group formed by using the single-core dual-color multi-sub-pixel LED chip of the present application can flexibly adjust the size of the LED chip while ensuring a small sub-pixel size under the conditions of the same light-emitting area and the same pixel density (Pixels Per Inch, abbreviated as PPI). At the same time, the number of LED chips is greatly reduced, thereby overcoming problems such as the difficulty of the manufacturing process, low product yield and high manufacturing cost, and helping to promote the mass production of mini LED and micro LED as soon as possible.

[0094] When the single-core, dual-color, multi-sub-pixel LED chips of this application are combined into a full-color integrated chipset (for example, three 2*n chips form a chipset), n*2 pixel units can be obtained. When combined with a backplane, the chipset used is 1 / 2n the size of a traditional MIP package, greatly reducing preparation time, process and raw material costs, and significantly improving yield. The pixel size applicable to the full-color integrated package of this application can be flexibly adjusted and can be far smaller than the pixel size applicable to traditional MIP processes.

[0095] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present application. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present application, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The embodiments of the present application are described in detail below in conjunction with the drawings.

[0096] In this application, some nouns can be understood as follows:

[0097] Sub-pixel (SP): A single blue light pixel, a single green light pixel, or a single red light pixel is called a sub-pixel. In this patent, a sub-pixel can also be a single arbitrary wavelength.

[0098] Pixel subgroup (PSG): A group of sub-pixels.

[0099] Pixel unit (PU): A unit that includes three primary colors: blue, green, and red sub-pixels, or includes three or more other sub-pixels of different wavelengths that can constitute white light.

[0100] Single-core monochrome single-sub-pixel chip: A single light-emitting diode chip can only emit one wavelength of light and contains only one sub-pixel, such as one blue light sub-pixel, one green light sub-pixel, or one red light sub-pixel.

[0101] Single-chip monochrome multi-sub-pixel chip: A single chip can only emit one wavelength of light, but contains more than or equal to two sub-pixels, such as two red sub-pixels, three red sub-pixels, or more red sub-pixels.

[0102] Single-core dual-color multi-sub-pixel chip; a single chip can emit two different wavelengths of light and contains more than or equal to two sub-pixels, such as 1 red sub-pixel + 1 green sub-pixel, 2 red sub-pixels + 2 green sub-pixels, multiple blue sub-pixels + multiple red sub-pixels, multiple green sub-pixels + multiple blue sub-pixels, or multiple green sub-pixels + multiple red sub-pixels.

[0103] Light-emitting diode chip (C) is a solid-state semiconductor device with a light-emitting layer between a P-type electrode and an N-type electrode.

[0104] Light-emitting diode chipset (CG): It is composed of two or more single-core dual (single) color multi-sub-pixel chips, containing one or more pixel units.

[0105] Display mini block (DMB): A display device formed by electrically connecting a light-emitting diode chipset and a driver backplane.

[0106] Electroluminescence (EL): When current passes through a P-type semiconductor and an N-type semiconductor, holes generated in the P-type semiconductor and electrons generated in the N-type semiconductor recombine in the light-emitting layer to emit light.

[0107] Photo-luminescence (PL): light emitted by a light-emitting layer.

[0108] In a first aspect, an embodiment of the present application provides a light-emitting diode chip, as shown in Figures 1 to 21, the light-emitting diode chip includes an N-type electrode, a P-type electrode, and a light-emitting layer arranged between the N-type electrode and the P-type electrode; the light-emitting layer is electrically conductive with the N-type electrode and the P-type electrode, respectively.

[0109] The light-emitting layer includes a first light-emitting layer 119a having a first light-emitting wavelength and a second light-emitting layer 119b having a second light-emitting wavelength, wherein the first light-emitting wavelength is shorter than the second light-emitting wavelength. At least a portion of the first light-emitting layer 119a and at least a portion of the second light-emitting layer 119b are stacked along the thickness direction of the light-emitting diode chip. In the stacked first light-emitting layer 119a and the second light-emitting layer 119b, the first light-emitting layer 119a is located on a side of the second light-emitting layer 119b close to the P-type electrode. Light emitted by the first light-emitting layer 119a is used to excite the second light-emitting layer 119b to emit light.

[0110] The first light emitting layer 119a and the second light emitting layer 119b are configured to form at least two sub-pixels arranged side by side, and the at least two sub-pixels include a first sub-pixel having a first light emitting wavelength and a second sub-pixel having a second light emitting wavelength.

[0111] It should be noted that an electric field is formed between the N-type electrode and the P-type electrode, and the light-emitting layer is arranged between the N-type electrode and the P-type electrode. It can be understood that the light-emitting layer is located in this electric field. Referring to Figures 2, 4, 6, 8, 9, 10-13, 15, 16, 18 and 20-25, in the thickness direction of the chip, the entire light-emitting layer or a portion of the light-emitting layer is located between the N-type electrode and the P-type electrode. The light-emitting layer is electrically conductive with the N-type electrode and the P-type electrode, respectively, which may mean that the light-emitting layer is in contact with the N-type electrode and the P-type electrode, respectively, or that the light-emitting layer is electrically conductive with the N-type electrode through the N-type semiconductor layer 103 and electrically conductive with the P-type electrode through the P-type semiconductor layer 105.

[0112] Among them, on the basis of satisfying that the first light-emitting wavelength is less than the second light-emitting wavelength, the first light-emitting layer 119a and the second light-emitting layer 119b are respectively any two of the red light-emitting material layer, the green light-emitting material layer, the blue light-emitting material layer, the purple light-emitting material layer and the ultraviolet light-emitting material layer.

[0113] For example, the first light-emitting layer is a green light-emitting material layer, and the second light-emitting layer is a red light-emitting material layer; or, the first light-emitting layer is a blue light-emitting material layer, and the second light-emitting layer is a green light-emitting material layer or a red light-emitting material layer; or, the first light-emitting layer is a purple light-emitting material layer, and the second light-emitting layer is a blue light-emitting material layer, a green light-emitting material layer or a red light-emitting material layer.

[0114] Correspondingly, on the basis of satisfying that the first light-emitting wavelength is less than the second light-emitting wavelength, the two sub-pixels formed by the first light-emitting layer and the second light-emitting layer can be any two of the red light sub-pixel (R), the green light sub-pixel (G), the blue light sub-pixel (B), the ultraviolet light sub-pixel (UVA) or the violet light sub-pixel (Pur).

[0115] For example, the first sub-pixel is a green sub-pixel, and the second sub-pixel is a red sub-pixel (i.e., G+R). Alternatively, the first sub-pixel is a blue sub-pixel, and the second sub-pixel is a green sub-pixel (i.e., B+G). Alternatively, the first sub-pixel is a blue sub-pixel, and the second sub-pixel is a red sub-pixel (i.e., B+R). Alternatively, the first sub-pixel is a violet sub-pixel, and the second sub-pixel is a blue sub-pixel (i.e., Pur+B). Alternatively, the first sub-pixel is a violet sub-pixel, and the second sub-pixel is a red sub-pixel (i.e., Pur+R). Alternatively, the first sub-pixel is a violet sub-pixel, and the second sub-pixel is a green sub-pixel (i.e., Pur+G). Alternatively, the first sub-pixel is an ultraviolet sub-pixel, and the second sub-pixel is a blue sub-pixel (i.e., UVA+B), as shown in Figures 31 and 32.

[0116] In the embodiment of the present application, the following description is given using as an example an example where the first light-emitting wavelength is a blue light wavelength, the first light-emitting layer is a blue light-emitting material layer, the first sub-pixel is a blue light sub-pixel (B), the second light-emitting wavelength is a green light wavelength, the second light-emitting layer is a green light-emitting material layer, and the second sub-pixel is a green light sub-pixel (G).

[0117] This application combines two sub-pixels with different luminous wavelengths into a light-emitting diode chip, that is, adopts a single-core dual-color multi-sub-pixel arrangement. Compared with the related art that uses a single sub-pixel to form a chip, this application can flexibly adjust the size of the light-emitting diode chip, reducing the transfer difficulty and alignment difficulty in mass transfer operations. In addition, it can effectively reduce the number of light-emitting diode chips required for display products with the same luminous area and the same pixel density, thereby reducing the complexity of mass transfer operations and reducing production costs. This can also improve the product yield of ultra-high-density pixel displays.

[0118] The structure and light-emitting mechanism of the light-emitting diode chip according to the embodiment of the present application are described below.

[0119] 1 and 2 , in a light-emitting diode chip of the first structure, the entire first light-emitting layer 119a and the entire second light-emitting layer 119b are stacked; the surface of the first light-emitting layer 119a facing away from the second light-emitting layer 119b is electrically connected to the P-type electrode, and the surface of the second light-emitting layer 119b facing away from the first light-emitting layer 119a is electrically connected to the N-type electrode.

[0120] The first light-emitting layer 119a includes a first region and a second region arranged side by side and at intervals, and the second light-emitting layer 119b includes a third region and a fourth region arranged side by side and at intervals; the first region and the third region are opposite to each other and are arranged to form a first sub-pixel, and the second region and the fourth region are opposite to each other and are arranged to form a second sub-pixel.

[0121] It should be noted that the first and second regions of the first light-emitting layer 119a can be two regions arranged side by side in a direction perpendicular to the thickness of the LED chip. The same applies to the third and fourth regions. For example, in Figure 2, the first region can be the portion of the first light-emitting layer 119a near the left side, the second region can be the portion of the first light-emitting layer 119a near the right side, the third region can be the portion of the second light-emitting layer 119b near the left side, and the fourth region can be the portion of the second light-emitting layer 119b near the right side. In other embodiments, the positions of the first and second regions can be interchanged, and the positions of the third and fourth regions can also be interchanged.

[0122] "Side by side" or "arranged side by side" in this application may mean that the two devices correspond to each other in a thickness direction perpendicular to the light-emitting diode chip, that is, the two devices are located at the same thickness position of the light-emitting diode chip; it may also mean that the two devices are on the same layer of the light-emitting diode chip, and the two devices may be considered side by side or arranged side by side even if they are misaligned in the thickness direction of the light-emitting diode chip.

[0123] The light-emitting diode chip of this embodiment further includes a first filter layer CF1 and a second filter layer CF2 arranged side by side, wherein the first filter layer CF1 corresponds to the first region, and the second filter layer CF2 corresponds to the second region; the first filter layer CF1 and the second filter layer CF2 are both located on the light-emitting side of the light-emitting diode; the transmission wavelength of the first filter layer CF1 is the first emission wavelength, and the transmission wavelength of the second filter layer CF2 is the second emission wavelength.

[0124] The first filter layer CF1 transmits the first emission wavelength. That is, of the light emitted by the first and second light-emitting layers 119a and 119b, only light with the first emission wavelength passes through the first filter layer CF1. Similarly, only light with the second emission wavelength passes through the second filter layer CF2. This allows the LED chip to emit light of two different wavelengths.

[0125] It should be noted that the filter layer can be a color filter or a Bragg reflector (or a distributed Bragg reflector, DBR for short). The Bragg reflector can also filter the wavelength of the light passing through, thereby emitting light with different wavelengths. The Bragg reflector can be an alternating stack of two materials: aluminum nitrogen and gallium nitrogen, or an alternating stack of two materials: titanium oxide and silicon oxide, or an alternating stack of two materials: silicon oxide and silicon nitride. Optionally, the thickness of the Bragg reflector is 2-6 microns. In other embodiments, the thickness value can be adjusted as needed, and this application does not impose any restrictions on it.

[0126] As shown in FIG9 , the LED chip of this embodiment further includes a reflective layer 107, which is located on the backlight side of the LED chip. Disposing the reflective layer 107 on the backlight side ensures that light is emitted from the light-emitting side. The reflective layer 107 shown in FIG9 is located on the side of the P-type electrode facing away from the N-type electrode. The side of the N-type electrode facing away from the P-type electrode forms the light-emitting side of the LED chip. The reflective layer 107 can be a metal layer or a Bragg reflector. The first filter layer CF1 and the second filter layer CF2 are disposed on the side of the N-type electrode facing away from the P-type electrode.

[0127] Continuing with reference to Figure 9, the light-emitting diode chip of this embodiment also includes a light-blocking layer 118, which is located on the light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels. Since the reflective layer 107 is arranged on the side of the P-type electrode away from the N-type electrode, the light-emitting side is limited to the side of the N-type electrode away from the P-type electrode. Therefore, the light-blocking layer 118 in this embodiment is located on the side of the N-type electrode away from the P-type electrode. The light-blocking layer 118 can be a black resin material with the function of absorbing and blocking light. The light-blocking layer 118 is located between two adjacent sub-pixels, that is, it can be located between the positions corresponding to the first and second regions, or between the positions corresponding to the third and fourth regions. In this way, the problem of light mixing between the two sub-pixels can be avoided, and the light-emitting effect of the light-emitting diode chip can be guaranteed.

[0128] Since the light-blocking layer 118, the first filter layer CF1 and the second filter layer CF2 are all arranged on the light-emitting side, the light-blocking layer 118 can be located between the first filter layer CF1 and the second filter layer CF2. In this way, both the light filtering and light-blocking effects can be ensured, and the structural regularity of the light-emitting diode chip can be ensured.

[0129] Continuing with Figure 9 , the LED chip of this embodiment further includes a hole-blocking layer 117, which is disposed between any two adjacent layers of the stacked first light-emitting layer 119a, the second light-emitting layer 119b, and the third light-emitting layer 119c. Hole-blocking layer 117 blocks the passage of holes while allowing electrons to pass through. The material of hole-blocking layer 117 can be silicon-doped gallium nitride. The combined thickness of hole-blocking layer 117 and the first light-emitting layer 119a can be greater than the diffusion length of holes, thereby preventing holes from migrating to the second light-emitting layer 119b.

[0130] As shown in Figure 9, during the operation of the light-emitting diode chip, after the N-type electrode is energized, it can provide electrons, and after the P-type electrode is energized, it can provide holes. Among them, the holes and electrons can migrate to the location of the first light-emitting layer 119a, and after the holes and electrons recombine, they can emit light with a first light-emitting wavelength. Due to the presence of the hole blocking layer 117, the holes will not migrate to the location of the second light-emitting layer 119b. The luminescence mechanism of the first light-emitting layer 119a is electroluminescence. The light with the first light-emitting wavelength emitted by the first light-emitting layer 119a can excite the second light-emitting layer 119b to emit light, and the luminescence mechanism of the second light-emitting layer 119b is photoluminescence. In summary, the luminescence mechanism of the light-emitting diode chip of the first structure is a mixed mechanism of electroluminescence and photoluminescence.

[0131] It should be noted that the reflective layer 107, light-blocking layer 118 and hole-blocking layer 117 in the light-emitting diode chip of the first structure can all be applied to the light-emitting diode chips of other structures described below, and have similar structures and functions to those in the light-emitting diode chip of the first structure, and will not be described in detail later.

[0132] In other embodiments, during operation of the LED chip, when the N-type electrode and the P-type electrode are energized, holes and electrons can migrate to the location of the first light-emitting layer 119a. Recombination of the holes and electrons can emit light having a first wavelength. When the hole-blocking layer 117 is not disposed between the first light-emitting layer 119a and the second light-emitting layer 119b, and the thickness of the first light-emitting layer 119a is relatively small, while the thickness of the second light-emitting layer 119b is relatively large, holes can also reach the location of the second light-emitting layer 119b. Recombination of the holes and electrons can emit light having a second wavelength. In this case, the light-emitting mechanism of the second light-emitting layer 119b is a hybrid of electroluminescence and photoluminescence.

[0133] In the light-emitting diode chip of the first structure described above, an isolation structure may also be provided, and the isolation structure is located between the first region and the second region, and between the third region and the fourth region. It should be noted that in some embodiments, the isolation structure may only include a channel (CN), that is, the channel may not be filled with an isolation material. The channel may spatially isolate the first region and the second region, or the third region and the fourth region. As shown in Figures 7 and 8, the electrically insulating isolation material 116 filled in the channel CN ​​may be, for example, silicon nitride or silicon oxide. In some embodiments, the electrically insulating isolation material may also have a light-shielding effect, such as a black organic material, so that light mixing between the first sub-pixel and the second sub-pixel can be reduced or avoided, thereby improving the light-emitting effect of the light-emitting diode chip. In other embodiments, the isolation structure may also be an ion implantation layer, a structure having both electrical isolation and light-blocking effects formed by an ion implantation process. In the following embodiments, the isolation structure is the same as that described above, and will not be described in detail.

[0134] In the LED chips shown in Figures 1, 2, and 9, the first sub-pixel and the second sub-pixel are driven synchronously. In other embodiments, the first sub-pixel and the second sub-pixel can also be driven independently. The following describes an LED chip that can be driven independently.

[0135] As shown in Figures 3 and 4, as the structure of the second light-emitting diode chip, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first region away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

[0136] When the first P-type electrode and the N-type electrode are powered, the first and third regions can be independently driven to emit light. When the second P-type electrode and the N-type electrode are powered, the second and fourth regions can be independently driven to emit light. This allows the first and second sub-pixels to emit light independently.

[0137] As shown in Figures 5 to 8, as the structures of the third and fourth light-emitting diode chips, the N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, the first N-type electrode is electrically conductive to the surface of the third region facing away from the P-type electrode, and the second N-type electrode is electrically conductive to the surface of the fourth region facing away from the P-type electrode; the isolation structure is also located between the first N-type electrode and the second N-type electrode.

[0138] When the first N-type electrode and the P-type electrode are powered, the first and third regions can be independently driven to emit light. When the second N-type electrode and the P-type electrode are powered, the second and fourth regions can be independently driven to emit light. This allows the first and second sub-pixels to emit light independently.

[0139] The light-emitting diode chip also includes an N-type semiconductor layer 103 and a P-type semiconductor layer 105. The N-type semiconductor and the P-type semiconductor are respectively located on opposite sides of the thickness direction of the light-emitting layer. The N-type electrode is electrically connected to the light-emitting layer through the N-type semiconductor, and the P-type electrode is electrically connected to the light-emitting layer through the P-type semiconductor. In the above-mentioned discrete N-type electrode and discrete P-type electrode, the isolation structure can also have the following settings.

[0140] As shown in FIG8 , when the N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, at least a portion of the isolation structure extends into the P-type semiconductor layer 105. Alternatively, when the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, at least a portion of the isolation structure extends into the N-type semiconductor layer 103 (not shown). This can reduce the process difficulty and improve the isolation effect of the isolation structure on the first sub-pixel and the second sub-pixel.

[0141] 10 to 13 , in the light-emitting diode chip, the first light-emitting layer 119 a includes a first region and a second region, and the first region and at least a portion of the thickness of the second region are arranged side by side between the N-type electrode and the P-type electrode; the first region is stacked with the second light-emitting layer 119 b and is configured to form a second sub-pixel; and the second region is configured to form a first sub-pixel.

[0142] The surface of the first region facing away from the second light-emitting layer 119b is electrically connected to the P-type electrode, the surface of the second light-emitting layer 119b facing away from the first region is electrically connected to the N-type electrode, and the second region is electrically connected to the P-type electrode and the N-type electrode respectively.

[0143] It should be noted that the first region is arranged side by side with the second region, which covers at least part of its thickness, and the first region and the second light-emitting layer 119b are stacked. When both the N-type electrode and the P-type electrode are energized, the first and second regions emit light through the recombination of electrons and holes, and the luminescence mechanism of both regions is electroluminescence. Light emitted by the first region can excite the stacked second light-emitting layer 119b to emit light, and the luminescence mechanism of the second light-emitting layer 119b is photoluminescence.

[0144] In the aforementioned LED chip, a filter layer is further provided on the light-emitting side of the LED. The filter layer corresponds to the first region and transmits light of the second wavelength. The filter layer allows light of the second wavelength to pass through. This allows the second sub-pixel corresponding to the first region to emit light of the second wavelength, while the first sub-pixel corresponding to the second region directly emits light of the first wavelength.

[0145] 13 , a reflective layer 107 is further provided on the backlight side of the LED chip. The reflective layer 107 is located on the side of the P-type electrode away from the N-type electrode. The side of the N-type electrode away from the P-type electrode is the light-emitting side of the LED chip.

[0146] The light-emitting side of the LED chip is also provided with a light-blocking layer 118, located between two adjacent sub-pixels. This layer prevents light from mixing between the two sub-pixels, ensuring optimal light output from the LED chip. Since the filter layer is located on the light-emitting side of the LED chip, the light-blocking layer 118 can be positioned side by side with the filter layer.

[0147] A hole-blocking layer 117 is disposed between the first region of the first light-emitting layer 119a and the second light-emitting layer 119b of the LED chip. The combined thickness of the hole-blocking layer 117 and the first light-emitting layer 119a can be greater than the diffusion length of holes. Thus, the hole-blocking layer 117 can prevent holes from migrating into the second light-emitting layer 119b.

[0148] 10 , as a first feasible embodiment, the first region and the second region of partial thickness are arranged side by side, and the second light emitting layer 119 b and the second region of partial thickness are arranged side by side.

[0149] In the above embodiment, the LED chip further includes an isolation structure, which is located between the first region and the second region arranged side by side, and between the second light-emitting layer 119b and the second region arranged side by side. The isolation structure can structurally and electrically isolate the first region and the second region arranged side by side, and between the second light-emitting layer 119b and the second region arranged side by side, to ensure the light extraction effect of the LED. A second filter layer CF2 is provided on the side of the N-type electrode facing away from the P-type electrode, i.e., on the light-exiting side of the LED chip, and the second filter layer CF2 is opposite the second light-emitting layer 119b.

[0150] 10( a ), in some other embodiments, the second filter layer CF2 may not be provided on the light-emitting side of the LED chip.

[0151] As shown in FIG12 , as a second achievable embodiment, the first region and at least a portion of the thickness of the P-type electrode are arranged side by side, and the second light-emitting layer 119b is arranged side by side with at least a portion of the thickness of the second region. The LED chip also includes an isolation structure, which is located between the first region and at least a portion of the thickness of the P-type electrode, and between the second light-emitting layer 119b and the side-by-side second region. The isolation structure can form structural and electrical isolation between the first region and at least a portion of the thickness of the side-by-side P-type electrode, and between the second light-emitting layer 119b and the side-by-side second region, to ensure the light output effect of the LED.

[0152] The first sub-pixel and the second sub-pixel formed by the above-mentioned light emitting diode chip can be driven synchronously. In other embodiments, the first sub-pixel and the second sub-pixel can also be driven independently. The following describes a light emitting diode chip that can be driven independently.

[0153] As shown in Figure 11, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other. The first P-type electrode electrically conducts the surface of the first region facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode. When the first P-type electrode and the N-type electrode are in a powered-on state, the first region and the second light-emitting layer 119b can be independently driven to emit light. When the second P-type electrode and the N-type electrode are in a powered-on state, the second region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately. Among them, a second filter layer CF2 is provided on the side of the N-type electrode facing away from the P-type electrode, that is, the light-emitting side of the light-emitting diode chip, and the second filter layer CF2 is opposite to the second light-emitting layer 119b.

[0154] 11( a ), in some other embodiments, the second filter layer CF2 may not be provided on the light-emitting side of the LED chip.

[0155] As shown in Figure 12, the N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other. The first N-type electrode electrically conducts to the surface of the second light-emitting layer 119b facing away from the P-type electrode, and the second N-type electrode electrically conducts to the surface of the second region facing away from the P-type electrode. The isolation structure is also located between the first N-type electrode and the second N-type electrode. When the first N-type electrode and the P-type electrode are in an energized state, the first region and the second light-emitting layer 119b can be independently driven to emit light. When the second N-type electrode and the P-type electrode are in an energized state, the second region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can be made to emit light separately. Among them, a second filter layer CF2 is provided on the side of the N-type electrode facing away from the P-type electrode, that is, the light-emitting side of the light-emitting diode chip, and the second filter layer CF2 is opposite to the second light-emitting layer 119b.

[0156] 12( a ), in some other embodiments, the second filter layer CF2 may not be provided on the light-emitting side of the LED chip.

[0157] 14 to 22 , the second light-emitting layer 119 b includes a third region and a fourth region, and the third region and at least a portion of the thickness of the fourth region are arranged side by side between the N-type electrode and the P-type electrode; the third region is stacked with the first light-emitting layer 119 a and is configured to form a first sub-pixel; and the fourth region is configured to form a second sub-pixel.

[0158] The surface of the third region facing away from the first light-emitting layer 119a is electrically connected to the N-type electrode, the surface of the first light-emitting layer 119a facing away from the third region is electrically connected to the P-type electrode, and the fourth region is electrically connected to the P-type electrode and the N-type electrode respectively.

[0159] It should be noted that the third region is arranged side by side with at least a portion of the thickness of the fourth region, and the third region is stacked with the first light-emitting layer 119a. When both the N-type electrode and the P-type electrode are energized, the first light-emitting layer 119a and the fourth region emit light through the recombination of electrons and holes, and the luminescence mechanism of both is electroluminescence. Light emitted by the first light-emitting layer 119a can excite the stacked third region to emit light, and the luminescence mechanism of the third region is photoluminescence.

[0160] In the aforementioned LED chip, a filter layer is further provided on the light-emitting side of the LED. The filter layer corresponds to the third region and transmits light of the first wavelength. The filter layer allows light of the first wavelength to pass through. This allows the first sub-pixel corresponding to the third region to emit light of the first wavelength, while the second sub-pixel corresponding to the fourth region directly emits light of the second wavelength.

[0161] 22 , a reflective layer 107 is further provided on the backlight side of the LED chip. The reflective layer 107 is located on the side of the P-type electrode away from the N-type electrode. The side of the N-type electrode away from the P-type electrode is the light-emitting side of the LED chip.

[0162] The light-emitting side of the LED chip is also provided with a light-blocking layer 118, located between two adjacent sub-pixels. This layer prevents light from mixing between the two sub-pixels, ensuring optimal light output from the LED chip. Since the filter layer is located on the light-emitting side of the LED chip, the light-blocking layer 118 can be positioned side by side with the filter layer.

[0163] A hole-blocking layer 117 is disposed between the first light-emitting layer 119a and the third region of the second light-emitting layer 119b of the LED chip. The combined thickness of the hole-blocking layer 117 and the first light-emitting layer 119a can be greater than the diffusion length of holes. Thus, the hole-blocking layer 117 can prevent holes from migrating into the third region.

[0164] 16 , as a first feasible embodiment, the third region is arranged side by side with a fourth region of partial thickness, and the first light emitting layer 119 a is arranged side by side with another fourth region of partial thickness.

[0165] In the above embodiment, the LED chip further includes an isolation structure located between the third region and the fourth region arranged side by side, and between the first light-emitting layer 119a and the fourth region arranged side by side. The isolation structure can structurally and electrically isolate the third region and the fourth region, and between the first light-emitting layer 119a and the fourth region arranged side by side, thereby ensuring the light output efficiency of the LED.

[0166] 15 , the third region is arranged side by side with the fourth region of full thickness, and the first light emitting layer 119 a is arranged side by side with the P-type electrode of partial thickness.

[0167] In the above embodiment, the LED chip further includes an isolation structure located between the third region and the fourth region, and between the first light-emitting layer 119a and the P-type electrodes arranged side by side. The isolation structure can structurally and electrically isolate the third region from the fourth region, and between the first light-emitting layer 119a and the P-type electrodes arranged side by side, thereby ensuring the light output efficiency of the LED.

[0168] The first sub-pixel and the second sub-pixel formed by the above-mentioned light emitting diode chip can be driven synchronously. In other embodiments, the first sub-pixel and the second sub-pixel can also be driven independently. The following describes a light emitting diode chip that can be driven independently.

[0169] As shown in Figure 18, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other. The first P-type electrode electrically conducts the surface of the first light-emitting layer 119a facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the fourth region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode. When the first P-type electrode and the N-type electrode are in a powered-on state, the first light-emitting layer 119a and the third region can be independently driven to emit light. When the second P-type electrode and the N-type electrode are in a powered-on state, the fourth region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately. Among them, the light-emitting side of the light-emitting diode chip is located on the side of the N-type electrode facing away from the P-type electrode, and a first filter layer CF1 can be provided on the side of the N-type electrode facing away from the P-type electrode.

[0170] In other embodiments, as shown in Figure 19, the first filter layer CF1 may not be provided on the side of the N-type electrode facing away from the P-type electrode. In this case, the light emitting side of the LED chip is located on the side of the P-type electrode facing away from the N-type electrode.

[0171] As shown in Figure 20, the N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other. The first N-type electrode is electrically conductive to the surface of the third region facing away from the P-type electrode, and the second N-type electrode is electrically conductive to the surface of the fourth region facing away from the P-type electrode. An isolation structure is also located between the first N-type electrode and the second N-type electrode. When the first N-type electrode and the P-type electrode are in an energized state, the first light-emitting layer 119a and the third region can be independently driven to emit light. When the second N-type electrode and the P-type electrode are in an energized state, the fourth region can be independently driven to emit light. In this way, the first sub-pixel and the second sub-pixel can emit light separately.

[0172] 23 to 26 , the light emitting layer further includes a third light emitting layer 119 c having a third light emitting wavelength, which is shorter than the first light emitting wavelength.

[0173] Along the thickness direction of the light-emitting diode chip, the third light-emitting layer 119c is stacked with at least one of the first light-emitting layer 119a and the second light-emitting layer 119b; in the stacking area, the third light-emitting layer 119c is located on the side of the corresponding stacked light-emitting layer close to the P-type electrode, and the light emitted by the third light-emitting layer 119c is used to excite the corresponding stacked light-emitting layer to emit light.

[0174] It should be noted that the third light-emitting layer 119c may also be selected from one of a red light-emitting material layer, a green light-emitting material layer, a blue light-emitting material layer, a purple light-emitting material layer, and an ultraviolet light-emitting material layer, as long as the third light-emitting wavelength is shorter than the first light-emitting wavelength and the second light-emitting wavelength. In other embodiments, the first light-emitting layer 119a, the second light-emitting layer 119b, and the third light-emitting layer 119c may also be selected from light-emitting material layers of other wavelengths, as long as the relationship between the three light-emitting wavelengths is maintained. This embodiment does not limit this.

[0175] The third light-emitting layer 119c can be stacked only with the first light-emitting layer 119a to excite the first light-emitting layer 119a to emit light. The third light-emitting layer 119c can also be stacked only with the second light-emitting layer 119b to excite the second light-emitting layer 119b to emit light.

[0176] In some embodiments, at least a portion of the third light-emitting layer 119c is stacked with the first light-emitting layer 119a and the second light-emitting layer 119b. In the stacked first light-emitting layer 119a, the second light-emitting layer 119b, and the third light-emitting layer 119c, the third light-emitting layer 119c, the first light-emitting layer 119a, and the second light-emitting layer 119b are arranged sequentially along the direction from the P-type electrode to the N-type electrode. The light emitted by the third light-emitting layer 119c is used to excite the first light-emitting layer 119a and the second light-emitting layer 119b to emit light.

[0177] Figure 23 shows that the first, second, and third light-emitting layers 119a, 119b, and 119c are all stacked. The third light-emitting layer 119c is electroluminescent, while the second and third light-emitting layers 119b, 119c are photoluminescent. The light-emitting side of the LED chip can be equipped with a first filter layer CF1 and a second filter layer CF2, each of which passes through different wavelengths. This allows light to be emitted at two different wavelengths, forming a first sub-pixel and a second sub-pixel, respectively.

[0178] Figure 24 shows a stacked arrangement of the third light-emitting layer 119c, the first region of the first light-emitting layer 119a, and the second light-emitting layer 119b. The third light-emitting layer 119c is stacked with the second region of the first light-emitting layer 119a. On the light-emitting side of the LED chip, a filter layer can be provided at a location corresponding to the second light-emitting layer 119b. The filter layer transmits light of the second wavelength. The location corresponding to the filter layer can emit light of the second wavelength, thereby forming a second sub-pixel. The location corresponding to the second region of the first light-emitting layer 119a can emit light of the first wavelength, thereby forming a first sub-pixel.

[0179] Figure 25 shows a stacked arrangement of the third light-emitting layer 119c, the first light-emitting layer 119a, and the third region of the second light-emitting layer 119b. The third light-emitting layer 119c and the fourth region of the second light-emitting layer 119b are stacked. On the light-emitting side of the LED chip, a filter layer can be provided at a location corresponding to the first light-emitting layer 119a. The filter layer transmits light of the first wavelength. The location corresponding to the filter layer can emit light of the first wavelength, thereby forming a first sub-pixel. The location corresponding to the fourth region of the second light-emitting layer 119b can emit light of the second wavelength, thereby forming a second sub-pixel.

[0180] 26 , the LED chip further includes a reflective layer 107 located on the backlight side of the LED chip. The reflective layer 107 is located on the side of the P-type electrode facing away from the N-type electrode, which forms the light-emitting side of the LED chip.

[0181] The aforementioned LED chip also includes a light-blocking layer 118, which is located on the light-emitting side of the LED chip and between two adjacent sub-pixels. This layer prevents light from mixing between the two sub-pixels, ensuring optimal light output from the LED chip. Since the first filter layer CF1 and the second filter layer CF2 are located on the light-emitting side of the LED chip, the light-blocking layer 118 can be located between them.

[0182] The LED chip also includes a hole-blocking layer 117, which is disposed between any two adjacent layers of the stacked first, second, and third light-emitting layers 119a, 119b, and 119c. The combined thickness of the hole-blocking layer 117 and the third light-emitting layer 119c can be greater than the diffusion length of holes. Thus, the hole-blocking layer 117 can prevent holes from migrating into the first and second light-emitting layers 119a, 119b.

[0183] The LED chip with the third light-emitting layer 119c can also be driven independently. Specifically, the N-type electrode can be configured as a separate first N-type electrode and a second N-type electrode, or the P-type electrode can be configured as a separate first P-type electrode and a second P-type electrode. In this separate configuration, an isolation structure can also be provided. The specific structure can be referenced to the above-described embodiment and will not be elaborated upon here.

[0184] In the light-emitting diode chip provided in the embodiment of the present application, the above-mentioned at least two sub-pixels can form a pixel subgroup or multiple pixel subgroups; the same pixel subgroup includes multiple sub-pixels, and among the multiple sub-pixels, the number of first sub-pixels and the number of second sub-pixels are equal or different.

[0185] It should be noted that the number of the first sub-pixel and the second sub-pixel can both be one. Alternatively, the number of both can be two, three, or four. Taking Figure 27 as an example, the four sub-pixels all belong to the same pixel sub-group, wherein the number of the first sub-pixel B can be three and the number of the second sub-pixel G can be one. Taking Figure 28 as an example, the four sub-pixels all belong to the same pixel sub-group, wherein the number of the second sub-pixel G can be three and the number of the first sub-pixel B can be one. This application does not limit the number of first sub-pixels and second sub-pixels in the same pixel sub-group.

[0186] Exemplarily, the number of sub-pixels in the pixel subgroup may be a positive integer greater than or equal to 2, and may be an odd number greater than 2, i.e., 3, 5, or 7. Exemplarily, the number of sub-pixels in the pixel subgroup may be an even number greater than or equal to 2, i.e., 2*N (see FIG. 47 ), where N is a positive integer greater than or equal to 1. For example, the number of sub-pixels in the pixel subgroup may be 2*10, 2*100, or 2*1000, etc.

[0187] In some embodiments, the sub-pixel shape is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides. Different sub-pixels may have the same or different shapes. That is, the first sub-pixel B and the second sub-pixel G may both be rectangular as shown in FIG. 1 or FIG. 3 .

[0188] In some embodiments, the shape of the LED chip can be any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram, and a polygon with more than four sides. When a plurality of LED chips form an LED chip group, the shapes of the different LED chips can be the same or different.

[0189] In some embodiments, the sizes of different sub-pixels are equal or different. The size of a sub-pixel affects its luminous area. That is, the luminous areas of different sub-pixels can be equal or different. The sizes of different sub-pixels can be adjusted according to the brightness attenuation of the sub-pixels. For example, if the brightness attenuation rate of a certain sub-pixel is large, the size of the sub-pixel can be appropriately increased to ensure uniform light output requirements. The sizes of different sub-pixels can also be adjusted according to whether the sub-pixels are shared between different pixel units (PU for short). For example, as shown in Figure 51, sub-pixel (B) and sub-pixel (R) are shared by two pixel units respectively in the process of forming pixel units PU1 and PU2, while sub-pixel (G) is not shared, but all belong to pixel unit PU1. Therefore, the sizes of sub-pixel (B) and sub-pixel (R) are larger than the size of sub-pixel (G). In this way, the luminous brightness of the shared sub-pixels in each pixel unit can be guaranteed.

[0190] It should be pointed out that the above-mentioned "size" can be understood as the extension length of the sub-pixel in a certain extension direction, for example, it can be the length or width of a rectangular sub-pixel, the major axis length or minor axis length of an elliptical sub-pixel, or the diameter of a circular sub-pixel, etc.

[0191] In some embodiments, the size of the pixel subgroup is greater than or equal to 50 microns. The size of the LED chip composed of the pixel subgroup may also be greater than or equal to 50 microns. For example, it may be 50-100 microns, or 100-150 microns, or greater than 150 microns. Of course, in some embodiments, the size of the LED chip may also be less than 50 microns. The size of the LED chip can be selected according to different usage scenarios.

[0192] In some embodiments, the sub-pixel size ranges from 0.001 to 200 microns. When the sub-pixel size is between 0.001 microns and 0.1 microns, the sub-pixel size is at the nanometer level, representing a nano-LED. During the nano-LED manufacturing process, the single-core, dual-color, multi-sub-pixel arrangement of the present application can be referenced, thereby facilitating an increase in the size of a single nano-LED chip containing multiple sub-pixels, bringing the size of the single chip close to or within the size range of LED chips currently accessible by mass transfer processes. This reduces the operational difficulty of the nano-LED manufacturing process and improves its operability.

[0193] In other embodiments, for example, a LED chip with 2*2 sub-pixels for large televisions can have a single sub-pixel size of 50 microns, with a spacing of 10 microns between two adjacent sub-pixels. The LED chip has a length and width of 110 microns, resulting in a size of 110*110 microns. LED chips of this size can utilize mini LED packaging processes.

[0194] The size of the LED chip and the size of the sub-pixel may vary depending on the usage scenario of the LED chip. Below, exemplary descriptions of the size of the LED chip and the size of the sub-pixel in different usage scenarios are given.

[0195] When the LED chip is used in display products such as home televisions and desktop computers, at a pixel density of 50-150, the size (pitch) of a pixel unit composed of several sub-pixels in multiple LED chips can be 150-700 microns, the size (sub pitch) of the sub-pixels in the LED chip can be less than 250 microns, and the size of the LED chip can be greater than 100 microns.

[0196] When the LED chip is used in display products such as laptops and tablets, when the pixel density is 150-250, the sub-pixel size can be less than 70 microns, the pixel unit size is 100-200 microns, and the LED chip size can be greater than 60 microns.

[0197] When the LED chip is used in display products such as mobile phones and electronic watches, when the pixel density is greater than 300, the sub-pixel size can be less than 30 microns, the pixel unit size is less than 100 microns, and the LED chip size can be greater than 50 microns.

[0198] Based on this, the light-emitting diode chip provided in the embodiment of the present application adopts a single-core, dual-color, multi-sub-pixel arrangement. The size of the sub-pixels and the size range of the light-emitting diode chip are relatively large, which can be applied to different usage scenarios, thereby increasing the applicability of the light-emitting diode chip.

[0199] 29 to 31 , the LED chip may include two pixel subgroups. In other embodiments, the LED chip may include three, four, five, or more pixel subgroups. Taking two pixel subgroups as an example, each pixel subgroup includes a first subpixel B and a second subpixel G. The first direction is the direction indicated by x in the figures, and the second direction is the direction indicated by y in the figures.

[0200] The pixel subgroups include a first pixel subgroup and a second pixel subgroup. The first subpixel B in the first pixel subgroup and the first subpixel B in the second pixel subgroup emit light at the same wavelength. The second subpixel G in the first pixel subgroup and the second subpixel G in the second pixel subgroup emit light at the same wavelength. Figures 29 to 31 each include two rows of subpixels, with the two subpixels in the first row forming the first pixel subgroup and the two subpixels in the second row forming the second pixel subgroup.

[0201] Optionally, as shown in FIG. 29 , along the first direction, the first subpixel B of the first pixel subgroup corresponds to the first subpixel B of the second pixel subgroup, and the second subpixel G of the first pixel subgroup corresponds to the second subpixel G of the second pixel subgroup.

[0202] Optionally, as shown in FIG30 , the first subpixel B of the first pixel subgroup corresponds to the second subpixel G of the second pixel subgroup, and the second subpixel G of the first pixel subgroup corresponds to the first subpixel B of the second pixel subgroup.

[0203] In the embodiment of the present application, the driving modes of the two pixel subgroups may include simultaneous driving and independent driving. The different arrangement structures of these two driving modes are described in detail below.

[0204] Optionally, the light-emitting diode chip includes an N-type electrode and a P-type electrode, and all sub-pixels in the two pixel subgroups are in contact with the N-type electrode and the P-type electrode, respectively, thereby achieving simultaneous driving of multiple sub-pixels.

[0205] Optionally, the N-type electrode includes at least two separate sub-N-type electrodes, with the number of sub-N-type electrodes being the same as the number of sub-pixels; a side of each sub-pixel facing away from the P-type electrode contacts a corresponding sub-N-type electrode; and a side of each sub-pixel facing away from the N-type electrode contacts the P-type electrode. In this way, when the multiple N-type electrodes are each energized and the P-type electrode is also energized, the multiple sub-pixels can be independently driven.

[0206] Optionally, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of sub-P-type electrodes is the same as the number of sub-pixels; the side of a sub-pixel facing away from the N-type electrode contacts a corresponding sub-P-type electrode; and the side of the sub-pixel facing away from the P-type electrode contacts the N-type electrode. In this way, when multiple P-type electrodes are respectively in a powered-on state and the N-type electrode is in a powered-on state, independent driving of multiple sub-pixels can be achieved. As shown in Figures 29 and 30, four sub-P-type electrodes are included, namely sub-P-type electrode P11, sub-P-type electrode P12, sub-P-type electrode P21 and sub-P-type electrode P22. The four sub-P-type electrodes are respectively connected to four sub-pixels, and the four sub-pixels are all connected to the N-type electrode.

[0207] In some embodiments, when the size of the entire LED chip is large and the conductivity of a single electrode is not high, if all sub-pixels share the same electrode, such as a P-type electrode or an N-type electrode, the sub-pixels in some areas will have lower luminance and uneven luminous effect of the entire LED chip. Therefore, the present application divides all sub-pixels of the entire LED chip into multiple areas and configures the sub-pixels in the same area to share electrodes. In this way, sub-pixels in the same area share one electrode, which can ensure uniform luminous effect of the sub-pixels in multiple areas and the entire LED chip, compared to sub-pixels in all areas sharing the same electrode.

[0208] Exemplarily, the N-type electrode includes at least two separate sub-N-type electrodes, with the number of sub-N-type electrodes being the same as the number of sub-pixels; the P-type electrode includes at least two separate sub-P-type electrodes, with the number of sub-P-type electrodes being less than the number of sub-pixels; the side of a sub-pixel facing away from the P-type electrode contacts a corresponding N-type sub-electrode, while the sides of a portion of the sub-pixels facing away from the N-type electrode contact the same P-type sub-electrode. That is, while multiple sub-pixels are independently driven, multiple sub-pixels in a portion of the area can share a single P-type sub-electrode.

[0209] In another exemplary embodiment, as shown in FIG31 , the P-type electrode includes at least two separate sub-P-type electrodes, the number of which is the same as the number of sub-pixels; the N-type electrode includes at least two separate sub-N-type electrodes, the number of which is less than the number of sub-pixels; the side of each sub-pixel facing away from the N-type electrode contacts a corresponding sub-P-type electrode, while the sides of a portion of the sub-pixels facing away from the P-type electrode contact the same sub-N-type electrode. FIG31 shows four sub-P-type electrodes and two sub-N-type electrodes, namely, sub-P-type electrode P11, sub-P-type electrode P12, sub-P-type electrode P21, and sub-P-type electrode P22, as well as sub-N-type electrode N1 and sub-N-type electrode N2. The first sub-pixel of the first pixel subgroup contacts sub-P-type electrode P11, the second sub-pixel contacts sub-P-type electrode P21, and both contact sub-N-type electrode N1. The first sub-pixel of the second pixel subgroup contacts sub-P-type electrode P22, and the second sub-pixel contacts sub-P-type electrode P12, and both contact sub-N-type electrode N2. In this way, all sub-pixels of the first pixel subgroup share one sub-N-type electrode, and all sub-pixels of the second pixel subgroup share another sub-N-type electrode, thereby ensuring the light uniformity of the entire LED chip.

[0210] In some embodiments, as shown in Figures 34 to 36, the light-emitting diode chip can also be a monochrome multi-sub-pixel chip. That is, the light-emitting layer includes multiple monochrome sub-pixels. For example, the light-emitting layer of the light-emitting diode chip C1 may include 4 sub-pixels B (Figure 34), or the light-emitting layer of the light-emitting diode chip C2 may include 4 sub-pixels G (Figure 35), or the light-emitting layer of the light-emitting diode chip C3 may include 4 sub-pixels R (Figure 36). In other embodiments, the number of monochrome sub-pixels of the light-emitting layer can be adjusted to 2, 3, 5 or more. Combining multiple monochrome sub-pixels to form a light-emitting diode chip can also flexibly adjust the size of the light-emitting diode chip.

[0211] The above details the structure and arrangement of the N-type electrode, the P-type electrode, and the light-emitting layer in the light-emitting diode chip. The following details other structures and arrangements of the light-emitting diode chip.

[0212] As shown in Figure 37, the light-emitting diode chip provided in an embodiment of the present application further includes a buffer layer 101, an N-type semiconductor layer 103, a P-type semiconductor layer 105, a current spreading layer 106, a reflective layer 107, and a first insulating layer 108. The buffer layer 101 and the N-type semiconductor layer 103 are stacked, with the light-emitting layer disposed on the side of the N-type semiconductor layer 103 facing away from the buffer layer 101, and the P-type semiconductor layer 105 disposed on the side of the light-emitting layer facing away from the buffer layer 101. The current spreading layer 106 contacts the side of the P-type semiconductor layer 105 facing away from the buffer layer 101, the N-type electrode 102 contacts the N-type semiconductor layer 103, and the P-type electrode 104 contacts the P-type semiconductor layer 105 and the current spreading layer 106. The first insulating layer 108 is disposed on the side of the current spreading layer 106 and a portion of the N-type semiconductor layer 103 facing away from the buffer layer 101. This creates a light-emitting diode chip with a thin-film flip-chip structure. The light-emitting layer includes a stacked first light-emitting layer 119a and a second light-emitting layer 119b.

[0213] Optionally, the reflective layer 107 is disposed on a side of the buffer layer 101 away from the light-emitting layer, so that the light emitting direction of the light-emitting diode chip is toward a direction away from the buffer layer 101 .

[0214] Optionally, as shown in Figure 37 , a reflective layer 107 is disposed on the side of the first insulating layer 108 facing away from the buffer layer 101. A second insulating layer 109 is also disposed on the side of the reflective layer 107 facing away from the buffer layer 101. In this way, light from the LED chip is directed toward the buffer layer 101, i.e., in the direction of the downward arrow shown in the figure. A first filter layer 114 and a second filter layer 115 are disposed at the bottom of the buffer layer 101, with a light-blocking layer 118 disposed between the first filter layer 114 and the second filter layer 115.

[0215] The buffer layer 101 can be made of one or more of gallium nitride, aluminum gallium nitride, and aluminum indium gallium nitride, and can have a thickness of 10-40 nanometers. The N-type semiconductor layer 103 can be made of N-type doped gallium nitride, and the P-type semiconductor layer 105 can be made of P-type doped gallium nitride. The current spreading layer 106 can be made of a transparent conductive material (indium tin oxide, ITO) or silver, and its function is to improve the distribution of the P-type electrode, ensuring that holes are distributed as evenly as possible in the area where the P-type semiconductor layer 105 is located. The first insulating layer 108 can be made of silicon oxide or silicon nitride.

[0216] 38 and 39 , based on the aforementioned thin-film LED chip, this LED chip further includes a substrate 100, which is disposed on the side of the buffer layer 101 facing away from the light-emitting layer. The material of substrate 100 can be a composite of one or more of sapphire, gallium nitride, aluminum nitride, silicon, and silicon carbide.

[0217] As shown in Figure 38 , when reflective layer 107 is disposed on the side of buffer layer 101 facing away from the light-emitting layer, reflective layer 107 is disposed on the side of substrate 100 facing away from buffer layer 101. The light emission direction in Figure 38 is the upward direction indicated by the arrow in the figure, forming a face-up structure LED chip. The first filter layer 114 and the second filter layer 115 are disposed on top of the first insulating layer 108. A light-blocking layer 118 may be disposed adjacent to the first filter layer 114 and the second filter layer 115. Light-blocking layer 118 is located on the side of the first filter layer 114 and the second filter layer 115 facing away from substrate 100. The light emission direction in Figure 39 is the downward direction indicated by the arrow in the figure, forming a flip-chip structure LED chip. The first filter layer 114 and the second filter layer 115 are disposed on the bottom of substrate 100, with light-blocking layer 118 located between them.

[0218] As shown in Figure 40, the light-emitting diode chip may also include a bonding substrate 110, a binding layer 111, an N-type semiconductor layer 103, a P-type semiconductor layer 105 and a reflective layer 107; the bonding substrate 110 and the binding layer 111 are sequentially arranged on the P-type electrode 104, the P-type semiconductor layer 105 is arranged on the side of the binding layer 111 away from the bonding substrate 110, and is in contact with the binding layer 111; the light-emitting layer is arranged on the side of the P-type semiconductor layer 105 away from the bonding substrate 110, the N-type semiconductor layer 103 is arranged on the side of the light-emitting layer away from the bonding substrate 110, and the N-type electrode 102 contacts the side of the N-type semiconductor layer 103 away from the bonding substrate 110; the reflective layer 107 is arranged on the side of the P-type semiconductor layer 105 close to the bonding substrate 110. The first filter layer 114 and the second filter layer 115 are disposed on top of the first insulating layer 108. A light-blocking layer 118 may be disposed adjacent to the first filter layer 114 and the second filter layer 115. The light-blocking layer 118 is located on the side of the first filter layer 114 and the second filter layer 115 facing away from the bonding substrate 110. The light emission direction of the LED chip may be upward, as indicated by the arrow in the figure, forming a vertically structured LED chip.

[0219] In a second aspect, an embodiment of the present application provides a method for preparing a light-emitting diode chip, which can be used to prepare the light-emitting diode chip described above.

[0220] As a first method for preparing a light-emitting diode chip, as shown in FIG41 , a first region of a first light-emitting layer 119a and a second light-emitting layer 119b are stacked, and a first sub-pixel and a second sub-pixel formed by the first light-emitting layer 119a and the second light-emitting layer 119b are synchronously driven. Specifically, the preparation method includes:

[0221] A substrate 100 is formed by a deposition process ( FIG41 (a) ); a buffer layer 101, an N-type semiconductor layer 103, and a second light-emitting layer 119b are sequentially formed on the substrate 100 by an epitaxial growth process ( FIG41 (b) ); the second light-emitting layer 119b in the fourth region is removed by a patterning process to expose a portion of the top surface of the N-type semiconductor layer 103 ( FIG41 (c) ); a first light-emitting layer 119a covering the second light-emitting layer 119b and the N-type semiconductor layer 103 is formed by an epitaxial growth process ( FIG41 (d) ); a P-type semiconductor layer 105 covering the first light-emitting layer 119a is formed by an epitaxial growth process ( FIG41 (e) ); a step is formed ( FIG41 (f) ); and a patterned current spreading layer 106 is formed ( FIG41 (f) ). 1(g)); forming a patterned first insulating layer 108 covering the current spreading layer 106, with a portion of the first insulating layer 108 located at the step (Figure 41(h)); forming a patterned reflective layer 107 covering the first insulating layer 108 (Figure 41(i)); forming a patterned second insulating layer 109 covering the reflective layer 107 (Figure 41(j)); forming an N-type electrode 102 and a P-type electrode 104 (Figure 41(k)); and forming a second filter layer 115 and a light-blocking layer 118 on the side of the substrate 100 facing away from the reflective layer 107 (Figure 41(l)). The second filter layer 115 can be formed first and the light-blocking layer 118 can be formed later, or the order of forming the two can be reversed, which is not limited in this embodiment. In the following embodiments, the order of forming the light-blocking layer 118 and the second filter layer 115 can be the same, which will not be repeated.

[0222] The second filter layer 115 may not be formed.

[0223] As a second method for preparing a light-emitting diode chip, as shown in FIG42 , a first region of a first light-emitting layer 119a and a second light-emitting layer 119b are stacked, with an isolation structure formed therebetween. The first sub-pixel and the second sub-pixel formed by the first light-emitting layer 119a and the second light-emitting layer 119b are independently driven (the isolation material filled in the trench is not shown in the figure). Specifically, the preparation method includes:

[0224] A substrate 100 is formed by a deposition process (FIG. 42(a)); a buffer layer 101, an N-type semiconductor layer 103, and a second light-emitting layer 119b are sequentially formed on the substrate 100 by an epitaxial growth process (FIG. 42(b)); the second light-emitting layer 119b in the fourth region is removed by a patterning process to expose a portion of the top surface of the N-type semiconductor layer 103 (FIG. 42(c)); a first light-emitting layer 119a covering the second light-emitting layer 119b and the N-type semiconductor layer 103 is formed by an epitaxial growth process (FIG. 42(d)); a P-type semiconductor layer 105 covering the first light-emitting layer 119a is formed by an epitaxial growth process (FIG. 42(e)); a step is formed. and a channel (FIG. 42(f)); forming a patterned current spreading layer 106 (FIG. 42(g)); forming a patterned first insulating layer 108 covering the current spreading layer 106, with part of the first insulating layer 108 being located at a step (FIG. 42(h)); forming a patterned reflective layer 107 covering the first insulating layer 108 (FIG. 42(i)); forming a patterned second insulating layer 109 covering the reflective layer 107 (FIG. 42(j)); forming an N-type electrode 102 and a P-type electrode 104 (FIG. 42(k)); and forming a second filter layer 115 and a light-blocking layer 118 on the side of the substrate 100 facing away from the reflective layer 107 (FIG. 42(l)).

[0225] The second filter layer 115 may not be formed.

[0226] As a third method for preparing a light-emitting diode chip, as shown in FIG43 , a first light-emitting layer 119a and a second light-emitting layer 119b can be stacked without forming an isolation structure therebetween, and a first sub-pixel and a second sub-pixel formed by the first light-emitting layer 119a and the second light-emitting layer 119b are driven simultaneously. Specifically, the preparation method includes:

[0227] A substrate 100 is formed by a deposition process (FIG. 43(a)); a buffer layer 101, an N-type semiconductor layer 103, a second light-emitting layer 119b, a first light-emitting layer 119a, and a P-type semiconductor layer 105 are sequentially formed on the substrate 100 by an epitaxial growth process (FIG. 43(b)); a step is formed (FIG. 43(c)); a patterned current spreading layer 106 is formed (FIG. 43(d)); a patterned first insulating layer 108 covering the current spreading layer 106 is formed, and a portion of the first insulating layer 108 is formed. The insulating layer 108 is located at the step (Figure 43(e)); a patterned reflective layer 107 covering the first insulating layer 108 is formed (Figure 43(f)); a patterned second insulating layer 109 covering the reflective layer 107 is formed (Figure 43(g)); an N-type electrode 102 and a P-type electrode 104 are formed (Figure 43(h)); and a first filter layer 114, a second filter layer 115 and a light-blocking layer 118 are formed on the side of the substrate 100 facing away from the reflective layer 107 (Figure 43(i)).

[0228] As a fourth method for preparing a light-emitting diode chip, as shown in FIG44 , a first light-emitting layer 119a and a second light-emitting layer 119b can be stacked, with an isolation structure formed between them. The first light-emitting layer 119a and the second light-emitting layer 119b are stacked and independently driven. (The isolation material filled in the trench is not shown in the figure.) Specifically, the preparation method includes:

[0229] A substrate 100 is formed by a deposition process (FIG. 44(a)); a buffer layer 101, an N-type semiconductor layer 103, a second light-emitting layer 119b, a first light-emitting layer 119a, and a P-type semiconductor layer 105 are sequentially formed on the substrate 100 by an epitaxial growth process (FIG. 44(b)); steps and channels are formed (FIG. 44(c)); a patterned current spreading layer 106 is formed (FIG. 44(d)); a patterned first insulating layer 108 covering the current spreading layer 106 is formed, and a portion of the first insulating layer 108 is formed. The first insulating layer 108 is located at the step (Figure 44(e)); a patterned reflective layer 107 covering the first insulating layer 108 is formed (Figure 44(f)); a patterned second insulating layer 109 covering the reflective layer 107 is formed (Figure 44(g)); an N-type electrode 102 and a P-type electrode 104 are formed (Figure 44(h)); and a first filter layer 114, a second filter layer 115 and a light-blocking layer 118 are formed on the side of the substrate 100 facing away from the reflective layer 107 (Figure 44(i)).

[0230] As shown in FIG45 , in some embodiments, the LED chip may further include a color conversion layer 112. The color conversion layer 112 is disposed on a portion of the light-emitting side of the LED chip and corresponds to at least a portion of the sub-pixel. The orthographic projection of the color conversion layer 112 on the surface where the corresponding sub-pixel resides may cover the entire area of ​​a single sub-pixel or only a portion of the area of ​​a single sub-pixel. The material of the color conversion layer 112 may be a quantum dot material, a phosphor material, or the like. The use of the color conversion layer 112 can adjust the wavelength of light emitted by the LED chip, enriching its light emission wavelength variety.

[0231] Taking a LED chip with a front-mounted structure as an example, the first sub-pixel SP1, the second sub-pixel SP2, and the color conversion layer 112 each emit light at different wavelengths. Thus, the color conversion layer 112 is positioned on the light-emitting side of the second sub-pixel SP2, facing a portion of the second sub-pixel SP2. This allows the color conversion layer 112 to convert a portion of the light emitted from the second sub-pixel SP2 into light of a third wavelength, in addition to the first wavelength of the first sub-pixel SP1 and the second wavelength of the second sub-pixel SP2. Therefore, the LED chip can emit light of the first, second, and third wavelengths. The light emission direction in Figure 45 is the upward direction indicated by the arrow in the figure.

[0232] In a third aspect, an embodiment of the present application provides a light-emitting diode chip group, comprising a plurality of the above-mentioned light-emitting diode chips, wherein the plurality of light-emitting diode chips are arranged in an array; two adjacent light-emitting diode chips include a first light-emitting diode chip and a second light-emitting diode chip, and a portion of the sub-pixels of the first light-emitting diode chip and a portion of the sub-pixels of the second light-emitting diode chip together constitute a pixel unit. It should be noted that the portion of the sub-pixels in the first light-emitting diode chip and the second light-emitting diode chip that constitute the pixel unit may be all or part of the sub-pixels in the same pixel subgroup. Optionally, the light-emitting wavelengths of the two sub-pixels of the first light-emitting diode chip and the one sub-pixel of the second light-emitting diode chip are different. In this way, a pixel unit with multiple light-emitting wavelengths can be formed.

[0233] In the following, the embodiment in which different LED chips are arranged in different ways to form pixel units and the dual-color multi-sub-pixel LED chips form a chipset will be described in detail.

[0234] As a first feasible implementation method, the entire area of ​​two sub-pixels of the first light-emitting diode chip and the entire area of ​​one sub-pixel of the second light-emitting diode chip together constitute a pixel unit. The starting sub-pixel can be any one, such as R, B, or G, and the arrangement order of the sub-pixels in the pixel unit can be changed arbitrarily.

[0235] For example, as shown in FIG46 , a first LED chip includes two pixel subgroups, i.e., two pixel subgroups in the first column, the pixel subgroup in the first row includes the first subpixel B and the second subpixel G, and the pixel subgroup in the second row includes the third subpixel B and the fourth subpixel G. A second LED chip includes two pixel subgroups, i.e., two pixel subgroups in the second column, the pixel subgroup in the first row includes the first subpixel R and the second subpixel B, and the pixel subgroup in the second row includes the third subpixel R and the fourth subpixel B.

[0236] In the above example, the first LED chip and the second LED chip form a pixel unit. The first sub-pixel B and the second sub-pixel G in the first row of the first LED chip, together with the first sub-pixel R in the first row of the second LED chip, form pixel unit PU1. According to this arrangement, the first LED chip and the second LED chip also form pixel unit PU2.

[0237] The light-emitting diode chip group can also include a third light-emitting diode chip. Continuing with reference to Figure 46, the third light-emitting diode chip includes two pixel subgroups, namely, two pixel subgroups in the third column. The pixel subgroup in the first row includes the first subpixel G and the second subpixel R, and the pixel subgroup in the second row includes the third subpixel G and the fourth subpixel R.

[0238] The second LED chip and the third LED chip form a pixel unit. The second sub-pixel B in the first row of the second LED chip and the first sub-pixel G and second sub-pixel R in the first row of the third LED chip together form pixel unit PU3. According to this arrangement, the second LED chip and the third LED chip also form pixel unit PU4.

[0239] 47 and 48 , in the above-mentioned arrangement, the light-emitting diode chip includes three pixel subgroups ( FIG. 47 ), or four pixel subgroups (not shown in the figure), or five pixel subgroups ( FIG. 48 shows five pixel subgroups, and subsequent ellipsis indicates more pixel subgroups), or even more pixel subgroups can form a pixel unit.

[0240] The aforementioned pixel unit PU1, pixel unit PU2, pixel unit PU3, and pixel unit PU4 together constitute a chipset CG1. According to the aforementioned arrangement, a chipset CG2 can be formed. Figures 46 to 48 each illustrate two chipsets, namely, chipset CG1 and chipset CG2. The arrangement of chipset CG1 and chipset CG2 can be the same, and the arrangement of the pixel units formed therein can also be the same. In other embodiments, the arrangement of chipset CG1 and chipset CG2 can also be different, and the arrangement of the pixel units formed therein can also be different.

[0241] In some embodiments, the arrangement of sub-pixels in the first LED chip, the second LED chip, and the third LED chip may differ from the above-described embodiment. Examples of different arrangements of sub-pixels in the first LED chip, the second LED chip, and the third LED chip are provided below.

[0242] As shown in FIG49 , in some embodiments, in a first LED chip in a first column, the pixel subgroup in the first row includes a first subpixel G and a second subpixel R. The pixel subgroup in the second row includes a first subpixel G and a second subpixel R. In a second LED chip in a second column, the pixel subgroup in the first row includes a first subpixel B and a second subpixel G, and the pixel subgroup in the second row includes a first subpixel B and a second subpixel G. In a third LED chip in a third column, the pixel subgroup in the first row includes a first subpixel R and a second subpixel B, and the pixel subgroup in the second row includes a first subpixel R and a second subpixel B. Thus, the first subpixel G and the second subpixel R in the pixel subgroup in the first row of the first LED chip, together with the first subpixel B in the pixel subgroup in the first row of the second LED chip, form pixel unit PU1. In this manner, pixel unit PU2, pixel unit PU3, and pixel unit PU4 can be formed. The subpixels and pixel units of chip groups CG1 and CG2 are arranged in the same manner.

[0243] As shown in FIG50 , in some embodiments, in a first LED chip in a first column, the pixel subgroups in the first row include a first subpixel R and a second subpixel B. The pixel subgroups in the second row include a first subpixel R and a second subpixel B. In a second LED chip in a second column, the pixel subgroups in the first row include a first subpixel G and a second subpixel R, and the pixel subgroups in the second row include a first subpixel G and a second subpixel R. In a third LED chip in a third column, the pixel subgroups in the first row include a first subpixel B and a second subpixel G, and the pixel subgroups in the second row include a first subpixel B and a second subpixel G. Thus, the first subpixel R and the second subpixel B in the pixel subgroup in the first row of the first LED chip, together with the first subpixel G in the pixel subgroup in the first row of the second LED chip, form pixel unit PU1. In this manner, pixel unit PU2, pixel unit PU3, and pixel unit PU4 can be formed. The subpixels and pixel units of chip groups CG1 and CG2 are arranged in the same manner.

[0244] In some embodiments, subpixels between different chip groups can also form pixel units. For example, as shown in FIG51 , chip group CG1 includes three pixel subgroups, wherein the subpixels in the three pixel subgroups are the first subpixel B and the second subpixel G of the first pixel subgroup, the third subpixel R and the fourth subpixel B of the second pixel subgroup, and the fifth subpixel G and the sixth subpixel R of the third pixel subgroup. Chip group CG2 includes multiple pixel subgroups, wherein the subpixels in the three pixel subgroups are the first subpixel B and the second subpixel G of the first pixel subgroup, the third subpixel R and the fourth subpixel B of the second pixel subgroup, and the fifth subpixel G and the sixth subpixel R of the third pixel subgroup. Chip group CG1 and chip group CG2 can be arranged in two rows and staggered with each other (i.e., along the arrangement direction of chip group CG1 and chip group CG2, the subpixels in chip group CG1 and chip group CG2 are staggered with each other). The subpixels in chipset CG1 and chipset CG2 can form multiple pixel units. Specifically, the first subpixel B of chipset CG1, together with the second subpixel G and third subpixel R of chipset CG2, form pixel unit PU1. The second subpixel G and third subpixel R of chipset CG1, together with the fourth subpixel B of chipset CG2, form pixel unit PU2. The fourth subpixel B of chipset CG1, together with the fifth subpixel G and sixth subpixel R of chipset CG2, form pixel unit PU3.

[0245] As a second achievable embodiment, partial areas of two subpixels of a first LED chip and partial areas of one subpixel of a second LED chip together form a pixel unit. Referring to FIG52 , the first LED chip in the first column includes a pixel subgroup, which includes a first subpixel B and a second subpixel G, with the first subpixel B being larger than the second subpixel G. The second LED chip in the second column includes a pixel subgroup, which includes a first subpixel R and a second subpixel G, with the first subpixel R being larger than the second subpixel G. The partial area of ​​the first subpixel B of the first LED chip, the entire area of ​​the second subpixel G, and the partial area of ​​the first subpixel R of the second LED chip together form pixel unit PU1.

[0246] The third LED chip in the third column includes a pixel subgroup, which includes a first subpixel B and a second subpixel G. The first subpixel B is larger than the second subpixel G. A partial area of ​​the first subpixel R of the second LED chip, the entire area of ​​the second subpixel G, and a partial area of ​​the first subpixel B of the three LED cores together form pixel unit PU2.

[0247] The first LED chip and the second LED chip together form a chipset group CG1. Using the above arrangement, the third LED chip and the fourth LED chip in the fourth column can form a chipset group CG2. Part of the first subpixel B of the third LED chip, the entire second subpixel G, and part of the first subpixel R of the fourth LED chip together form a pixel unit PU3.

[0248] In the above embodiment, the sub-pixels shared are sub-pixels B and R. In other embodiments, the sub-pixels shared by the pixel units are different. The following is an embodiment of the arrangement of chip groups that share different sub-pixels.

[0249] As shown in Figure 53, the first LED chip in the first column includes a pixel subgroup, which includes a first subpixel B and a second subpixel G. The size of the first subpixel B is smaller than that of the second subpixel G. The second LED chip in the second column includes a pixel subgroup, which includes a first subpixel B and a second subpixel R. The size of the first subpixel B is smaller than that of the second subpixel R. The partial area of ​​the first subpixel G of the first LED chip, the entire area of ​​the first subpixel B of the second LED chip, and the partial area of ​​the second subpixel R together constitute pixel unit PU1. In this way, pixel units PU2 and PU3 can be formed. In this embodiment, subpixels G and R are shared.

[0250] As shown in Figure 54, the first LED chip in the first column includes a pixel subgroup, which includes a first subpixel B and a second subpixel G. The size of the first subpixel B is smaller than that of the second subpixel G. The second LED chip in the second column includes a pixel subgroup, which includes a first subpixel R and a second subpixel B. The size of the first subpixel R is smaller than that of the second subpixel R. Partial area of ​​the first subpixel G of the first LED chip, and the entire area of ​​the first subpixel R and partial area of ​​the second subpixel R of the second LED chip together constitute pixel unit PU1. In this way, pixel units PU2 and PU3 can be formed. In this embodiment, subpixels G and B are shared.

[0251] It should be noted that in two adjacent pixel units, for example, the first pixel unit and the second pixel unit. When the sub-pixels in the first pixel unit are not bright enough, part or all of the sub-pixels in the adjacent second pixel unit can be flexibly borrowed to complete the light emission of the second pixel unit. That is, the borrowed sub-pixels in the first pixel unit can be set not to emit light for the first pixel unit, but to emit light for the second pixel unit. In this way, the structural flexibility and light emission effect of the chip can be improved. Among them, the first pixel unit can also borrow the sub-pixels of the second pixel unit to emit light for other reasons, which is not limited in this application.

[0252] As a third feasible implementation, among at least two sub-pixels of the first LED chip and at least two sub-pixels of the second LED chip, a portion of the sub-pixels have the same light-emitting wavelength; and, at least two sub-pixels of the first LED chip and at least two sub-pixels of the second LED chip together constitute a pixel unit.

[0253] As shown in Figure 55 , the first LED chip C1 in the first column includes multiple pixel subgroups, with the pixel subgroups in the first row including a first subpixel R and a second subpixel B. The second LED chip C2 in the second column includes multiple pixel subgroups, with the pixel subgroups in the first row including a first subpixel G and a second subpixel R. The first subpixel R and second subpixel B of the first LED chip C1, and the first subpixel G and second subpixel R of the second LED chip C2, together form a pixel unit PU. This pixel unit contains more than three subpixels and includes subpixels with three different emission wavelengths. With this arrangement, the pixel subgroups in the second row of the first LED chip C1 and the pixel subgroups in the second row of the second LED chip C2 can also form another pixel unit.

[0254] The pixel unit shown in FIG56 includes two sub-pixels R, one sub-pixel G, and one sub-pixel B. In other embodiments, the pixel unit may also include two sub-pixels R, two sub-pixels B, and one sub-pixel G. Alternatively, the pixel unit may include five sub-pixels, such as three sub-pixels R, one sub-pixel B, and one sub-pixel G. Alternatively, the pixel unit may include six, seven, eight, or more sub-pixels. The first LED chip C1 and the second LED chip C2 together constitute a chipset group CG.

[0255] Because sub-pixels with different luminous wavelengths have different luminous efficiencies, the above arrangement can be used to adjust the uniformity of light of different wavelengths within a pixel unit, ensuring consistent light output and improving the light output performance of the LED chipset. Furthermore, if there are multiple sub-pixels, for example, if one of the two sub-pixels R is damaged, the other sub-pixel R can be used to emit light instead.

[0256] 56 , the first LED chip C1 may include a pixel subgroup including a first subpixel G and a second subpixel B, and the second LED chip C2 may include a pixel subgroup including a first subpixel B and a second subpixel R. The pixel subgroup of the first LED chip C1 and the pixel subgroup of the second LED chip C2 together constitute a pixel unit including two subpixels B, one subpixel G, and one subpixel R.

[0257] 57 , the first LED chip C1 may include a pixel subgroup including a first subpixel G and a second subpixel B, and the second LED chip C2 may include a pixel subgroup including a first subpixel G and a second subpixel R. The pixel subgroup of the first LED chip C1 and the pixel subgroup of the second LED chip C2 together constitute a pixel unit including two subpixels G, one subpixel B, and one subpixel R.

[0258] 46 to 50 , the shapes of different light emitting diode chips may be the same and regular.

[0259] As shown in Figures 58 to 62 , in the LED chip set provided in this embodiment, the first LED chip C1 and the second LED chip C2 can both be irregularly shaped, with the first LED chip C1 having a protruding area and the second LED chip C2 having a recessed area. The protruding area can be a cube, a pyramid, a hemisphere, or other irregular shape, with the protruding and recessed areas matching and interlocking. The number of protruding and recessed areas can be one, two, or more, and the number of both can be equal.

[0260] It should be noted that, using FIG. 58 as an example, the first LED chip C1 and the second LED chip C2 are both stepped, and the protruding area A2 of the step of the first LED chip C1 is aligned with the recessed area A1 of the step of the second LED chip C2, thereby achieving splicing. In this way, the first LED chip C1, the second LED chip C2, and the third LED chip C3 are assembled. The sub-pixels in the first LED chip C1 have the same size. In this application, the protruding and recessed areas are aligned and joined together to form a "mortise and tenon structure," thereby facilitating self-alignment assembly of different LED chips, reducing alignment difficulty, and improving manufacturing efficiency and yield.

[0261] Of course, the shape of the LED chip can also be convex or concave (as shown in Figure 59); or, in a stepped LED chip, different sub-pixels have different sizes (as shown in Figure 60); or, the LED chip has a serrated edge (as shown in Figure 61); or, the LED chip has an arc-shaped edge (as shown in Figure 62).

[0262] 63 , the LED chip group includes a first LED chip C1, a second LED chip C2, and a third LED chip C3 that are arranged adjacent to each other. Each of the first LED chip C1, the second LED chip C2, and the third LED chip C3 includes a pixel subgroup.

[0263] The first subpixel B and second subpixel G of the first LED chip C1 (the pixel subgroup in the first row and first column) and the first subpixel R of the second LED chip C2 (the pixel subgroup in the first row and second column) each emit light at different wavelengths and together constitute a first pixel unit. The second subpixel B of the second LED chip C2 and the first subpixel G and second subpixel R of the third LED chip C3 (the pixel subgroup in the first row and third column) each emit light at different wavelengths and together constitute a second pixel unit. The first LED chip C1, the second LED chip C2, and the third LED chip C3 together constitute a chipset group CG1.

[0264] The plurality of light-emitting diode chips form a plurality of chip groups arranged in an array, and the plurality of chip groups may further include a chip group CG2, a chip group CG3, and a chip group CG4.

[0265] As shown in FIG63 , along the second direction y, in chip group CG1, the sum of the size of the first subpixel B of the first LED chip and the pitch between the first subpixel B of the first LED chip and the second subpixel G of the first LED chip is a first size. The size of the first subpixel B of the first LED chip is a, and the pitch between the first subpixel B of the first LED chip and the second subpixel G of the first LED chip is b. The first size = a + b, and the first size is the subpixel size (sub pitch) of the first subpixel B.

[0266] The sum of the size of the second subpixel G of the first LED chip and the spacing between the second subpixel G of the first LED chip and the first subpixel R of the second LED chip is the second size. The size of the second subpixel G of the first LED chip is c, and the spacing between the second subpixel G of the first LED chip and the first subpixel R of the second LED chip is d. The second size = c + d, and the second size is the subpixel size of the second subpixel G.

[0267] The sum of the size of the first subpixel R of the second LED chip and the spacing between the first subpixel R of the second LED chip and the second subpixel B of the second LED chip is the third size. The size of the first subpixel R of the second LED chip is e, and the spacing between the first subpixel R of the second LED chip and the second subpixel B of the second LED chip is f. The third size = e + f, and the third size is the subpixel size of the first subpixel R.

[0268] The sum of the size of the second subpixel B of the second LED chip and the spacing between the second subpixel B of the second LED chip and the first subpixel G of the third LED chip is a fourth size. The size of the second subpixel B of the second LED chip is a, and the spacing between the second subpixel B of the second LED chip and the first subpixel G of the third LED chip is g. The fourth size = a + g, and the fourth size is the subpixel size of the second subpixel B.

[0269] The sum of the size of the first subpixel G of the third LED chip and the spacing between the first subpixel G of the third LED chip and the second subpixel R of the third LED chip is a fifth size. The size of the first subpixel G of the third LED chip is c, and the spacing between the first subpixel G of the third LED chip and the second subpixel R of the third LED chip is h. The fifth size = c + h, and the fifth size is the subpixel size of the first subpixel G.

[0270] The sum of the spacing between the first sub-pixel B of the first LED chip and the edge of the chip group CG1, the size of the second sub-pixel R of the third LED chip, the spacing between the second sub-pixel R of the third LED chip and the edge of the chip group CG1, and the spacing between the adjacent chip group CG1 and chip group CG2 is the sixth size.

[0271] The spacing between the first subpixel B of the first LED chip and the edge of chipset group CG1 is k, the size of the second subpixel R of the third LED chip is e, the spacing between the second subpixel R of the third LED chip and the edge of chipset group CG1 is i, and the spacing between adjacent chipsets CG1 and CG2 is l. Sixth dimension = k + e + i + l.

[0272] Optionally, the first size, second size, third size, fourth size, fifth size, and sixth size are all equal; and the sum of the first size, second size, and third size is equal to the sum of the fourth size, fifth size, and sixth size. The sum of the first size, second size, and third size may be the pixel pitch of a pixel unit consisting of the first subpixel B of the first LED chip, the second subpixel G of the first LED chip, and the first subpixel R of the second LED chip. Similarly, the sum of the fourth size, fifth size, and sixth size may be the pixel pitch of a pixel unit consisting of the second subpixel B of the second LED chip, the first subpixel G of the third LED chip, and the second subpixel R of the third LED chip. Of course, in other embodiments, the first size, second size, third size, fourth size, fifth size, and sixth size may be different. The sum of the first size, second size, and third size may also not be equal to the sum of the fourth size, fifth size, and sixth size.

[0273] 63 , along the first direction x, the size of the first subpixel B of the first LED chip in chipset CG1 is m. The spacing between the first subpixel B of the first LED chip in chipset CG1 and the first subpixel B of the first LED chip in chipset CG3 is n.

[0274] The first subpixel B, the second subpixel G, and the first subpixel R of the second LED chip of chip group CG1 can form a pixel unit. The sum of m and n can be the pixel size of the pixel unit along the first direction x. The sum of a, b, c, d, e, and f can be the pixel size of the pixel unit along the second direction y. The sum of m and n can be equal to or different from the sum of a, b, c, d, e, and f.

[0275] When the number of sub-pixels in a chipset along the first direction x is 1, the sum of the chip size and the spacing between chipsets along the first direction x can be flexibly adjusted. That is, the sum of m and n shown in FIG63 can be flexibly adjusted. This can accommodate display panels with different pixel sizes.

[0276] When the number of sub-pixels of the chipset along the first direction x is greater than 1, the sum of the chip size and the spacing between the chipsets along the first direction x is limited. Continuing with reference to Figure 63(a), the chipset has 2 sub-pixels along the first direction x as an example. In chipset CG1 and chipset CG2, the size of the first sub-pixel B is m. In chipset CG1, the spacing between two adjacent first sub-pixels B is n. In chipset CG2, the spacing between two adjacent first sub-pixels is p. The spacing between the first sub-pixel B of chipset CG1 and the first sub-pixel B of chipset CG2 is o. The above dimensions need to satisfy that the sum of m and n, the sum of m and o, and the sum of m and p can be equal or unequal. m, n, o, and p can all be flexibly adjusted according to display panels with different pixel sizes to flexibly correspond to display panels with different pixel sizes.

[0277] In the embodiments of the present application, multiple LED chips form multiple chip groups arranged in an array and multiple pixel units arranged in an array. For example, if one LED chip includes one pixel subgroup, each pixel subgroup includes two sub-pixels, and multiple LED chips form an LED chip group, the number of sub-pixels in the pixel units may vary, as described in detail below.

[0278] 64 and 65 , each of the LED chip group CG1 and the LED chip group CG2 includes a LED chip C1 , a LED chip C2 , and a LED chip C3 .

[0279] The formed pixel unit includes an odd number of sub-pixels. For example, referring to FIG64 , pixel unit PU1, pixel unit PU2, pixel unit PU3, and pixel unit PU4 are formed, each of which has three sub-pixels. Referring to FIG65 , pixel unit PU1 and pixel unit PU2 are formed, each of which has five sub-pixels. In other embodiments, the number of sub-pixels in a pixel unit can also be 7, 9, 11, or another odd number.

[0280] In each LED chip, the spacing between two adjacent sub-pixels can be d1. The spacing between adjacent chip groups can be d2. The spacing between adjacent pixel units can be d3. The spacing between two adjacent LED chips can be d4. When the number of sub-pixels in a pixel unit is an odd number, d1, d2, d3, and d4 are all equal, which ensures uniform light output from each LED chip.

[0281] 66 and 67 , the LED chip group CG1 and the LED chip group CG2 also include a LED chip C1 , a LED chip C2 , and a LED chip C3 .

[0282] The formed pixel unit includes an even number of sub-pixels. For example, referring to FIG66 , pixel unit PU1, pixel unit PU2, and pixel unit PU3 are formed, each of which has four sub-pixels. Referring to FIG67 , pixel unit PU1 and pixel unit PU2 are formed, each of which has six sub-pixels. In other embodiments, the number of sub-pixels in a pixel unit can also be 8, 10, or another even number.

[0283] When the number of sub-pixels in a pixel unit is even, d1, d2, d3, and d4 can be equal or unequal. That is, d1 can be unequal to d2, d3, or d4; d2 can be unequal to d3, d4, or d3. D3 can be determined by the PPI of the full-color display fabricated using the LED chipset. Flexible adjustment of d3 enables efficient layouts for a variety of applications, from watches to large-screen TVs.

[0284] In this way, d1 can be smaller than d3, allowing for flexible adjustment of the spacing between sub-pixels in the LED chip, thereby adjusting the LED chip layout area and avoiding waste of layout area. Furthermore, d2 can be larger than d1, which facilitates the layout of the LED chips and facilitates assembly. Of course, when d1, d2, d3, and d4 are equal, the layout regularity of each sub-pixel, each LED chip, each LED chip group, and each pixel unit can be effectively improved, thereby improving light uniformity.

[0285] As shown in Figures 68 and 69, in some embodiments, a dual-color LED chip can be combined with a monochrome LED chip to form a full-color chipset. As shown in Figure 68, LED chip C1 includes two sub-pixels with different emission wavelengths (i.e., sub-pixel B and sub-pixel G), which is a dual-color LED chip. LED chip C2 includes one sub-pixel R. The two sub-pixels of LED chip C1 and the one sub-pixel of LED chip C2 can form a full-color pixel unit. In this embodiment, the two sub-pixels of LED chip C1 and the one sub-pixel of LED chip C2 can be equal in size.

[0286] 69 , in some other embodiments, the sizes of the two sub-pixels of LED chip C1 and the one sub-pixel of LED chip C2 may be different. For example, the size of sub-pixel R is larger than that of sub-pixel G and sub-pixel B.

[0287] In a fourth aspect, embodiments of the present application provide a display module comprising a driver backplane and the aforementioned light-emitting diode chipset, wherein the light-emitting diode chipset is disposed on and electrically connected to the driver backplane.

[0288] The driving backplane may be a TFT (Thin Film Transistor, thin film field effect transistor) driving backplane, or a CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) driving backplane.

[0289] As a first possible implementation, as shown in FIG70 , there are multiple LED chip groups arranged in an array on a driver backplane 200. Driver backplane 200 can provide driving current to the multiple LED chip groups, thereby driving the multiple LED chip groups to emit light. FIG70 shows LED chip group CG1 and LED chip group CG2 arranged on driver backplane 200. In some embodiments, there may be three, four, or more LED chip groups arranged in an array.

[0290] LED chip group CG1 and LED chip group CG2 each include LED chip C1, LED chip C2, and LED chip C3. Each LED chip includes a pixel subgroup, each of which includes two sub-pixels. In some embodiments, the number of LED chips in the LED chip group, and the number of pixel subgroups and sub-pixels in the LED chip, can be adjusted, and this embodiment does not limit this.

[0291] As a second achievable embodiment, as shown in FIG71 , the driving backplane 200 includes a driving substrate 201 and a plurality of driving units 202. One driving unit 202 is electrically connected to one corresponding light-emitting diode chipset, and the plurality of driving units 202 are all electrically connected to the driving substrate 201. The driving units 202 and the driving substrate 201 may also be TFTs and CMOSs.

[0292] A driving unit 202 and an LED chipset can form a micro-display module. FIG71 shows micro-display modules DMB1 and DMB2. Both are electrically connected to a driving substrate 201. The driving substrate 201 can provide driving current to the driving unit 202 in the micro-display module, thereby driving the LED chipset to emit light. In some embodiments, the number of micro-display modules can be 3, 4, 5, or more, and this embodiment does not impose any limitation on this number.

[0293] FIG71 shows that LED chip group CG1 and LED chip group CG2 are electrically connected to two different drive units 202, respectively. Both drive units 202 are electrically connected to a drive substrate 201. Both LED chip group CG1 and LED chip group CG2 include LED chips C1, C2, and C3. Each LED chip includes a pixel subgroup, each of which includes two sub-pixels. In this embodiment, the number of LED chip groups, the number of LED chips in an LED chip group, and the number of pixel subgroups and sub-pixels in an LED chip can be adjusted, and this embodiment also does not impose any limitations on this.

[0294] In a fifth aspect, an embodiment of the present application provides a full-color display screen, which can be manufactured by encapsulating the above-mentioned display module.

[0295] In a sixth aspect, embodiments of the present application provide an electronic device comprising the aforementioned full-color display. The electronic device may be a television, an electronic watch, an e-book, a desktop computer, a laptop computer, a tablet computer, a mobile phone, an AR device (Augmented Reality) or a VR device (Virtual Reality). When the light-emitting diode chip of the electronic device includes ultraviolet light pixels, the electronic device may also be a UV curing lamp or a UV detection lamp.

[0296] In the description of the embodiments of the present application, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In the description of this application, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0297] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0298] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light-emitting diode chip, comprising an N-type electrode, a P-type electrode, and a light-emitting layer disposed between the N-type electrode and the P-type electrode; the light-emitting layer being electrically connected to the N-type electrode and the P-type electrode, respectively; The light-emitting layer includes a first light-emitting layer having a first light-emitting wavelength and a second light-emitting layer having a second light-emitting wavelength, wherein the first light-emitting wavelength is smaller than the second light-emitting wavelength; at least a portion of the first light-emitting layer and at least a portion of the second light-emitting layer are stacked along the thickness direction of the light-emitting diode chip; in the stacked first light-emitting layer and the second light-emitting layer, the first light-emitting layer is located on a side of the second light-emitting layer close to the P-type electrode, and light emitted by the first light-emitting layer is used to excite the second light-emitting layer to emit light; The first light-emitting layer and the second light-emitting layer are configured to form at least two sub-pixels arranged side by side, and the at least two sub-pixels include a first sub-pixel having a first light-emitting wavelength and a second sub-pixel having a second light-emitting wavelength.

2. The light-emitting diode chip according to claim 1, wherein: The entire first light-emitting layer and the entire second light-emitting layer are stacked; The surface of the first light-emitting layer facing away from the second light-emitting layer is electrically connected to the P-type electrode, and the surface of the second light-emitting layer facing away from the first light-emitting layer is electrically connected to the N-type electrode; The first light-emitting layer includes a first region and a second region arranged side by side and at intervals, and the second light-emitting layer includes a third region and a fourth region arranged side by side and at intervals; the first region and the third region are opposite to each other and are arranged to form the first sub-pixel, and the second region and the fourth region are opposite to each other and are arranged to form the second sub-pixel. 3 . The light emitting diode chip according to claim 2 , further comprising an isolation structure, wherein the isolation structure is located between the first region and the second region, and between the third region and the fourth region.

4. The light-emitting diode chip according to claim 2, further comprising a first filter layer and a second filter layer arranged side by side, the first filter layer corresponding to the first region, and the second filter layer corresponding to the second region; the first filter layer and the second filter layer are both located on the light-emitting side of the light-emitting diode; the transmission wavelength of the first filter layer is the first emission wavelength, and the transmission wavelength of the second filter layer is the second emission wavelength.

5. The light-emitting diode chip according to claim 3, wherein: The N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, the first N-type electrode electrically conducting to a surface of the third region facing away from the P-type electrode, and the second N-type electrode electrically conducting to a surface of the fourth region facing away from the P-type electrode; the isolation structure is further located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first region facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode. The light-emitting diode chip according to claim 1 , wherein: The first light-emitting layer includes a first region and a second region, the first region and at least a portion of the thickness of the second region being arranged side by side between the N-type electrode and the P-type electrode; the first region is stacked with the second light-emitting layer and configured to form the second sub-pixel; and the second region is configured to form the first sub-pixel; The surface of the first region facing away from the second light-emitting layer is electrically connected to the P-type electrode, the surface of the second light-emitting layer facing away from the first region is electrically connected to the N-type electrode, and the second region is electrically connected to the P-type electrode and the N-type electrode respectively. 7 . The light-emitting diode chip according to claim 6 , further comprising a filter layer, wherein the filter layer is located on the light-emitting side of the light-emitting diode and corresponds to the first region, and a passing wavelength of the filter layer is the second emission wavelength.

8. The light-emitting diode chip according to claim 6, wherein: The first region and a partial thickness of the second region are arranged side by side, and the second light-emitting layer and another partial thickness of the second region are arranged side by side.

9. The light-emitting diode chip according to claim 8, further comprising an isolation structure, wherein the isolation structure is located between the first region and the second region arranged side by side, and between the second light-emitting layer and the second region arranged side by side; The N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, the first N-type electrode electrically conducting to a surface of the second light-emitting layer facing away from the P-type electrode, and the second N-type electrode electrically conducting to a surface of the second region facing away from the P-type electrode; the isolation structure is further located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first region facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

10. The light-emitting diode chip according to claim 6, wherein: The first region and at least a portion of the thickness of the P-type electrode are arranged side by side, and the second light-emitting layer and at least a portion of the thickness of the second region are arranged side by side.

11. The light-emitting diode chip according to claim 10, further comprising an isolation structure, wherein the isolation structure is located between the first region and the second region, and between the second light-emitting layer and the N-type electrodes arranged side by side; The N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, the first N-type electrode electrically conducting to a surface of the second light-emitting layer facing away from the P-type electrode, and the second N-type electrode electrically conducting to a surface of the second region facing away from the P-type electrode; the isolation structure is further located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first region facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the second region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

12. The light-emitting diode chip according to claim 1, wherein: The second light-emitting layer includes a third region and a fourth region, wherein the third region and at least a portion of the fourth region are arranged side by side between the N-type electrode and the P-type electrode; the third region is stacked with the first light-emitting layer and is configured to form the first sub-pixel; The fourth area is configured to form the second sub-pixel; The surface of the third region facing away from the first light-emitting layer is electrically connected to the N-type electrode, the surface of the first light-emitting layer facing away from the third region is electrically connected to the P-type electrode, and the fourth region is electrically connected to the P-type electrode and the N-type electrode respectively. 13 . The LED chip according to claim 12 , further comprising a filter layer, wherein the filter layer is located on the light-emitting side of the LED chip and corresponds to the third region, and a passing wavelength of the filter layer is the first emission wavelength.

14. The light-emitting diode chip according to claim 12, wherein: The third region is arranged side by side with a partial thickness of the fourth region, and the first light-emitting layer is arranged side by side with another partial thickness of the fourth region.

15. The light-emitting diode chip according to claim 14, further comprising an isolation structure, wherein the isolation structure is located between the third region and the fourth region arranged side by side, and between the first light-emitting layer and the fourth region arranged side by side; The N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, the first N-type electrode electrically conducting to a surface of the third region facing away from the P-type electrode, and the second N-type electrode electrically conducting to a surface of the fourth region facing away from the P-type electrode; the isolation structure is further located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first light-emitting layer facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the fourth region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

16. The light-emitting diode chip according to claim 12, wherein: The third region is arranged side by side with the fourth region having a full thickness, and the first light emitting layer is arranged side by side with the P-type electrode having a partial thickness.

17. The light-emitting diode chip according to claim 16, further comprising an isolation structure, wherein the isolation structure is located between the third region and the fourth region, and between the first light-emitting layer and the P-type electrodes arranged side by side; The N-type electrode includes a first N-type electrode and a second N-type electrode that are separate from each other, the first N-type electrode electrically conducting to a surface of the third region facing away from the P-type electrode, and the second N-type electrode electrically conducting to a surface of the fourth region facing away from the P-type electrode; the isolation structure is further located between the first N-type electrode and the second N-type electrode; Alternatively, the P-type electrode includes a first P-type electrode and a second P-type electrode that are separate from each other, the first P-type electrode electrically conducts the surface of the first light-emitting layer facing away from the N-type electrode, and the second P-type electrode electrically conducts the surface of the fourth region facing away from the N-type electrode; the isolation structure is also located between the first P-type electrode and the second P-type electrode.

18. The light-emitting diode chip according to any one of claims 1 to 17, wherein: The light-emitting layer further includes a third light-emitting layer having a third light-emitting wavelength, wherein the third light-emitting wavelength is smaller than the first light-emitting wavelength; Along the thickness direction of the light-emitting diode chip, the third light-emitting layer is stacked with at least one of the first light-emitting layer and the second light-emitting layer; in the stacking area, the third light-emitting layer is located on the side of the corresponding stacked light-emitting layer close to the P-type electrode, and the light emitted by the third light-emitting layer is used to excite the corresponding stacked light-emitting layer to emit light.

19. The light-emitting diode chip according to claim 18, wherein: At least a portion of the third light-emitting layer is stacked with the first light-emitting layer and the second light-emitting layer; In the stacked first light-emitting layer, second light-emitting layer and third light-emitting layer, the third light-emitting layer, the first light-emitting layer and the second light-emitting layer are arranged in sequence along the direction from the P-type electrode to the N-type electrode, and the light emitted by the third light-emitting layer is used to excite the first light-emitting layer and the second light-emitting layer to emit light. 20 . The light-emitting diode chip according to claim 2 , further comprising a reflective layer, wherein the reflective layer is located on a backlight side of the light-emitting diode chip. 21 . The light-emitting diode chip according to claim 2 , further comprising a light-blocking layer, wherein the light-blocking layer is located on a light-emitting side of the light-emitting diode chip and between two adjacent sub-pixels. 22 . The light-emitting diode chip according to claim 18 , further comprising a hole blocking layer, wherein the hole blocking layer is provided between any two adjacent layers of the stacked first light-emitting layer, the second light-emitting layer, and the third light-emitting layer.

23. The light-emitting diode chip according to any one of claims 18 to 19, wherein: The first light-emitting layer, the second light-emitting layer and the third light-emitting layer are any three of a red light-emitting material layer, a green light-emitting material layer, a blue light-emitting material layer, a purple light-emitting material layer and an ultraviolet light-emitting material layer respectively.

24. The light-emitting diode chip according to any one of claims 3, 5, 9, 11, 15 and 17, wherein: The isolation structure includes a channel; or, the isolation structure includes a channel and an isolation material disposed in the channel; or, the isolation structure is an ion implantation layer; The light-emitting diode chip further includes an N-type semiconductor layer and a P-type semiconductor layer, wherein the N-type semiconductor and the P-type semiconductor are respectively located on opposite sides of the light-emitting layer in a thickness direction, the N-type electrode is electrically connected to the light-emitting layer via the N-type semiconductor, and the P-type electrode is electrically connected to the light-emitting layer via the P-type semiconductor; In response to the N-type electrode including a first N-type electrode and a second N-type electrode separated from each other, at least a portion of the isolation structure extends into the P-type semiconductor layer; In response to the P-type electrode including a first P-type electrode and a second P-type electrode separated from each other, at least a portion of the isolation structure extends into the N-type semiconductor layer.

25. The light-emitting diode chip according to any one of claims 1 to 17, wherein: At least two of the sub-pixels form a pixel subgroup or a plurality of pixel subgroups; The same pixel subgroup includes a plurality of sub-pixels, and among the plurality of sub-pixels, the number of the first sub-pixels and the number of the second sub-pixels are equal to or different from each other.

26. The light-emitting diode chip according to claim 25, wherein: The light-emitting diode chip includes at least two pixel subgroups, which are arranged in sequence along a first direction, and the first subpixels and the second subpixels are arranged in sequence along a second direction; wherein the first direction and the second direction intersect each other.

27. The light-emitting diode chip according to claim 26, wherein: The at least two pixel subgroups include a first pixel subgroup and a second pixel subgroup, wherein the first subpixel of the first pixel subgroup and the first subpixel of the second pixel subgroup have the same light emission wavelength, and the second subpixel of the first pixel subgroup and the second subpixel of the second pixel subgroup have the same light emission wavelength; Along the first direction, the first subpixel of the first pixel subgroup corresponds to the first subpixel of the second pixel subgroup, and the second subpixel of the first pixel subgroup corresponds to the second subpixel of the second pixel subgroup; or, the first subpixel of the first pixel subgroup corresponds to the second subpixel of the second pixel subgroup, and the second subpixel of the first pixel subgroup corresponds to the first subpixel of the second pixel subgroup.

28. The light-emitting diode chip according to claim 26, wherein: The N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as the number of the sub-pixels; one side of each sub-pixel facing away from the P-type electrode is electrically connected to one sub-N-type electrode; The side of the sub-pixel facing away from the N-type electrode is electrically connected to the P-type electrode; Alternatively, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as the number of the sub-pixels; one side of the sub-pixel facing away from the N-type electrode is electrically connected to one sub-P-type electrode; and one side of the sub-pixel facing away from the P-type electrode is electrically connected to the N-type electrode.

29. The light-emitting diode chip according to claim 26, wherein: The N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is the same as the number of the sub-pixels; the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is less than the number of the sub-pixels; a side of each sub-pixel facing away from the P-type electrode is electrically connected to one sub-N-type electrode, and a portion of the sub-pixels have sides facing away from the N-type electrode electrically connected to the same sub-P-type electrode; Alternatively, the P-type electrode includes at least two separate sub-P-type electrodes, and the number of the sub-P-type electrodes is the same as the number of the sub-pixels; the N-type electrode includes at least two separate sub-N-type electrodes, and the number of the sub-N-type electrodes is less than the number of the sub-pixels; one side of the sub-pixel facing away from the N-type electrode is electrically connected to one sub-P-type electrode, and a part of the sub-pixels have one side facing away from the P-type electrode electrically connected to the same sub-N-type electrode.

30. The light-emitting diode chip according to any one of claims 1 to 17, wherein: The light-emitting diode chip satisfies at least one of the following requirements: The size of the light emitting diode chip is greater than or equal to 50 microns; The shape of the light emitting diode chip is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; The size of the sub-pixel is in the range of 0.001-200 microns; The shape of the sub-pixel is any one of a rectangle, a square, a circle, an ellipse, a triangle, a rhombus, a parallelogram and a polygon with more than four sides; The shapes of the different sub-pixels are the same or different; The sizes of different sub-pixels are equal or different.

31. The light-emitting diode chip according to any one of claims 1 to 17, further comprising a buffer layer, an N-type semiconductor layer, a P-type semiconductor layer, a current spreading layer, a reflective layer, and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is arranged on a side of the N-type semiconductor layer away from the buffer layer, and the P-type semiconductor layer is arranged on a side of the light-emitting layer away from the buffer layer; The current spreading layer contacts a side of the P-type semiconductor layer facing away from the buffer layer, the N-type electrode contacts the N-type semiconductor layer, and the P-type electrode contacts the P-type semiconductor layer and the current spreading layer; The first insulating layer is arranged on a side of the current spreading layer away from the buffer layer; The reflective layer is arranged on a side of the buffer layer away from the light-emitting layer, or the reflective layer is arranged on a side of the first insulating layer away from the buffer layer, and a second insulating layer is further arranged on the side of the reflective layer away from the buffer layer.

32. The light-emitting diode chip according to claim 31, further comprising a substrate, wherein the substrate is disposed on a side of the buffer layer away from the light-emitting layer; In response to the reflective layer being arranged on the side of the buffer layer away from the light-emitting layer, the reflective layer is arranged on the side of the substrate away from the buffer layer.

33. The light-emitting diode chip according to any one of claims 1 to 17, further comprising a bonding substrate, a binding layer, an N-type semiconductor layer, a P-type semiconductor layer, and a reflective layer; The bonding substrate and the binding layer are sequentially arranged on the P-type electrode, and the P-type semiconductor layer is arranged on a side of the binding layer away from the bonding substrate and in contact with the binding layer; The light-emitting layer is provided on a side of the P-type semiconductor layer away from the bonding substrate, the N-type semiconductor layer is provided on a side of the light-emitting layer away from the bonding substrate, and the N-type electrode contacts the side of the N-type semiconductor layer away from the bonding substrate; The reflective layer is arranged on a side of the P-type semiconductor layer close to the bonding substrate.

34. The light-emitting diode chip according to any one of claims 1 to 17, further comprising a color conversion layer, wherein the color conversion layer is disposed on a portion of the light-emitting side of the light-emitting diode chip and corresponds to at least a portion of the sub-pixel area.

35. A light-emitting diode chip set, comprising a plurality of light-emitting diode chips according to any one of claims 1 to 34, wherein the plurality of light-emitting diode chips are arranged in an array; The two adjacent LED chips include a first LED chip and a second LED chip, and part of the sub-pixels of the first LED chip and part of the sub-pixels of the second LED chip together form a pixel unit.

36. The light emitting diode chip set according to claim 35, wherein: The light emitting wavelengths of the two sub-pixels of the first LED chip and the light emitting wavelength of the one sub-pixel of the second LED chip are different.

37. The light emitting diode chip set according to claim 36, wherein: The entire area of ​​the two sub-pixels of the first LED chip and the entire area of ​​one sub-pixel of the second LED chip together constitute one pixel unit.

38. The light emitting diode chip set according to claim 36, wherein: Partial areas of the two sub-pixels of the first LED chip and partial areas of one sub-pixel of the second LED chip together form one pixel unit.

39. The light emitting diode chip set according to claim 35, wherein: Among the at least two sub-pixels of the first LED chip and the at least two sub-pixels of the second LED chip, some of the sub-pixels have the same light-emitting wavelength; Furthermore, the at least two sub-pixels of the first LED chip and the at least two sub-pixels of the second LED chip together constitute one pixel unit.

40. The light emitting diode chip set according to any one of claims 35 to 39, wherein: The first LED chip and the second LED chip are both irregularly shaped, the first LED chip has a protruding area, and the second LED chip has a concave area; The protruding area and the recessed area are adapted in shape and fit together.

41. The LED chip group according to claim 35, further comprising a third LED chip, wherein the first LED chip, the second LED chip and the third LED chip are arranged adjacent to each other in sequence; The first sub-pixel and the second sub-pixel of the first LED chip and the first sub-pixel of the second LED chip emit light at different wavelengths and together constitute a first pixel unit; the second sub-pixel of the second LED chip and the first sub-pixel and the second sub-pixel of the third LED chip emit light at different wavelengths and together constitute a second pixel unit; The first LED chip, the second LED chip and the third LED chip together constitute a LED chip group; in, The plurality of light emitting diode chips form a plurality of light emitting diode chip groups arranged in an array.

42. The light emitting diode chip set according to claim 35, wherein: The plurality of light-emitting diode chips form a plurality of light-emitting diode chip groups arranged in an array and a plurality of pixel units arranged in an array; In the same LED chip, the spacing between adjacent sub-pixels is d1; the spacing between adjacent chip groups is d2; the spacing between adjacent pixel units is d3; and the spacing between adjacent LED chips is d4. In response to the pixel unit including an odd number of the sub-pixels, d1, d2, d3 and d4 are all equal; In response to the pixel unit including an even number of the sub-pixels, d1, d2, d3 and d4 are all equal, or d1, d2, d3 and d4 are unequal in pairs.

43. A display module, comprising a driving backplane and the light-emitting diode chipset according to any one of claims 35 to 42, wherein the light-emitting diode chipset is arranged on the driving backplane and electrically connected to the driving backplane.

44. The display module according to claim 43, wherein: There are multiple light emitting diode chip groups; The plurality of light emitting diode chip groups are arranged in an array on the driving backplane; Alternatively, the driving backplane includes a driving substrate and a plurality of driving units, one driving unit is electrically connected to one light emitting diode chip group, and the plurality of driving units are electrically connected to the driving substrate.

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