Module

Abstract

To improve the freedom of chip component mounting layout.SOLUTION: A module includes a wiring board, a first chip component provided on the wiring board and having a first electrode portion, a first non-electrode portion, and a second electrode portion, a second chip component stacked on the first chip component and having a third electrode portion, a second non-electrode portion, and a fourth electrode portion. The second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion. The second electrode portion is positioned between the second non-electrode portion and the wiring board.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a module. [Background technology]

[0002] In recent years, the integration of semiconductor devices (ICs) has significantly increased the size and density of electronic circuits. However, discrete circuit components such as capacitors and resistors are still used in IC peripheral circuits, and printed circuit boards are formed by mounting these components on printed wiring boards. To achieve higher performance in electronic devices, the number of signals handled by ICs and their operating speeds are increasing. This has led to an increase in the number of components required for signal waveform shaping and noise suppression in signals and power supplies. Components mounted on printed circuit boards are increasingly being chipped, and chip components such as chip capacitors and chip resistors are also becoming smaller. However, due to the aforementioned trend toward an increasing number of mounted components and the demand for smaller electronic devices, there is a growing need to improve the mounting density of chip components on printed circuit boards.

[0003] In response to this situation, attempts have been made to increase the volume utilization rate of electronic devices including printed wiring boards and arrange electronic components three-dimensionally, thereby realizing small printed wiring boards, such as small electronic devices such as control devices. For example, Patent Document 1 discloses a mounting configuration in which multiple chip components are mounted on top of another chip component. However, when stacking chip components so that the electrodes of the upper chip component are directly connected to the electrodes of the lower chip component, the distance between the electrodes of the upper chip component limits the width of the gaps between the multiple chip components in the lower layer. In other words, there is a problem in that the distance between the electrodes of the lower chip components cannot be made closer than the distance determined by the size of the upper chip component. As a result, the gaps between the lower chip components become dead space, which can limit the flexibility of the chip component mounting layout. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-216884 Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, an object of the present disclosure is to provide a module that improves the degree of freedom in the mounting layout of chip components. [Means for solving the problem]

[0006] The module according to the present disclosure comprises a wiring board, a first chip component having a first electrode portion, a first non-electrode portion, and a second electrode portion and provided on the wiring board, and a second chip component having a third electrode portion, a second non-electrode portion, and a fourth electrode portion and stacked on the first chip component, wherein the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion, and the second electrode portion is located between the second non-electrode portion and the wiring board. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a module that improves the degree of freedom in the mounting layout of chip components. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic diagram illustrating an electronic device according to a first embodiment. [Figure 2A] FIG. 2 is a top view of a processing module according to the first embodiment. [Figure 2B] FIG. 2B is a cross-sectional view taken along dotted line A101-A'101 in FIG. 2A. [Figure 3] 1 is a diagram showing a conventional processing module. [Figure 4A] FIG. 10 is a top view showing a processing module according to a second embodiment. [Figure 4B] 4B is a cross-sectional view taken along dotted line A201-A'201 in FIG. 4A. [Figure 5A] FIG. 10 is a top view showing a processing module according to a third embodiment. [Figure 5B] 5B is a cross-sectional view of the XZ plane taken along the dotted line A301-A'301 in FIG. 5A. [Figure 5C] 5B is a cross-sectional view of the XY plane taken along the dotted line B301-B'301 in FIG. 5B. [Figure 6A] FIG. 11 is a top view showing a processing module according to a comparative example for explaining the effects of the third embodiment. [Figure 6B] FIG. 10 is a cross-sectional view of the processing module according to the comparative example taken along the XZ plane along the dotted line A351-A'351. [Figure 6C] 6B is a cross-sectional view of the XY plane taken along the dotted line B351-B'351 in FIG. 6B. [Figure 7] FIG. 10 is a diagram showing the simulation results of the power supply impedance in Example 1 and the comparative example. [Figure 8] FIG. 10 is a diagram illustrating a processing module according to a fourth embodiment. [Figure 9] FIG. 13 is a diagram showing a processing module 4505 according to a comparative example for explaining the effects of the fourth embodiment. [Figure 10] FIG. 10 is a diagram showing the simulation results of the power supply impedance of Example 2 and the comparative example. [Figure 11] FIG. 10 is a diagram illustrating a processing module according to a fifth embodiment. [Figure 12] FIG. 13 is a diagram showing a processing module according to a comparative example for explaining the effects of the fifth embodiment. [Figure 13] 10 shows simulation results of power supply impedance in Example 3 and Comparative Example. [Figure 14] FIG. 13 is a diagram illustrating a processing module according to a sixth embodiment. [Figure 15] FIG. 13 is a diagram showing a processing module according to a seventh embodiment. [Figure 16] FIG. 13 is a diagram showing a processing module according to an eighth embodiment. [Figure 17] FIG. 13 is a diagram showing a processing module according to the ninth embodiment. [Figure 18]FIG. 20 is a diagram showing a processing module according to a tenth embodiment. [Figure 19] FIG. 22 is a diagram showing a processing module according to an eleventh embodiment. [Figure 20] FIG. 23 is a diagram showing a processing module according to a twelfth embodiment. [Figure 21] FIG. 23 is a diagram showing a processing module according to the thirteenth embodiment. [Figure 22] FIG. 23 is a diagram showing a processing module according to a fourteenth embodiment. [Figure 23] FIG. 23 is a diagram showing a processing module according to the fifteenth embodiment. [Figure 24] FIG. 22 is a diagram showing a processing module according to the sixteenth embodiment. [Figure 25] FIG. 22 is a diagram showing a processing module according to the seventeenth embodiment. [Figure 26] FIG. 22 is a diagram showing a processing module according to the eighteenth embodiment. [Figure 27A] FIG. 23 is a top view of a processing module according to the nineteenth embodiment. [Figure 27B] 27B is a cross-sectional view taken along dotted line BB' in FIG. 27A. [Figure 28A] FIG. 20 is a top view of a processing module according to the twentieth embodiment. [Figure 28B] 28B is a cross-sectional view taken along dotted line CC′ in FIG. 28A. [Figure 28C] 28B is a cross-sectional view taken along dotted line CC′ in FIG. 28A. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments for carrying out the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to the following embodiments and can be modified as appropriate without departing from the spirit of the present disclosure. In addition, in the drawings described below, parts having the same functions are given the same reference numerals, and their description may be omitted or simplified.

[0010] [First embodiment] FIG. 1 is a schematic diagram showing an example of an electronic device according to a first embodiment. Here, a digital camera 1, which is an imaging device, is shown as the electronic device. The digital camera 1 is an interchangeable lens digital camera and includes a camera body 2. A lens unit (lens barrel) 3 including a lens is detachably attached to the camera body 2. The camera body 2 includes a housing 4, a processing module 5, and a sensor module 6. The processing module 5 and the sensor module 6 are disposed inside the housing 4.

[0011] The processing module 5 is an example of an electronic module and is composed of a printed circuit board. The processing module 5 and the sensor module 6 are electrically connected by a connection member 7. The connection member 7 may include a flexible printed circuit board (FPC), a flexible flat cable (FFC), a connector, etc. A battery 8 is disposed inside the housing 4. The battery 8 is a power source that supplies power to the processing module 5, the sensor module 6, etc. The sensor module 6 has an image sensor 9, which is an imaging device, and a printed wiring board 11. The printed wiring board 11 is a rigid wiring board. The image sensor 9 is mounted on the printed wiring board 11.

[0012] The image sensor 9 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor. The image sensor 9 has a function of converting light incident through the lens unit 3 into an electrical signal. The processing module 5 has a power supply unit 12, a load unit 13, and a printed wiring board 10. The printed wiring board 10 is a rigid wiring board. The power supply unit 12 and the load unit 13 are mounted on the printed wiring board 10.

[0013] FIG. 2A is a top view showing a processing module 5 according to the first embodiment. FIG. 2B is a cross-sectional view of the processing module 5 according to the first embodiment taken along dotted line A101-A'101. The printed wiring board 10 includes an insulating substrate 111 and at least one conductor layer. The at least one conductor layer includes a surface layer 113 located on a main surface 112 of the insulating substrate 111. The power supply unit 12 and the load unit 13 are disposed on the main surface 112 of the insulating substrate 111. That is, the power supply unit 12 and the load unit 13 are disposed on the surface layer 113. The insulating substrate 111 is formed of an electrically insulating insulator, such as glass epoxy resin. The surface layer 113 is provided with conductor patterns forming various wiring such as power wiring, ground wiring, and signal wiring. The conductor patterns are formed of a metal, such as copper or gold.

[0014] The load unit 13 includes a plurality of loads, such as semiconductor devices. The load may be, for example, a digital signal processor. The digital processor has the function of acquiring an electrical signal from the image sensor 9, correcting the acquired electrical signal, and generating image data. The load may be, for example, a memory device, such as a DRAM (Dynamic Random Access Memory). The memory device has the function of transmitting and receiving electrical signals to and from the digital signal processor, and temporarily storing data such as image data. The processing module 5 has a power supply wiring section (not shown). The power supply wiring section is used to supply the voltage output from the power supply unit 12 to the plurality of loads of the load unit 13.

[0015] The first chip component 103 and the third chip component 104 are arranged on the surface layer 113 of the printed wiring board 10. The second chip component 102 is stacked on the first chip component 103 and the third chip component 104. The first chip component 103, the second chip component 102, and the third chip component 104 are chip components such as capacitors, resistors, and inductors.

[0016] The first chip component 103 has a first electrode portion 103A, a first non-electrode portion 103B, and a second electrode portion 103C. The second chip component 102 has a third electrode portion 102A, a second non-electrode portion 102B, and a fourth electrode portion 102C. The third chip component 104 has a fifth electrode portion 104A, a third non-electrode portion 104B, and a sixth electrode portion 104C. The first electrode portion 103A and the third electrode portion 102A are electrically connected by a conductive adhesive 105 such as solder. In each chip component, the non-electrode portion is provided between a pair of electrode portions.

[0017] Similarly, the fifth electrode portion 104A of the third chip component 104 and the fourth electrode portion 102C of the second chip component 102 are electrically connected by a conductive adhesive 105. That is, the conductive adhesive 105 forms a conductive adhesive layer. The first electrode portion 103A and the second electrode portion 103C of the first chip component 103 and the fifth electrode portion 104A and the sixth electrode portion 104C of the third chip component 104 are connected to the printed wiring board 10 via conductive pads 106. Note that the conductive adhesive 105 may be used instead of the conductive pads 106. The conductive pads 106 are connected to the load unit 13 via wiring (not shown) formed on the printed wiring board 10.

[0018] FIG. 3 is a diagram showing a conventional processing module 15. FIG. 3(a) is a top view showing the processing module 15. FIG. 3(b) is a cross-sectional view taken along dotted line A51-A'51 in FIG. 3(a). A first chip component 53 and a third chip component 54 are disposed on a surface layer 59 of a printed wiring board 50. A second chip component 52 is stacked on the first chip component 53 and the third chip component 54. The first chip component 53, the second chip component 52, and the third chip component 54 are chip components such as capacitors, resistors, and inductors.

[0019] The first chip component 53 has a first electrode portion 53A, a first non-electrode portion 53B, and a second electrode portion 53C. The second chip component 52 has a third electrode portion 52A, a second non-electrode portion 52B, and a fourth electrode portion 52C. The third chip component 54 has a fifth electrode portion 54A, a third non-electrode portion 54B, and a sixth electrode portion 54C. In each chip component, the non-electrode portion is provided between a pair of electrode portions.

[0020] The first electrode portion 53A of the first chip component 53 and the third electrode portion 52A of the second chip component 52 are connected by a conductive adhesive 55 such as solder. Similarly, the fifth electrode portion 54A of the third chip component 54 and the fourth electrode portion 52C of the second chip component 52 are connected by the conductive adhesive 55. The first electrode portion 53A, the second electrode portion 53C, the fifth electrode portion 54A, and the sixth electrode portion 54C are connected to the printed wiring board 50 via conductive pads 56. Note that the conductive adhesive 55 may be used instead of the conductive pads 56. The conductive pads 56 are also connected to a load unit (not shown) via wiring (not shown) formed on the printed wiring board 50.

[0021] In a top view from the Z direction, the second electrode portion 53C of the first chip component 53 and the sixth electrode portion 54C of the third chip component 54 are located outside the second chip component 52. The second electrode portion 53C of the first chip component 53 is electrically disconnected from the third electrode portion 52A and the fourth electrode portion 52C of the second chip component 52. In other words, the second electrode portion 53C of the first chip component 53 is electrically isolated from the third electrode portion 52A and the fourth electrode portion 52C of the second chip component 52. Similarly, the fifth electrode portion 54A of the third chip component 54 is electrically isolated from the third electrode portion 52A and the fourth electrode portion 52C of the second chip component 52.

[0022] In the first embodiment and the prior art, the size of the second chip components 102, 52 is larger than the sizes of the first chip components 103, 53 and the third chip components 104, 54. For example, the first chip components 103, 53 and the third chip components 104, 54 are chip components with a size of 0.4 mm x 0.2 mm (hereinafter referred to as "0402 size"). Also, the second chip components 102, 52 are chip components with a size of 1.0 mm x 0.5 mm (hereinafter referred to as "1005 size").

[0023] 2A and 3A, when comparing the occupied area of ​​chip components on printed wiring boards 10 and 50, the first embodiment is smaller than the prior art, allowing chip components to be arranged at a higher density. Comparing the occupied area for the example component sizes mentioned above, the prior art had a 0.632 mm 2 In contrast, in the first embodiment, it is 0.5 mm 2 Expressed in terms of the number of components that can be placed per unit area, the conventional technology achieves 4.7 components / mm 2 In contrast, in the first embodiment, it is 6 pieces / mm 2 As described above, according to the first embodiment of the present disclosure, components can be mounted at a higher density than with conventional techniques, and the degree of freedom in the layout of components and wiring is improved.

[0024] In the first embodiment, minute gaps 107 exist between the first chip component 103 and the second chip component 102, and between the third chip component 104 and the second chip component 102, due to the thickness of the adhesive layer formed by the conductive adhesive 105. The distance of the gap 107 in the stacking direction (Z direction) between the first chip component 103 and the second chip component 102 is, for example, less than 200 μm. In the gap 107, the second electrode portion 103C of the first chip component 103 is electrically isolated from the third electrode portion 102A and the fourth electrode portion 102C of the second chip component 102. Similarly, the sixth electrode portion 104C of the third chip component 104 is electrically isolated from the third electrode portion 102A and the fourth electrode portion 102C of the second chip component 102.

[0025] Furthermore, the second electrode portion 103C of the first chip component 103 is located between the second non-electrode portion 102B of the second chip component 102 and the printed wiring board 10. The second electrode portion 103C of the first chip component 103 overlaps the second non-electrode portion 102B of the second chip component 102 in a top view from the Z direction. Furthermore, the sixth electrode portion 104C of the third chip component 104 is located between the second non-electrode portion 102B and the printed wiring board 10. In a top view from the Z direction, the sixth electrode portion 104C of the third chip component 104 overlaps the second non-electrode portion 102B of the second chip component 102.

[0026] In this way, the second electrode portion 103C of the first chip component 103 and the sixth electrode portion 104C of the third chip component 104 are electrically isolated from the third electrode portion 102A and fourth electrode portion 102C of the second chip component 102 by the gap 107. By arranging the second electrode portion 103C of the first chip component 103 and the sixth electrode portion 104C of the third chip component 104 so as to overlap the second non-electrode portion 102B when viewed from above in the Z direction, multiple chip components can be arranged at high density.

[0027] Furthermore, when an interposer substrate or the like is interposed between the first chip component 103 and the second chip component 102, and between the third chip component 104 and the second chip component 102, as in the past, parasitic resistance and inductance of the wiring occur between the electrically connected electrodes (between the first electrode portion 103A of the first chip component 103 and the third electrode portion 102A of the second chip component 102, between the fifth electrode portion 104A of the third chip component 104 and the fourth electrode portion 102C of the second chip component 102, etc.), and the impedance in the path between the load unit and the chip components becomes large.

[0028] In contrast, in the first embodiment, an interposer substrate or the like is not interposed between the first chip component 103 and the second chip component 102, and between the third chip component 104 and the second chip component 102, and therefore it is possible to keep low the impedance in the path between the load unit and the chip components. Note that in the first embodiment, the power supply unit 12, the load unit 13, the first chip component 103, the second chip component 102, and the third chip component 104 are arranged on the same surface of the surface layer 113 of the printed wiring board 10, but they do not have to be arranged on the same surface.

[0029] [Second embodiment] FIG. 4A is a top view showing a processing module 2005 according to the second embodiment. FIG. 4B is a cross-sectional view taken along dotted line A201-A'201 in FIG. 4A. The following describes the differences between the second embodiment and the first embodiment. In the second embodiment, in addition to the first chip component 203 and the third chip component 204, a fourth chip component 214, a fifth chip component 215, a sixth chip component 216, and a seventh chip component 217 are arranged between the second non-electrode portion 202B of the second chip component 202 and the printed wiring board 210.

[0030] In the second embodiment, the size of the second chip component 202 is larger than the sizes of the first chip component 203, the third chip component 204, and the fourth chip component 214. For example, the first chip component 203, the third chip component 204, and the fourth chip component 214 are 0402 size chip components, and the second chip component is 1608 size chip component. When the number of components that can be placed per unit area is calculated, it is 4.7 components / mm with the prior art. 2 In contrast, in the second embodiment, it is 5.4 pieces / mm 2In other words, since many components can be arranged in a small area, it is possible to improve the degree of freedom in the layout of components and wiring. The size of each chip component is not limited to that described above. In addition, it is sufficient that the long side of the second chip component 202 is longer than the long sides of the first chip component 203, the third chip component 204, and the fourth chip component 214. For example, the length of each long side of the first chip component 203, the third chip component 204, and the fourth chip component 214 is half or less the length of the long side of the second chip component 202.

[0031] The seventh electrode portion 214A and the eighth electrode portion 214C of the fourth chip component 214 are electrically isolated from the third electrode portion 202A and the fourth electrode portion 202C of the second chip component 202 by a gap 207. The first chip component 203, the third chip component 204, and the fourth chip component 214 are arranged linearly along the longitudinal direction of the second chip component 202. In a top view from the Z direction, the seventh electrode portion 214A and the eighth electrode portion 214C of the fourth chip component 214 overlap with the second non-electrode portion 202B of the second chip component 202.

[0032] In this way, the seventh electrode portion 214A and the eighth electrode portion 214C of the fourth chip component 214 are electrically isolated from the third electrode portion 202A and the fourth electrode portion 202C of the second chip component 202 via the gap 207. The seventh electrode portion 214A and the eighth electrode portion 214C of the fourth chip component 214 are arranged so as to overlap the second non-electrode portion 202B of the second chip component 202 in a top view from the Z direction, thereby enabling components to be arranged at a high density. Furthermore, as shown in FIG. 4A , a fifth chip component 215, a sixth chip component 216, and a seventh chip component 217 are additionally arranged in the +Y direction of the fourth chip component 214. This allows chip components to be arranged at a high density on the printed wiring board 210.

[0033] Furthermore, the fourth chip component 214 may be electrically disconnected from the first chip component 203, the second chip component 202, and the third chip component 204. The first chip component 203, the second chip component 202, and the third chip component 204 may be connected such that a pair of electrodes thereof has a power supply potential V201 and a GND potential G201, and a pair of electrodes thereof has a power supply potential V202 and a GND potential G202. Whether or not to electrically connect them can be selected depending on the circuit to be realized.

[0034] [Third embodiment] Fig. 5A is a top view showing a processing module 3005 according to the third embodiment. Fig. 5B is a cross-sectional view in the XZ plane taken along dotted line A301-A'301 in Fig. 5A. Fig. 5C is a cross-sectional view in the XY plane taken along dotted line B301-B'301 in Fig. 5B. Differences between the third embodiment and the second embodiment will be described below.

[0035] In the third embodiment, a semiconductor device 350 is mounted on a surface layer 331 located on a surface 330 opposite to the main surface 312 of an insulating substrate 311. The semiconductor device 350 is an example of a load, such as a DRAM. In the third embodiment, the first chip component 303, the second chip component 302, the third chip component 304, the fourth chip component 314, the fifth chip component 315, the sixth chip component 316, and the seventh chip component 317 are capacitors. In the third embodiment, the second chip component 302 is larger in component size than the first chip component 303, the third chip component 304, the fourth chip component 314, the fifth chip component 315, the sixth chip component 316, and the seventh chip component 317. For example, the second chip component 302 may be a 1608 size chip component, and the other chip components may be 0402 size chip components.

[0036] The first electrode portion 303A of the first chip component 303 is connected to a power terminal of the semiconductor device 350 via the conductive adhesive 305, a power pad 303PV1, a power via 303VV, a power pad 303PV2, a bonding portion 303BV, and a power pad 303PV3.

[0037] The second electrode portion 303C of the first chip component 303 is connected to the GND terminal of the semiconductor device 350 via the conductive adhesive 305, the GND pad 303PG1, the GND via 303VG, the GND pad 303PG2, the bonding portion 303BG, and the GND pad 303PG3.

[0038] The sixth electrode portion 304C of the third chip component 304 is connected to the power terminal of the semiconductor device 350 via the conductive adhesive 305, the power pad 304PV1, the power via 304VV, the power pad 304PV2, the bonding portion 304BV, and the power pad 304PV3.

[0039] The fifth electrode portion 304A of the third chip component 304 is connected to the GND terminal of the semiconductor device 350 via the conductive adhesive 305, a GND pad 304PG1, a GND via 304VG, a GND pad 304PG2, a bonding portion 304BG, and a GND pad 304PG3.

[0040] The eighth electrode portion 314C of the fourth chip component 314 is connected to the power terminal of the semiconductor device 350 via the conductive adhesive 305, the power pad 314PV1, the power via 314VV, the power pad 314PV2, the bonding portion 314BV, and the power pad 314PV3.

[0041] The seventh electrode portion 314A of the fourth chip component 314 is connected to the GND terminal of the semiconductor device 350 via the conductive adhesive 305, a GND pad 314PG1, a GND via 314VG, a GND pad 314PG2, a bonding portion 314BG, and a GND pad 314PG3.

[0042] The third electrode portion 302A of the second chip component 302 is connected to a power supply terminal of the semiconductor device 350 via the conductive adhesive 305 and the first electrode portion 303A of the first chip component 303. The fourth electrode portion 302C of the second chip component 302 is connected to a GND terminal of the semiconductor device 350 via the conductive adhesive 305 and the second electrode portion 303C of the first chip component 303.

[0043] Similarly, the electrodes of the fifth chip component 315, the sixth chip component 316, and the seventh chip components 317 are connected to the semiconductor device 350 via conductive pads, vias, conductive adhesives, etc. As shown in Fig. 5B, the multiple power supply vias and the multiple GND vias are arranged parallel to each other in a cross-sectional view.

[0044] The first electrode portion 303A, the fifth electrode portion 304A, the seventh electrode portion 314A, the ninth electrode portion 315A, the eleventh electrode portion 316A, and the thirteenth electrode portion 317A are electrically connected via a power pad, a power via, and a power wiring 300TV. The second electrode portion 303C, the sixth electrode portion 304C, the eighth electrode portion 314C, the tenth electrode portion 315C, the twelfth electrode portion 316C, and the fourteenth electrode portion 317C are electrically connected via a GND pad, a GND via, and a GND wiring 300TG. A gap 307 partially exists between the fourth chip component 314 and the second chip component 302. Therefore, the seventh electrode portion 314A and the eighth electrode portion 314C of the fourth chip component 314 are electrically isolated from the third electrode portion 302A and the fourth electrode portion 302C of the second chip component 302 via the gap 307.

[0045] The third embodiment differs from the second embodiment in that the first chip component 303, the third chip component 304, the fifth chip component 315, and the sixth chip component 316 are arranged so that portions of them extend outside the second chip component. In this way, the arrangement of the multiple chip components (303, 304, 314, 315, 316, 317) arranged in the lower tier of stacked chip components can be adjusted to an optimal arrangement by adjusting the terminal pitch and via pitch of the semiconductor device 350. Furthermore, by arranging the chip components arranged in the lower tier at wider intervals, the risk of short circuits during solder mounting of the components can be reduced.

[0046] 5A and 5B, the direction of current in the processing module 3005 is indicated by dotted line I300. Here, the direction of current in the second chip component 302 is opposite to the direction of current in the fourth chip component 314 and the seventh chip component 317. The opposing currents have the effect of canceling out the magnetic fields they generate, so that the parasitic inductance (=ESL) of the capacitors can be reduced between the second chip component 302 and the fourth chip component 314 and between the second chip component 302 and the seventh chip component 317.

[0047] In addition, in top view, the multiple vias are arranged at positions overlapping with the respective electrode portions of the first chip component 303, the third chip component 304, and the fourth chip component 314. For example, in top view, the power supply via 303VV is arranged to overlap the first electrode portion 303A of the first chip component 303, and the GND via 303VG is arranged to overlap the second electrode portion 303B.

[0048] Furthermore, currents flow in opposite directions between power supply via 304VV and GND via 304VG, power supply via 314VV and GND via 314VG, power supply via 303VV and GND via 303VG, power supply via 315VV and GND via 315VG, power supply via 316VV and GND via 316VG, and power supply via 317VV and GND via 317VG. Specifically, the direction of current in power supply via 304VV is the +Z direction in FIG. 5B. GND via 304VG is adjacent to power supply via 304VV in the -X direction. The direction of current in GND via 304VG is the -Z direction in FIG. 5B.

[0049] Furthermore, currents flow oppositely between power supply via 314VV and GND via 304VG, between power supply via 317VV and GND via 316VG, between power supply via 315VV and GND via 317VG, and between power supply via 317VV and GND via 316VG. Specifically, the direction of current flow in power supply via 314VV is the +Z direction in FIG. 5B. GND via 304VG is adjacent to power supply via 314VV in the +X direction. The direction of current flow in GND via 304VG is the -Z direction in FIG. 5B. Opposing currents cancel out the magnetic fields they generate, thereby reducing the inductance of the power supply and GND vias.

[0050] A reduction in inductance reduces impedance, which has the effect of reducing potential fluctuations that occur at the power supply terminals of the semiconductor device due to displacement currents.

[0051] In the third embodiment, power supply pads 303PV1 and 315PV1, power supply pads 314PV1 and 317PV1, and power supply pads 304PV1 and 316PV1 are formed as separate pads, but they may be formed as a single pad. In that case, power supply vias 303VV and 315VV, power supply vias 314VV and 317VV, and power supply vias 304VV and 316VV may be formed as a single via rather than as separate vias. The same applies to GND pad 304PG1, GND pad 314PG1, GND pad 316PG1, GND pad 317PG1, GND via 304VG, GND via 314VG, GND via 316VG, and GND via 317VG.

[0052] [Example 1] Fig. 6A is a top view showing a processing module 3505 according to a comparative example for explaining the effects of the third embodiment. Fig. 6B is a cross-sectional view in the XZ plane taken along dotted line A351-A'351 in Fig. 6A. Fig. 6C is a cross-sectional view in the XY plane taken along dotted line B351-B'351 in Fig. 6B. Differences between the comparative example and the third embodiment will be described below.

[0053] As shown in FIGS. 6A and 6B , in the comparative example, the arrangement of the conductive pads, power supply vias, and GND vias from each of the fourth chip component 364 and the seventh chip component 367 to the semiconductor device 350 is reversed compared to the third embodiment. As a result, the direction of current flow in the fourth chip component 364 and the seventh chip component 367 is reversed compared to the third embodiment. Specifically, the direction of current flow in the fourth chip component 364 is the +X direction in a top view. Similarly, the direction of current flow in the seventh chip component 367 is the +X direction. The second chip component 352 is stacked on the fourth chip component 364 and the seventh chip component 367. The direction of current I350 in the second chip component 352 is the +X direction. Thus, the comparative example differs from the third embodiment in that the direction of current flow in the fourth chip component 364 and the seventh chip component 367 is the same as the direction of current flow in the second chip component 352. In the configuration of the comparative example, the currents of adjacent chip components do not flow in opposite directions, and therefore the magnetic fields generated do not cancel each other out.

[0054] FIG. 7 shows the simulation results of power impedance for Example 1 and the Comparative Example. In both Example 1 according to the third embodiment and the Comparative Example, the first chip component and the third to seventh chip components were multilayer ceramic capacitors with a component size of 0402 and a capacitance of 0.1 μF. The second chip component was a multilayer ceramic capacitor with a component size of 1608 and a capacitance of 10 μF. The multilayer ceramic capacitors were mounted on power supply pads and GND pads formed on the main surface of a 1 mm-thick printed wiring board. The electrical circuit of the multilayer ceramic capacitor was then extended to the opposite surface of the printed wiring board through 0.2 mm-diameter vias, and the impedance characteristics between the power supply and GND were observed. ANSYS Electronics Desktop 2021 R2 from ANSYS was used as the simulation tool. As shown in FIG. 7, Example 1 according to the third embodiment had lower impedance than the Comparative Example; for example, a reduction of 8.1% was observed at a frequency of 1 GHz.

[0055] [Fourth embodiment] FIG. 8 is a diagram showing a processing module 4005 according to the fourth embodiment. FIG. 8(a) is a top view showing the processing module 4005. FIG. 8(b) is a cross-sectional view in the XZ plane taken along dotted line A401-A'401 in FIG. 8(a). FIG. 8(c) is a cross-sectional view in the XY plane taken along dotted line B401-B'401 in FIG. 8(b). The following mainly describes the differences between the fourth embodiment and the other embodiments.

[0056] The semiconductor device 450 is an example of a load, such as an LSI package. In the fourth embodiment, the first chip component 403, the second chip component 402, the third chip component 404, the fourth chip component 414, the fifth chip component 415, the sixth chip component 416, the seventh chip component 417, the eighth chip component 418, and the ninth chip component 419 are capacitors. In the fourth embodiment, the size of the second chip component 402 is larger than the sizes of the other chip components (403, 404, 414, 415, 416, 417, 418, 419). For example, the second chip component 402 is a 1608 size chip component. The chip components other than the second chip component 402 are 0.6 mm x 0.3 mm in size (hereinafter referred to as "0603 size"). The first chip component 403 and the third to ninth chip components 404 to 419 are arranged so that their longitudinal directions are perpendicular to the longitudinal direction of the second chip component 402 (X direction).

[0057] 8(a) and 8(b), the direction of current in the processing module 4005 is indicated by dotted line I400. Among the first chip component 403, the third chip component 404, the fourth chip component 414, the fifth chip component 415, the sixth chip component 416, the seventh chip component 417, the eighth chip component 418, and the ninth chip component 419, the currents flow in opposite directions between adjacent capacitors in the X or Y direction. For example, in FIG. 8(a), the direction of current in the first chip component 403 is the -Y direction. The first chip component 403 is adjacent to the fourth chip component 414 in the X direction and to the sixth chip component 416 in the Y direction. The direction of current in the fourth chip component 414 is the +Y direction. Similarly, the direction of current in the sixth chip component 416 is the +Y direction. Opposing currents have the effect of canceling out the magnetic fields they generate, reducing the capacitor's parasitic inductance (ESL).

[0058] Furthermore, as shown in Fig. 8(b), when adjacent capacitors are arranged so that currents flow in opposite directions, the current directions in adjacent power supply vias and GND vias also flow in opposite directions. For example, in Fig. 8(b), the current direction in the GND via 414VG of the fourth chip component 414 is the -Z direction. In contrast, the current direction in the power supply via 415VV of the fifth chip component 415 is the +Z direction. The opposing currents cancel out the generated magnetic fields, thereby reducing the inductance of the power supply vias and GND vias.

[0059] [Example 2] 9A and 9B are diagrams showing a processing module 4505 according to a comparative example for explaining the effects of the fourth embodiment. FIG. 9A is a top view showing the processing module 4505. FIG. 9B is a cross-sectional view in the XZ plane taken along dotted line A451-A'451 in FIG. 9A. FIG. 9C is a cross-sectional view in the XY plane taken along dotted line B451-B'451 in FIG. 9B. The following describes the differences between the comparative example and the fourth embodiment.

[0060] 9(a) and 9(b), in the comparative example, the arrangement of the conductive pads, power supply vias, and GND vias from the fourth chip component 464, the fifth chip component 465, the eighth chip component 468, and the ninth chip component 469 to the semiconductor device 450 is opposite to that in the fourth embodiment. As a result, the direction of current in the fourth chip component 464, the fifth chip component 465, the eighth chip component 468, and the ninth chip component 469 is opposite to that in the fourth embodiment. As a result, in the comparative example, the magnetic field cancellation effect does not work between adjacent components (between the first chip component 453 and the fourth chip component 464, between the third chip component 454 and the fifth chip component 465, between the sixth chip component 466 and the eighth chip component 468, and between the seventh chip component 467 and the ninth chip component 469).

[0061] Similarly, between adjacent components (between the first chip component 453 and the fourth chip component 464, between the third chip component 454 and the fifth chip component 465, between the sixth chip component 466 and the eighth chip component 468, and between the seventh chip component 467 and the ninth chip component 469), the magnetic field cancellation effect between power supply vias and between GND vias no longer works.

[0062] FIG. 10 shows the simulation results of power supply impedance for Example 2 and the Comparative Example. In both Example 2 according to the fourth embodiment and the Comparative Example, the first chip component and the third to ninth chip components were multilayer ceramic capacitors with a component size of 0603 and a capacitance of 0.1 μF. The second chip component was a multilayer ceramic capacitor with a component size of 1608 and a capacitance of 10 μF. The multilayer ceramic capacitors were mounted on power supply pads and GND pads formed on the main surface of a 1 mm-thick printed wiring board. The electrical circuit of the multilayer ceramic capacitor was then extended to the opposite surface of the printed wiring board through vias with a diameter of 0.2 mm, and the impedance characteristics between the power supply and GND were observed. As shown in FIG. 10, Example 2 according to the fourth embodiment had lower impedance than the Comparative Example; for example, a 13.7% reduction was confirmed at a frequency of 1 GHz.

[0063] [Fifth embodiment] FIG. 11 is a diagram showing a processing module 5005 according to the fifth embodiment. FIG. 11(a) is a top view showing the processing module 5005. FIG. 11(b) is a cross-sectional view in the XZ plane taken along dotted line A501-A'501 in FIG. 11(a). FIG. 11(c) is a cross-sectional view in the XY plane taken along dotted line B501-B'501 in FIG. 11(b). FIG. 11(d) is a diagram expressing the processing module 5005 according to the fifth embodiment in the form of an equivalent circuit. The following mainly describes the differences between the fifth embodiment and the other embodiments.

[0064] In the fifth embodiment, the first chip component 503, the second chip component 502, and the fourth chip component 514 are capacitors. In the fifth embodiment, the third chip component 504 is a chip resistor. In the fifth embodiment, the second chip component 502 is larger in size than the first chip component 503, the third chip component 504, and the fourth chip component 514. For example, the first chip component 503, the third chip component 504, and the fourth chip component 514 are 0603 size chip components, and the second chip component is 1608 size chip component. Furthermore, in the Z direction of FIG. 11(b), the height of the third chip component 504 is lower than the heights of the first chip component 503 and the fourth chip component 514. Therefore, in the fifth embodiment, a spacer 506 is disposed between the second chip component 502 and the third chip component 504 to align the heights of the components. The spacer 506 is a non-conductive material. The spacer 506 may be omitted.

[0065] The fourth electrode portion 502C of the second chip component 502 and the fifth electrode portion 504A of the third chip component 504 are connected by a conductive adhesive 505 such as solder. In addition, the second electrode portion 503C of the first chip component 503 and the sixth electrode portion 504C of the third chip component 504 are connected via a GND pad 503PG1.

[0066] The fifth electrode portion 504A of the third chip component 504 is fixed to the dummy pad 504PD with a conductive adhesive 505. The fifth electrode portion 504A of the third chip component 504 and the dummy pad 504PD may be in contact with each other without the conductive adhesive 505. Also, the dummy pad 504PD may not be present.

[0067] 11(a) and 11(b), the dotted lines indicate the direction of current in the processing module 5005. For example, the dotted line I500 indicates the direction of current in the second chip component 502.

[0068] 11(d), multiple chip components are connected in parallel between a power supply terminal 550V and a GND terminal 550G of a semiconductor device 550. A capacitor C502 is the second chip component 502, a capacitor C503 is the first chip component 503, a capacitor C514 is the fourth chip component 514, and a chip resistor R504 is the third chip component 504.

[0069] As shown in FIGS. 11(a)-(d), in the fifth embodiment, a chip resistor R504 is connected in series with a capacitor C502. The effect of the chip resistor R504 will now be described. In a circuit in which multiple capacitors are connected in parallel, an anti-resonance phenomenon occurs, increasing impedance at the anti-resonance frequency. This increased impedance peak can cause fluctuations in the power supply potential, potentially resulting in malfunction of the semiconductor device. The anti-resonance frequency and peak magnitude are determined by the capacitance, internal parasitic inductance, and internal resistance of each capacitor, as well as the inductance and resistance of the wiring between the capacitors. One way to reduce the anti-resonance peak value is to increase the resistance of the wiring between the capacitors. The chip resistor R504 is added to increase the resistance of the wiring between the capacitors.

[0070] [Example 3] FIG. 12 is a diagram showing a processing module 5505 according to a comparative example for explaining the effects of the fifth embodiment. FIG. 12(a) is a top view showing the processing module 5505. FIG. 12(b) is a cross-sectional view in the XZ plane taken along dotted line A551-A'551 in FIG. 12(a). FIG. 12(c) is a cross-sectional view in the XY plane taken along dotted line B551-B'551 in FIG. 12(b). FIG. 12(d) is a diagram expressing the processing module 5505 according to the comparative example in the form of an equivalent circuit. Below, differences between the comparative example and the fifth embodiment will be described.

[0071] The comparative example differs from the fifth embodiment in that the third chip component 504 (chip resistor R504) shown in Figures 11(a)-(d) is not present in the circuit. In addition, the comparative example differs from the fifth embodiment in the positions of the first chip component 553 and the fourth chip component 564, which are capacitors, and the positions of the power supply pads, GND pads, and vias connected to each capacitor. The layout of this comparative example is the same as that in the first embodiment described above.

[0072] FIG. 13 shows the results of a simulation experiment for Example 3 according to the fifth embodiment and a comparative example. The first and fourth chip components were multilayer ceramic capacitors with a component size of 0603 and a capacitance of 0.1 μF. The second chip component was a multilayer ceramic capacitor with a component size of 1608 and a capacitance of 10 μF. The fourth chip component was a chip resistor with a component size of 0603 and an electrical resistance of 40 mΩ. The multilayer ceramic capacitor was mounted on power supply pads and GND pads formed on the main surface of a 1 mm thick printed wiring board. The electrical circuit of the multilayer ceramic capacitor was extended to the opposite surface of the printed wiring board through a 0.2 mm diameter via, and the impedance characteristics between the power supply and GND were observed.

[0073] As shown in FIG. 13, an anti-resonance peak is observed in the comparative example at a frequency of around 0.01 GHz. In contrast, in Example 3 according to the fifth embodiment, the anti-resonance peak detected in the comparative example is reduced. Typically, a semiconductor device has a tolerance set for each frequency as the impedance characteristic of the power supply. The tolerance is determined by the operating frequency of the semiconductor device and its sensitivity to external noise. Assuming that the tolerance is set as shown by the dotted line in FIG. 13, the calculated value in the comparative example exceeds the tolerance, whereas the calculated value in Example 3 meets the tolerance.

[0074] [Sixth embodiment] FIG. 14 is a diagram showing a processing module 6005 according to the sixth embodiment. FIG. 14(a) is a top view showing the processing module 6005. FIG. 14(b) is a side view showing the processing module 6005. FIG. 14(c) is a cross-sectional view in the XY plane taken along dotted line B601-B'601 in FIG. 14(b). The following mainly describes the differences between the sixth embodiment and the other embodiments.

[0075] In the sixth embodiment, the second chip component 602, the third chip component 604, the fourth chip component 603, and the fifth chip component 601 are chip resistors. The first chip component 605 is a capacitor. In the sixth embodiment, the first to fifth chip components are all the same component size. The first to fifth chip components are, for example, 0402 size chip components.

[0076] The first chip component 605, the third chip component 604, and the fourth chip component 603 are mounted on the main surface of a printed wiring board 610. Dummy pads 603PD and 604PD are provided between the first chip component 605, the third chip component 604, and the fourth chip component 603 and the printed wiring board 610.

[0077] A second chip component 602 and a fifth chip component 601 are stacked on the first chip component 605. A non-conductive member 606 is provided between the first chip component 605 and the second chip component 602 and fifth chip component 601. The second chip component 602 is connected to the fifth chip component 601 by a conductive adhesive 607.

[0078] Furthermore, the electrode portions at both ends of the first chip component 605 overlap the non-electrode portions of the fifth chip component 601 and the non-electrode portions of the second chip component 602, respectively, when viewed from above in the Z direction. The electrode portions of the first chip component 605 are electrically isolated from the electrode portions of the fifth chip component 601 and the second chip component 602. In contrast, the fourth chip component 603, the fifth chip component 601, the second chip component 602, and the third chip component 604 are connected via a conductive adhesive 607. In other words, the first chip component 605 is not electrically connected to any of the fourth chip component 603, the fifth chip component 601, the second chip component 602, and the third chip component 604. Thus, according to the sixth embodiment, by arranging chip components that are not connected to each other so that their electrode portions and non-electrode portions overlap, separate circuits can be configured in the Z direction.

[0079] [Seventh embodiment] FIG. 15 is a diagram showing a processing module 7005 according to the seventh embodiment. FIG. 15(a) is a top view showing the processing module 7005. FIG. 15(b) is a side view showing the processing module 7005. FIG. 15(c) is a cross-sectional view in the XY plane taken along dotted line B701-B'701 in FIG. 15(b). FIG. 15(d) is a cross-sectional view in the XY plane taken along dotted line C701-C'701 in FIG. 15(b). The following mainly describes the differences between the seventh embodiment and the other embodiments.

[0080] In the seventh embodiment, the first chip component 702 and the second chip component 701 are chip components of the same component size. The first chip component 702 and the second chip component 701 are, for example, 0402 size capacitors. Electrode portions on both ends of the first chip component 702 are connected to a power supply pad 702PV1 and a GND pad 702PG1, respectively, formed on a printed wiring board 710. Electrode portions on both ends of the second chip component 701 are connected to a power supply pad 701PV1 and a dummy pad 701PD, respectively, formed on a printed wiring board 711.

[0081] Furthermore, of the electrode portions on both ends of the first chip component 702, one electrode portion (the electrode portion in the -X direction in the figure) is connected to a power supply pad 701PV2 formed on the printed wiring board 710 via a conductive adhesive 705 such as solder. The other electrode portion (the electrode portion in the +X direction in the figure) of the first chip component 702 is connected to a power supply pad 701PV1 formed on the printed wiring board 711. As shown in FIG. 15(b), the two chip components are sandwiched between the two printed wiring boards 710, 711. Here, the dotted line I700 indicates the direction of current flowing through the printed wiring board 711, the second chip component 701, the conductive adhesive 705, and the printed wiring board 710.

[0082] Thus, according to the seventh embodiment, by arranging the electrode portion of the second chip component 701 so that it overlaps the non-electrode portion of the first chip component 702 in the Z direction, it is possible to configure a circuit spanning the upper and lower printed wiring boards 710, 711 and a circuit closed between the printed wiring board 710 and the first chip component 702 separately in a narrow area.

[0083] [Eighth embodiment] FIG. 16 is a diagram showing a processing module 8005 according to the eighth embodiment. FIG. 16(a) is a top view showing the processing module 8005. FIG. 16(b) is a side view showing the processing module 8005. FIG. 16(c) is a cross-sectional view in the XY plane taken along dotted line B801-B'801 in FIG. 16(b). FIG. 16(d) is a cross-sectional view in the XY plane taken along dotted line C801-C'801 in FIG. 16(b). The following mainly describes the differences between the eighth embodiment and the other embodiments.

[0084] In the eighth embodiment, the first chip component 802, the second chip component 801, and the third chip component 803 are all chip components of the same size, such as an 0402-size capacitor. The electrodes of the first chip component 802 and the third chip component 803 are connected to a power supply pad 802PV1, a GND pad 802PG1, a power supply pad 803PV1, and a GND pad 803PG1, respectively, formed on a printed wiring board 810. The dotted line I801 indicates that a current flows from the printed wiring board 810 to the first chip component 802 and returns to the printed wiring board 810. Similarly, the dotted line I802 indicates that a current flows from the printed wiring board 810 to the third chip component 803 and returns to the printed wiring board 810.

[0085] 16(b), the three chip components are sandwiched between two printed wiring boards 810 and 811. The dotted line I800 indicates that a current flows from the printed wiring board 811 to the second chip component 801 and returns to the printed wiring board 811.

[0086] According to the eighth embodiment, separate circuits can be formed in the Z direction by arranging the two electrode portions of the second chip component 801 so that they overlap the non-electrode portions of the first chip component 802 and the third chip component 803. The circuits can be formed without using the conductive adhesive used in the seventh embodiment.

[0087] [Ninth embodiment] FIG. 17 is a diagram showing a processing module 9005 according to the ninth embodiment. FIG. 17(a) is a top view showing the processing module 9005 according to the ninth embodiment. FIG. 17(b) is a side view showing the processing module 9005 according to the ninth embodiment. FIG. 17(c) is a cross-sectional view in the XY plane taken along dotted line B901-B'901 in FIG. 17(b). FIG. 17(d) is a cross-sectional view in the XY plane taken along dotted line C901-C'901 in FIG. 17(b). The following mainly describes the differences between the ninth embodiment and the other embodiments.

[0088] In the ninth embodiment, the first chip component 902, the second chip component 901, and the third chip component 903 are all chip components of the same size, for example, 0402 size capacitors. The electrodes of the first chip component 902 and the third chip component 903 are connected to a power supply pad 902PV1, a GND pad 902PG1, and a GND pad 902PG1 formed on a printed wiring board 910. The electrodes of the second chip component 901 are connected to a power supply pad 901PV1 and a GND pad 901PG1 formed on a printed wiring board 911, respectively.

[0089] As shown in FIG. 17(b), three chip components are sandwiched between two printed wiring boards 910 and 911. By arranging the electrode portion of the second chip component 901 so that it overlaps with the electrode portion of the first chip component 902 and the non-electrode portion of the third chip component 903, separate circuits can be configured in the Z direction. In the ninth embodiment, the component layout shape on the lower printed wiring board 910 differs from that in the eighth embodiment. In this way, the ninth embodiment allows for free layout.

[0090] [Tenth embodiment] FIG. 18 is a diagram showing a processing module 10005 according to the tenth embodiment. FIG. 18(a) is a top view showing the processing module 10005. FIG. 18(b) is a side view showing the processing module 10005. FIG. 18(c) is a cross-sectional view in the XY plane taken along dotted line B1001-B'1001 in FIG. 18(b). FIG. 18(d) is a cross-sectional view in the XY plane taken along dotted line C1001-C'1001 in FIG. 18(b). The following mainly describes the differences between the tenth embodiment and the other embodiments.

[0091] In the tenth embodiment, the first chip component 1002, the second chip component 1001, and the third chip component 1003 are all chip components of the same size, such as a 0402 size capacitor. The electrode portion of the first chip component 1002 is connected to a power supply pad 1002PV1 and a GND pad 1002PG1 formed on the printed wiring board 1010. The electrode portion of the third chip component 1003 is connected to power supply pads 1002PV1 and 1003PG1 formed on the printed wiring board 1010. That is, the electrode portions of two chip components are connected to the power supply pad 1002PV1. The electrode portion of the second chip component 1001 is connected to a power supply pad 1001PV1 and a GND pad 1001PG1 formed on the upper printed wiring board 1011. As shown in FIG. 18(b), the three chip components are sandwiched between the two printed wiring boards 1010 and 1011.

[0092] In this way, by arranging the electrode portions of the second chip component 1001 so that they overlap the non-electrode portions of the first chip component 1002 and the non-electrode portions of the third chip component 1003, separate circuits can be configured in the Z direction. In the tenth embodiment, the shape of the component layout on the upper printed wiring board 1011 differs from that in the ninth embodiment, and the projected area of ​​the chip components as viewed in the Z direction can be made smaller than in the ninth embodiment. This improves the degree of freedom in layout.

[0093] [Eleventh embodiment] FIG. 19 is a diagram showing a processing module 11005 according to the eleventh embodiment. FIG. 19(a) is a top view showing the processing module 11005. FIG. 19(b) is a side view showing the processing module 11005. FIG. 19(c) is a cross-sectional view in the XY plane taken along dotted line B1101-B'1101 in FIG. 19(b). FIG. 19(d) is a cross-sectional view in the XY plane taken along dotted line C1101-C'1101 in FIG. 19(b). The following mainly describes the differences between the eleventh embodiment and the other embodiments.

[0094] In the eleventh embodiment, a first chip component 1102, a second chip component 1101, a third chip component 1103, a fourth chip component 1104, and a fifth chip component 1105 are all chip components of the same size, for example, 0402 size capacitors. The electrodes of the first chip component 1102, the third chip component 1103, the fourth chip component 1104, and the fifth chip component 1105 are connected to power supply pads 1102PV1, 1104PV1, 1105PV1, GND pads 1102PG1, 1103PG1, 1104PG1, and GND pads 1105PG1 formed on a printed wiring board 1110, respectively.

[0095] The electrode portions of the second chip component 1101 are connected to a power supply pad 1101PV1 and a GND pad 1101PG1 formed on a printed wiring board 1111. As shown in FIGS. 19(a) and 19(b), five chip components are sandwiched between two printed wiring boards 1110 and 1111. When viewed from above, the chip components are arranged so that two electrode portions of the second chip component 1101 overlap non-electrode portions of any of the first chip component 1102, the third chip component 1103, the fourth chip component 1104, and the fifth chip component 1105, and the electrode portions of the first chip component 1102, the third chip component 1103, the fourth chip component 1104, and the fifth chip component 1105 overlap non-electrode portions of the second chip component, thereby forming separate circuits in the Z direction. In the eleventh embodiment, more chip components can be mounted and layout freedom is improved compared to the tenth embodiment.

[0096] [Twelfth embodiment] FIG. 20 is a diagram showing a processing module 12005 according to the twelfth embodiment. FIG. 20(a) is a side view showing the processing module 12005. FIG. 20(b) is a top view showing the processing module 12005. FIG. 20(c) is a cross-sectional view in the XY plane taken along dotted line B1101-B'1101 in FIG. 20(a). The following mainly describes the differences between the twelfth embodiment and the other embodiments.

[0097] In the twelfth embodiment, the first chip component 1202, the third chip component 1203, and the fourth chip component 1204 are all chip components of the same size, for example, 0402 size capacitors. The second chip component 1201 is, for example, a 1005 size capacitor.

[0098] One electrode portion of the first chip component 1202 (the electrode portion in the -X direction in the figure) is connected to one electrode portion of the second chip component 1201 (the electrode portion in the -X direction in the figure). Similarly, one electrode portion of the third chip component 1203 (the electrode portion in the +X direction in the figure) is connected to the other electrode portion of the second chip component 1201 (the electrode portion in the +X direction in the figure). This configuration is the same as in the first embodiment. In the twelfth embodiment, the fourth chip component 1204 is disposed adjacent to the first chip component 1202 and the third chip component 1203. Neither of the electrode portions on either end of the fourth chip component 1204 is connected to the electrode portions of the other components.

[0099] 20(c), on the printed wiring board 1210, the fourth chip component 1204 is positioned further in the Y direction than the first chip component 1202 and the third chip component 1203, and is arranged so as to straddle the first chip component 1202 and the third chip component 1203 in the X direction. As a result, the first chip component 1202, the third chip component 1203, and the fourth chip component 1204 are arranged in greater numbers in the longitudinal direction of the second chip component 1201 than in the lateral direction. According to the twelfth embodiment, one more chip component is mounted than in the first embodiment in an area having the same area as the first embodiment, further improving the degree of freedom in layout.

[0100] [Thirteenth embodiment] FIG. 21 is a diagram showing a processing module 13005 according to the thirteenth embodiment. FIGS. 21(a) and 21(b) are perspective views for explaining the manufacturing process of the processing module 13005. FIG. 21(c) is a side view showing the processing module 13005. FIG. 21(d) is a top view showing the processing module 13005. FIG. 21(e) is a cross-sectional view in the XY plane taken along dotted line B1101-B'1101 in FIG. 21(c). The following mainly describes the differences between the thirteenth embodiment and the other embodiments.

[0101] In the thirteenth embodiment, the first chip component 1302, the third chip component 1303, the fourth chip component 1304, and the fifth chip component 1305 are all chip components of the same size, such as 0402 size capacitors. The second chip component 1301 is, for example, a 1005 size capacitor.

[0102] Here, in the first chip component 1302, the electrode in the +X direction is referred to as the first electrode portion, the electrode in the -X direction as the second electrode portion, and the space between the two electrode portions as the first non-electrode portion. Similarly, in the second chip component 1301, the electrode in the +X direction is referred to as the third electrode portion, the electrode in the -X direction as the fourth electrode portion, and the space between the two electrode portions as the second non-electrode portion. In the third chip component 1303, the electrode in the +X direction is referred to as the fifth electrode portion, the electrode in the -X direction as the sixth electrode portion, and the space between the two electrode portions as the third non-electrode portion. In the fourth chip component 1304, the electrode in the +X direction is referred to as the seventh electrode portion, the electrode in the -X direction as the eighth electrode portion, and the space between the two electrode portions as the fourth non-electrode portion. In the fifth chip component 1305, the electrode in the +X direction is referred to as the ninth electrode portion, the electrode in the -X direction as the tenth electrode portion, and the space between the two electrode portions as the fifth non-electrode portion.

[0103] As shown in FIG. 21(a), a first chip component 1302, a third chip component 1303, a fourth chip component 1304, and a fifth chip component 1305 are arranged on a printed wiring board 1310. Next, a second chip component 1301 is stacked on the first chip component 1302, the third chip component 1303, the fourth chip component 1304, and the fifth chip component 1305. At this time, as shown in FIG. 21(b), the longitudinal sides of the first chip component 1302, the third chip component 1303, the fourth chip component 1304, and the fifth chip component 1305 are arranged so that they intersect at a predetermined angle with the longitudinal side of the second chip component 1301. As a result, the second electrode portion, the sixth electrode portion, the seventh electrode portion, the eighth electrode portion, and the ninth electrode portion each partially protrude from the second non-electrode portion of the second chip component 1301 in a top view. The third electrode portion and the fourth electrode portion partially protrude from the first non-electrode portion, the third non-electrode portion, the fourth non-electrode portion, and the fifth non-electrode portion in top view, thereby reducing the area occupied by the multiple chip components in top view, and the stacked structure of the chip components establishes multiple electric circuits between printed wiring board 1310 and the chip components.

[0104] According to the thirteenth embodiment, it is possible to increase the number of components that can be arranged on the mounting surface of the printed wiring board 1310. In the thirteenth embodiment, for example, one more chip component can be arranged on the mounting surface of the same area compared to the first embodiment.

[0105] [Fourteenth embodiment] Fig. 22 is a diagram showing a processing module 14005 according to the fourteenth embodiment. Fig. 22(a) is a top view showing the processing module 14005. Fig. 22(b) is a cross-sectional view of the processing module 14005 in the XY plane. The following mainly describes the differences between the fourteenth embodiment and the other embodiments.

[0106] The first chip component 1402, the third chip component 1403, the fourth chip component 1404, the fifth chip component 1405, the sixth chip component 1406, and the seventh chip component 1407 are all chip components of the same size, such as a 0402 size capacitor. The second chip component 1401 is a chip component larger in size than the other chip components, such as a 1608 size capacitor.

[0107] The longitudinal sides of the first chip component 1402, the fourth chip component 1404, and the sixth chip component 1406 are all arranged parallel to one another. In contrast, the longitudinal sides of the third chip component 1403, the fifth chip component 1405, and the seventh chip component 1407 are all arranged parallel to one another. The longitudinal sides of the first chip component 1402, the fourth chip component 1404, and the sixth chip component 1406 intersect at a predetermined angle with the longitudinal sides of the third chip component 1403, the fifth chip component 1405, and the seventh chip component 1407. For example, in FIG. 22(a), the longitudinal side of the first chip component 1402 intersects at a 90-degree angle with the longitudinal side of the adjacent third chip component 1403.

[0108] Furthermore, the longitudinal sides of the second chip component 1401 intersect at an angle that is half the angle formed by the longitudinal sides of the two sets of chip capacitors. The angle at which the two sides intersect is, for example, 45 degrees. The power supply pad 1402PV1 is a power supply pad that connects the electrode portion of the first chip component 1402. The GND pad 1402PG1 is a common GND pad that connects the electrode portions of the first chip component 1402, the third chip component 1403, the fifth chip component 1405, and the sixth chip component 1406.

[0109] The power supply pad 1403PV1 is a common power supply pad that connects the electrodes of the third chip component 1403 and the fourth chip component 1404. The GND pad 1403PG1 is a common GND pad that connects the electrodes of the fourth chip component 1404 and the seventh chip component 1407. The power supply pad 1405PV1 is a power supply pad that connects the electrodes of the fifth chip component 1405. The power supply pad 1406PV1 is a common power supply pad that connects the electrodes of the sixth chip component 1406 and the seventh chip component 1407.

[0110] The electrodes of the first chip component 1402 and the fifth chip component 1405 connected to the power supply pads 1402PV1 and 1405PV1 are connected to one electrode of the second chip component 1401 stacked on top of them. Furthermore, the electrodes of the fourth chip component 1404 and the seventh chip component 1407 connected to the GND pad 1403PG1 are connected to the other electrode of the second chip component 1401 stacked on top of them.

[0111] The above configuration allows for an increased number of mounted components. Also, as can be seen from the current direction indicated by the arrows in Figure 22(a), the currents in the parallel facing chip components flow in opposite directions and cancel each other out, which has the effect of reducing inductance.

[0112] [Fifteenth embodiment] Figure 23 is a diagram showing a processing module 15005 according to the fifteenth embodiment. Figure 23(a) is a top view showing the processing module 15005. Figure 23(b) is a cross-sectional view of the processing module 15005 in the XY plane. The following mainly describes the differences between the fifteenth embodiment and the other embodiments.

[0113] The first chip component 1503, the third chip component 1504, the fourth chip component 1505, and the fifth chip component 1506 are all the same size, for example, 0603 size capacitors. The second chip component 1501 and the sixth chip component 1502 are, for example, 1005 size capacitors.

[0114] The power supply pad 1503PV1 is a common power supply pad that connects the electrode portions of the first chip component 1503 and the third chip component 1504. The GND pad 1503PG1 is a common GND pad that connects the electrode portions of the first chip component 1503 and the fifth chip component 1506. The power supply pad 1505PV1 is a common power supply pad that connects the electrode portions of the fourth chip component 1505 and the fifth chip component 1506. The GND pad 1505PG1 is a common GND pad that connects the electrode portions of the third chip component 1504 and the fourth chip component 1505.

[0115] An electrode portion of the third chip component 1504 is connected to a power supply pad 1503PV1. An electrode portion of the third chip component 1504 is connected to one electrode portion of the second chip component 1501 stacked on top of it. Furthermore, each electrode of the first chip component 1503 and the fifth chip component 1506 is connected to a GND pad 1503PG1. Each electrode portion of the first chip component 1503 and the fifth chip component 1506 is connected to the other electrode portion of the second chip component 1501 stacked on top of it.

[0116] The electrode portion of the fifth chip component 1506 is connected to a power supply pad 1505PV1. The electrode portion of the fifth chip component 1506 is connected to one of the electrodes of the second chip component 1501 stacked on top. Furthermore, the electrodes of the third chip component 1504 and the fourth chip component 1505 are connected to a GND pad 1505PG1. The electrodes of the third chip component 1504 and the fourth chip component 1505 are connected to the other of the electrodes of the sixth chip component 1502 stacked on top. With the above configuration, it is possible to increase the number of components to be mounted.

[0117] [16th embodiment] FIG. 24 is a diagram showing a processing module 16005 according to the sixteenth embodiment. FIG. 24(a) is a top view showing the processing module 16005. FIG. 24(b) is a cross-sectional view of the processing module 16005 in the XZ plane taken along dotted line A1601-A'1601. FIG. 24(c) is a cross-sectional view of the processing module 16005 in the XY plane taken along dotted line B1601-B'1601 in FIG. 24(b). FIG. 24(d) is a diagram expressing the processing module 16005 in the form of an equivalent circuit. The following mainly describes the differences between the sixteenth embodiment and the other embodiments, particularly the fifth embodiment.

[0118] The sixteenth embodiment differs from the fifth embodiment in the position of the via. In the fifth embodiment shown in FIGS. 11(a)-(d), the GND 503VG via is connected to the GND pad 503PG1. The GND pad 503PG1 is connected to the electrode portion 503A of the first chip component 503. In contrast, in the sixteenth embodiment, the GND via 1604VG is connected to the GND pad 1604PG1. The GND pad 1604PG1 is connected to the electrode portion 1604A of the third chip component 1604 (chip resistor R1604). Although the distance between the power supply via and the GND via is greater than in the fifth mounting embodiment, and the inductance of the via increases, the effect of suppressing the increase in impedance due to antiresonance can be similarly obtained.

[0119] [17th embodiment] FIG. 25 is a diagram showing a processing module 17005 according to the seventeenth embodiment. FIG. 25(a) is a top view showing the processing module 17005. FIG. 25(b) is a cross-sectional view of the XZ plane taken along dotted line A1701-A'1701 in FIG. 25(a). FIG. 25(c) is a side view of the processing module 17005 according to the seventeenth embodiment from the X direction. The following mainly describes the differences between the seventeenth embodiment and the other embodiments.

[0120] First chip component 1703, third chip component 1704, fourth chip component 1705, and fifth chip component 1706 are all the same size, for example, a 0402 size capacitor. Second chip component 1702 is, for example, a 1005 size capacitor. First chip component 1703 and third chip component 1704 are mounted on the main surface of printed wiring board 1710, with chip component 1702 mounted on top of them, and fourth chip component 1705 and fifth chip component 1706 mounted on top of that.

[0121] The electrode portions of the first chip component 1703 and the third chip component 1704 are connected to conductive pads formed on the main surface of the printed wiring board 1710. One electrode portion of the first chip component 1703 and the fourth chip component 1705 is connected to one electrode portion of the second chip component 1702, and one electrode portion of the third chip component 1704 and the fifth chip component 1706 is connected to the other electrode portion of the second chip component 1702. The electrode portion of the fourth chip component 1705 and the electrode portion of the fifth chip component 1706 are connected to each other by a conductive adhesive 1707 such as solder.

[0122] In this way, it is possible to form multiple circuits on a printed wiring board even with a structure in which components are stacked three levels. According to the seventeenth embodiment, by extending the circuits in a direction perpendicular to the main surface of the printed wiring board, it is possible to reduce the area occupied by chip components on the printed wiring board, and further improve the degree of freedom in layout.

[0123] [Eighteenth embodiment] FIG. 26 is a diagram showing a processing module 18005 according to the eighteenth embodiment. FIG. 26(a) is a side view showing the processing module 18005. FIG. 26(b) is a cross-sectional view in the ZY plane taken along dotted line A1801-A'1801 in FIG. 26(a). FIG. 26(c) is a cross-sectional view in the XY plane taken along dotted line B1801-B'1801 in FIG. 26(a). FIG. 26(d) is a cross-sectional view in the XY plane taken along dotted line C1801-C'1801 in FIG. 26(a). The following mainly describes the differences between the eighteenth embodiment and the other embodiments.

[0124] The first chip component 1803, the third chip component 1804, the fourth chip component 1805, and the fifth chip component 1806 are all capacitors of the same size (first capacitor), for example, an 0402 size capacitor. The second chip component 1802 is a capacitor (second capacitor) larger than the first capacitor, for example, a 1005 size capacitor. The first chip component 1803 and the third chip component 1804 are mounted on the main surface of the printed wiring board 1810. The second chip component 1802 is mounted on the first chip component 1803 and the third chip component 1804. The fourth chip component 1805 and the fifth chip component 1806 are mounted on the second chip component 1802. Another printed wiring board 1820 is provided on the fourth chip component 1805 and the fifth chip component 1806.

[0125] The electrode portions of the first chip component 1803 and the third chip component 1804 are connected to conductive pads formed on the main surface of a printed wiring board (first wiring board) 1810. One electrode portion of the first chip component 1803 is also connected to one electrode portion of the second chip component 1802. Similarly, one electrode portion of the third chip component 1804 is also connected to the other electrode portion of the second chip component 1802. The electrode portions of the fourth chip component 1805 and the fifth chip component 1806 are connected to conductive pads formed on the main surface of a printed wiring board (second wiring board) 1820. One electrode portion of the fourth chip component 1805 is also connected to one electrode portion of the second chip component 1802. And one electrode portion of the fifth chip component 1806 is also connected to the other electrode portion of the second chip component 1802.

[0126] Of the two main surfaces of printed wiring board 1810, a first semiconductor device 1850 is mounted on the surface on which first chip component 1803 and third chip component 1804 are not mounted. Furthermore, of the main surfaces of printed wiring board 1820, a second semiconductor device 1860 is mounted on the surface on which fourth chip component 1805 and fifth chip component 1806 are not mounted. In this way, the capacitors (first chip component 1803, second chip component 1802 to fifth chip component 1806) are electrically connected to first semiconductor device 1850 and second semiconductor device 1860 via conductor pads and vias.

[0127] This configuration allows the first semiconductor device 1850 and the second semiconductor device 1860 to share the second chip component 1802, which is a capacitor. A large-sized capacitor such as the second chip component 1802 is effective in suppressing low-frequency potential fluctuations in the semiconductor device, and compared to capacitors for high frequencies (the first chip component 1803, the third chip components 1804 to the fifth chip components 1806), it is effective even when located somewhat farther away from the first semiconductor device 1850 and the second semiconductor device 1860. By sharing the second chip component 1802 at a position slightly farther away from the first semiconductor device 1850 and the second semiconductor device 1860, the area occupied by the chip components on the main surface of the printed wiring board is reduced, improving the degree of freedom in layout.

[0128] [19th embodiment] FIG. 27A is a top view of a processing module 19001 according to the nineteenth embodiment. FIG. 27B is a cross-sectional view of the processing module 19001 according to the nineteenth embodiment taken along line BB'. The printed wiring board 1903 has an insulating substrate 1915 and at least one conductor layer. The at least one conductor layer includes a surface layer 1914 located on a main surface 1913 of the insulating substrate 1915. A first pad 1905, a second pad 1906, a third pad 1907, and a fourth pad 1908 are provided on the surface layer 1914 of the printed wiring board 1903 as electrodes.

[0129] The first pad 1905 is bonded to a first bonding material 1909. The second pad 1906 is bonded to a second bonding material 1910. The third pad 1907 is bonded to a third bonding material 1911. The fourth pad 1908 is bonded to a fourth bonding material 1912. The bonding area between the third bonding material 1911 and the third pad 1907 and the bonding area between the fourth bonding material 1912 and the fourth pad 1908 are both larger than the bonding area between the first bonding material 1909 and the first pad 1905 and the bonding area between the second bonding material 1910 and the second pad 1906.

[0130] A first chip component 1901 is disposed on a surface layer 1914 of a printed wiring board 1903. A second chip component 1902 is stacked on top of the first chip component 1901. The first chip component 1901 and the second chip component 1902 are chip components such as a capacitor, a resistor, an inductor, etc.

[0131] The first chip component 1901 has a first electrode portion 1901A, a first non-electrode portion 1901B, and a second electrode portion 1901C. The second chip component 1902 has a third electrode portion 1902A, a second non-electrode portion 1902B, and a fourth electrode portion 1902C. As shown in Fig. 27A, the longitudinal directions of the first chip component 1901 and the second chip component 1902 are the same axial direction (the X-axis direction in the figure).

[0132] A first electrode portion 1901A of the first chip component 1901 is connected to a first pad 1905 provided on the printed wiring board 1903 via a first bonding material 1909. A third electrode portion 1902A of the second chip component 1902 is connected to a third pad 1907 provided on the printed wiring board 1903 via a third bonding material 1911. Furthermore, the first electrode portion 1901A and the third electrode portion 1902A are not bonded to each other via the first bonding material 1909 and the third bonding material 1911.

[0133] A second electrode portion 1901C of the first chip component 1901 is connected to a second pad 1906 provided on the printed wiring board 1903 via a second bonding material 1910. A fourth electrode portion 1902C of the second chip component 1902 is connected to a fourth pad 1908 provided on the printed wiring board 1903 via a fourth bonding material 1912. The second electrode portion 1901C and the fourth electrode portion 1902C are not bonded to each other via the second bonding material 1910 and the fourth bonding material 1912. In this way, the first bonding material 1909, the second bonding material 1910, the third bonding material 1911, and the fourth bonding material 1912 are separated from each other.

[0134] The first bonding material 1909 electrically connects only the first electrode portion 1901A of the first chip component 1901 to the first pad 1905 of the printed wiring board 1903. The second bonding material 1910 electrically connects only the second electrode portion 1901C of the first chip component 1901 to the second pad 1906 of the printed wiring board 1903. The first bonding material 1909 and the second bonding material 1910 are in contact with the second non-electrode portion 1902B of the second chip component 1902.

[0135] The third bonding material 1911 connects only the third electrode portion 1902A of the second chip component 1902 to the third pad 1907 of the printed wiring board 1903. The fourth bonding material 1912 connects only the fourth electrode portion 1902C of the second chip component 1902 to the fourth pad 1908 of the printed wiring board 1903. In other words, there is a gap between the first electrode portion 1901A and the third electrode portion 1902A. Similarly, there is a gap between the second electrode portion 1901C and the fourth electrode portion 1902C. As a result, the first electrode portion 1901A is electrically isolated from the third electrode portion 1902A and the fourth electrode portion 1902C via the gap in the stacking direction of the first chip component 1901 and the second chip component 1902. Similarly, the second electrode portion 1901C is electrically isolated from the third electrode portion 1902A and the fourth electrode portion 1902C via a gap in the stacking direction of the first chip component 1901 and the second chip component 1902.

[0136] This allows a significant reduction in the amount of bonding material to be supplied compared to when first electrode portion 1901A of first chip component 1901, third electrode portion 1902A of second chip component 1902, and third pad 1907 of printed wiring board 1903 are connected using the same bonding material. Therefore, the minimum amount of bonding material required can be supplied during manufacturing to bond printed wiring board 1903, first chip component 1901, and second chip component 1902, making it possible to narrow the spacing between other electronic components. In other words, chip components can be laid out densely on printed wiring board 1903 while minimizing constraints on the bonding material supply process, thereby enabling the miniaturization of printed wiring board 1903.

[0137] Furthermore, no other chip components are disposed between third electrode portion 1902A of second chip component 1902 and third pad 1907 of printed wiring board 1903, and between fourth electrode portion 1902C of second chip component 1902 and fourth pad 1908 of printed wiring board 1903. Therefore, third pad 1907 and fourth pad 1908 can be provided on surface layer 1914 of printed wiring board 1903, with areas approximately the same as those of third electrode portion 1902A and fourth electrode portion 1902C. Furthermore, second chip component 1902 can be stacked on first chip component 1901 without reducing the bonding area of ​​the electrodes of second chip component 1902. In other words, the bonding strength of second chip component 1902 can be ensured without being affected by the size of first chip component 1901, thereby achieving a stacked structure of chip components with high bonding strength.

[0138] 27A, first pad 1905 and third pad 1907 of printed wiring board 1903 are not electrically connected by wiring. However, first pad 1905 and third pad 1907 can be electrically connected if they are connected by wiring, and can be electrically isolated if they are not connected by wiring.

[0139] Similarly, second pad 1906 and fourth pad 1908 on printed wiring board 1903 are not connected. However, if second pad 1906 and fourth pad 1908 are connected by wiring, they can be electrically connected, and if second pad 1906 and fourth pad 1908 are not connected by wiring, they can be electrically isolated. In this way, by connecting the electrode portions of two chip components, one above the other, to multiple pads (electrodes) provided on printed wiring board 1903, it is possible to select whether to electrically connect or isolate them by wiring on printed wiring board 1903. This improves the degree of freedom in the layout of wiring on printed wiring board 1903.

[0140] Consider a case where the second chip component 1902 is larger than the first chip component 1901, for example, a case where the first chip component 1901 is 0402 size and a second chip component 1902 is 0603 size stacked on top of it. Combining a first chip component 1901 of 0402 size, which has a small lower tolerance limit, with a second chip component 1902 of 0603 size, which has an upper tolerance limit, will result in misalignment of the chip component electrodes. This makes it difficult to manufacture a non-defective product. However, even when chip components of different sizes are stacked, as in the 19th embodiment, by providing separate electrodes on the printed wiring board 1903 and bonding them with a bonding material, high yields can be achieved even if the electrode positions do not completely overlap due to tolerances.

[0141] 27B, the first electrode portion 1901A is covered with a first bonding material 1909 and is in contact with a second non-electrode portion 1902B of the second chip component 1902. There is a gap between the first non-electrode portion 1901B and the second non-electrode portion 1902B. The second electrode portion 1901C is covered with a second bonding material 1910 and is in contact with the second non-electrode portion 1902B of the second chip component 1902. As shown in FIG. 27A, in a top view of the printed wiring board 1903, the center of gravity of the second chip component 1902 is included in the area in which the first chip component 1901 is present.

[0142] The third bonding material 1911 may be elongated from a sphere and bond the third electrode portion 1902A to the third pad 1907. Similarly, the fourth bonding material 1912 may be elongated from a sphere and bond the fourth electrode portion 1902C to the fourth pad 1908. As a result, when the solder is melted in a reflow furnace, the surface tension of the solder presses the second non-electrode portion 1902B of the second chip component 1902 against the first electrode portion 1901A and the second electrode portion 1901C of the first chip component 1901, resulting in a connected state. Furthermore, as shown in FIG. 27A , the center of gravity of the second chip component 1902 is included within the area where the first chip component 1901 is present. This allows the second chip component 1902 stacked on the first chip component 1901 to maintain a stable state, resulting in a high manufacturing yield.

[0143] The first bonding material 1909, the second bonding material 1910, the third bonding material 1911, and the fourth bonding material 1912 are solder. In the nineteenth embodiment, the first bonding material 1909, the second bonding material 1910, the third bonding material 1911, and the fourth bonding material 1912 are electrically isolated from one another. By using solder as the bonding material, for example, the first bonding material 1909 and the second bonding material 1910 can be supplied by screen printing. Furthermore, the third bonding material 1911 and the fourth bonding material 1912 can also be manufactured by combining the supply of solder balls or solder preforms. In this way, using solder as the bonding material improves the flexibility of the bonding material supply method.

[0144] In the 19th embodiment, the size of the second chip component 1902 is larger than the size of the first chip component 1901. For example, the first chip component 1901 is a 0402 size chip component, and the second chip component 1902 is a 1608 size chip component. The bonding area between the first electrode portion 1901A and the second electrode portion 1901C of the first chip component 1901 and the first pad 1905 and the second pad 1906 of the printed wiring board 1903 was calculated using the 0402 size of a general-purpose chip multilayer ceramic capacitor published by Murata Manufacturing Co., Ltd. As a result, the bonding area was calculated as 0.1125 mm × 0.2 mm = 0.0225 mm 2 Similarly, the bonding area between the third electrode portion 1902A and the fourth electrode portion 1902C of the second chip component 1902 and the third pad 1907 and the fourth pad 1908 of the printed wiring board 1903 was calculated using the size of a general-purpose chip multilayer ceramic capacitor 1608 published by Murata Manufacturing Co., Ltd. As a result, the bonding area was calculated to be 0.35 mm × 0.8 mm = 0.28 mm 2 The area occupied by the printed wiring board 1903 having the laminated structure of the first chip component 1901 and the second chip component 1902 in the 19th embodiment is 1.6 mm×0.8 mm=1.28 mm 2 is.

[0145] In this way, third electrode portion 1902A and fourth electrode portion 1902C of second chip component 1902 are directly connected to third pad 1907 and fourth pad 1908 provided on printed wiring board 1903 by a bonding material. This ensures a sufficient bonding area with printed wiring board 1903 regardless of the size of first chip component 1901 located below second chip component 1902. Therefore, the bonding strength of second chip component 1902 can be ensured without being affected by the size of first chip component 1901 as in the prior art, and a stacked structure of chip components with high bonding strength can be realized.

[0146] [Twentieth Embodiment] FIG. 28A is a top view of a processing module 20001 according to the twentieth embodiment. FIGS. 28B and 28C are cross-sectional views of the processing module 20001 according to the twentieth embodiment taken along line CC′. FIG. 28B is a view of the cross section taken along line CC′ in FIG. 28A as viewed in the −X direction. FIG. 28C is a view of the same cross section as viewed in the +X direction. The printed wiring board 2003 includes an insulating substrate 2015 and at least one conductor layer. The at least one conductor layer includes a surface layer 2014 located on a main surface 2013 of the insulating substrate 2015. The surface layer 2014 of the printed wiring board 2003 is provided with a first pad 2004, a second pad 2006, a third pad 2007, and a fourth pad 2008 as electrodes.

[0147] A first chip component 2001 is disposed on a surface layer 2014 of a printed wiring board 2003. A second chip component 2002 is stacked on top of the first chip component 2001. The first chip component 2001 and the second chip component 2002 are chip components such as a capacitor, a resistor, an inductor, etc.

[0148] 28B, a first electrode portion 2001A of a first chip component 2001 is connected to a first pad 2004 provided on a printed wiring board 2003 via a first bonding material 2009. A third electrode portion 2002A of a second chip component 2002 is connected to a third pad 2007 provided on a printed wiring board 2003 via a third bonding material 2011. The first electrode portion 2001A and the third electrode portion 2002A are not bonded to each other via the first bonding material 2009 and the third bonding material 2011.

[0149] 28C, the second electrode portion 2001C of the first chip component 2001 is connected to a second pad 2006 provided on the printed wiring board 2003 via a second bonding material 2010. The fourth electrode portion 2002C of the second chip component 2002 is connected to a fourth pad 2008 provided on the printed wiring board 2003 via a fourth bonding material 2012. The second electrode portion 2001C and the fourth electrode portion 2002C are not bonded to each other via the second bonding material 2010 and the fourth bonding material 2012.

[0150] The first bonding material 2009 connects only the first electrode portion 2001A of the first chip component 2001 to the first pad 2004 of the printed wiring board 2003. The second bonding material 2010 connects only the second electrode portion 2001C of the first chip component 2001 to the second pad 2006 of the printed wiring board 2003.

[0151] The third bonding material 2011 connects only the third electrode portion 2002A of the second chip component 2002 to the third pad 2007 of the printed wiring board 2003. The fourth bonding material 2012 connects only the fourth electrode portion 2002C of the second chip component 2002 to the fourth pad 2008 of the printed wiring board 2003. In other words, there is a gap between the first electrode portion 2001A and the third electrode portion 2002A. Similarly, there is a gap between the second electrode portion 2001C and the fourth electrode portion 2002C.

[0152] The following describes the differences between the 20th embodiment and the 19th embodiment. In the 20th embodiment, the second chip component 2002 is stacked on the first chip component 2001 with the longitudinal direction of the first chip component 2001 and the longitudinal direction of the second chip component 2002 intersecting at right angles. The first chip component 2001 has a first electrode portion 2001A, a first non-electrode portion 2001B, and a second electrode portion 2001C. The second chip component 2002 has a third electrode portion 2002A, a second non-electrode portion 2002B, and a fourth electrode portion 2002C.

[0153] 28A shows a state in which the longitudinal directions of the first chip component 2001 and the second chip component 2002 are perpendicular to each other, but this is not necessarily required. As long as the first chip component 2001 is in contact with the second non-electrode portion 2002B of the second chip component 2002 and a gap is provided between the electrode portion of the first chip component 2001 and the electrode portion of the second chip component 2002, the longitudinal axes of the first chip component and the second chip component may be arranged so as to intersect at an angle other than 90 degrees.

[0154] In the twentieth embodiment, the size of the second chip component 2002 is larger than the size of the first chip component 2001. For example, the first chip component 2001 is a 0402 size chip component, and the second chip component 2002 is a 1005 size chip component. According to the outline tolerance of general-purpose chip multilayer ceramic capacitors published by Murata Manufacturing Co., Ltd., the outline of the 0402 size is a maximum of 0.45 mm × 0.25 mm, and the non-electrode portion of the 1005 size is a minimum of 0.45 mm × 0.3 mm. Therefore, even when the outline tolerance of the chip components is taken into consideration, by orthogonally orthogonally orthogonalizing the longitudinal directions of the first and second chip components, the 0402 size first chip component 2001 can be arranged within the range of the non-electrode portion of the 1005 size second chip component 2002. In other words, it is possible to isolate the first electrode portion 200A of the first chip component 2001 from the third electrode portion 2002A of the second chip component 2002, the second electrode portion 2001C of the first chip component 2001 from the fourth electrode portion 2002C of the second chip component 2002, and the first pad 2004, the second pad 2006, the third pad 2007, and the fourth pad 2008 of the printed wiring board 2003 from the third electrode portion 2002A and the fourth electrode portion 2002C of the second chip component 2002, respectively, thereby making it possible to bond them with a reduced risk of short circuiting.

[0155] In the twentieth embodiment, the area occupied by the printed wiring board 2003 due to the laminated structure of the first chip component 2001 and the second chip component 2002 is 1.0 mm×0.5 mm=0.50 mm 2 As described above, unlike the 19th embodiment, it is possible to stack 1005 size components as the second chip components 2002 instead of 1608 size components. Therefore, the 20th embodiment allows chip components to be arranged at a higher density than the 19th embodiment.

[0156] [Modified embodiment] The present disclosure is not limited to the above-described embodiments and various modifications are possible. For example, an example in which part of the configuration of one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also an embodiment of the present disclosure.

[0157] The structures described as printed circuit boards and printed wiring boards are manufactured using various printing technologies (printing techniques), such as screen printing, flexography, gravure printing, inkjet printing, and offset printing. However, the use of printing technologies (printing techniques) is not essential; photolithography techniques and film formation and etching techniques, such as semiconductor manufacturing techniques, can also be used. In addition to printed circuit boards and printed wiring boards, circuit boards and wiring boards can also be used that do not use printing technologies. For example, a silicon interposer is an example of a wiring board manufactured using semiconductor manufacturing techniques.

[0158] An electronic device having a circuit board disposed inside its housing is not limited to a camera. For example, the electronic device may be a mobile communication device. For example, the electronic device may be an information device such as a smartphone or a personal computer, or a communication device such as a modem or a router. Alternatively, the electronic device may be office equipment such as a printer or a copier, medical equipment such as a radiographic device, a magnetic imaging device, an ultrasound imaging device, or an endoscope, industrial equipment such as a robot or a semiconductor manufacturing device, or transportation equipment such as a vehicle, an airplane, or a ship. By using the electronic module of the present disclosure in the limited space inside the housing of the electronic device, it is possible to reduce the size and increase the density of the electronic device. Furthermore, by using the circuit board of the present disclosure in an electronic device having multiple electronic modules, it is possible to reduce the size and increase the density of the electronic device.

[0159] The present disclosure includes the following configurations. (Configuration 1) A wiring board; a first chip component having a first electrode portion, a first non-electrode portion, and a second electrode portion, and provided on the wiring board; a second chip component having a third electrode portion, a second non-electrode portion, and a fourth electrode portion, and stacked on the first chip component; the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion; The module, wherein the second electrode portion is located between the second non-electrode portion and the wiring board. (Configuration 2) A wiring board; a first chip component having a first electrode portion, a first non-electrode portion, and a second electrode portion, and provided on the wiring board; a second chip component having a third electrode portion, a second non-electrode portion, and a fourth electrode portion, and stacked on the first chip component; the third electrode portion is electrically isolated from the first electrode portion and the second electrode portion; A module, characterized in that the first non-electrode portion is located between the third electrode portion and the wiring board. (Configuration 3) A wiring board; a first chip component having a first electrode portion, a first non-electrode portion, and a second electrode portion, and provided on the wiring board; a second chip component having a third electrode portion, a second non-electrode portion, and a fourth electrode portion, and stacked on the first chip component; the first electrode portion is bonded to the wiring board via a first bonding material, the second electrode portion is bonded to the wiring board via a second bonding material, the third electrode portion is joined to the wiring board via a third joining material, the fourth electrode portion is joined to the wiring board via a fourth bonding material, A module, characterized in that the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material are separated from each other. (Configuration 4) The module described in configuration 1, wherein the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion via a gap in the stacking direction of the first chip component and the second chip component. (Configuration 5) The module described in configuration 2, wherein the third electrode portion is electrically isolated from the first electrode portion and the second electrode portion via a gap in the stacking direction of the first chip component and the second chip component. (Configuration 6) 6. The module according to any one of configurations 1 to 5, wherein the second chip component is larger in size than the first chip component. (Configuration 7) 6. The module of claim 4 or 5, wherein the gap distance is less than 200 μm. (Configuration 8) a third chip component having a fifth electrode portion, a third non-electrode portion, and a sixth electrode portion, the third chip component being provided on the wiring board; 6. The module according to configuration 4 or 5, wherein the third chip component is disposed between the wiring board and the second chip component. (Configuration 9) The module described in configuration 8, characterized in that the sixth electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion via the gap and is located between the second non-electrode portion and the wiring board. (Configuration 10) the fourth electrode portion is electrically isolated from the fifth electrode portion and the sixth electrode portion via the gap; 9. The module according to configuration 8, wherein the third non-electrode portion is located between the fourth electrode portion and the wiring board. (Configuration 11) 9. The module according to configuration 8, wherein the size of the second chip component is larger than the sizes of the first chip component and the third chip component. (Configuration 12) 6. The module according to any one of configurations 1 to 5, wherein the first electrode portion is electrically connected to the third electrode portion or the fourth electrode portion. (Configuration 13) 9. The module according to configuration 8, wherein the fifth electrode portion is electrically connected to the third electrode portion or the fourth electrode portion. (Configuration 14) a fourth chip component having a seventh electrode portion, a fourth non-electrode portion, and an eighth electrode portion, and provided between the first chip component and the third chip component on the wiring board; the second chip component is larger in size than the first chip component, the third chip component, and the fourth chip component; the seventh electrode portion and the eighth electrode portion are electrically isolated from the third electrode portion and the fourth electrode portion via the gap; The module described in configuration 8, wherein the seventh electrode portion and the eighth electrode portion are located between the second non-electrode portion and the wiring board. (Configuration 15) The module described in configuration 14, characterized in that each of the second electrode portion, the sixth electrode portion, the seventh electrode portion, and the eighth electrode portion partially protrudes from the second non-electrode portion when viewed from above. (Configuration 16) The module described in configuration 14, characterized in that the third electrode portion and the fourth electrode portion partially protrude from the first non-electrode portion, the third non-electrode portion, and the fourth non-electrode portion when viewed from above. (Configuration 17) The module described in configuration 14, characterized in that the length of each of the long sides of the first chip component, the third chip component, and the fourth chip component is less than half the length of the long side of the second chip component. (Configuration 18) The module described in configuration 14, characterized in that the first chip component, the third chip component, and the fourth chip component are arranged in a straight line along the longitudinal direction of the second chip component. (Configuration 19) 15. The module according to configuration 14, wherein the first chip component, the third chip component, and the fourth chip component are arranged in greater numbers in the longitudinal direction of the second chip component than in the lateral direction. (Configuration 20) The module described in configuration 14, further comprising a plurality of power supply vias and a plurality of GND vias arranged in positions that overlap any of the first electrode portion, the second electrode portion, the fifth electrode portion, the sixth electrode portion, the seventh electrode portion, and the eighth electrode portion when viewed from above. (Configuration 21) a semiconductor device including a power supply terminal and a GND terminal and disposed on the wiring board; the plurality of power supply vias connect the power supply terminal to each of the first electrode portion, the fifth electrode portion, and the seventh electrode portion; the plurality of GND vias connect the GND terminal to each of the second electrode portion, the sixth electrode portion, and the eighth electrode portion; 15. The module of claim 14, wherein the plurality of power supply vias and the plurality of GND vias are arranged parallel to each other in a cross-sectional view. (Configuration 22) the first chip component, the third chip component, and the fourth chip component are first capacitors of the same size; 22. The module of claim 21, wherein the second chip component is a second capacitor that is larger than the first capacitor. (Configuration 23) The module described in configuration 21, characterized in that the multiple power supply vias and the multiple GND vias are connected to the first chip component, the third chip component, and the fourth chip component, respectively, so that the current directions in the first chip component, the third chip component, and the fourth chip component are opposite between adjacent components when viewed from above. (Configuration 24) 22. The module according to configuration 21, wherein the current directions between adjacent vias among the plurality of power supply vias and the plurality of GND vias are opposite to each other. (Configuration 25) The module of configuration 21, characterized in that at least one of the first chip component, the second chip component, the third chip component, and the fourth chip component is a chip resistor. (Configuration 26) The module described in configuration 22, characterized in that the second capacitor and chip resistor are connected in series to the power supply terminal and the GND terminal, and the first capacitor is connected to the power supply terminal and the GND terminal. (Configuration 27) the first capacitor and the chip resistor are connected in series to the power supply terminal and the GND terminal; 23. The module of claim 22, wherein the second capacitor is connected to the power supply terminal and the GND terminal. (Configuration 28) The wiring board is a first wiring board, and the semiconductor device is a first semiconductor device, a second wiring board; a second semiconductor device provided on the second wiring board; the first chip component, the second chip component, the third chip component, and the fourth chip component are disposed between the first wiring board and the second wiring board; The module described in configuration 21, characterized in that the first semiconductor device is electrically connected to the semiconductor device via the first chip component, the second chip component, the third chip component, and the fourth chip component. (Configuration 29) When viewed from above, the center of gravity of the second chip component is located within an area where the first chip component is present. 4. The module according to configuration 3. (Configuration 30) the wiring board has a first pad bonded to the first bonding material, a second pad bonded to the second bonding material, a third pad bonded to the third bonding material, and a fourth pad bonded to the fourth bonding material; The module described in configuration 3, characterized in that the bonding area between the third bonding material and the third pad and the bonding area between the fourth bonding material and the fourth pad are both larger than the bonding area between the first bonding material and the first pad and the bonding area between the second bonding material and the second pad. (Configuration 31) The module described in any one of configurations 3, 29, and 30, characterized in that the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material are solder, and the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material are electrically isolated. (Configuration 32) A module described in any one of configurations 3, 29, and 30, characterized in that the first bonding material and the second bonding material are in contact with the second non-electrode portion, and / or the first electrode portion is in contact with the second non-electrode portion. (Configuration 33) A module described in any one of configurations 3, 29, and 30, characterized in that the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion via a gap in the stacking direction of the first chip component and the second chip component. (Configuration 34) The housing and The module according to any one of configurations 1 to 5, which is disposed inside the housing; and An apparatus comprising: (Configuration 35) A first module including the module according to any one of configurations 1 to 5; A second module; wherein the first module and the second module are electrically connected by a connecting member.

[0160] The disclosure of this specification includes not only what is explicitly described in this specification, but also all matters that can be understood from this specification and the drawings attached hereto. The disclosure of this specification also includes the complement of the individual concepts described in this specification. In other words, if this specification states, for example, that "A is B," it can be said that this specification discloses that "A is not B," even if it omits the statement that "A is not B." This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration. [Explanation of symbols]

[0161] 10, 11, 50, 210, 311, 361, 411, 461, 511, 561, 610, 710, 711, 810, 811, 910, 911, 1010, 1011, 1110, 1111, 1210, 1310, 1410, 1510, 1610, 1710, 1810, 1820, 1903, 2003...Printed wiring board 52, 102, 202, 302, 402, 502, 602, 702, 802, 902, 1002, 1102, 1202, 1302, 1402, 1502, 1602, 1702, 1802, 1901, 2001... First chip component 53, 103, 203, 303, 403, 503, 603, 703, 803, 903, 1003, 1103, 1203, 1303, 1403, 1503, 1603, 1703, 1803, 1902, 2002... Second chip component 107, 207, 307...Gap

Claims

1. A wiring board; a first chip component having a first electrode portion, a first non-electrode portion, and a second electrode portion, the first chip component being provided on the wiring board; a second chip component having a third electrode portion, a second non-electrode portion, and a fourth electrode portion, and stacked on the first chip component; the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion; The module, wherein the second electrode portion is located between the second non-electrode portion and the wiring board.

2. A wiring board; a first chip component having a first electrode portion, a first non-electrode portion, and a second electrode portion, the first chip component being provided on the wiring board; a second chip component having a third electrode portion, a second non-electrode portion, and a fourth electrode portion, and stacked on the first chip component; the third electrode portion is electrically isolated from the first electrode portion and the second electrode portion; The module, wherein the first non-electrode portion is located between the third electrode portion and the wiring board.

3. A wiring board; a first chip component having a first electrode portion, a first non-electrode portion, and a second electrode portion, the first chip component being provided on the wiring board; a second chip component having a third electrode portion, a second non-electrode portion, and a fourth electrode portion, and stacked on the first chip component; the first electrode portion is bonded to the wiring board via a first bonding material, the second electrode portion is bonded to the wiring board via a second bonding material, the third electrode portion is bonded to the wiring board via a third bonding material, the fourth electrode portion is bonded to the wiring board via a fourth bonding material, The module, wherein the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material are separated from each other.

4. 2. The module according to claim 1, wherein the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion via a gap in the stacking direction of the first chip component and the second chip component.

5. 3. The module according to claim 2, wherein the third electrode portion is electrically isolated from the first electrode portion and the second electrode portion via a gap in the stacking direction of the first chip component and the second chip component.

6. 6. The module according to claim 1, wherein the second chip component is larger in size than the first chip component.

7. 6. The module according to claim 4 or 5, wherein the gap distance is less than 200 μm.

8. a third chip component having a fifth electrode portion, a third non-electrode portion, and a sixth electrode portion, the third chip component being provided on the wiring board; 6. The module according to claim 4, wherein the third chip component is disposed between the wiring board and the second chip component.

9. 9. The module according to claim 8, wherein the sixth electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion via the gap and is located between the second non-electrode portion and the wiring board.

10. the fourth electrode portion is electrically isolated from the fifth electrode portion and the sixth electrode portion via the gap; The module according to claim 8 , wherein the third non-electrode portion is located between the fourth electrode portion and the wiring board.

11. 9. The module according to claim 8, wherein the second chip component is larger in size than the first chip component and the third chip component.

12. 6. The module according to claim 1, wherein the first electrode portion is electrically connected to the third electrode portion or the fourth electrode portion.

13. The module according to claim 8 , wherein the fifth electrode portion is electrically connected to the third electrode portion or the fourth electrode portion.

14. a fourth chip component having a seventh electrode portion, a fourth non-electrode portion, and an eighth electrode portion, and provided between the first chip component and the third chip component on the wiring board; the second chip component is larger in size than the first chip component, the third chip component, and the fourth chip component; the seventh electrode portion and the eighth electrode portion are electrically isolated from the third electrode portion and the fourth electrode portion via the gap; The module according to claim 8 , wherein the seventh electrode portion and the eighth electrode portion are located between the second non-electrode portion and the wiring board.

15. 15. The module according to claim 14, wherein each of the second electrode portion, the sixth electrode portion, the seventh electrode portion, and the eighth electrode portion partially protrudes from the second non-electrode portion in a top view.

16. 15. The module according to claim 14, wherein the third electrode portion and the fourth electrode portion partially protrude from the first non-electrode portion, the third non-electrode portion, and the fourth non-electrode portion in a top view.

17. 15. The module according to claim 14, wherein the length of each of the long sides of the first chip component, the third chip component, and the fourth chip component is equal to or less than half the length of the long side of the second chip component.

18. 15. The module according to claim 14, wherein the first chip component, the third chip component, and the fourth chip component are arranged in a straight line along the longitudinal direction of the second chip component.

19. 15. The module according to claim 14, wherein the first chip component, the third chip component, and the fourth chip component are arranged in greater numbers in a longitudinal direction of the second chip component than in a lateral direction thereof.

20. 15. The module of claim 14, further comprising a plurality of power supply vias and a plurality of GND vias arranged in positions that overlap any of the first electrode portion, the second electrode portion, the fifth electrode portion, the sixth electrode portion, the seventh electrode portion, and the eighth electrode portion when viewed from above.

21. a semiconductor device including a power supply terminal and a GND terminal and provided on the wiring board; the plurality of power supply vias connect the power supply terminal to each of the first electrode portion, the fifth electrode portion, and the seventh electrode portion; the plurality of GND vias connect the GND terminal to each of the second electrode portion, the sixth electrode portion, and the eighth electrode portion; The module according to claim 14 , wherein the plurality of power supply vias and the plurality of GND vias are arranged parallel to each other in a cross-sectional view.

22. the first chip component, the third chip component, and the fourth chip component are first capacitors of the same size; 22. The module of claim 21, wherein the second chip component is a second capacitor that is larger than the first capacitor.

23. 22. The module according to claim 21, wherein the plurality of power supply vias and the plurality of GND vias are connected to the first chip component, the third chip component, and the fourth chip component, respectively, such that current directions in the first chip component, the third chip component, and the fourth chip component are opposite to each other between adjacent components in a top view.

24. 22. The module according to claim 21, wherein the current flows in opposite directions between adjacent vias among the plurality of power supply vias and the plurality of GND vias.

25. 22. The module of claim 21, wherein at least one of the first chip component, the second chip component, the third chip component, and the fourth chip component is a chip resistor.

26. 23. The module of claim 22, wherein the second capacitor and a chip resistor are connected in series to the power supply terminal and the GND terminal, and the first capacitor is connected to the power supply terminal and the GND terminal.

27. the first capacitor and the chip resistor are connected in series to the power supply terminal and the GND terminal; 23. The module according to claim 22, wherein the second capacitor is connected to the power supply terminal and the GND terminal.

28. The wiring board is a first wiring board, and the semiconductor device is a first semiconductor device, a second wiring board; a second semiconductor device provided on the second wiring board; the first chip component, the second chip component, the third chip component, and the fourth chip component are disposed between the first wiring board and the second wiring board; 22. The module according to claim 21, wherein the first semiconductor device is electrically connected to the semiconductor device via the first chip component, the second chip component, the third chip component, and the fourth chip component.

29. When viewed from above, the center of gravity of the second chip component is included within an area where the first chip component is present.

4. The module of claim 3.

30. the wiring board has a first pad bonded to the first bonding material, a second pad bonded to the second bonding material, a third pad bonded to the third bonding material, and a fourth pad bonded to the fourth bonding material; The module described in claim 3, characterized in that the bonding area between the third bonding material and the third pad and the bonding area between the fourth bonding material and the fourth pad are both larger than the bonding area between the first bonding material and the first pad and the bonding area between the second bonding material and the second pad.

31. 31. The module of claim 3, 29, or 30, wherein the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material are solder, and the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material are electrically isolated.

32. The module described in any one of claims 3, 29, and 30, characterized in that the first bonding material and the second bonding material are in contact with the second non-electrode portion, and / or the first electrode portion is in contact with the second non-electrode portion.

33. The module described in any one of claims 3, 29, and 30, characterized in that the second electrode portion is electrically isolated from the third electrode portion and the fourth electrode portion via a gap in the stacking direction of the first chip component and the second chip component.

34. The housing and A module according to any one of claims 1 to 5, disposed inside the housing; An apparatus comprising:

35. a first module comprising a module according to any one of claims 1 to 5; a second module; and wherein the first module and the second module are electrically connected by a connecting member.

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