Converter arrangement

Abstract

A mechanism for improved ease of achieving zero voltage switching during voltage conversion, using a switched-mode power supply. A field-effect transistor is connected to a same switch node as a pulse-width modulated switch, and biased with a biasing arrangement.

Description

[0001] Converter arrangement

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to the field of DC-to-DC converters, and in particular to converters that make use of a single switch to control an output power.

[0004] BACKGROUND OF THE INVENTION

[0005] DC-to-DC converters, such as buck or boost converters, are becoming increasingly popular for use in driving loads with variable power demands, such as dimmable LED loads. Moreover, recent development of transistors, such as the production of GaN or SiC transistors, has made small and highly efficient buck or boost converters possible.

[0006] One known category of DC-to-DC converters makes use of a single switch to control the current flow through the DC-to-DC converter, particularly to control the output power of the DC-to-DC converter.

[0007] To reduce a risk of component damage, reduce radiated emission and / or to reduce switching losses, there is an ongoing desire to perform zero-voltage switching of the (single) switch.

[0008] SUMMARY OF THE INVENTION

[0009] The invention is defined by the claims.

[0010] According to examples in accordance with an aspect of the invention, there is provided a converter arrangement.

[0011] The converter arrangement comprises a first switch connected between a first node and a switch node; a field-effect transistor connected between the switch node and a second node; a biasing arrangement configured to apply a bias voltage to the field-effect transistor to configure the field-effect transistor to operate in a sub-threshold mode; an inductor connected between the switch node and a third node; and a control arrangement configured to define a magnitude of the output power of the converter arrangement using pulse width modulation of only the first switch. The linearity of a charge stored by the first switch, with respect to a voltage across the first switch, is different to a linearity of a charge stored by the field-effect transistor, with respect to a voltage across the field-effect transistor. The present disclosure provides a converter arrangement with improved zero voltage switching of the first switch during operation of the first switch.

[0012] When the first switch is deactivated, the voltage at the switch node will move away from the voltage at the first node (e.g., towards a voltage at second / third node), before resonantly swinging back towards the voltage at the first node. It has been recognized that the proximity of the swinging voltage to the voltage at the first node is at least partially dependent upon the charge-voltage relationship of the components connected between the first node and the second node. Historically, these components have included a diode connected between the switch node and the second node. In particular, if the linearity of the charge-voltage relationship of the first switch is different to the linearity of the chargevoltage relationship of the field-effect transistor, then a critical gain (being a gain at which zero voltage switching is achievable) is changed.

[0013] The use of a biased field-effect transistor effectively provides a singlecomponent arrangement, that replaces a diode of a known converter arrangement circuit, with a rectifying arrangement having a greater storage of charge at relatively low voltages (e.g., than a single diode). This approach facilitates increased magnitude of a voltage during a resonant oscillation of the voltage at the switch node when the first switch is deactivated (e.g., during the pulse width modulation). This facilitates reduced risk of a swinging voltage at the switch node failing to reach the voltage at the first node, thereby reducing a risk that zero-voltage switching cannot be achieved.

[0014] The first switch and the field-effect transistor are different types of transistor. In this way, the first switch and the field-effect transistor may have capacitances of different linearities and / or store different amounts of charge (for a same voltage thereacross). It has been recognized that both of these characteristics contribute to a change in the critical gain of the converter arrangement. The critical gain, also known as the minimum operational gain, is the smallest gain of the converter arrangement for which zero voltage switching can be achieved. If the first switch and field-effect transistor have equivalent properties, then the critical gain would be 0.5.

[0015] In some examples, the charge stored by the first switch is less than the charge stored by the field-effect transistor if a non-zero voltage, within a working voltage range of the converter arrangement, is applied across the first and second node.

[0016] In the context of the present disclosure, a working voltage range is a rated voltage or desired voltage range in which the converter arrangement operates. This may depend, for instance, upon the use-case scenario for the converter arrangement. It has been advantageously recognized that the critical gain, at which zero voltage switching of the first switch can be achieved is reduced when the field-effect transistor stores more charge than the first switch for a same applied voltage.

[0017] In some examples, the capacitance of the first switch is less linear than the capacitance of the field-effect transistor. It has been advantageously recognized that the critical gain is reduced when the capacitance of the field-effect transistor is less linear (i.e., more non-linear) than the capacitance of the first switch. The charge of a linear capacitor is proportional to the voltage. The charge of a non-linear capacitor is non-linearly related to the voltage. Here, a non-linearity of a capacitance of a component may be defined as the (maximum) change in capacitance for a change in voltage across the component.

[0018] The biasing arrangement may be configured to control the value of the bias voltage responsive to the output power of the converter arrangement. This provides a technique for controlling the effective reverse recovery time of the field-effect transistor. In particular, a reverse recovery time of some field-effect transistors is controlled to be at least partially responsive to a voltage provided at the gate thereof, i.e., the bias voltage. This allows, for instance, for the effective reverse recovery time to be modified after manufacture of the converter arrangement, e.g., for use in a specific use-case scenario and / or circuitry arrangement.

[0019] This thereby provides a mechanism for tuning or selecting the reverse recovery time of the field-effect transistor. It has also been recognized that the reverse recovery time of the field-effect transistor will control the maximum reverse current through the field-effect transistor as the magnetic field produced by the inductor collapses. This maximum reverse current will, in turn, contribute to defining the (swinging) voltage that is induced across the field-effect transistor when the field-effect transistor begins to block current again. In this way, the reverse current effectively acts to offset a charge across the field-effect transistor.

[0020] In some examples, the converter arrangement is configured to increase the value of the bias voltage responsive to the output power of the converter arrangement increasing. More particular, the converter arrangement may be configured to increase the value of the bias voltage responsive to the output voltage of the converter arrangement increasing.

[0021] This approach provides a dynamic feedback for adjusting or modifying the effective reverse recovery time of the field-effect transistor. In particular, it has been recognized that the output power of the converter arrangement will affect or influence the necessary gain of the converter arrangement, i.e., the required value for the minimum operational gain or critical gain of the converter arrangement. Providing the capability to tune the effective reverse recovery time of the field-effect transistor allows for direct and controllable modification to the critical gain of the converter arrangement.

[0022] The field-effect transistor may be a MOSFET. Some MOSFETs advantageously have relatively large and non-linear capacitances.

[0023] The field-effect transistor is preferably a silicon superjunction, Si-SJ, MOSFET. The extremely large non-linearity of the capacitance, as well as the extremely large capacitance, of an Si-SJ MOSFET is exploited to advantage in this embodiment to significantly reduce the critical gain of the converter arrangement. This is particularly advantageous if the first switch is embodied as a (GaN) HEMT or a SiC MOSFET, or other similar device having a more linear and / or smaller capacitance.

[0024] The converter arrangement may further comprise: a first diode arrangement connected in parallel to the field-effect transistor; and a second diode arrangement connected in parallel to the first diode arrangement and the field-effect transistor, wherein a reverse recovery time of the first diode arrangement is different to a reverse recovery time of the second diode arrangement.

[0025] The first diode arrangement, second diode arrangement and field effect transistor may together form a rectifying arrangement for the converter arrangement. The use of the first and second diode arrangements provides a mechanism for further tuning or selecting the reverse recovery time of the rectifying arrangement. It has also been recognized that the reverse recovery time of the rectifying arrangement will control the maximum reverse current through the rectifying arrangement as the magnetic field produced by the inductor collapses. This maximum reverse current will, in turn, define the voltage that is induced across the rectifying arrangement when the rectifying arrangement begins to block current again.

[0026] In this way, use of two diode arrangements connected in parallel facilitates a selection of an effective reverse recovery time that lies between the reverse recovery times of each individual diode arrangement. This facilitates increased flexibility in selecting or designing an appropriate reverse recovery time that achieves effective and energy-efficient zero voltage switching of the first switch.

[0027] The converter arrangement may further comprise a variable resistance connected in series with the first diode arrangement and a resistor control arrangement configured to control the resistance of the variable resistor responsive to the output power of the converter arrangement.

[0028] In some examples, I reverse recovery time of the first diode arrangement may be less than the reverse recovery time of the second diode arrangement; and the resistor control arrangement may be configured to, responsive to an increase in the output power of the converter arrangement, control the resistance of the variable resistance to decrease the ratio of the resistance of the first diode arrangement and the resistance of the second diode arrangement.

[0029] The resistance of the first diode arrangement may be less than the resistance of the second diode arrangement; and the reverse recovery time of the first diode arrangement may be less than the reverse recovery time of the second diode arrangement.

[0030] There is also proposed a converter arrangement comprising: a first switch connected between a first node and a switch node; a rectifying arrangement connected between the switch node and a second node, wherein either the first node or the second node is connected to a ground or return line; an inductor connected between the switch node and a third node; a control arrangement configured to define a magnitude of the output power of the converter arrangement using pulse width modulation of only the first switch; wherein the rectifying arrangement comprises at least a first diode arrangement and a second diode arrangement connected in parallel, wherein a reverse recovery time of the first diode arrangement is different to a reverse recovery time of the second diode arrangement.

[0031] This provides a mechanism for tuning or selecting the reverse recovery time of the rectifying arrangement. It has also been recognized that the reverse recovery time of the rectifying arrangement will control the maximum reverse current through the rectifying arrangement as the magnetic field produced by the inductor collapses. This maximum reverse current will, in turn, define the voltage that is induced across the rectifying arrangement when the rectifying arrangement begins to block current again.

[0032] In this way, use of two diode arrangements connected in parallel facilitates a selection of an effective reverse recovery time that lies between the reverse recovery times of each individual diode arrangement. This facilitates increased flexibility in selecting or designing an appropriate reverse recovery time that achieves effective and energy-efficient zero voltage switching of the first switch.

[0033] Also, the maximum reverse recovery current this rectifying arrangement experiences is less susceptible to its maximum forward current when compared to a single diode rectifier. The first diode arrangement and / or the second diode arrangement may comprise a diode and resistor connected in series.

[0034] In some examples, the resistor is a variable resistor. This technique provides a mechanism by which the effective reverse recovery time of the rectifying arrangement can be tuned or controlled. This allows, for instance, for the effective reverse recovery time to be modified after manufacture of the converter arrangement, e.g., for use in a specific use-case scenario and / or circuitry arrangement.

[0035] The resistor control arrangement may be configured to control the resistance of the variable resistor responsive to the output power of the converter arrangement. This provides a dynamic feedback for adjusting or modifying the effective reverse recovery time of the rectifying arrangement. In particular, it has been recognized that the output power of the converter arrangement will affect or influence the necessary gain of the converter arrangement, i.e., the required value for the minimum operational gain or critical gain of the converter arrangement. Providing the capability to tune the effective reverse recovery time of the rectifying arrangement allows for direct and controllable modification to the critical gain of the converter arrangement.

[0036] In some examples, the reverse recovery time of the first diode arrangement is less than the reverse recovery time of the second diode arrangement; and the resistor control arrangement is configured to, responsive to an increase in the output power (particularly the output voltage) of the converter arrangement, control the resistance of the variable resistance to decrease the ratio of the resistance of the first diode arrangement and the resistance of the second diode arrangement.

[0037] This approach provides a technique for increasing the effective reverse recovery time of the rectifying arrangement as the required value for the minimum operational gain or critical gain of the converter arrangement increases (i.e., as the output volage increases). This allows the critical gain of the converter arrangement to track or follow the required value.

[0038] In some examples, the variable resistor comprises a transistor. This provides a reliable and easily controllable variable resistor.

[0039] In some examples, the resistance of the first diode arrangement is less than the resistance of the second diode arrangement; and the reverse recovery time of the first diode arrangement is greater than the reverse recovery time of the second diode arrangement.

[0040] In some examples, the rectifying arrangement comprises: a field-effect transistor; and a biasing arrangement configured to apply a bias voltage to the gate of the field-effect transistor to configure the field-effect transistor to operate in a sub-threshold mode. This effectively provides a field-effect transistor that functions as a diode (e.g., relying upon the body-diode effect of the field-effect transistor). The use of a field-effect transistor provides an extremely large and non-linear capacitance, for improved reduction of the minimum operational gain (critical gain) to achieve zero-voltage switching.

[0041] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment s) described hereinafter.

[0042] BRIEF DESCRIPTION OF THE DRAWINGS

[0043] For a better understanding of the invention, and to show more clearly how it may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0044] Figure 1 illustrates an existing buck converter arrangement;

[0045] Figure 2 illustrates another existing buck converter arrangement;

[0046] Figure 3 illustrates an existing boost converter arrangement;

[0047] Figure 4 illustrates a Vi-state plane of a converter arrangement;

[0048] Figure 5 illustrates a proposed converter arrangement;

[0049] Figure 6 illustrates another proposed converter arrangement;

[0050] Figure 7 illustrates waveforms in a converter arrangement;

[0051] Figure 8 illustrates waveforms in another converter arrangement;

[0052] Figure 9 illustrates waveforms in a proposed converter arrangement; and Figure 10 illustrates yet another proposed converter arrangement.

[0053] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] The invention will be described with reference to the Figures.

[0055] It should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the apparatus, systems and methods, are intended for purposes of illustration only and are not intended to limit the scope of the invention. These and other features, aspects, and advantages of the apparatus, systems and methods of the present invention will become better understood from the following description, appended claims, and accompanying drawings. It should be understood that the Figures are merely schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the Figures to indicate the same or similar parts. The invention provides a mechanism for improved ease of achieving zero voltage switching during voltage conversion, using a switched-mode power supply. A fieldeffect transistor is connected to a same switch node as a pulse-width modulated switch, and biased with a biasing arrangement.

[0056] Proposed embodiments are based on two realizations relating to the critical gain of a converter arrangement. A critical gain is the minimum operational gain of the converter arrangement for which zero-voltage switching can be achieved. A first realization is that the critical gain is reduced if a rectifying arrangement or component connected to a switch node has a different capacitance than the pulse-modulated switch (for a same voltage there across) and at least one of the first switch and rectifying arrangement / component has a different charge-voltage relationship. A second realization is that the critical gain is affected or influenced by the reverse recovery time of the rectifying arrangement.

[0057] Figures 1, 2 and 3 illustrate different examples of converter arrangements for improved contextual understanding. However, embodiments are not limited to the illustrated examples, and the skilled person would be readily capable of adapting the herein proposed techniques for use with other converter arrangements.

[0058] Figure 1 illustrates a first example of a converter arrangement 100. The illustrated converter arrangement 100 is here embodied as a buck converter.

[0059] The converter arrangement comprises a first switch 110; a rectifying arrangement 120; an inductor LI and a control arrangement 150. For the purposes of the illustrated converter arrangement, an input power is provided between a first node N1 A and a second node N2A (which is connected to a ground or return line). Similarly, the output power is provided or defined as lying between a third node N3 A and the second node N2A.

[0060] Thus, the input voltage to the converter arrangement is the voltage at the first node N1 A (i.e., between the first node N1 A and ground) and the output power is the voltage at the third node N3A (i.e., between the third node N3A and ground).

[0061] The first switch 110 is connected between a first node N1 A and a switch node NXA. The operation of the first switch 110 is controlled by the control arrangement 150, e.g., using a control signal SI. The first switch 110 may be embodied as any suitable transistor, such as a MOSFET or GaN HEMT. Other examples will be apparent to the appropriately skilled person.

[0062] The rectifying arrangement 120 is connected between the second node N2A and the switch node NXA. In particular, the rectifying arrangement 120 is configured to permit current flow from the second node N2A to the switch node NXA and prevent or restrict current flow in the opposite direction. Thus, the rectifying arrangement functions as a diode connected from the second node N2A to the switch node NXA.

[0063] The inductor LI is connected between the switch node NXA and the third node N3 A.

[0064] The control arrangement 150 is configured to define a magnitude of the output power of the converter arrangement using pulse width modulation (PWM) of only the first switch. Thus, the control arrangement controls the converter arrangement to function or operate as a single-switch DC-to-DC converter. Approaches for appropriate PWM control of a switch, to achieve a desired voltage output, are well known in the art.

[0065] In some examples, a buffer capacitor Cl may be connected between the third node N3 A and second node N2A.

[0066] Figure 2 illustrates a second example of a converter arrangement 200. The illustrated converter arrangement 200 is here also embodied as a buck converter.

[0067] The converter arrangement 200 comprises a first switch 210; a rectifying arrangement 220; an inductor L2 and a control arrangement 250. For the purposes of the illustrated converter arrangement 200, an input power is provided between a second node N2B and a first node NIB (which is connected to a ground or return line). Differently to the previously described embodiment, the output power is provided or defined as lying between the second node N2B and a third node N3B.

[0068] Thus, the input voltage to the converter arrangement is the voltage at the second node N2B (i.e., between the second node N2B and ground) and the output power is the voltage between the second node N2B and the third node N3B.

[0069] The first switch 210 is connected between the first node NIB and a switch node NXB. The operation of the first switch 210 is controlled by the control arrangement 250, e.g., using a control signal S2. The first switch 210 may be embodied as any suitable transistor, such as a MOSFET or GaN HEMT. Other examples will be apparent to the appropriately skilled person.

[0070] The rectifying arrangement 220 is connected between the second node N2B and the switch node NXB. In particular, the rectifying arrangement 220 is configured to permit current flow from the switch node NXB to the second node N2B and prevent or restrict current flow in the opposite direction. Thus, the rectifying arrangement 220 functions as a diode connected from the switch node NXB to the second node N2B.

[0071] The inductor L2 is connected between the switch node NXA and the third node N3B. The control arrangement 250 is configured to define a magnitude of the output power of the converter arrangement using pulse width modulation (PWM) of only the first switch. Thus, the control arrangement controls the converter arrangement to function or operate as a single-switch DC-to-DC converter. Approaches for appropriate PWM control of a switch, to achieve a desired voltage output, are well known in the art.

[0072] In some examples, a buffer capacitor C2 may be connected between the second node N2B and the third node N3B.

[0073] Figure 3 illustrates a third example of a converter arrangement 300. The illustrated converter arrangement 300 is here embodied as a boost converter.

[0074] The converter arrangement 300 comprises a first switch 310; a rectifying arrangement 320; an inductor L3 and a control arrangement 350. For the purposes of the illustrated converter arrangement 300, an input power is provided between a third node N3C and a first node NIC (which is connected to a ground or return line). The output power is provided or defined as lying between a second node N2C and the first node NIC.

[0075] Thus, the input voltage to the converter arrangement is the voltage at the third node N3C (i.e., between the third node N3C and ground) and the output power is the voltage between at the second node N2C (i.e., between the second node N2C and ground).

[0076] The first switch 310 is connected between the first node NIC and a switch node NXC. The operation of the first switch 310 is controlled by the control arrangement 350, e.g., using a control signal S3. The first switch 310 may be embodied as any suitable transistor, such as a MOSFET or GaN HEMT. Other examples will be apparent to the appropriately skilled person.

[0077] The rectifying arrangement 320 is connected between the second node N2C and the switch node NXC. In particular, the rectifying arrangement 320 is configured to permit current flow from the switch node NXC to the second node N2C and prevent or restrict current flow in the opposite direction. Thus, the rectifying arrangement 320 functions as a diode connected from the switch node NXC to the second node N2C.

[0078] The inductor L3 is connected between the switch node NXA and the third node N3C.

[0079] The control arrangement 350 is configured to define a magnitude of the output power (between the second node N2C and the first node NIC) of the converter arrangement using pulse width modulation (PWM) of only the first switch. Thus, the control arrangement controls the converter arrangement to function or operate as a single-switch DC-to-DC converter. Approaches for appropriate PWM control of a switch, to achieve a desired voltage output, are well known in the art.

[0080] In some examples, a buffer capacitor C3 may be connected between the second node N2C and the first node NIC.

[0081] The preceding examples illustrate a number of converter arrangement configurations in which pulse width modulation control over a single switch controls the power flow to an output. In particular, a duty cycle of the pulse width modulation controls the power flow to the output. In general, the greater the duty cycle of the pulse width modulation, the greater the gain of the converter arrangement.

[0082] In each example, an appropriately positioned and configured rectifying arrangement is exploited in the conversion of power. Traditionally, the rectifying arrangement is formed from a single diode for controlling the permitted and / or restricted direction(s) of current flow.

[0083] The present disclosure proposes variations for this rectifying arrangement that facilitates improved performance of the converter arrangement. In particular, the proposed approaches facilitate (e.g., more efficient) zero-voltage switching of the single switch for lower gains and / or lower duty cycles (e.g., below 0.5) of the pulse width modulation of the (single) switch.

[0084] In a converter arrangement in which an output power is controlled by pulse width modulation of a single switch, the gain of the converter arrangement has a defined relationship with the duty cycle of the pulse width modulation. For a buck converter, the duty cycle is effectively equal to the gain. For a boost converter, the gain is effectively equal to the reciprocal of I minus the duty cycle.

[0085] Some proposed embodiments are at least partially based on the realization that the critical gain can differ if the charge stored by the first switch and the rectifying arrangement differ from one another. This can be achieved, for instance, if a linearity of the capacitance of the first switch differs from the linearity of the capacitance of the rectifying arrangement. The greater this difference in linearity, then the more the critical gain can differ from 0.5.

[0086] More particularly, in such circumstances, it has been recognized that if the rectifying arrangement stores a greater amount of charge than the first switch (e.g., during normal operation of the converter arrangement), then zero voltage switching can be achieved at lower gains and / or duty cycles. For the avoidance of doubt, in the context of the present disclosure, the term “critical gain” refers to the lowest ratio of the output to input voltage at which zero voltage switching of the first switch is possible.

[0087] Some embodiments are also based on the realization that the (maximum) voltage across the rectifying arrangement during one or more resonant oscillations at the switch at least partly depends upon a reverse recovery time of the rectifying arrangement. This can be exploited to control the voltage at the switch node.

[0088] For the sake of explanative ease, hereafter described embodiments are described in the context of a buck converter arrangement, first illustrated in Figure 1. However, the skilled person would be readily capable of incorporating the proposed approach in any form of converter arrangement in which the voltage of an output power is controlled using PWM of a single switch, such as the other examples previously provided, such as those illustrated in Figures 2 and 3.

[0089] Figure 4 illustrates a turn-on trajectory in the Vi-state plane of the buck converter arrangement first illustrated in Figure 1. Continued reference is made to the buck converter arrangement illustrated in Figure 1.

[0090] When the first switch is deactivated, the voltage at the switch node falls towards zero. The inductor current i(L 1 ) continues to flow, but decreases towards zero. The inductor current i(Ll) will then resonantly reverse its direction of flow causing the voltage at the switch node NXA to increase. The switch node voltage is able to increase to the voltage at the first node N1A (i.e., a supply voltage).

[0091] At least for the buck converter arrangement first illustrated in Figure 1, a zerovoltage boundary case (for a turn-on transistion of the first switch) is characterized by the inductor current i(Ll) reaching zero just as the switch node voltage vx arrives at the supply voltage (e.g., for a first time since the first switch is switched off). This indicates that there has been a sufficiently large negative current - for the switch node voltage to reach the supply voltage.

[0092] Considering the inductor current i(Ll) in more detail, and applying the above description of the zero-voltage switching boundary case (for the turn-on transition), which commences at zero current (with switch node voltage V(NXA) at 0) and ends again at zero current (but with the switch node voltage V(NXA) at the voltage V(N1 A) of the first node N1A). Using standard component characteristics, the following can be derived: 1to(1) ix(t0) = 0 = — vx— vodt. 'b JQ where to is the time at which the first switch is (re)activated, t is 0 when the inductor current crosses zero, ix(to) is the inductor current i(L 1) at time to, Lb is the indicator of the inductor LI, vxis the switch node voltage V(NXA) and v0is the output voltage, i.e., the voltage V(N3 A) at the third node N3 A.

[0093] If both sides of equation (1) are multiplied by Lb and integrated over ix, the following is produced:

[0094] Equation (2) can be reformulated as: r Qxo

[0095] 0 = 1 Vo— VxdQx Jo using the differential charge (dQx= — dixdt) flowing into the switch node NXA in the period between t=0 and t=to with QxO is the charge at tO. Qxrepresents the charge at the switch node NXA, where Qxorepresents the charge at the switch node NXA at time to.

[0096] Expressing equation (3) in terms of the capacitance Cxand voltage vxat the switch node (in which dQx= Cxdvx) yields the following equation: rvb

[0097] 0 = (vo- vx) ■ Cx(vx) dvx.

[0098] Jo

[0099] More specifically, Cx(vx) is the voltage-dependent switch node capacitance, which is composed of the low- and high-side elements or assemblies either serving as the first switch or the rectifying arrangement (hereafter taking indices s and r respectively). Thus, the capacitance Crrepresents the capacitance of the rectifying arrangement - as measured between the switch node and the second node. The capacitance Cs represents the capacitance of the first switch - as measured between the first node and the switch node, i.e., the source-drain capacitance of the first switch when embodied as a transistor.

[0100] Taking into account the configuration of the two capacitors in the illustrated buck converter arrangement, the switch node capacitance Cxis:

[0101] Cx(vx) = Cr(vx) + Cs(vb- vx). (5) where Vb is an alternative label for the voltage V(N1A) at the first node N1A, i.e., the input voltage.

[0102] For given capacitances at the switch node NXA, a critical value for the output voltage Vo can be identified that satisfies equation (4), provided that the properties of the capacitances are appropriately defined. This may be performed using two parameters for each capacitor. The values QrO and QsO may denote the relevant capacitors’ charge when charged up to the voltage V(N1 A), vb at the first node N1 A. Second, the coefficients mrand msare used to describe the degree of non-linearity of the respective CV characteristics where m=0 represents a linear capacitor and increasing values of m indicate an increasing non-linearity of the capacitor.

[0103] Using these properties, it is possible to approximate the capacitances as the following:

[0104] Equation (6) represents an approximation of the capacitances known from modelling the depletion capacitance of pn-junctions where the parameter m is referred to as the grading coefficient. As the value of parameter m approaches 0, the effective linearity of the corresponding capacitance increases, such that a vanishingly small coefficient (e,g, when m=0) represents a linear capacitor. An increasing value for m increasing (towards unity) describes an increasingly pronounced non-linearity.

[0105] Combining equations ((6), (5) and (4), and then, solving for the ratio between the output voltage voand the input voltage Vb yields1 + a. 1 ~ mr1 - ms(7) vo> > 2 — mr2 — ms

[0106] ~~Crit t i ~ • vb1 + qrwhere dcritdenotes the critical gain, and qris the charge ratio (qr= Qro / Qso) between the charge Qro stored by the rectifying arrangement and the charge Qso stored by the first switch.

[0107] One approach for calculating the coefficients mrand ms(i.e., measures of nonlinearity of the rectifying arrangement and first switch respectively) is to approximate the capacitance vs. voltage characteristics to equation (6) fitting the two parameters m and Q appropriately. Another way is to determine a co-energy factor Ilco,r, Ilco,s of the rectifying arrangement and first switch respectively. A co-energy factor for a component can be defined as the ratio between the co-energy and stored energy of the component (e.g., definable using a QV curve of the component). A co-energy factor can be defined as Eco / Estored, where Ecois the co-energy and Estored is the stored energy of the component. The relationship between a coefficient mx(where x = r or s) and a co-energy factor nco,xis as follows:

[0108] 1(8) nc co o X = 7 - ■ 'x1 - mx

[0109] From equation (7) it can be clearly identified that the charge ratio and the nonlinearity of the first switch and / or rectifying arrangement affect the critical gain. In particular, the greater the charge ratio, the lower the critical gain. .It can also be seen that in case of only linear capacitances (mr= ms= 0), then the critical gain is always 0.5 and thus independent of the charge ratio.

[0110] In other words, an improved critical gain can be achieved if a total charge stored by the rectifying arrangement is greater than a total charge stored by the first switch (e.g., across the operational range of voltages of the converter arrangement).

[0111] Put yet another way, an improved critical gain can be achieved if the charge stored across the first switch is less than the charge stored across the rectifying arrangement if a same non-zero voltage, at least within a working voltage range of the converter arrangement, is applied across both the first switch and the field-effect transistor. In other words, an improved critical gain can be achieved if the output charge of the first switch is less than the output charge of the second switch (where the output charge is the charge stored by the output capacitance of the relevant component). Similarly, it can also be seen from equation (7) that a difference in the linearity of the capacitance of the first switch and the rectifying arrangement also affects the critical gain. More particularly, an improved critical gain can be achieved when the capacitance of the rectifying arrangement has a greater degree of non-linearity than the capacitance of the first switch.

[0112] Figure 5 illustrates an example of a converter arrangement 500 that exploits the above-described recognition, best set out by equation (7).

[0113] The converter arrangement 500 is modified such that the rectifying arrangement 120, of the converter arrangement illustrated in Figure 1, comprises a field-effect transistor 510 and a biasing arrangement 520.

[0114] The field-effect transistor 510 is configured to function or operate as a diode. In particular, a body diode (or effective body diode) of the field-effect transistor 510 performs the function of a diode in the rectifying arrangement.

[0115] The biasing arrangement 520 is configured to apply a bias voltage to the gate of the field-effect transistor. This bias voltage is configured to operate the field-effect transistor in a sub-threshold mode, e.g., so that the field-effect transistor does not permit or allow two-way current flow through the field-effect transistor, thereby controlling the fieldeffect transistor to function or operate as a diode.

[0116] To achieve a non-unity charge ratio, the first switch and the field-effect transistor may be different types of transistors. For an improved operation, the capacitance of the field-effect transistor is less linear than the capacitance of the first switch, i.e., the capacitance of the first switch is more linear than the capacitance of the field-effect transistor. As set out by equation (7), this will significantly decrease critical gain of the converter arrangement.

[0117] As a working example, the first switch may comprise a HEMT, and the fieldeffect transistor may comprise a silicon superjunction, Si-SJ, MOSFET. This provides a fieldeffect transistor with an extremely high degree of non-linearity (e.g., compared to an HEMT) and a relatively high stored output charge (e.g., compared to an HEMT) for improving or reducing the critical gain of the converter arrangement. The use of a Si-SJ MOSFET also provides a more compact and resource efficient converter arrangement.

[0118] Other arrangements and configurations for the first switch and the field-effect transistor can be used. In general, it is advantageous if the total charge stored by the field-effect transistor is greater than the total charge stored by the first switch (for any non-zero voltage of the working / operational / rated voltage range of the converter arrangement) and / or the capacitance of the field-effect transistor is less linear than the capacitance of the first switch. These characteristics can be achieved through appropriate selection of the type and / or material of the first switch and the field-effect transistor.

[0119] The biasing arrangement is configured to apply a DC-voltage smaller than the gate-source threshold between the gate and source of the field-effect transistor. The DC- voltage may be positive, negative, or simply a short-circuit connection between the gate and the source. Thus, the field-effect transistor may operate in a sub-threshold mode of operation.

[0120] To achieve an improved critical gain of the converter circuit, the field-effect transistor may be configured to operate in a reverse recovery state.

[0121] Some types of field-effect transistor (e.g., dependent on one or more further factors such as the peak current, its decay rate, and temperature) may experience some reverse recovery current. This can occur even though the decay rates given by the inductor and the output voltage are relatively small. More particularly, some reverse recovery charge may pass the field-effect transistor in a reverse direction (i.e., from the switch node to the second node) before the field-effect transistor starts blocking such that the voltage at the switch node can begin to rise. This charge (Qrr) may be considered as an offset to the QV characteristic of the rectifying arrangement.

[0122] More particularly, the reverse recovery effect acts to effectively increase both the non-linearity mr of the rectifying arrangement as well as the charge QrO stored by the rectifying arrangement, both of which contribute to lowering the critical gain of the converter arrangement.

[0123] As an example, consider a basic scenario in which the charge stored by and the non-linearity of the rectifying arrangement and the first switch are the same (e.g., mr=mr=0.5 and Qr0=Qs0). In this basic scenario, if the non-linearity mr of the rectifying arrangement is increased to 0.81 (e.g., as a result of a reverse recovery effect) and the charge QrO stored by the rectifying arrangement is doubled, then the critical gain decreases from 0.5 to 0.33. This effectively means that reverse recovery can be made use of for operating the converter arrangement at reduced output powers while still facilitating zero-voltage switching.

[0124] In some field-effect transistors the gate bias has an influence on the reverse recovery charge (and time) of the field effect transistor. This effect can be used to control or modify the properties of the rectifying arrangement, e.g., increase a charge stored thereby, e.g., to control the voltage range within which the converter runs most efficiently. The closer the gate bias approaches the gate threshold voltage, the more the reverse recovery is suppressed. Thus, in some examples, the lower the desired critical gain, the lower the bias. Accordingly, the biasing arrangement 520 may be configured to control the value of the bias voltage responsive to the output power of the converter arrangement. In particular, the converter arrangement may be configured to: increase the value of the bias voltage responsive to the output voltage of the converter arrangement increasing; and decrease the value of the bias voltage responsive to the output voltage of the converter arrangement decreasing. The output voltage is the voltage of the output power. This can provide a more efficient converter arrangement.

[0125] The previously described embodiments make use of a field-effect transistor to provide a rectifying arrangement, that has a greater capacitance than the first switch, and is non-linear. This embodiment also has an advantage in that the (effective) reverse recovery time can be readily controlled, to thereby facilitate control over the critical gain of the converter arrangement.

[0126] However, the skilled person would be readily capable of defining or providing other forms of rectifying arrangements that have a greater capacitance than the first switch, and are non-linear. By way of working example, the rectifying arrangement may comprise a non-linear capacitor and a diode connected in parallel to one another, which may function or act in a similar manner.

[0127] It has been previously mentioned how a (maximum) voltage across the rectifying arrangement during one or more resonant oscillations at the switch at least partly depends upon a reverse recovery time of the rectifying arrangement. This can be exploited to control the voltage at the switch node, e.g., to achieve zero-voltage switching.

[0128] In particular, it is possible to tune or define the reverse recovery time to achieve highly efficient zero voltage switching.

[0129] Figure 6 illustrates a converter arrangement 600 in which the rectifying arrangement 120 comprises at least two diode arrangements 610, 620 connected in parallel.

[0130] The rectifying arrangement here comprises a first diode arrangement 610 and a second diode arrangement 620 connected in parallel. A reverse recovery time of the first diode arrangement 610 is different to a reverse recovery time of the second diode arrangement 620. This approach provides a technique for configuring or defining the effective reverse recovery time of the rectifying arrangement.

[0131] This embodiment relies upon the property that, after the first switch is deactivated or turned off, an inductor current i(L 1) will initially move towards a zerocrossing, before passing beyond the zero-crossing to have an opposite polarity. This is due to the collapse of the magnetic field carried by the inductor LI causing a reverse in the current flow through the inductor LI. Due to the natural resonance of the converter arrangement, without any further switching of the first switch, the inductor current would then continue to oscillate around the zero crossing. These oscillations cause the switch node voltage to oscillate.

[0132] To achieve zero-voltage switching of the first switch, the voltage at the switch node NXA must at least reach the voltage at the first node when the first switch is turned on or reactivated. This can only be achieved for low output voltages if the reverse current flow through the inductor (after the first switch is first deactivated) reaches a sufficiently high value during a reverse conduction state of the rectifying arrangement (when the rectifying arrangement begins blocking) to produce the necessary voltage at the switch node NXA. The occurrence of a reverse current flow through a previously forward biased diode is a well- established phenomenon.

[0133] The length of time that there is reverse current flow is defined by the reverse recovery time of the rectifying arrangement. Put another way, the length of time that the rectifying arrangement will operate in the reverse conduction state is defined by the reverse recovery time of the rectifying arrangement. The greater the reverse recovery time, the more likely that there will be a sufficiently large reverse current flowing through - the rectifying arrangement to cause the voltage at the switch node NXA to oscillate and reach the voltage at the first node NlA.

[0134] Figure 7 illustrates two waveforms of the converter arrangement in a first scenario in which the rectifying arrangement (of the converter arrangement illustrated in Figure 1) is replaced with a single diode (having a relatively fast reverse recovery time and a relatively small capacitance with a relatively small degree of non-linearity). A first waveform 150 depicts a voltage V(NXA) at the switch node NXA and a second waveform 720 depicts a current i(Ll) through the inductor LI. The current i(D) through the diode is also illustrated for the sake of completeness.

[0135] In this first scenario, the reverse recovery time of the rectifying arrangement is not sufficient to cause the voltage at the switch node NXA to oscillate and reach the voltage at the first node N1A.

[0136] Time tO represents a time at which the first switch is activated or switched on.

[0137] At a time tl, the first switch is deactivated or switched off. The reverse recovery time of the rectifying arrangement is not sufficient to cause the voltage at the switch node NXA to oscillate and reach the voltage at the first node N1 A. This means that zero voltage switching cannot occur, e.g., when the first switch is reactivated at a time t2 (after or at a peak of the oscillation of the voltage V(NXA) at the switch node), incurring significant power inefficiencies in the converter.

[0138] Figure 8 illustrates two waveforms of the converter arrangement in a second scenario in which the rectifying arrangement (of the converter arrangement illustrated in Figure 1) is replaced with a single diode (having a relatively slow reverse recovery time). A first waveform 810 depicts a voltage V(NXA) at the switch node NXA and a second waveform 820 depicts a current i(Ll) through the inductor LI. The current i(D) through the diode is also illustrated for the sake of completeness.

[0139] Time tO represents a time at which the first switch is activated or switched on.

[0140] At a time tl, the first switch is deactivated or switched off. In this second scenario, the reverse recovery time of the rectifying arrangement is sufficient to cause the voltage at the switch node NXA to oscillate and reach the voltage V(N1 A) at the first node N1 A at a time t2. However, in the second example, the reverse recovery time of the rectifying arrangement is extremely large. This causes the voltage at the switch node NXA to reach the voltage at the first node whilst the current i(L 1) is still highly negative. This can unacceptably increase the reactive current, creating significant inefficiencies in the converter.

[0141] The present disclosure recognizes that existing diodes, for use as a rectifying arrangement, may not (by themselves) be able to achieve a target reverse recovery time that balances between these two scenarios.

[0142] As an example, a diode having an ultrafast reverse recovery time (e.g., <50ns) will not be sufficient to cause the voltage at the switch node NXA to oscillate and reach the voltage at the first node N1 A.

[0143] As another example, a diode having a fast reverse recovery time (e.g., > 100 ns and < 250 ns) will cause the voltage at the switch node NXA to reach the voltage at the first node whilst the current i(L 1 ) is still highly negative, resulting in significant reactive current.

[0144] There is a clear desire to balance between these two positions, in particular to target a zero-voltage switching (ZVS) boundary case. A ZVS boundary case is characterized by the inductor current i(Ll) reaching zero just as the switch node voltage vx (first) arrives at the supply voltage.

[0145] One herein proposed approach makes use of two diode arrangements, connected in parallel, with different reverse recovery times. This effectively allows or facilitates the tuning or selecting of an overall, effective reverse recovery time that can achieve zero voltage switching without significant reactive current.

[0146] Thus, turning back to Figure 6, the solution provided by the use of two diode arrangements effectively makes use of two parallel rectifier diode paths. A first path comprises a first diode arrangement 610 (e.g., a single diode DI) having a first reverse recovery time and the other path comprises a second diode arrangement 620 (e.g., comprising a single diode D2) having a second, slower reverse recovery time.

[0147] Figure 9 illustrates a number of waveforms of the converter arrangement, illustrated in Figure 6. A first waveform 910 depicts a voltage at the switch node NXA. A second waveform 920 depicts a current i(L 1) through the inductor LI, a third waveform 930 depicts a current through the first diode arrangement 610 and a fourth waveform 940 depicts a current through the second diode arrangement 620.

[0148] In some examples, and as illustrated in Figure 9, the second diode arrangement latter takes a smaller share of the total current through the rectifying arrangement. This is achieved by forming the second diode arrangement from a diode D2 and resistor R2 connected in series. The resistance value of the resistor R2 may be selected to create only negligible losses. The diode’s current slew rate (diD2 / dt) may be chosen to still be sufficient to incite just enough reverse current enabling a zero voltage switching turn-on transition with less reactive current than a single diode approach, e.g., as previously described with reference to Figure 8.

[0149] In essence, the task of the first diode arrangement 610 is to perform the rectification. The second diode arrangement 620 is used to generate a certain amount of reverse current, which is controlled by the resistor R2. Because typically, a diode’s forward voltage drop is slightly higher for types of diode that experience less reverse recovery, then the resistor R2 is able to shift current flow to the first diode arrangement 610 and reduce the current flow through the diode D2 following the turning off of the first switch.

[0150] Although only two diode arrangements are illustrated in Figure 6, it will be appreciated that, in practice, the rectifying arrangement may comprise more than two diode arrangements (connected in parallel) to better adapt the converter arrangement to the preferred behavior, e.g., for a range of output voltages.

[0151] Figure 10 illustrates a modified version of the converter arrangement 1000.

[0152] In this approach, the resistor R2 is formed as a variable resistor, here embodied as a transistor 1050, such as a low-voltage (MOS)FET. The resistance of the resistor R2 will affect the reverse recovery time of the rectifying arrangement 120. More particularly, the resistance of the resistor R2 will control or change an amount of current that passes through the second diode arrangement 620. As the first and second diode arrangements have different reverse recovery times, changing the distribution of current flow through the diode arrangements will change the effective reverse recovery time of the rectifying arrangement.

[0153] A resistor control arrangement 1055 is configured to control the resistance of the variable resistor, responsive to the output power (e.g., the voltage at the third node N3A). In this illustrated example, the resistor control arrangement may control a gate voltage of the transistor 1050 to variably operate the transistor 1050 within its linear region, to thereby control the resistance of the transistor.

[0154] Approaches for providing a controllable gate voltage to a transistor are well known in the art, and may comprise using a microcontroller to provide a desired voltage to the transistor.

[0155] In particular, the resistor control arrangement may be configured to, responsive to an increase in the output power of the converter arrangement, control the resistance of the variable resistance to decrease the ratio of the resistance of the first diode arrangement and the resistance of the second diode arrangement.

[0156] More particularly, for the buck converter configuration, at low output powers (and preferably low output voltages) - the overall reverse recovery time for the rectifying arrangement should be increased (e.g., to ensure zero voltage switching). Thus, if the reverse recovery time of the second diode D2 is greater than the reverse recovery time of the first diode DI, then the resistance of the variable resistor should be decreased to increase the effective overall reverse recovery time of the rectifying arrangement.

[0157] Similarly, for the buck converter configuration, at high output powers (preferably high output voltages) - the overall reverse recovery time for the rectifying arrangement can be decreased for more efficient operation (e.g., reduced reactive current). Thus, if the reverse recovery time of the second diode D2 is greater than the reverse recovery time of the first diode DI, then the resistance of the variable resistor should be increased to increase the effective overall reverse recovery time of the rectifying arrangement. The variable resistor can also be employed to counteract an undesired effect that higher output voltages lead to larger current decay rates (didt) and in turn, to more reverse recovery current (when it is not needed). In this way, the effective reverse recovery time of the rectifying arrangement can be manipulated or tuned to the specific output power being provided by the converter arrangement.

[0158] The variable resistance can also or otherwise be exploited to provide protection or robustness to temperature effects on the reverse recovery. In particular, it is recognized that higher temperatures will increase a reverse recovery current. The impact of higher temperatures can be handled by using the variable resistance to control a distribution of current through the rectifying arrangement.

[0159] The skilled person will readily appreciate that the resistor R2 may be formed from another form of variable resistor, such as a digital potentiometer or the like.

[0160] In some examples, the converter arrangement may further comprise a fieldeffect transistor connected in parallel to the first and second diode arrangements. The converter arrangement may further comprise a biasing arrangement configured to apply a bias voltage to the field-effect transistor to configure the field-effect transistor to operate in a sub-threshold mode. Thus, the embodiments illustrated in Figs. 5 and 10 (and described with reference thereto) may be effectively combined, with the relevant sub-embodiments of both embodiments being variants of the combined embodiment.

[0161] The bias voltage may be considered a steady DC (direct current) voltage that is applied to the field effect transistor. The bias voltage can be a positive or a negative voltage, depending on the application and the desired operating characteristics of the field effect transistor. Preferably, the bias voltage is a steady voltage over more than one, preferably more than two, switching moments of the PWM of the first switch.

[0162] The preceding embodiment(s) and example(s) make use of defining a reverse recovery time to achieve more efficient zero-voltage switching of a first switch in a converter arrangement.

[0163] Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality.

[0164] The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0165] If the term "adapted to" is used in the claims or description, it is noted the term "adapted to" is intended to be equivalent to the term "configured to". If the term "arrangement" is used in the claims or description, it is noted the term "arrangement" is intended to be equivalent to the term "system", and vice versa.

[0166] Any reference signs in the claims should not be construed as limiting the scope.

Claims

CLAIMS:

1. A converter arrangement (500) comprising: a first switch (110) connected between a first node (N1 A) and a switch node (NXA); a field-effect transistor (510) connected between the switch node (NXA) and a second node (N2A); a biasing arrangement (520) configured to apply a bias voltage to the fieldeffect transistor (510) to configure the field-effect transistor (510) to operate in a subthreshold mode; an inductor (LI) connected between the switch node (NXA) and a third node (N3A); and a control arrangement (150) configured to define a magnitude of the output power of the converter arrangement (500) using pulse width modulation, PWM, of only the first switch (110), wherein a linearity of a charge stored by the first switch (110), with respect to a voltage across the first switch (110), is different to a linearity of a charge stored by the field-effect transistor (510), with respect to a voltage across the field-effect transistor (510), wherein the bias voltage is steady over more than one switching moment of the PWM of the first switch (110).

2. The converter arrangement of claim 1, wherein the first switch and the fieldeffect transistor are different types of transistor.

3. The converter arrangement of claim 1 or 2, the charge stored by the first switch is less than the charge stored by the field-effect transistor if a non-zero voltage, within a working voltage range of the converter arrangement, is applied across the first and second node.

4. The converter arrangement of any of claims 1 to 3, wherein the capacitance of the field-effect transistor is less linear than the capacitance of the first switch.

5. The converter arrangement of any one of claims 1 to 4, wherein the biasing arrangement is configured to control the value of the bias voltage responsive to the output power of the converter arrangement.

6. The converter arrangement of claim 5, wherein the biasing arrangement is configured to increase the value of the bias voltage responsive to the output power of the converter arrangement increasing.

7. The converter arrangement of any one of claims 1 to 6, wherein the field-effect transistor is a MOSFET.

8. The converter arrangement of any one of claims 1 to 7, wherein the field-effect transistor is a silicon superjunction, Si-SJ, MOSFET.

9. The converter arrangement of any one of claims 1 to 8, further comprising: a first diode arrangement connected in parallel to the field-effect transistor; and a second diode arrangement connected in parallel to the first diode arrangement and the field-effect transistor, wherein a reverse recovery time of the first diode arrangement is different to a reverse recovery time of the second diode arrangement.

10. The converter arrangement of claim 9, further comprising: a variable resistance connected in series with the first diode arrangement; and a resistor control arrangement configured to control the resistance of the variable resistor responsive to the output power of the converter arrangement.

11. The converter arrangement of claim 10, wherein: a reverse recovery time of the first diode arrangement is less than the reverse recovery time of the second diode arrangement; and the resistor control arrangement is configured to, responsive to an increase in the output power of the converter arrangement, control the resistance of the variableresistance to decrease the ratio of the resistance of the first diode arrangement and the resistance of the second diode arrangement.

12. The converter arrangement of any one of claims 9 to 11, wherein: the resistance of the first diode arrangement is less than the resistance of the second diode arrangement; and the reverse recovery time of the first diode arrangement is less than the reverse recovery time of the second diode arrangement.

Images