Memory access information processing method, devices, storage medium and program product

Abstract

The embodiments of the present disclosure provide a memory access information processing method, devices, a storage medium and a program product. In an embodiment of the present disclosure, a virtualization technique is used to emulate a virtual IO device on a hardware acceleration device, and a virtualized instance executes an access request for the virtual IO device by means of a virtualization manager. During the process, the hardware acceleration device parses the access request into memory address information and access behavior information of the virtual IO device. The virtual IO device is controlled to perform direct memory access; in addition, the memory address information and the access behavior information are converted into memory access information at the virtual IO device dimension, and the memory access information is provided to the virtualization manager, such that the virtualization manager perceives the memory access information of the virtual IO device. Furthermore, compatibility with hardware resources of various versions can be realized without the need to modify page tables of IOMMUs, and the number of memory accesses by each virtual IO device can also be accurately acquired without the need to scan a page table.

Description

[0001] Memory Access Information Processing Method, Device, Storage Medium, and Program Product TECHNICAL FIELD The present disclosure relates to the field of cloud computing technology, and more particularly to a memory access information processing method, device, storage medium, and program product. Background: A memory management unit (MMU) is a hardware module that implements virtual memory management between a central processing unit (CPU) and memory. The MMU converts virtual addresses to physical addresses based on a page table and records CPU memory access information using reserved access bits and dirty bits in the page table. Thus, scanning the MMU's page table reveals which memory pages have been accessed or modified. However, some input / output (IO) devices can access memory using direct memory access (DMA) without going through the MMU. In such cases, it is impossible to obtain IO device memory access information from the MMU's page table. Therefore, obtaining IO device memory access information is a pressing technical issue. SUMMARY OF THE INVENTION Various aspects of the present disclosure provide a memory access information processing method, device, storage medium, and program product for obtaining memory access information of a device. Embodiments of the present disclosure provide a computer device comprising: a physical machine and a hardware acceleration device; the physical machine and the hardware acceleration device interact via input / output buffers, the input / output buffers comprising a first input / output buffer and a second input / output buffer; a virtualization manager on the physical machine writes an access request from a virtualization instance to its first virtual input / output device into the first input / output buffer, and reads memory access information of the first virtual input / output device from the second input / output buffer; the hardware acceleration device reads the access request from the first input / output buffer, parses the access request into memory address information and access behavior information of the first virtual input / output device, controls the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; and converts the memory address information and access behavior information into memory access information of the first virtual input / output device, and writes the memory access information into the second input / output buffer of the second virtual input / output device for reading by the virtualization manager.An embodiment of the present disclosure further provides a hardware acceleration device, wherein the hardware acceleration device implements input / output buffers required for interacting with a physical machine, the input / output buffers including a first input / output buffer and a second input / output buffer. The hardware acceleration device reads an access request from a virtualization instance to its first virtual input / output device from the first input / output buffer, where the access request is written to the first input / output buffer by a virtualization manager on the physical machine. The hardware acceleration device parses the access request into memory address information and access behavior information of the first virtual input / output device, controls the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information, and converts the memory address information and access behavior information into memory access information of the first virtual input / output device, and writes the memory access information to the second input / output buffer of the second virtual input / output device for reading by the virtualization manager. An embodiment of the present disclosure also provides a memory access information processing method, applied to a hardware acceleration device, wherein the hardware acceleration device implements input / output buffers required for interacting with a physical machine, the input / output buffers including a first input / output buffer and a second input / output buffer. The method comprises: reading, from the first input / output buffer, an access request from a virtualization instance to its first virtual input / output device, the access request being written into the first input / output buffer by a virtualization manager on the physical machine; parsing the access request into memory address information and access behavior information of the first virtual input / output device, controlling the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; and converting the memory address information and access behavior information into memory access information of the first virtual input / output device, and writing the memory access information into the second input / output buffer of the second virtual input / output device for reading by the virtualization manager. An embodiment of the present disclosure provides a method for processing memory access information, which is applied to a virtualization manager running on a physical machine. The physical machine interacts with a hardware acceleration device via input / output buffers, wherein the input / output buffers include a first input / output buffer and a second input / output buffer. The method comprises: writing an access request from a virtualization instance to its first virtual input / output device into the first input / output buffer, where the first virtual input / output device is required by the virtualization instance and implemented on the hardware acceleration device; and reading memory access information of the first virtual input / output device from the second input / output buffer, where the memory access information is converted by the hardware acceleration device based on memory address information and access behavior information in the access request.An embodiment of the present disclosure provides a computer device, comprising: a physical machine and a hardware acceleration device; the physical machine runs a virtualization manager to create and manage a virtualization instance; the hardware acceleration device implements a first virtual input / output device required by the virtualization instance, parses an access request from the virtualization instance to the first virtual input / output device into memory address information and access behavior information of the first virtual input / output device, and controls the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; the hardware acceleration device converts the memory address information and access behavior information into memory access information of the first virtual input / output device, and provides the memory access information of the first virtual input / output device to the virtualization manager. Embodiments of the present disclosure also provide a method for processing memory access information, applied to a hardware acceleration device of a computer device, wherein a first virtual input / output device required by a virtualization instance is implemented on the hardware acceleration device. The method comprises: parsing an access request from the virtualization instance to the first virtual input / output device into memory address information and access behavior information of the first virtual input / output device, thereby controlling the first virtual input / output device to perform direct memory access; converting the memory address information and access behavior information into memory access information of the first virtual input / output device; and providing the memory access information of the first virtual input / output device to a virtualization manager, so that the virtualization manager can obtain the memory access information. Embodiments of the present disclosure also provide a method for processing memory access information, applied to a virtualization manager running on a computer device. The method comprises: providing an access request from the virtualization instance to the first virtual input / output device to the hardware acceleration device, wherein the first virtual input / output device is a virtual input / output device required by the virtualization instance and implemented on the hardware acceleration device; and obtaining memory access information of the first virtual input / output device provided by the hardware acceleration device, wherein the memory access information is converted by the hardware acceleration device based on the memory address information and access behavior information in the access request. Embodiments of the present disclosure further provide an electronic device, comprising: a memory and a processor; the memory being configured to store a computer program; and the processor being coupled to the memory and configured to execute the computer program to implement the steps of the memory access information processing method provided in the embodiments of the present disclosure. Embodiments of the present disclosure further provide a computer-readable storage medium storing the computer program. When the computer program is executed by the processor, the processor implements the steps of the memory access information processing method provided in the embodiments of the present disclosure.The present disclosure also provides a computer program product, including a computer program / instructions. When executed by a processor, the computer program / instructions cause the processor to implement the steps of the memory access information processing method provided in the present disclosure. In the present disclosure, virtualization technology is used to simulate a virtual device on a hardware acceleration device. The virtualized instance executes access requests for the virtual device through a virtualization manager. During this process, the hardware acceleration device parses the access request into memory address information and access behavior information of the virtual device. The hardware acceleration device controls the virtual device to perform direct memory access and converts the memory address information and access behavior information into memory access information in the virtual device dimension. The information is then provided to the virtualization manager, allowing the virtualization manager to perceive the memory access information of the virtual device. Because traditional methods bypass the virtualization manager and access memory directly through the IOMMU, it's impossible to detect which memory the device accesses. Compared to methods that add bits to the IOMMU's page table to record memory access information, the disclosed embodiments do not require modification to the IOMMU's page table, are compatible with various versions of hardware resources, and do not require scanning page tables. The number of memory accesses by each virtual IOM device can be accurately obtained. Furthermore, the overhead of obtaining memory access information does not increase with increasing memory capacity, resulting in strong scalability. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings described herein are provided to provide a further understanding of the present disclosure and constitute a part thereof. The illustrative embodiments of the present disclosure and their descriptions are provided to explain the present disclosure and are not intended to unduly limit the present disclosure. In the accompanying drawings: Figure 1 is a schematic diagram illustrating the interconnection relationship between a processor, a page table, a memory, and an I / O device according to an exemplary embodiment of the present disclosure; Figure 2a is a schematic diagram illustrating the structure of a computer device according to an exemplary embodiment of the present disclosure; Figure 2b is a schematic diagram illustrating the structure of another computer device according to an exemplary embodiment of the present disclosure; Figure 2c is a schematic diagram illustrating the structure of an I / O buffer according to an exemplary embodiment of the present disclosure; Figures 3a-3c are flowcharts illustrating a method for processing memory access information according to an exemplary embodiment of the present disclosure; Figure 4 is a schematic diagram illustrating the flow of another method for processing memory access information according to an exemplary embodiment of the present disclosure; Figure 5 is a schematic diagram illustrating the structure of a memory access information processing device according to an exemplary embodiment of the present disclosure; Figure 6 is a schematic diagram illustrating the structure of another memory access information processing device according to an exemplary embodiment of the present disclosure; and Figure 7 is a schematic diagram illustrating the structure of an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION To further clarify the objectives, technical solutions, and advantages of the present disclosure, the technical solutions of the present disclosure will be described clearly and completely below in conjunction with the specific embodiments of the present disclosure and the corresponding drawings.Obviously, the described embodiments are only some of the embodiments of this disclosure, and not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure. It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display, etc.) involved in this disclosure are all authorized by the user or fully authorized by all parties. The collection, use, and processing of relevant data must comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or deny. Applications on a physical machine can access memory through the CPU. During the CPU's memory access process, memory access information can be recorded for subsequent use. As shown in Figure 1, the CPU can access memory through the MMU. The CPU provides a virtual address (VA) to the MMU. The MMU converts the virtual address (VA) into a physical address (PA) of the memory using a page table. The CPU accesses the memory through the PA, enabling the CPU to access the memory. When the CPU accesses memory, memory access information can be obtained by reserving an access bit and a dirty bit in the MMU's page table to record CPU memory access information. The access bit records accessed memory pages, and the dirty bit records modified memory pages. Scanning the MMU's page table can reveal which memory pages have been accessed or modified. However, page table scanning suffers from poor scalability. Scanning the global memory page table takes a long time. As memory capacity increases, the overhead of page table scanning becomes non-negligible. To reduce the overhead of page table scanning, the periodic scanning frequency is reduced. However, this comes at the cost of being unable to accurately count the access frequency of a single memory page. For example, if the CPU accesses the same memory page 10 million times between two scans, reducing the scanning frequency will yield a scan count of 10 accesses. In this embodiment, in addition to the CPU accessing memory, there are also cases where 10 devices access memory. Device 10 is an input / output device that can input data into a physical machine or output data from a physical machine to other devices.For example, a device can be a storage device such as a hard drive or USB flash drive, an input device such as a keyboard or mouse, an output device such as a monitor, or a network communication device such as a network adapter. Typically, a device accesses memory through the CPU. The CPU reads data provided by the device and writes it to memory, or reads data from memory and provides it to the device. To reduce the CPU's workload, direct access memory (DMA) can be used for data transfer between the device and memory. The device directly writes data to memory, or reads data directly from memory, without the CPU acting as a "middleman." When a device accesses memory using DMA, it provides a virtual address, referred to as IOVA. When the device accesses memory, the device's memory management unit, referred to as IOMMU, converts the virtual address (IOVA) into a physical address (PA) using the page table (IOPT) it maintains. Memory is then accessed based on this physical address, as shown in Figure 1. When an I / O device accesses memory, since it can access memory directly without going through the CPU, address translation through the MMU's page tables is unnecessary. Instead, address translation is performed through the I / O MMU's page tables. In this case, it is impossible to obtain memory access information from the MMU's page tables. Therefore, obtaining memory access information from I / O devices becomes a pressing technical issue. To address this issue, in an optional embodiment of the present disclosure, a bit is added to the I / O MMU's IOPT to track memory access information. For example, an access bit is added to the I / O MMU's page table (IOPT). However, this approach requires hardware upgrades and is not applicable to earlier models. Furthermore, scanning the I / O page table (IOPT), like scanning the MMU's page table (PT), still suffers from high scanning overhead, poor scalability, and the inability to accurately obtain access counts. To address the above technical issues, in another optional embodiment of the present disclosure, virtualization technology is adopted to simulate a virtual device on a hardware acceleration device. The virtualized instance executes an access request for the virtual device through a virtualization manager. During this process, the hardware acceleration device parses the access request into memory address information and access behavior information that the virtual device can understand. On the one hand, it controls the virtual device to perform direct memory access. On the other hand, it converts the memory address information and access behavior information into memory access information in the virtual device dimension and provides it to the virtualization manager, so that the virtualization manager can perceive the memory access information of the virtual device.Because traditional methods bypass the virtualization manager and access memory directly through the IOMMU, it's impossible to detect which memory the device accesses. Compared to methods that add bits to the IOMMU's page table to record memory access information, the present embodiment eliminates the need to modify the IOMMU's page table, ensuring compatibility with various versions of hardware resources. Page table scanning also eliminates the need to accurately obtain the number of memory accesses by each virtual device. Furthermore, the overhead of obtaining memory access information does not increase with increasing memory capacity, resulting in strong scalability. A solution provided by an embodiment of the present invention is described in detail below, in conjunction with the accompanying drawings. Figure 2a is a schematic diagram of the physical machine structure provided by an exemplary embodiment of the present invention. As shown in Figure 2a, the computer device includes a physical machine 10 and a hardware acceleration device 20. In this embodiment, the physical machine 10 includes at least a physical computing resource object 101. Physical computing resource objects 101 can be various physical resource objects with computing capabilities, such as CPUs, graphics processing units (GPUs), data processing units (DPUs), tensor processing units (TPUs), cloud infrastructure processing units (CIPUs), and application-specific integrated circuits (ASICs). Figure 2a illustrates physical computing resource objects 101 using a CPU as an example. In addition, physical machine 10 also includes other components, such as memory, communication components, displays, power components, and audio components, which are not described in detail here. In this embodiment, a virtualization manager 102 runs on physical computing resource objects 101, and virtualization manager 102 is used to create and manage multiple virtualization instances 103. o Any virtualization manager that can manage virtualized instances is applicable to the embodiments of the present disclosure. For example, a virtualization manager can be a Virtual Machine Manager (VMM), which can also be called a Hypervisor. oA hypervisor allows multiple operating systems and applications to share a set of basic physical resources. Therefore, it can also be considered a "meta" operating system in a virtual environment and is the core of virtualization technology. Virtualization instances may include, but are not limited to, cloud hosts, Elastic Compute Service (ECS), virtual machines (VMs), or containers. In this embodiment, with the development of cloud computing technology, to improve virtualization efficiency, a hardware acceleration device 20 has been introduced for physical machines. Hardware acceleration device 20 is a device that implements virtualization technology and can help interconnected physical machines implement at least some virtualization functions. In other words, the physical machine can offload some or all virtualization functions to the hardware acceleration device 20, thereby achieving performance acceleration. This embodiment does not limit the implementation form of the hardware acceleration device 20; its implementation form may include, but is not limited to, an application-specific integrated circuit (ASIC), a system-on-chip (SOC), a field programmable gate array (FPGA), or a complex programmable logic device (CPLD). In addition, the hardware acceleration device 20 has its own hardware resources, such as computing resources, storage resources, and network resources. The computing resources of the hardware acceleration device 20 include, but are not limited to, CPUs, GPUs, and TPUs, and are not limited to these. The storage resources of the hardware acceleration device 20 may include, but are not limited to, local storage resources such as memory and hard disks, and may include cloud storage resources such as cloud disks and Network Attached Storage (NAS). Network resources may include, but are not limited to, communication components such as network cards. In this embodiment, the hardware acceleration device 20 may adopt a hardware-software integrated design, including not only the aforementioned hardware resources but also software resources running on the hardware resources, such as an operating system and related hardware drivers. The hardware acceleration device 20 may be interconnected with the physical machine 10 via an interconnect bus, which may include, but is not limited to, a Peripheral Component Interconnect (PCI) bus and a Peripheral Component Interconnect Express (PCIE) bus.In this embodiment, the hardware acceleration device 20 can implement a virtual device 201 required by the virtualization instance 103. For ease of distinction and description, the virtual device implemented by the hardware acceleration device 20 for the virtualization instance 103 is referred to as a first virtual device. The first virtual device is a virtual device accessible by the virtualization instance 103. For example, the first virtual device may include, but is not limited to, a virtual keyboard, a virtual mouse, a virtual printer, or a virtual network card. The first virtual device 201 may be a PCI device or a PCIE device. The hardware acceleration device 20 may pre-implement the first virtual device 201 and assign it to the virtualization instance; alternatively, the hardware acceleration device 20 may implement the first virtual device 201 as needed for the virtualization instance. A virtualization instance may correspond to one or more first virtual devices. The hardware acceleration device 20 may implement the first virtual device through software based on the interface definition and memory design specifications of the actual device. The hardware acceleration device 20 can simulate the same resources for the virtual device based on the actual device's resources. For example, a physical computing resource object 101 (e.g., a CPU) is connected to IOS devices via a PCI bus. From the perspective of physical computing resource object 101, each IOS device is a PCI device. Each PCI device has a set of important registers, called base address registers. The virtualization manager emulates these base address registers for the virtualization instance, allowing the virtualization instance to discover the virtual IOS device. In this embodiment, when virtualization instance 103 accesses the first virtual IOS device 201, an exception may be triggered, causing the virtualization instance to exit (e.g., a VM exit), trapping the virtualization manager 102. Virtualization manager 102 may detect the virtualization instance's access to the first virtual IOS device and intercept the access request. Virtualization manager 102 may also provide virtualization instance 103's access request for the first virtual IOS device to the hardware acceleration device 20. In the process of creating a virtualization instance, the virtualization manager 102 may pre-configure a capability for the virtualization instance 103 to trap to the virtualization manager 102, and pre-record which events will cause the virtualization instance 103 to trap to the virtualization manager 102. In this embodiment, it may be configured that when the virtualization instance 103 sends an access request to the first virtual device 103, the virtualization instance 103 traps to the virtualization manager 102. In this embodiment, the hardware acceleration device 20 may parse the access request into memory address information and access behavior information of the first virtual device 103.The access request may exist in the form of a descriptor. A descriptor is a data structure or object containing the information required for the access request. The descriptor is used to describe the characteristics, behavior, and other relevant parameters of the access request. The descriptor may include, but is not limited to, the source address, destination address, port number, protocol type, access behavior information, and access permission information. The destination address may be the memory address information to be accessed, for example, the memory address information may include the starting address and length information, and the access behavior information may include read or write. The memory address information and access behavior information are in a data format that the virtual machine can recognize and process accordingly. In this embodiment, the hardware acceleration device 20 can control the virtual machine to perform direct memory access based on the memory address information and access behavior information. Direct memory access reflects the direct access feature of the first virtual machine to memory. Direct memory access means that the first virtual machine implemented by the hardware acceleration device 20 can directly access memory without passing through the physical computing resource object 101 of the physical machine, writing data to the physical machine's memory or reading data from the memory. For example, if the access behavior information indicates writing data, the hardware acceleration device 20 may write data to the location indicated by the memory address information; if the access behavior information indicates reading data, the hardware acceleration device 20 may read data from the location indicated by the memory address information. In this embodiment, in addition to controlling the first virtual device to perform direct memory access based on the memory address information and access behavior information, the hardware acceleration device 20 may also convert the memory address information and access behavior information into memory access information for the first virtual device. The memory access information may include, but is not limited to, access behavior information, memory address information, and identification information of the virtual device. The memory access information may also be referred to as a memory access log (Page Modification Log, PML) or a memory access log (Page Access Log, PAL). The hardware acceleration device 20 may also provide the memory access information of the first virtual device to the virtualization manager 102. oIn an optional embodiment, the virtualization manager 102 obtains memory access information of the first virtual device and tracks memory access behavior based on the memory access information of the first virtual device. Specifically, the virtualization manager 102 can track memory access behavior based on the memory access information of the first virtual device. An exemplary explanation is provided below. Example A1: When a memory management trigger event occurs, the virtualization manager 102 performs memory management on the physical machine or virtualized instance based on the memory access information of the first virtual device. Memory management includes memory space allocation and deallocation, memory swapping, and other tasks. Memory space allocation and deallocation primarily address how to allocate space for processes, manage memory space, and reclaim process memory space after the process terminates. Memory swapping primarily addresses the issue of a program's running memory exceeding physical memory by swapping a portion of disk space into memory for use by the currently running program. For example, when performing memory swapping on a physical machine, memory access information from a first virtual device is used to count which memory pages in the physical memory of the physical machine have been accessed (access information), and the access frequency of the memory pages is further determined. Based on the access frequency of the memory pages, hot and cold data in the memory are identified, and memory pages with access frequencies below a set threshold are swapped to the hard disk to expand the physical memory space. For another example, when performing memory space management on a virtualized instance, memory access information in the virtualized instance dimension is counted based on the memory access information from a first virtual device. Based on the memory access information in the virtualized instance dimension, it is determined whether to expand or shrink the memory space of the virtualized instance. A virtualized instance corresponds to one or more virtual devices, and memory access information in the virtualized instance dimension can be obtained based on the memory access information of the one or more first virtual devices. Specifically, the identification information of the first virtual device can be used to uniquely identify the corresponding virtualized instance. For example, the identification information of the first virtual 10 device is: Bus Number-Device Number-Function Number (Bus-Device-Function, BDF). According to the BDF of the first virtual 10 device, the client physical address (GPA) corresponding to the virtualization instance can be determined, thereby determining the virtualization instance corresponding to the first virtual 10 device.Example A2: For ease of distinction and description, during a live migration, memory access information generated by the first virtual device 100 modifying memory is referred to as write-type memory access information, while memory access information generated by unmodified memory is referred to as read-type memory access information. During live migration, incremental replication can be used to complete the transfer of corresponding memory states through multiple copy rounds. To this end, each copy round must determine which memory pages have been modified between the completion of the previous copy round and the current time, and migrate any "dirty pages" generated during this period. Specifically, during live migration of a virtualized instance or memory data, write-type memory access information is selected from the memory access information of the first virtual device 100, and live migration is performed based on this write-type memory access information. For example, based on the write-type memory access information, the modified memory pages are determined and migrated. Example A3: The virtualization manager 102 can execute the implementations described in Examples A1 and A2 above. For detailed descriptions, please refer to the previous embodiments and will not be repeated here. Using virtualization technology, a virtual I / O device is simulated on a hardware accelerator. The virtualized instance executes access requests for the virtual I / O device through the virtualization manager. During this process, the hardware accelerator parses the access request into memory address information and access behavior information that the virtual I / O device can understand. This not only controls the virtual I / O device for direct memory access, but also converts the memory address and access behavior information into virtual I / O device-specific memory access information and provides it to the virtualization manager, allowing the virtualization manager to perceive the virtual I / O device's memory access information. Because traditional methods bypass the virtualization manager and perform memory access directly through the I / O MMU, it is impossible to detect which memory the I / O device accesses. Compared to methods that add bits to the I / O MMU page table to record memory access information, the disclosed embodiments do not require modification to the I / O MMU page table, are compatible with various versions of hardware resources, and do not require page table scanning. Accurately obtain the number of memory accesses by each virtual I / O device. The overhead of obtaining memory access information does not increase with increasing memory capacity, resulting in strong scalability. The above embodiment does not limit the manner in which the hardware acceleration device 20 interacts with the virtualization manager 102 on the physical machine 10. Specifically, it does not limit the manner in which access requests are obtained or the manner in which memory access information is provided to the virtualization manager 102. In an optional embodiment XI, the hardware acceleration device 20 and the physical machine 10 may interact via a buffer 10.The 10 buffer can be a memory access log input / output ring (PML IO Ring). The 10 Ring can be a circular queue data structure. Its characteristic is that when new memory access information is inserted at the end of the queue, if the queue is full, the existing information is deleted from the head of the queue. This achieves "recycling" of queue space and avoids wasting queue space. Of course, the 10 buffer can also be a queue. As shown in Figure 2c, the 10 buffer is used as an example. The 10 buffer includes memory access information. For example, the memory access information can be PML1, PML2, PML3, and PML4. Each memory access information PML can occupy 8 bytes. The queue direction is shown in Figure 2c. In the 10 buffer, a quantity threshold can be set to trigger an interrupt. Optionally, the 10 cache area includes 10 buffer A and 10 buffer B, as shown in Figure 2b. The first virtual IO device 201 corresponds to a second IO buffer A, which can store access requests from the virtualization instance to the first virtual IO device. The second virtual IO device 202 corresponds to a first IO buffer B, which can store memory access information of the first virtual IO device. A virtualization instance can correspond to one or more first virtual IO devices, each of which corresponds to one or more IO buffers A. FIG2b illustrates an example in which there are two virtualization instances 103, each corresponding to one virtual IO device, and each corresponding to one IO buffer A, but the present invention is not limited to this example. The second virtual IO device 202 is a virtual IO device emulated by the hardware acceleration device 20 for the virtualization manager 102 and is used to transmit memory access information between the hardware acceleration device 20 and the virtualization manager 102. The hardware acceleration device 20 may provide memory access information of the first virtual IO device to the virtualization manager 102. The virtualization manager 102 may then access the second virtual IO device to obtain the memory access information of the first virtual IO device. The second virtual IO device 202 may be a virtual PCI device or a virtual PCIE device, also known as an input / output page modification log (IO-PML) device. The second virtual IO device 202 may be presented to the physical machine as a general VirtIO device and further presented to the virtualization manager 102. VirtIO is an IO virtualization solution and a general IO device virtualization program.The implementation of the second virtual IO device can be found in the description of the first virtual IO device and will not be repeated here. Optionally, the second virtual IO device can also be implemented using other hardware forms based on a shared memory queue. In Example XI, the process of interaction between the hardware acceleration device 20 and the physical machine 10 through the IO buffer can be as follows: the virtualization manager 102 can write the virtualization instance's access request for its first virtual IO device into the second IO buffer A. The hardware acceleration device 20 reads the access request from the second IO buffer A, parses the access request into memory address information and access behavior information of the first virtual IO device, and controls the first virtual IO device to perform direct memory access based on the memory address information and access behavior information. The hardware acceleration device 20 converts the memory address information and access behavior information into memory access information of the first virtual IO device, and writes the memory access information into the first IO buffer B of the second virtual IO device. The virtualization manager 102 reads the memory access information of the first virtual IO device from the first IO buffer B. In an optional embodiment, an access request includes a command type field, an operand address field, and an operand length field. Parsing the access request into memory address information and access behavior information of the first virtual input / output device may include: parsing the access request according to a descriptor format corresponding to the access request to derive the command type, operand address, and operand length from the command type field, operand address field, and operand length field, respectively; using the command type as read / write behavior information; and using the operand address and operand length as memory address information. In an optional embodiment, memory access information includes an identification field, an address field, a length field, and a read / write field. Converting the memory address information and access behavior information into memory access information of the first virtual I / O device may include: appending the starting address information in the memory address information to the address field, appending the length information in the memory address information to the length field; and appending the identification information of the first virtual I / O device to the identification field and the access behavior information to the read / write field to obtain the memory access information. The starting address information indicated in the memory address information is the guest physical address (GPA). When accessing the memory later, the guest physical address (GPA) can be converted into a host physical address (HPA) through the IOMMU page table.For example, memory access information includes the following fields: an identification field (VF BDF), an address field, a length field (long), and a property field (Property). The identification field includes identification information for the first virtual IO device, the address field stores the GPA address accessed by the virtualization instance, the length field stores the address length accessed by the virtualization instance, and the property field includes a read / write field and several reserved fields for expansion. In an optional embodiment, the internal implementation of the hardware acceleration device 20 is not limited. The internal structure of the hardware acceleration device is provided below. As shown in Figure 2b, the hardware acceleration device 20 includes a conversion device 203, a parsing device 204, and an IO simulation device 205. Optionally, the hardware acceleration device 20 also includes a port 206 interconnected with the internal memory. Port 206 primarily implements direct memory access to the internal memory of the physical machine 10. The conversion device 203, the parsing device 204, the IO simulation device 205, and the port 206 are illustrated with dashed lines, indicating an optional implementation. The implementation of the parsing device 204, the IO simulation device 205, the conversion device 203, and the port 206 is not limited. For example, the parsing device 204, the IO simulation device 205, the conversion device 203, and the port 206 are hardware modules implemented based on a programmable device, including at least one of an FPGA, a CPLD, or an ASIC. In another example, the parsing device 204, the IO simulation device 205, the conversion device 203, and the port 206 are implemented in software, specifically by a processor on the hardware acceleration device 20 executing corresponding program code to implement the parsing device 204, the IO simulation device 205, the conversion device 203, and the port 206. The conversion device 203 may be a memory access log encoding module (PML encoder). The parsing device 204 may be a descriptor decoding module, and the IO simulation device 205 may be an input / output emulation module. oIn this embodiment, the virtualization manager 102 can intercept access requests from the virtualization instance 103 to the first virtual IO device 201 and write the access requests into the second IO buffer A. The parsing device 204 reads the access requests from the second IO buffer A, parses the access requests into memory address information and access behavior information of the first virtual IO device, and provides the information to the conversion device 203 and the IO simulation device 205. The parsing device 204 can periodically scan the second IO buffer A to read the access requests. Alternatively, when the virtualization manager 102 writes the access request into the second IO buffer A, it sends an interrupt signal to the parsing device 204. Upon receiving the interrupt signal, the parsing device 204 reads the access request from the second IO buffer A. It should be noted that the parsing device 204 can also obtain identification information of the first virtual IO device. For example, the parsing device maintains a correspondence between the second IO buffer A and the first virtual IO device. When reading the access request from the second IO buffer A, the identification information of the first virtual IO device to which the IO buffer belongs can be obtained. For another example, the access request may include the identification information of the first virtual IO device. Accordingly, during the parsing of the access request, the parsing device 204 can obtain not only the memory address information and access behavior information of the first virtual IO device, but also the identification information of the first virtual IO device. The IO simulation device 205 controls the first virtual IO device to perform direct memory access based on the memory address information and access behavior information. At the hardware acceleration device 20 level, these first virtual IO devices are files based on the local file system, and these files have corresponding locations in memory (i.e., internal storage). Accesses by the virtualized instance to the first virtual IO device are converted into reads and writes to the corresponding locations in memory at the hardware acceleration device level. The IO simulation device 205 is primarily used to simulate the actual behavior of the first virtual IO device. For example, if the first virtual IO device is a network card, the IO simulation device can simulate the network card receiving external data and writing the received data to the memory location corresponding to the network card. Alternatively, it can simulate the network card sending data externally by reading data from the memory location corresponding to the network card and sending the data. If the first virtual IO device is a keyboard, the IO simulation device can simulate the keyboard receiving input data and writing the input data to the memory location corresponding to the keyboard. If the first virtual IO device is a printer, the IO simulation device can simulate the printer, reading data from the memory location corresponding to the printer and outputting it externally to achieve printing.The conversion device 203 converts the memory address information and access behavior information into memory access information of the first virtual IO device and writes the memory access information into the first IO buffer B for reading by the virtualization manager. The implementation method by which the virtualization manager 102 reads the memory access information of the first virtual IO device 201 from the first IO buffer B is not limited. An example is provided below. In one optional embodiment, the virtualization manager 102 may periodically poll the first buffer to read the memory access information of the first virtual IO device. In another optional embodiment, the virtualization manager 102 implements a driver 102a corresponding to the second virtual IO device. When the memory access information is written into the first IO buffer B, the second virtual IO device 202 sends an interrupt signal to the driver 102a. Upon receiving the interrupt signal, the driver 102a reads the memory access information of the first virtual IO device from the first IO buffer B and records the memory access information of the first virtual IO device. Furthermore, to prevent excessive interrupts from the second virtual IO device 202 when IO traffic is high, interrupt aggregation is used to send interrupt signals to the first IO buffer B. When the memory access information in the first IO buffer B exceeds a set threshold, the second virtual IO device 202 sends an interrupt signal to the driver 102a. Upon receiving the interrupt signal, the driver 102a reads the memory access information of the first virtual IO device from the first IO buffer B and records it. The set threshold is not limited. For example, the set threshold can be 70%, 80%, or 95% of the total amount of memory access information that can be stored in the first IO buffer B, and this is not a limitation. As shown in FIG2c , when the first IO buffer B is implemented as a queue, the set threshold is 70% of the total amount of memory access information that can be stored in the queue, but the present invention is not limited to this. Optionally, the implementation method of the IO simulation device 205 controlling the first virtual IO device to perform direct memory access to the internal memory of the physical machine based on the memory address information and the access behavior information is not limited. The IO simulation device can be implemented in software or hardware. Depending on the implementation of the IO simulation device, the implementation method of controlling the first virtual IO device to perform direct memory access to the internal memory of the physical machine based on the memory address information and the access behavior information may also vary.For example, if the IO simulation device is implemented as software, the IO simulation device can load and run the program code of the first virtual IO device to simulate the first virtual IO device performing direct memory access based on the memory address information and access behavior information. In addition to providing the memory address information and access behavior information to the IO simulation device, the parsing device can also provide the identification information of the first virtual IO device accessed by the virtualized instance to the IO simulation device. The IO simulation device can obtain the program code of the first virtual IO device based on the identification information of the first virtual IO device. For another example, if the IO simulation device is implemented as hardware, the IO simulation device includes multiple hardware execution modules and a control module. Different hardware execution modules correspond to different first virtual IO devices. The control module is configured to control the corresponding hardware execution module to perform direct memory access based on the memory address information and access behavior information. For example, the control module can determine the hardware execution module corresponding to the first virtual IO device based on the identification information of the first virtual IO device, and drive the hardware execution module corresponding to the first virtual IO device to perform direct memory access based on the memory address information and access behavior information. In an optional embodiment, the virtualization manager 102 includes a memory management module 102b and a live migration module 102c. The driver 102a can provide read and write memory access information to the memory management module 102b, for example, by providing access logs to the memory management module 102b. When a memory management trigger event occurs, the memory management module 102b performs memory management for the physical machine or virtualized instance based on the read and write memory access information. The driver 102a can also provide write memory access information to the live migration module 102c, that is, by providing dirty logs to the live migration module 102c. During the live migration of a virtualized instance or memory data, the live migration module 102c performs live migration based on the write memory access information. A detailed description of memory management and live migration can be found in Examples A1 to A3 above and will not be repeated here.The present disclosure also provides a hardware acceleration device, as shown in FIG2b . The hardware acceleration device implements input / output buffers required for interacting with a physical machine. The input / output buffers include a first input / output buffer and a second input / output buffer. The hardware acceleration device reads an access request from a virtualization instance to its first virtual input / output device from the first input / output buffer. The access request is written to the first input / output buffer by a virtualization manager on the physical machine. The hardware acceleration device parses the access request into memory address information and access behavior information of the first virtual input / output device, controls the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information, and converts the memory address information and access behavior information into memory access information of the first virtual input / output device. The memory access information is written to the second input / output buffer of the second virtual input / output device for reading by the virtualization manager. In an optional embodiment, as shown in FIG2b , the hardware acceleration device includes: an interconnected parsing device, an I / O simulation device, and a conversion device. The parsing device reads access requests from a first I / O buffer, parses the access requests into memory address information and access behavior information of a first virtual I / O device, and provides the parsing device and the I / O simulation device with the parsing device. The I / O simulation device controls the first virtual I / O device to perform direct memory access based on the memory address information and access behavior information. The conversion device converts the memory address information and access behavior information into memory access information of the first virtual I / O device, and writes the memory access information into a second I / O buffer for retrieval by the virtualization manager. In an optional embodiment, the virtualization manager implements a driver corresponding to the second virtual I / O device. When the amount of memory access information in the second I / O buffer exceeds a set threshold, the second virtual I / O device sends an interrupt signal to the driver. Upon receiving the interrupt signal, the driver reads the memory access information of the first virtual I / O device from the second I / O buffer and records the memory access information of the first virtual I / O device. For an introduction to the hardware acceleration device and its internal implementation, please refer to the aforementioned embodiment and will not be repeated here. In addition to providing system embodiments, the present disclosure also provides a method for processing memory access information. The following describes the process of the memory access information processing method provided by the present disclosure. Figure 3a is a schematic flow chart of a memory access information processing method provided by an exemplary embodiment of the present disclosure. The method is applied to a hardware acceleration device that implements input and output buffers required for interacting with a physical machine. The input and output buffers include a first input and output buffer and a second input and output buffer. As shown in Figure 3a, the method includes:

[0002] 301a. Reading from a first input / output buffer an access request from a virtualization instance to its first virtual input / output device, where the access request is written into the first input / output buffer by a virtualization manager on a physical machine.

[0003] 302a. Parse the access request into memory address information and access behavior information of the first virtual I / O device, and control the first virtual I / O device to perform direct memory access based on the memory address information and access behavior information. 303a. Convert the memory address information and access behavior information into memory access information for the first virtual I / O device, and write the memory access information into a second I / O buffer of the second virtual I / O device for reading by the virtualization manager. In an optional embodiment, the memory access information includes an identification field, an address field, a length field, and a read / write field. Converting the memory address information and access behavior information into the memory access information of the first virtual I / O device includes: appending the starting address information in the memory address information to the address field, appending the length information in the memory address information to the length field; appending the identification information of the first virtual I / O device to the identification field, and appending the access behavior information to the read / write field, to obtain the memory access information of the first virtual I / O device. In an optional embodiment, an access request includes a command type field, an operand address field, and an operand length field; parsing the access request into memory address information and access behavior information of the first virtual input / output device includes: parsing the access request according to the descriptor format corresponding to the access request to derive the command type, operand address, and operand length from the command type field, operand address field, and operand length field, respectively; using the command type as read / write behavior information; and using the operand address and operand length as memory address information. In an optional embodiment, the method provided by an embodiment of the present disclosure further includes: when the amount of memory access information in the first input / output buffer exceeds a set threshold, issuing an interrupt signal to a virtualization manager, so that the virtualization manager can read the memory access information from the first input / output buffer. Figure 3b is a flow diagram of another memory access information processing method provided by an exemplary embodiment of the present disclosure. This method is applied to a virtualization manager running on a physical machine, where the physical machine interacts with a hardware acceleration device through input / output buffers, which include a first input / output buffer and a second input / output buffer. The method includes:

[0004] 301b. Write an access request of the virtualization instance to its first virtual input / output device into a first input / output buffer, where the first virtual input / output device is a virtual input / output device required by the virtualization instance and implemented on a hardware acceleration device.

[0005] 302b. Read memory access information of the first virtual input / output device from the second input / output buffer. The memory access information is converted by the hardware acceleration device based on the memory address information and access behavior information in the access request. In an optional embodiment, the method provided by the embodiment of the present disclosure further includes: upon the occurrence of a memory management trigger event, performing memory management on the physical machine or the virtualized instance based on the memory access information of the first virtual input / output device; and / or during the hot migration of the virtualized instance or memory data, selecting write-type memory access information from the memory access information of the first virtual input / output device and performing hot migration processing on the write-type memory access information. Figure 3c is a flow diagram of another memory access information processing method provided by the exemplary embodiment of the present disclosure. The method is applied to a hardware acceleration device of a computer device, wherein the hardware acceleration device implements a first virtual 10 device required by the virtualized instance. As shown in Figure 3c, the method includes:

[0006] 301c. Parse the access request of the virtualization instance to the first virtual device into memory address information and access behavior information of the first virtual device to control the first virtual device to perform direct memory access.

[0007] 302c, converting the memory address information and the access behavior information into memory access information of the first virtual device;

[0008] 303c. Provide the memory access information of the first virtual device 10 to the virtualization manager, so that the virtualization manager can obtain the memory access information. FIG4 is a flowchart of another memory access information processing method provided by an exemplary embodiment of the present disclosure. The method is applied to a virtualization manager running on a computer device. As shown in FIG4, the method includes:

[0009] 401. Provide a virtualization instance's access request to a first virtual 10 device to a hardware acceleration device, where the first virtual 10 device is a virtual 10 device required by the virtualization instance and implemented on the hardware acceleration device.

[0010] 402. Obtain memory access information of the first virtual device provided by the hardware acceleration device. The memory access information is converted by the hardware acceleration device based on the memory address information and access behavior information in the access request. The detailed implementation and beneficial effects of each step in the method shown in Figures 3a to 3c and Figure 4 according to the embodiments of this disclosure have been described in detail in the previous embodiments and will not be elaborated upon here. It should be noted that each step of the method provided in the above embodiments can be executed by the same device, or the method can be executed by different devices. For example, steps 301a to 303a can be executed by a device; for another example, steps 301a and 302a can be executed by a device, and step 303a can be executed by device B; and so on. In addition, some processes described in the above embodiments and accompanying figures include multiple operations that appear in a specific order. However, it should be understood that these operations may be executed in a different order than the order in which they appear herein or in parallel. Operation sequence numbers, such as 301a and 302a, are merely used to distinguish between different operations and do not represent any specific execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that terms such as "first" and "second" are used herein to distinguish between different messages, devices, modules, and the like, and do not represent a sequential order or limit the "first" and "second" to different types. FIG. 5 is a schematic structural diagram of a memory access information processing device provided by an exemplary embodiment of the present disclosure. This device corresponds to a hardware acceleration device of a computer device. A first virtual device 10 required for a virtualization instance is implemented on the hardware acceleration device. As shown in FIG. 5 , this device includes a parsing module 51, a conversion module 52, and a providing module 53. A parsing module 51 is configured to parse a virtualization instance's access request to a first virtual device into memory address information and access behavior information of the first virtual device, thereby controlling the first virtual device to perform direct memory access. A conversion module 52 is configured to convert the memory address information and access behavior information into memory access information of the first virtual device. A providing module 53 is configured to provide the memory access information of the first virtual device to a virtualization manager, so that the virtualization manager can obtain the memory access information. Figure 6 illustrates another memory access information processing device provided in an exemplary embodiment of the present disclosure. This device corresponds to a virtualization manager running on a computer device and includes a providing module 61, an obtaining module 62, and a processing module 63.A providing module 61 is configured to provide a hardware acceleration device with an access request from a virtualization instance to a first virtual IOD device. The first virtual IOD device is a virtual IOD device required by the virtualization instance and implemented on the hardware acceleration device. An acquiring module 62 is configured to acquire memory access information of the first virtual IOD device provided by the hardware acceleration device. The memory access information is obtained by the hardware acceleration device based on memory address information and access behavior information in the access request. The detailed implementation and beneficial effects of each step in the apparatus shown in Figures 5 and 6 according to the embodiments of the present disclosure have been described in detail in the previous embodiments and will not be elaborated on here. An embodiment of the present disclosure further provides a memory access information processing apparatus, which corresponds to a hardware acceleration device. The hardware acceleration device implements an input / output buffer required for interacting with a physical machine, wherein the input / output buffer includes a first input / output buffer and a second input / output buffer. The apparatus includes: a reading module configured to read, from the first input / output buffer, an access request of a virtualization instance to its first virtual input / output device, where the access request is written into the first input / output buffer by a virtualization manager on the physical machine; a parsing module configured to parse the access request into memory address information and access behavior information of the first virtual input / output device; a control module configured to control the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; a conversion module configured to convert the memory address information and access behavior information into memory access information of the first virtual input / output device; and a writing module configured to write the memory access information into the second input / output buffer of the second virtual input / output device for reading by the virtualization manager. In an optional embodiment, the memory access information includes: an identification field, an address field, a length field, and a read / write field; the conversion module is specifically configured to: add the starting address information in the memory address information to the address field, add the length information in the memory address information to the length field; and add the identification information of the first virtual input / output device to the identification field, and add the access behavior information to the read / write field, so as to obtain the memory access information of the first virtual input / output device.In an optional embodiment, the access request includes a command type field, an operand address field, and an operand length field; the parsing module is specifically configured to: parse the access request according to a descriptor format corresponding to the access request, to derive the command type, operand address, and operand length from the command type field, operand address field, and operand length field, respectively; use the command type as read / write behavior information; and use the operand address and operand length as memory address information. In an optional embodiment, the apparatus further includes: an issuing module; the issuing module is configured to, when the amount of memory access information in the first input / output buffer exceeds a set threshold, issue an interrupt signal to the virtualization manager, so that the virtualization manager can read the memory access information from the first input / output buffer. An embodiment of the present disclosure also provides a memory access information processing device, corresponding to a virtualization manager running on a physical machine. The physical machine interacts with a hardware acceleration device via input / output buffers, wherein the input / output buffers include a first input / output buffer and a second input / output buffer. The device includes: a write module configured to write an access request from a virtualization instance to its first virtual input / output device into the first input / output buffer. The first virtual input / output device is a virtual input / output device required by the virtualization instance and implemented on the hardware acceleration device; and a read module configured to read memory access information of the first virtual input / output device from the second input / output buffer. The memory access information is converted by the hardware acceleration device based on memory address information and access behavior information in the access request. In an optional embodiment, the device also includes a memory management module and a hot migration module. The memory management module is configured to perform memory management on the physical machine or the virtualized instance based on the memory access information of the first virtual input / output device when a memory management trigger event occurs; and / or the hot migration module is configured to select write-type memory access information from the memory access information of the first virtual input / output device during hot migration of the virtualized instance or memory data, and perform hot migration processing on the write-type memory access information. Figure 7 is a schematic structural diagram of an electronic device provided by an exemplary embodiment of the present disclosure. The electronic device corresponds to a hardware acceleration device of a computer device. The hardware acceleration device implements a first virtual device required for the virtualized instance. As shown in Figure 7, the device includes a memory 74 and a processor 75. Memory 74 is configured to store computer programs and can be configured to store various other data to support operations on the electronic device.Examples of this data include instructions for any application or method configured to operate on the electronic device. The processor 75 is coupled to the memory 74 and configured to execute a computer program in the memory 74. The processor 75 is configured to: parse an access request from the virtualization instance to the first virtual device 10 into memory address information and access behavior information of the first virtual device 10, thereby controlling the first virtual device 10 to perform direct memory access; convert the memory address information and access behavior information into memory access information of the first virtual device 10; and provide the memory access information of the first virtual device 10 to the virtualization manager for the virtualization manager to obtain the memory access information. The detailed implementation and beneficial effects of each step in the device shown in FIG. 7 according to the embodiments of the present disclosure have been described in detail in the previous embodiments and will not be elaborated on here. Furthermore, as shown in FIG. 7 , the electronic device also includes other components, such as a communication component 76, a display 77, a power supply component 78, and an audio component 79. FIG. 7 only schematically illustrates some components and does not imply that the electronic device only includes the components shown in FIG. 7 . In addition, the components within the dashed box in FIG. 7 are optional, not mandatory, components, depending on the product form factor of the electronic device. The electronic device of this embodiment can be implemented as a terminal device such as a desktop computer, laptop computer, smartphone, or IoT device, or as a server-side device such as a conventional server, cloud server, or server array. If the electronic device of this embodiment is implemented as a terminal device such as a desktop computer, laptop computer, or smartphone, it may include the components within the dashed box in FIG. 7 ; if the electronic device of this embodiment is implemented as a server-side device such as a conventional server, cloud server, or server array, it may not include the components within the dashed box in FIG. The disclosed embodiments also provide an electronic device corresponding to a virtualization manager running on a computer device. The implementation structure of this electronic device is the same as or similar to that of the electronic device shown in FIG. The electronic device provided in this embodiment differs from the electronic device shown in FIG. 7 primarily in the functions implemented by the processor executing the computer program stored in the memory. For the electronic device provided in this embodiment, its processor executes a computer program stored in a memory, which can be used to: provide an access request from a virtualization instance to a first virtual device to a hardware acceleration device, where the first virtual device is a virtual device required by the virtualization instance and implemented on the hardware acceleration device; and obtain memory access information of the first virtual device provided by the hardware acceleration device, where the memory access information is converted by the hardware acceleration device based on memory address information and access behavior information in the access request.The detailed implementation and beneficial effects of the electronic device provided by the embodiments of the present disclosure have been described in detail in the preceding embodiments and will not be elaborated upon here. The embodiments of the present disclosure also provide an electronic device corresponding to a hardware acceleration device. The hardware acceleration device implements input and output buffers required for interaction with a physical machine. The input and output buffers include a first input and output buffer and a second input and output buffer. The implementation structure of this electronic device is the same as or similar to the implementation structure of the electronic device shown in FIG7 , and can be implemented with reference to the structure of the electronic device shown in FIG7 . The electronic device provided by this embodiment differs primarily from the electronic device shown in FIG7 in that the functions implemented by the processor executing the computer program stored in the memory are different. For the electronic device provided in this embodiment, its processor executes a computer program stored in a memory, and is configured to: read, from the first input / output buffer, an access request of the virtualization instance to its first virtual input / output device, where the access request is written to the first input / output buffer by the virtualization manager on the physical machine; parse the access request into memory address information and access behavior information of the first virtual input / output device, and control the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; and convert the memory address information and access behavior information into memory access information of the first virtual input / output device, and write the memory access information into a second input / output buffer of the second virtual input / output device for reading by the virtualization manager. In an optional embodiment, the memory access information includes: an identification field, an address field, a length field, and a read / write field; and when the processor converts the memory address information and the access behavior information into the memory access information of the first virtual input / output device, the processor is specifically configured to: add the starting address information in the memory address information to the address field, and add the length information in the memory address information to the length field; and add the identification information of the first virtual input / output device to the identification field, and add the access behavior information to the read / write field, so as to obtain the memory access information of the first virtual input / output device.In an optional embodiment, the access request includes a command type field, an operand address field, and an operand length field. When parsing the access request into memory address information and access behavior information of the first virtual input / output device, the processor is specifically configured to: parse the access request according to a descriptor format corresponding to the access request to derive the command type, operand address, and operand length from the command type field, operand address field, and operand length field, respectively; use the command type as read / write behavior information; and use the operand address and operand length as memory address information. In an optional embodiment, the processor is further configured to: if the amount of memory access information in the first input / output buffer exceeds a set threshold, issue an interrupt signal to the virtualization manager, so that the virtualization manager can read the memory access information from the first input / output buffer. An embodiment of the present disclosure also provides an electronic device corresponding to a virtualization manager running on a physical machine. The physical machine interacts with a hardware acceleration device via input / output buffers, which include a first input / output buffer and a second input / output buffer. The implementation structure of this electronic device is the same as or similar to the implementation structure of the electronic device shown in FIG7 , and can be implemented with reference to the structure of the electronic device shown in FIG7 . The electronic device provided in this embodiment differs primarily in the functions implemented by the processor executing a computer program stored in memory. In the electronic device provided in this embodiment, the processor executes the computer program stored in memory, which is configured to: write an access request from a virtualization instance to its first virtual input / output device, required by the virtualization instance and implemented on the hardware acceleration device, into the first input / output buffer; and read memory access information of the first virtual input / output device from the second input / output buffer. The memory access information is converted by the hardware acceleration device based on the memory address information and access behavior information in the access request. In an optional embodiment, the processor is further configured to: when a memory management triggering event occurs, perform memory management on the physical machine or the virtualization instance according to the memory access information of the first virtual input / output device; and / or during hot migration of the virtualization instance or memory data, select write-type memory access information from the memory access information of the first virtual input / output device, and perform hot migration processing on the write-type memory access information.Accordingly, embodiments of the present disclosure further provide a computer-readable storage medium storing a computer program. When executed, the computer program can implement the steps described in Figures 3a to 3c and the method embodiment shown in Figure 4 , which can be performed by an electronic device. Accordingly, embodiments of the present disclosure further provide a computer program product, including a computer program / instructions. When executed by a processor, the computer program / instructions causes the processor to implement the steps described in Figures 3a to 3c and the method embodiment shown in Figure 4 , which can be performed by an electronic device. The aforementioned memory can be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The aforementioned communication component is configured to facilitate wired or wireless communication between the device containing the communication component and other devices. The device containing the communication component can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G, or other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID), infrared data association (IrDA), ultra-wideband (UWB), Bluetooth (BT), and other technologies. The aforementioned display includes a screen, which can include a liquid crystal display (LCD) and a touch panel (TP).OIf the screen includes a touch panel, it can be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide action. The power supply assembly described above provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located. The audio assembly described above can be configured to output and / or input audio signals. For example, the audio assembly includes a microphone (MIC) that is configured to receive external audio signals when the device in which the audio assembly is located is in an operating mode, such as call mode, recording mode, or voice recognition mode. The received audio signals may be further stored in a memory or transmitted via a communication component. In some embodiments, the audio assembly also includes a speaker for outputting audio signals. Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) containing computer-usable program code. The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present disclosure. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing device, produce means for implementing the functions specified in one or more processes in the flowcharts and / or one or more blocks in the block diagrams. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing the computer or other programmable device to execute a series of operational steps to produce a computer-implemented process. The instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flow charts and / or one or more blocks in a block diagram. In a typical configuration, a computing device includes one or more processors (Central Processing Units, CPUs), input / output interfaces, network interfaces, and memory. Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. oMemory is an example of computer-readable media. Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can implement information storage using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmitting medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves. It should also be noted that the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, product, or apparatus comprising a list of elements may include not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. Without further limitation, the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, product, or apparatus comprising the elements. The foregoing are merely examples of the present disclosure and are not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, improvements, and the like made within the spirit and principles of the present disclosure are intended to be encompassed by the claims of the present disclosure.

Claims

Claims 1. A computer device, comprising: A physical machine and a hardware acceleration device; the physical machine and the hardware acceleration device interact with each other via input / output buffers, the input / output buffers including a first input / output buffer and a second input / output buffer; a virtualization manager on the physical machine writes an access request of a virtualization instance to its first virtual input / output device into the first input / output buffer, and reads memory access information of the first virtual input / output device from the second input / output buffer; the hardware acceleration device reads the access request from the first input / output buffer, parses the access request into memory address information and access behavior information of the first virtual input / output device, and controls the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; The memory address information and the access behavior information are converted into memory access information of the first virtual input / output device, and the memory access information is written into a second input / output buffer of the second virtual input / output device for reading by the virtualization manager.

2. The device according to claim 1, wherein: The hardware acceleration device includes: an interconnected parsing device, an input / output simulation device, and a conversion device; the parsing device reads the access request from the first input / output buffer, parses the access request into memory address information and access behavior information of the first virtual input / output device, and provides the information to the conversion device and the input / output simulation device; the input / output simulation device controls the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; the conversion device converts the memory address information and access behavior information into memory access information of the first virtual input / output device, and writes the memory access information into the second input / output buffer for reading by the virtualization manager.

3. The device according to claim 2, wherein: The input / output simulation device is specifically configured to: load and run the program code of the first virtual input / output device to simulate the first virtual input / output device performing direct memory access according to the memory address information and the access behavior information; or drive a hardware execution module corresponding to the first virtual input / output device to perform direct memory access according to the memory address information and the access behavior information.

4. The device according to claim 1, wherein: The virtualization manager implements a driver corresponding to the second virtual input / output device; when the memory access information in the second input / output buffer exceeds a set number threshold, the second virtual input / output device sends an interrupt signal to the driver; when the driver receives the interrupt signal, it reads the first virtual input / output device from the second input / output buffer. The memory access information of the virtual input / output device is recorded, and the memory access information of the first virtual input / output device is recorded.

5. The device according to any one of claims 1 to 4, wherein: The virtualization manager is further configured to: perform memory management on the physical machine or the virtualized instance according to the memory access information of the first virtual input / output device when a memory management triggering event occurs; and / or select write-type memory access information from the memory access information of the first virtual input / output device during hot migration of the virtualized instance or memory data, and perform hot migration processing on the write-type memory access information.

6. A hardware acceleration device, comprising: an input / output buffer required for interacting with a physical machine, the input / output buffer comprising a first input / output buffer and a second input / output buffer; the hardware acceleration device reading an access request from a virtualization instance to its first virtual input / output device from the first input / output buffer, the access request being written into the first input / output buffer by a virtualization manager on the physical machine; parsing the access request into memory address information and access behavior information of the first virtual input / output device; controlling the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; and converting the memory address information and access behavior information into memory access information of the first virtual input / output device, and writing the memory access information into the second input / output buffer of the second virtual input / output device for reading by the virtualization manager.

7. The device according to claim 6, wherein: The hardware acceleration device includes: an interconnected parsing device, an input / output simulation device, and a conversion device; the parsing device reads the access request from the first input / output buffer, parses the access request into memory address information and access behavior information of the first virtual input / output device, and provides the information to the conversion device and the input / output simulation device; the input / output simulation device controls the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; the conversion device converts the memory address information and access behavior information into memory access information of the first virtual input / output device, and writes the memory access information into the second input / output buffer for reading by the virtualization manager.

8. The device according to claim 6 or 7, wherein: A driver corresponding to the second virtual input / output device is implemented in the virtualization manager; when the amount of memory access information in the second input / output buffer exceeds a set threshold, the second virtual input / output device sends an interrupt signal to the driver; when the driver receives the interrupt signal, reads the memory access information of the first virtual input / output device from the second input / output buffer and records the memory access information of the first virtual input / output device.

9. A memory access information processing method, applied to a hardware acceleration device, wherein the hardware acceleration device implements an input / output buffer required for interacting with a physical machine, the input / output buffer including a first input / output buffer and a second input / output buffer. Input and output buffer; The method includes: reading, from the first input / output buffer, an access request from the virtualization instance to its first virtual input / output device, the access request being written into the first input / output buffer by the virtualization manager on the physical machine; parsing the access request into memory address information and access behavior information of the first virtual input / output device, and controlling the first virtual input / output device to perform direct memory access based on the memory address information and access behavior information; and converting the memory address information and the access behavior information into memory access information of the first virtual input / output device, and writing the memory access information into a second input / output buffer of the second virtual input / output device for reading by the virtualization manager.

10. The method according to claim 9, wherein: The memory access information includes: an identification field, an address field, a length field, and a read / write field. Converting the memory address information and the access behavior information into the memory access information of the first virtual input / output device includes: adding the starting address information in the memory address information to the address field, and adding the length information in the memory address information to the length field; and adding the identification information of the first virtual input / output device to the identification field, and adding the access behavior information to the read / write field, so as to obtain the memory access information of the first virtual input / output device.

11. The method according to claim 9, wherein: The access request includes a command type field, an operand address field, and an operand length field; Parsing the access request into memory address information and access behavior information of the first virtual input / output device includes: parsing the access request according to a descriptor format corresponding to the access request to derive a command type, an operand address, and an operand length from the command type field, the operand address field, and the operand length field, respectively; using the command type as read / write behavior information; and using the operand address and operand length as memory address information.

12. The method according to any one of claims 9 to 11, wherein: Also includes: When the memory access information in the first input / output buffer exceeds a set quantity threshold, an interrupt signal is sent to the virtualization manager so that the virtualization manager reads the memory access information from the first input / output buffer.

13. A method for processing memory access information, applied to a virtualization manager running on a physical machine, wherein the physical machine interacts with a hardware acceleration device via an input / output buffer, wherein the input / output buffer includes a first input / output buffer and a second input / output buffer; the method comprising: Writing an access request of the virtualization instance to its first virtual input / output device into the first input / output buffer, where the first virtual input / output device is a virtual input / output device required by the virtualization instance and implemented on the hardware acceleration device; Memory access information of the first virtual input / output device is read from the second input / output buffer, where the memory access information is converted by the hardware acceleration device according to memory address information and access behavior information in the access request.

14. The method according to claim 13, wherein: Also includes: When a memory management triggering event occurs, performing memory management on the physical machine or the virtualized instance according to the memory access information of the first virtual input / output device; And / or during the hot migration of the virtualized instance or memory data, selecting write-type memory access information from the memory access information of the first virtual input / output device, and performing hot migration processing on the write-type memory access information.

15. A computer device comprising: Physical machines and hardware acceleration devices; The physical machine runs a virtualization manager to create and manage virtualization instances; The hardware acceleration device implements a first virtual input / output device required by the virtualization instance, parses an access request from the virtualization instance to the first virtual input / output device into memory address information and access behavior information of the first virtual input / output device, and controls the first virtual input / output device to perform direct memory access according to the memory address information and access behavior information; The hardware acceleration device converts the memory address information and the access behavior information into memory access information of the first virtual input / output device, and provides the memory access information of the first virtual input / output device to the virtualization manager.

16. The device according to claim 15, wherein: The hardware acceleration device includes a conversion device and implements a second virtual input / output device, wherein the second virtual input / output device includes: a first input / output buffer; the conversion device is configured to convert the memory address information and access behavior information into memory access information of the first virtual input / output device, and write the memory access information of the first virtual input / output device into the first input / output buffer, so that the virtualization manager can read the memory access information of the first virtual input / output device from the first input / output buffer.

17. A memory access information processing method, applied to a hardware acceleration device of a computer device, wherein a first virtual input / output device required for a virtualization instance is implemented on the hardware acceleration device, the method comprising: parsing an access request of the virtualization instance to the first virtual input / output device into memory address information and access behavior information of the first virtual input / output device, so as to control the first virtual input / output device to perform direct memory access; and converting the memory address information and the access behavior information into memory access information of the first virtual input and output device; The memory access information of the first virtual input / output device is provided to the virtualization manager, so that the virtualization manager obtains the memory access information.

18. A memory access information processing method, applied to a virtualization manager running on a computer device, the method comprising: Providing an access request from the virtualization instance to a first virtual input / output device to a hardware acceleration device, where the first virtual input / output device is a virtual input / output device required by the virtualization instance and implemented on the hardware acceleration device; and obtaining memory access information of the first virtual input / output device provided by the hardware acceleration device, where the memory access information is converted by the hardware acceleration device based on memory address information and access behavior information in the access request.

19. An electronic device, comprising: memory and processor; The memory is used to store a computer program; the processor is coupled to the memory and is used to execute the computer program to implement the steps in the method of any one of claims 9-12, claims 13-14, claim 17 and claim 18.

20. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 9 to 12, claims 13 to 14, claim 17, and claim 18.

21. A computer program product, comprising a computer program / instructions, which, when executed by a processor, causes the processor to implement the steps of the method of any one of claims 9 to 12, claims 13 to 14, claim 17, and claim 18.

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