Method for using semiconductor device, and semiconductor device

Abstract

[Problem] To provide a method for using a semiconductor device and a semiconductor device that make it possible to significantly ease area restriction of distal-end packaging and significantly improve computation processing performance. [Solution] An electronic substrate including a semiconductor device that is designed to operate while satisfying the condition that the design junction temperature Tjd is 1-40°C is waterproofed. The waterproofed electronic substrate is immersed in water at a temperature Tw lower than the design junction temperature Tjd, and the semiconductor device is operated at an operation junction temperature Tjo lower than the design junction temperature Tjd. The semiconductor device comprises: a package substrate; one or more logic dies that are provided on one surface of the package substrate and are electrically connected to the package substrate; a plurality of memory dies that are provided on one surface of the package substrate and are electrically connected to the package substrate; one or more connection structures that connect the logic die and each of the plurality of memory dies; and a package material that surrounds the logic die, the plurality of memory dies, and the connection structure.

Description

Method of using semiconductor device and semiconductor device

[0001] The present invention relates to a method for using a semiconductor device and the semiconductor device itself, and in particular to a semiconductor device for artificial intelligence (AI) or high performance computing (HPC), more specifically to a method for using a semiconductor device that requires high performance, stable operation, or low power consumption operation and generates a large amount of heat, such as a supercomputer or data center, an AI processing system, a quantum computing system, a cryptographic processing system, or a blockchain processing system.

[0002] The widespread use of large-scale text processing, image processing, and voice processing has led to a rapid increase in demand for high-performance semiconductor devices as computing resources. Examples of such semiconductor devices include high-performance graphics processing units (GPUs) or general-purpose graphics processing units (GPGPUs), which process large-scale language models in generative AI, also known as conversational AI. A semiconductor device known as an arithmetic processing unit (APU), which integrates a GPU and a central processing unit (CPU), is also considered to have performance equivalent to that of a high-performance GPU.

[0003] A high-performance GPU includes a logic die and multiple memory dies. A die is a semiconductor with a desired function that is cut to a desired size from a silicon wafer after wafer processing. It is also sometimes called a chip or chiplet. The logic die is manufactured using cutting-edge processes, and tens of billions or more transistors can be integrated into a single relatively large semiconductor die. On the other hand, the memory die is a high-capacity, ultra-high-bandwidth semiconductor memory die directly connected adjacent to the logic die. Currently, high-performance GPUs suitable for generative AI applications or general-purpose GPUs are manufactured and used with HBMs (High Bandwidth Memory), which are made up of 8 to 16 stacked layers of multiple DRAM (Dynamic Random Access Memory) dies.

[0004] For high-performance semiconductor devices, including high-performance GPUs, various technologies have been developed to integrate and encapsulate multiple dies with different functions in the same semiconductor package as if they were a single die. Among these, two-dimensional packaging has a structure in which dies are connected to each other via a silicon interposer or organic interposer on a package substrate, or a silicon bridge embedded in the package substrate. For example, this technology has already been put into practical use by the semiconductor manufacturer TSMC under the name CoWoS (Chip on Wafer on Substrate) (see, for example, Non-Patent Document 1).

[0005] Nikkei Electronics, June 2023 issue, "Challenges include heat management and cost reduction, as development competition for heterogeneous chip integration accelerates," pp. 60-69 (May 20, 2023), Nikkei BP

[0006] The silicon interposer, organic interposer, or silicon bridge described above is an integration technology whose primary purpose is to prevent irreversible disconnections caused by differences in the linear (thermal) expansion coefficients between the silicon die and the organic packaging substrate, which can occur when a semiconductor device is operated at a power consumption of several hundred watts or significantly more. This integration technology requires complex and expensive advanced packaging technology. However, the current yield of advanced packaging processes is not sufficiently high, and the production of advanced packaging equipment, which requires high mounting precision, is challenging. This, combined with a significant shortage of advanced packaging processes relative to demand, has significantly delayed the production of semiconductor devices. This has resulted in significant delivery delays for high-performance semiconductor devices required for AI applications, for example, or in a market shortage where only one-tenth of the actual demand can be supplied.

[0007] Furthermore, the cost of advanced packaging technology is very high due to the high mounting accuracy required for advanced packaging equipment and the high defect rate associated with complex packaging. Furthermore, the low process yield of advanced packaging technology wastes valuable advanced semiconductor resources. This leads to a decrease in the supply of high-performance semiconductor devices and an increase in manufacturing costs.

[0008] Furthermore, existing two-dimensional packaging integration technologies do not fully address the difference in linear expansion coefficients between silicon and other materials. In particular, the difference in linear expansion coefficients between materials due to high heat becomes significant at the periphery of packaged components, preventing semiconductor devices from functioning in advanced packages exceeding a certain area. In other words, existing two-dimensional packaging integration technologies are subject to the area constraints of advanced packaging, which prevent the die mounting area from being further enlarged. This area constraint significantly limits the flexibility of semiconductor device configuration, making it impossible to freely integrate dies with different functions to build a large number of higher-performance semiconductor devices.

[0009] Furthermore, as mentioned above, in high-performance semiconductor devices such as high-performance GPUs required for generative AI, it is conceivable to further improve performance by increasing the number of high-performance logic dies and large-capacity, ultra-wideband high-performance memory dies and arranging them horizontally, or by increasing the number of layers when stacking either or both of them vertically. However, due to the large total amount of heat generated within the package of a high-performance semiconductor device and the area constraints of advanced packaging, the realization of this is very limited.

[0010] Furthermore, as described above, even if a complex and large semiconductor device is constructed using advanced packaging such as a silicon interposer by applying a technology that absorbs the difference in the thermal expansion coefficient between materials, the area constraints of the advanced packaging are unavoidable. Therefore, there is a demand for a new method or a new configuration that does not require consideration of the difference in the linear expansion coefficient between silicon and other materials due to high temperatures.

[0011] Therefore, one object of the present invention is to provide a method for using a semiconductor device and a semiconductor device that solves the above-mentioned problems of the conventional technology, eliminates or significantly alleviates the area constraints of advanced packaging, and significantly improves computing performance.

[0012] Another object of the present invention is to provide a method for using a semiconductor device, and a semiconductor device, which can ignore the difference in the linear expansion coefficient due to high heat between silicon and other materials, even if the die mounting area is expanded beyond the area constraints of advanced packaging.

[0013] In order to solve the above-mentioned problems, according to one aspect of the present invention, there is provided a method of using a semiconductor device, which comprises waterproofing an electronic substrate including at least one semiconductor device, the semiconductor device being designed to operate at a design junction temperature Tjd of 1° C. or higher and 40° C. or lower, and immersing the waterproofed electronic substrate in water at a temperature Tw lower than the design junction temperature Tjd to operate the semiconductor device at an operating junction temperature Tjo lower than the design junction temperature Tjd. The at least one semiconductor device may include a package substrate, one or more logic dies arranged on one side of the package substrate and electrically connected to the package substrate, a plurality of memory dies arranged on one side of the package substrate and electrically connected to the package substrate, one or more connection structures connecting the logic die and each of the plurality of memory dies, and a packaging material surrounding the logic die, the plurality of memory dies, and the connection structures.

[0014] In a preferred embodiment of the above method, the semiconductor device may be designed to operate with a design junction temperature Tjd satisfying the condition of 20° C. or higher and 30° C. or lower.

[0015] In a preferred embodiment of the above method, the waterproofing treatment may include covering the electronic board including the semiconductor device with a waterproof coating or a waterproof bag.

[0016] Furthermore, in a preferred embodiment of the above method, a cold plate may be thermally connected to the surfaces of the logic die and the plurality of memory dies, and the waterproofed electronic substrate may be immersed in a cooling bath through which water flows to cool the entire electronic substrate, and a coolant may be flowed through channels in the cold plate to locally cool the logic die and the plurality of memory dies.

[0017] In a preferred embodiment of the above method, the coolant flowing through the flow passages in the cold plate is water.

[0018] Furthermore, in a preferred embodiment of the above method, a heat sink may be thermally connected to the surfaces of the logic die and the multiple memory dies so that the surface of the heat sink is located outside the waterproof coating or waterproof bag, and the waterproofed electronic substrate may be immersed in a cooling bath through which water flows to cool the entire electronic substrate, and the logic die and the multiple memory dies may be locally cooled by flowing water through the channels on the surface of the heat sink.

[0019] Furthermore, in a preferred embodiment of the above method, the semiconductor device may be a logic semiconductor including at least one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a GPGPU (General Purpose Graphics Processing Unit), an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit), and the memory die may be an SRAM (Static Random Access Memory) die and / or an HBM (High Bandwidth Memory) formed by vertically stacking multiple DRAM (Dynamic Random Access Memory) dies.

[0020] Furthermore, in a preferred embodiment of the above method, the SRAM die may be a large discrete SRAM die or a High Bandwidth Static Memory (HBSM) made up of multiple large discrete SRAM dies stacked vertically.

[0021] In a preferred embodiment of the above method, the logic die may be formed by arranging a plurality of logic dies horizontally or stacking them vertically.

[0022] Furthermore, in a preferred embodiment of the above method, the connection structure may further include a connection structure that connects the plurality of logic dies to each other.

[0023] Additionally, according to another aspect of the present invention, there is provided a semiconductor device including a package substrate, one or more logic dies arranged on one side of the package substrate and electrically connected to the package substrate, a plurality of memory dies arranged on one side of the package substrate and electrically connected to the package substrate, at least one connection structure connecting the logic die and each of the plurality of memory dies, and a packaging material surrounding the logic die, the plurality of memory dies, and the connection structure, wherein the semiconductor device is designed to operate at a design junction temperature Tjd of 1°C or higher and 40°C or lower, and is immersed in water at a temperature Tw lower than the design junction temperature Tjd in a waterproofed state to operate the semiconductor device at an operating junction temperature Tjo lower than the design junction temperature Tjd.

[0024] In a preferred embodiment of the semiconductor device, the semiconductor device may be designed to operate while satisfying the condition that the design junction temperature Tjd is 20° C. or higher and 30° C. or lower.

[0025] In a preferred embodiment of the semiconductor device, the waterproofing treatment may include covering the semiconductor device with a waterproof film or a waterproof bag.

[0026] Furthermore, in a preferred embodiment of the semiconductor device described above, a cold plate may be thermally connected to surfaces of the logic die and the plurality of memory dies, and a coolant may flow through a flow path in the cold plate, thereby locally cooling the logic die and the plurality of memory dies.

[0027] In a preferred embodiment of the semiconductor device, the coolant flowing through the flow path in the cold plate may be water.

[0028] Furthermore, in a preferred embodiment of the semiconductor device described above, a heat sink may be thermally connected to the surfaces of the logic die and the plurality of memory dies so that the surface of the heat sink is located outside the waterproof coating or waterproof bag, and the waterproofed semiconductor device may be immersed in a cooling tank through which water flows, and the logic die and the plurality of memory dies may be locally cooled by the water flowing through the channels on the surface of the heat sink.

[0029] In addition, in a preferred embodiment of the semiconductor device, the semiconductor device may be a logic semiconductor including at least one of a CPU, a GPU, a GPGPU, an FPGA, or an ASIC, and the memory die may be an SRAM die and / or an HBM formed by vertically stacking multiple DRAM dies.

[0030] Furthermore, in a preferred embodiment of the semiconductor device, the SRAM die may be a large scale discrete SRAM die or an HBSM formed by vertically stacking a plurality of large scale discrete SRAM dies.

[0031] In a preferred embodiment of the semiconductor device, the logic die may be formed by arranging a plurality of logic dies in the horizontal direction or stacking a plurality of logic dies in the vertical direction.

[0032] Furthermore, in a preferred embodiment of the semiconductor device described above, the connection structure may further include a connection structure that connects the plurality of logic dies to each other.

[0033] In addition, in a preferred embodiment of the semiconductor device, the logic die may perform calculation processing in the generative AI processing, and the multiple memory dies may function as memory in the inference processing and / or training processing.

[0034] According to the present invention, as will be described in detail later, in a high-performance semiconductor device, it is possible to eliminate or significantly alleviate the area constraints of advanced packaging, thereby significantly improving the processing performance. Furthermore, even if the die mounting area is expanded beyond the area constraints of advanced packaging, the difference in the linear expansion coefficients due to high temperatures between silicon and other materials can be ignored.

[0035] The above and other objects and advantages of the present invention will be more clearly understood through the following description of the embodiments, although the embodiments described below are merely examples and the present invention is not limited thereto.

[0036] 1 is a diagram for explaining a temperature index; FIG. 1 is a partial cross-sectional view of an example of a waterproofed electronic device; FIG. 2 is a diagram for explaining the overall configuration of an example of a cooling system that provides a suitable usage environment for a semiconductor device; FIG. 3 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 4 is a diagram for explaining an example of packaging of a semiconductor device; FIG. 5 is a diagram for explaining another example of packaging of a semiconductor device; FIG. 6 is a diagram for explaining another example of packaging of a semiconductor device; FIG. 7 is a diagram for explaining another example of packaging of a semiconductor device; FIG. 8 is a diagram for explaining another example of packaging of a semiconductor device; FIG. 9 is a diagram for explaining another example of packaging of a semiconductor device; FIG. 10 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 11 is a diagram for explaining another example of packaging of a semiconductor device; FIG. 12 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 13 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 14 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 15 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 16 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 17 is a diagram for explaining relaxation of area constraints on packaging in a semiconductor device; FIG. 1 is a partial cross-sectional view of yet another example of a waterproofed electronic device. FIG. 2 is a partial cross-sectional view of yet another example of a waterproofed electronic device. FIG. 3 is a diagram showing the configuration of a main part of yet another example of a cooling system that provides a suitable environment for using a semiconductor device. FIG. 4 is a partial cross-sectional view of yet another example of a waterproofed electronic device. FIG. 5 is a partial cross-sectional view of yet another example of a waterproofed electronic device. FIG. 6 is a diagram showing the configuration of a main part of yet another example of a cooling system that provides a suitable environment for using a semiconductor device. FIG. 7 is a diagram showing the configuration of a main part of yet another example of a cooling system that provides a suitable environment for using a semiconductor device. FIG. 8 is a partial cross-sectional view of yet another example of a waterproofed electronic device.

[0037] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for using a semiconductor device and a number of preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the drawings.

[0038] [Basic Concepts and Impact on Existing Semiconductor Device Design]

[0039] First, with reference to FIGS. 1 to 3, we will explain basic concepts regarding the use and configuration of a semiconductor device. FIG. 1 is a diagram illustrating temperature indices in the use of a semiconductor device. For a semiconductor device, a design junction temperature (Tjd) and an operating junction temperature (Tjo) are specified. The design junction temperature (Tjd) refers to the upper limit of the operating temperature of the semiconductor device, determined when designing the semiconductor device packaging. As an example, a temperature referred to as the maximum operating temperature (Tjmax) of a semiconductor device such as a high-performance GPU may be considered equivalent to the design junction temperature (Tjd). Next, the operating junction temperature (Tjo) refers to the temperature actually measured inside or on the surface of a waterproofed electronic device or a waterproofed semiconductor device under actual operating conditions, as described below (FIG. 2). The operating junction temperature (Tjo) of the semiconductor device may be measured using an application similar to an application for monitoring the operating temperature of a semiconductor device provided for existing high-performance semiconductor devices.

[0040] In an embodiment, the design junction temperature Tj0 and the operating junction temperature Tj0 of the semiconductor device preferably satisfy the conditions of 1° C.≦Tjd, Tj0≦40° C., and Tj0<Tjd. Here, Tjd and Tj0 are set to 1° C. or higher because, as will be described later, water is primarily used as the coolant in the cooling system, and therefore temperatures higher than the freezing point of water are desirable. Furthermore, Tjd and Tj0 are set to 40° C. or lower to avoid the fact that temperatures above 40° C. substantially change various parameters related to packaging area constraints, resulting in stricter constraints on free die configuration. The semiconductor device may be designed to operate such that the design junction temperature Tjd satisfies the condition of 20° C. or higher and 30° C. or lower. That is, the semiconductor device may be designed to operate, particularly, within a room temperature range of 25° C.±5° C.

[0041] In the embodiment, a temperature Tw of the coolant, i.e., the cooling water, for cooling the waterproofed semiconductor device is specified. In the embodiment, the temperature Tw of the cooling water may be the temperature of the water in the water immersion tank. As shown in FIG. 3 , for example, the water immersion tank water temperature refers to the temperature of the coolant (cooling water) when the waterproofed electronic device 100 is used by immersing it in the coolant (cooling water) 4 in the cooling tank (water immersion tank) 3. As shown in FIG. 3 , the water immersion tank water temperature may be the water temperature Twbi near the cooling water inlet at the bottom of the cooling tank 3. Alternatively, the water immersion tank water temperature may be the water temperature Twbo near the cooling water outlet at the top of the cooling tank 3, or may be the water temperature at any location within the cooling tank 3.

[0042] In this embodiment, the temperature Tw of the cooling water should satisfy the following conditions: 1°C≦Tw≦40°C, Tw<Tjo-ΔTb, and 0 degrees<ΔTb. Here, ΔTb represents the increase in the temperature of the water in the immersion tank based on some or all of the total heat generated by all electronic devices immersed in the water immersion tank. Ideally, ΔTb should be minimized by optimizing the flow rate, flow rate, and other conditions of the cooling water circulating in the water immersion tank.

[0043] 2 and 3, a cold plate 20 may be thermally connected to the surface of a waterproof semiconductor device 33, and the semiconductor device may be locally cooled by a coolant flowing through a flow path in the cold plate 20. In this case, the cold plate inflow water temperature Twci may be defined as an additional temperature indicator.

[0044] In an embodiment, the cold plate inflow water temperature Twc i preferably satisfies the following conditions: 1° C.≦Twc i ≦40° C., Twc i < Tjo − ΔTc, and 0 degrees < ΔTc. Here, ΔTc represents the increase in the cold plate inflow water temperature based on the amount of heat generated by each semiconductor device immersed in the water immersion bath and removed by the cooling water flowing through the cold plate. Ideally, ΔTc can be minimized (so that the cold plate inflow water temperature Twc approaches the cold plate inflow water temperature Twc i ) by optimizing the number of fins, fin width, and fin length (or the number of grooves, slits, or grids, groove width, slit width, or grid width, and groove length, slit length, or grid depth) that define the flow paths (microchannels) in the cold plate, as well as the flow rate and flow rate of the cooling water flowing through the flow paths in the cold plate, while taking pressure loss into consideration.

[0045] In an embodiment, by designing and using a semiconductor device such that the design junction temperature Tjo and the operating junction temperature Tjo of the semiconductor device, and the temperature Tw of the cooling water when a waterproofed electronic device or a waterproofed semiconductor device is immersed in water for cooling, satisfy predetermined conditions, the area constraints of advanced packaging that are unavoidable with existing technology can be eliminated or significantly alleviated. This is because the waterproofing treatment described below achieves both a watertight and electrically insulating structure for the semiconductor device, and the cooling water (usually running water) in the water immersion tank provides enhanced cooling functionality, thereby making it possible to ignore the difference in the linear expansion coefficients of silicon and other materials due to high temperatures. Figure 4 illustrates this relaxation of the packaging area constraints. In an existing semiconductor device 1001 such as a high-performance GPU, the die mounting area (shown in gray) cannot be expanded due to the difference in the linear expansion coefficients caused by high temperatures between the package substrate 1011, the connecting structure 1016 (e.g., a silicon interposer or organic interposer) mounted thereon, the logic die 112, the memory die 114, the IO die 115, and the surrounding packaging material (not shown). However, in an embodiment, if the difference in linear expansion coefficients caused by high temperatures can be ignored, the expanded die mounting area (shown in gray) can be secured by mounting the expanded connecting structure 116 on the expanded package substrate 111. As described below, this expanded die mounting area can accommodate multiple large-capacity discrete SRAM memory dies 113.

[0046] Furthermore, if the difference in linear expansion coefficient due to high temperatures can be ignored, it becomes possible to expand the die mounting area beyond the area constraints of advanced packaging, thereby expanding the package size of the semiconductor device and increasing the heat dissipation area, which leads to further improvement of the cooling function of the semiconductor device by the cooling water in the water immersion tank.

[0047] Furthermore, by expanding the die mounting area beyond the area constraints of advanced packaging, it becomes possible to mount large-capacity, large-scale discrete SRAM memory dies, which were difficult to mount with existing technology due to area constraints, without being subject to area constraints. For example, as described below, multiple large-capacity, large-scale discrete SRAM memory dies of 3 GB to 8 GB or more can be mounted in various arrangements. This means that, compared to conventional technology using an HBM consisting of 8 to 16 layers of stacked DRAM dies, SRAMs with significantly faster access times than DRAMs can be integrated to form a single huge, large-capacity, large-scale discrete SRAM memory die, and multiple discrete SRAM memory dies can be arranged horizontally or vertically for use, thereby significantly improving the computational processing performance of a single semiconductor device. This also makes it possible to have a logic die in a single semiconductor device perform computational processing in generative AI processing, and have multiple memory dies function as memories for inference processing and / or training processing in generative AI processing.

[0048] [Semiconductor Device Packaging]

[0049] Several examples of packaging for semiconductor devices will be described with reference to Figures 5 to 17. Note that like reference numerals are used to designate like parts of semiconductor devices.

[0050] 5 shows an example of packaging of a semiconductor device. The semiconductor device 101 includes a package substrate 111, a logic die 112 that performs arithmetic processing functions for a CPU or GPU and is disposed on one side of the package substrate 111 and electrically connected to the package substrate 111, a plurality of discrete SRAM dies 113 and HBMs (DRAM) 114 that are disposed on one side of the package substrate 111 and electrically connected to the package substrate 111, an interposer 116 that connects the logic die 112 to each of the discrete SRAM dies 113 and HBM 114, and a packaging material (not shown) that surrounds the logic die 112, the discrete SRAM dies 113, the HBM 114, and the interposer 116. The discrete SRAM dies 113 and the HBM 114 correspond to a plurality of memory dies, and the interposer 116 corresponds to a connection structure. The semiconductor device is designed to operate at a design junction temperature Tjd of 1° C. or higher and 40° C. or lower. As will be described later, an electronic device (electronic substrate) including the semiconductor device 101 is waterproofed. The waterproofed electronic device (electronic substrate) is immersed in water at a temperature Tw lower than the design junction temperature Tjd, and the semiconductor device 101 operates at an operating junction temperature Tjo lower than the design junction temperature Tjd.

[0051] As already explained, large-scale discrete SRAM dies with capacities of 3 GB to 8 GB or more can be used in packaging the semiconductor device 101. In this example, for example, two 8 GB discrete SRAM dies 113 are used, providing a memory capacity of 16 GB. This enables inference processing based on a large-scale language model, for example, with 7 billion parameters, to be performed in a single semiconductor device package. Furthermore, since the logic die and the discrete SRAM die can be directly connected, extremely high-speed inference processing can be achieved without bottlenecks such as communication delays between the two. The HBM 114 may be, for example, a 16 GB HBM3. In this example, four 16 GB HBMs (HBM3) 114 are used to provide a high-bandwidth memory capacity of 62 GB. The IO die 115 is a die that performs functions such as memory controller, input / output, and security, and is similar to the IO die in the prior art.

[0052] 6 shows another example of packaging for a semiconductor device. The semiconductor device 102 uses two 32 GB HBMs (HBM4) 117, instead of the four HBMs (HBM3) 114 in the semiconductor device 101 shown in FIG. 5, to ensure a wideband memory capacity of 64 GB.

[0053] 7 shows yet another example of packaging for a semiconductor device. The semiconductor device 103 uses one 8 GB discrete SRAM die 113 instead of the two HBMs (HBM3) 114 in the semiconductor device 101 shown in FIG. 5, ensuring a memory capacity of 24 GB SRAM. Furthermore, two 16 GB HBMs (HBM3) 114 are used, ensuring a wideband memory capacity of 32 GB.

[0054] 8 shows yet another example of packaging for a semiconductor device. The semiconductor device 104 uses one 32 GB HBM (HBM4) 117 instead of the two HBMs (HBM3) 114 in the semiconductor device 101 shown in FIG. 7, thereby ensuring a wideband memory capacity of 32 GB.

[0055] 9 shows yet another example of semiconductor device packaging. Semiconductor device 105 uses one 8 GB discrete SRAM die 113 instead of the single HBM (HBM4) 117 in semiconductor device 101 shown in FIG. 7. A total of four 8 GB discrete SRAM dies are used to ensure a large SRAM memory capacity of 32 GB. This realizes packaging of a semiconductor device that does not include an HBM and ensures memory capacity using all discrete SRAM dies.

[0056] 10 shows yet another example of semiconductor device packaging. The semiconductor device 106 uses two integrated sets, each consisting of one logic die 112, three discrete SRAM dies 113, and one IO die 115. A large-scale SRAM memory capacity of 24 GB per set is secured, for a total of 48 GB. This realizes packaging of a semiconductor device that secures memory capacity using all discrete SRAM dies without including an HBM.

[0057] Figure 11 shows yet another example of packaging for a semiconductor device. The semiconductor device 107 uses four integrated sets, each consisting of one logic die 112, three discrete SRAM dies 113, and one IO die 115, as shown in Figure 11. A large-scale SRAM memory capacity of 96 GB in total is secured. This realizes packaging for a semiconductor device that secures memory capacity using all discrete SRAM dies without including an HBM.

[0058] To further increase the memory capacity of the discrete SRAM die, a high bandwidth static memory (HBSM) may be used, which is made by stacking multiple discrete SRAM dies vertically. The relaxation of packaging area constraints has made it possible to mount large-capacity, large-scale discrete SRAM dies, and the enhanced cooling function provided by the cooling water (usually running water) in the water immersion bath makes it possible to operate the semiconductor device so that its design junction temperature Tj and operating junction temperature Tj satisfy the conditions of 1° C.≦Tjd, Tj≦40° C., and Tj<Tjd, even when using HBSM.

[0059] 12 to 14 show yet another example of semiconductor device packaging using a 64 GB HBSM 213, which is formed by stacking eight layers of 8 GB discrete SRAM dies vertically. The layout of the logic die, SRAM die, and IO die in the packaging of semiconductor devices 201, 202, and 203 is similar to the layout of these dies in the packaging of semiconductor devices 105, 106, and 107 shown in FIGS. 9 to 11. Semiconductor device 201 uses a total of four 64 GB discrete SRAM dies to ensure a large SRAM memory capacity of 256 GB.

[0060] 13, two sets of one logic die 112, three HBSMs 213, and one IO die 115 are integrated together. A large-scale SRAM memory capacity of 192 GB per set, totaling 384 GB, is secured.

[0061] Furthermore, in the semiconductor device 203 shown in FIG. 14, four sets, each consisting of one logic die 112, two HBSMs 213, and one IO die 115, are integrated to provide a total of 512 GB of large-scale SRAM memory capacity. Furthermore, semiconductor devices 201, 202, and 203 do not include an HBM, and instead provide semiconductor device packaging with memory capacity secured by all-discrete SRAM dies. The combination of four logic dies 112 and the 512 GB of large-scale SRAM memory capacity provides high-level computing performance commensurate with this enormous memory capacity. This means that training processes, which currently require processing by multiple semiconductor devices with existing technology, can now be performed at high speed using a single semiconductor device package.

[0062] 15-17 show yet another example of packaging for a semiconductor device using one or more 128 GB HBSMs 313, each consisting of 16 vertical layers of 8 GB discrete SRAM dies, and also using one or more logic dies 312, each consisting of 8 vertical layers of logic dies.

[0063] The semiconductor device 301 shown in Figure 15 uses four 128 GB HBSMs 313 to provide a total of 512 GB of large-scale SRAM memory capacity. The combination of one eight-layer stacked and enhanced logic die 312 with the 512 GB of large-scale SRAM memory capacity provides ultra-high levels of computing performance commensurate with this enormous memory capacity. This means that training processes, which currently require processing by multiple semiconductor devices with existing technology, can now be performed at ultra-high speeds using a single semiconductor device package.

[0064] 16, a semiconductor device 302 is used that integrates four sets of one eight-layer stacked and reinforced logic die 312, three 128 GB HBSMs 313, and one IO die 115, ensuring a large-scale SRAM memory capacity of 768 GB in total. This semiconductor device can also provide ultra-high-level computing performance commensurate with this huge memory capacity.

[0065] 17, a semiconductor device 303 is used that integrates four sets of one eight-layer stacked and reinforced logic die 312, two 128 GB HBSMs 313, and one IO die 115, ensuring a large-scale SRAM memory capacity of 1,024 GB in total. This semiconductor device can also provide ultra-high-level computing performance commensurate with this huge memory capacity.

[0066] [Waterproofed electronic substrate or semiconductor device, and water immersion cooling system]

[0067] 2 and 3 , an example of a water immersion cooling system for waterproofing an electronic device including any of the semiconductor devices according to the various embodiments described above as a heat-generating element and for providing a suitable environment for using the semiconductor device will be described. In the following description, the term "heat-generating element" will be understood to mean any of the semiconductor devices according to the various embodiments described above, and the term "electronic device" will be understood to mean an electronic circuit board on which any of the semiconductor devices according to the various embodiments described above are mounted. The cooling system 1 shown as an example includes a cooling tank (water immersion tank) 3 containing a coolant 4 (water), a waterproof electronic device 100 formed by covering an electronic device 10 including a circuit board (PCB) 31 and multiple heat-generating elements 33 mounted on the circuit board 31 with a waterproof bag 11, multiple cold plates 20, and a pump 8. The cold plate 20 includes a main body 21, a fluid inlet 23, and a fluid outlet 25. A fluid flow path is formed within the main body 21 of the cold plate 20. The flow path may be formed so as to increase the area with which the fluid comes into contact, and for example, a mesh-like hole, a zigzag hole, or a space with a number of fins or pins arranged at predetermined intervals may be formed in the main body 21.

[0068] In the illustrated example, all of the multiple cold plates 20 may be disposed outside the waterproof bag 11, and at least one surface (e.g., the back surface) of the main body 21 of each of the multiple cold plates 20 may be thermally connected to each of the multiple heating elements 33. In this case, an opening 15 having an area larger than the area of ​​the heating element 33 may be formed in the waterproof bag 11, and the surrounding area of ​​the opening 15 and the back surface of the main body 21 of the cold plate 20 may be watertightly connected via a bonding layer 41.

[0069] The bonding layer 41 is formed by using a dissimilar material bonding film, double-sided adhesive tape, or watertight packing to connect the back surface of the body of the cold plate 20 to the outer surface of the waterproof bag. An opening having a shape similar to that of the opening 15 may be formed in the dissimilar material bonding film, double-sided adhesive tape, or watertight packing that forms the bonding layer 41.

[0070] An example of a dissimilar material bonding film for forming the bonding layer 41 is the "Metaseal" (product name of Fujimori Kogyou Co., Ltd.) series. Because this dissimilar material bonding film is formed into a film of uniform thickness, it can be sandwiched between the back surface (rear surface) of the cold plate 20 and the outer surface (inner surface) of the waterproof bag 11 and then heat-pressed to form a bonding layer bonding the cold plate 20 and the waterproof bag 11. A heat press or an iron-type heater can be used for heat-pressing, allowing the bonding process between the base block 21B and the non-conductive bag 11 to be completed easily and in a short time (several seconds or less). The method for forming the bonding layer 41 is not limited to heat-pressing, and various methods, such as pressure, ultrasonic waves, electromagnetic waves, and light irradiation, can also be used.

[0071] By forming the bonding layer 41 from a dissimilar material bonding film, it is possible to achieve a surface bond between the back surface (rear surface) of the cold plate 20 and the outer surface (inner surface) of the waterproof bag 11 with a uniform film thickness and no variation in adhesive strength.

[0072] Another example of a dissimilar material bonding film that forms a bonding layer is "WelQuick" (a Resonac product name) manufactured by Resonac Corporation. This dissimilar material bonding film utilizes the solid-liquid phase change of the film material to complete the bonding process in a short time (a few seconds). It also allows for reheating after bonding to allow for peeling and re-adhesion. This allows for easy collection of waterproofed electronic devices from cooling systems after a certain period of use, and for the cold plate 20 to be easily peeled from the waterproof bag 11, resulting in high resource reusability.

[0073] Here, the dissimilar material bonding film can be preferably formed into a sheet or film shape and then cut. However, this is not limiting. For example, if a certain environment is established in which various conditions, including the film thickness and shape, can be appropriately controlled, a bonding layer 41 formed from the dissimilar material bonding film can be obtained starting with a liquid or gel adhesive material. Specifically, as an example, a mold is first placed on the surface of the cold plate and filled with the liquid or gel adhesive material, thereby forming a coating of the adhesive material of the desired shape and volume on the surface of the cold plate. Next, with the coating of the adhesive material in contact with the back surface (surface) of the cold plate and the outer surface (inner surface) of the waterproof bag, the coating of the adhesive material can be solidified by methods such as thermocompression, pressure, ultrasound, electromagnetic waves, or light irradiation. In this way, a bonding layer formed from the dissimilar material bonding film can be obtained starting from a liquid or gel adhesive material.

[0074] Alternatively, the bonding layer may be formed using double-sided adhesive tape. For example, a high-strength acrylic foam tape (e.g., 3M VHB Tape) can be cut to the desired size and shape to prepare the double-sided adhesive tape for the bonding layer. One side of the double-sided adhesive tape is pressed onto the back surface (surface) of the cold plate or the outer surface (inner surface) of the waterproof bag, and then the outer surface (inner surface) of the waterproof bag 11 or the back surface (surface) of the cold plate is pressed onto the other side of the double-sided adhesive tape to form a bonding layer bonding the cold plate and the waterproof bag. The use of double-sided adhesive tape has the advantage that it does not require a heat treatment, making it easy to form the bonding layer. When using double-sided adhesive tape, it is preferable to arrange the cut tape so that the bonding layer forms a continuous, closed band surrounding the opening of the bag 11.

[0075] Alternatively, the bonding layer may be formed by a watertight packing. For example, various rubber packings (typically O-rings) in a continuous, closed strip or line shape can be used. The watertight packing is placed between the back surface of the cold plate and the outer surface of the waterproof bag so as to surround the opening of the bag 11. The cold plate is then fixed to the substrate by screwing or the like. In this fixed state, the watertight packing elastically deforms, applying an appropriate surface pressure in a strip or line shape to the area surrounding the opening 15 of the bag 11, thereby maintaining a watertight seal on both sides of the surrounding area.

[0076] In the illustrated example, an inlet manifold 27 and an outlet manifold 29 may be disposed outside the waterproof bag 11. Each outlet of the inlet manifold 27 may be fluidly connected to each fluid inlet 23 of the multiple cold plates 20, and each inlet of the outlet manifold 29 may be fluidly connected to each fluid outlet 25 of the multiple cold plates 20.

[0077] In the circulation path that runs from the fluid outlet 25 of the cold plate 20 through the outlet manifold 29, the fluid return pipe 7b, the heat exchanger 9, the pump 8, the fluid feed pipe 7a, the inlet manifold 27, and back to the fluid inlet 23 of the cold plate 20, the pump 8 applies pressure energy from the fluid inlet 23 to the fluid outlet 25 to the fluid passing through the flow path formed in the body 21 of the cold plate 20. The fluid heated in the cold plate 20 by the action of the pump 8 passes through the heat exchanger 9, where it is cooled and sent to the cold plate 20. This circulating fluid may be water, but may also be another refrigerant.

[0078] The waterproof bag 11 may be made of a film of synthetic resin (e.g., polyethylene, polypropylene, polyester, etc.) that is water-resistant and resistant to relatively low temperatures (e.g., 100°C or higher) and can maintain watertightness. In the illustrated example, the upper part of the waterproof bag 11 does not need to be airtight / watertight; it is sufficient that at least the portion immersed in the coolant is airtight. In this case, when the cooling system 1 is in operation, the relatively flexible waterproof bag 11 is pressed by the hydraulic pressure of the surrounding coolant 4, so that the inner surface of the waterproof bag 11 can be brought into relatively close contact with both sides of the circuit board 31, the various electronic components 35 mounted on the circuit board, the network communication cable 36, the power cable 37, and the surfaces of the connectors connecting them.

[0079] The cooling tank 3 contains a sufficient amount of coolant 4 to immerse the waterproof electronic device 100. The coolant 4 may be ordinary water (tap water, industrial water, seawater, etc.). A coolant supply pipe 5a and a coolant return pipe 5b connected to the cooling tank 3 provide paths for discharging the coolant heated in the cooling tank 3 from the cooling tank 3 and returning the coolant cooled by a heat exchanger (not shown) to the cooling tank 3. In the waterproof electronic device 100 immersed in the coolant 4, the coolant 4 cools the entire waterproof electronic device 100, and the fluid forced to pass through the flow path formed in the body 21 of the cold plate 20 locally and powerfully removes heat from the heat-generating element 33.

[0080] Next, other examples of cooling systems and other examples of waterproofed electronic devices will be described with reference to Figures 18 to 32. Note that like reference numerals are used for like parts to those in Figures 2 and 3.

[0081] Fig. 18 shows the configuration of the main parts of another example of a cooling system, and Fig. 19 shows a partial cross section of a waterproofed electronic device. This cooling system differs from the cooling systems shown in Figs. 2 and 3 in that, in the waterproofed electronic device 200, all of the multiple cold plates 20 are disposed inside the waterproof bag 11, and the inlet manifold 27 and the outlet manifold 29 are also disposed inside the waterproof bag 11.

[0082] FIG. 20 shows a partial cross section of a waterproofed electronic device in yet another example of a cooling system. This cooling system differs from the cooling systems shown in FIGS. 18 and 19 in that the opening of the fluid outlet 25 of the cold plate 20 in the waterproofed electronic device 210 is located outside the waterproof bag 11 and that the outlet manifold 29 and fluid return pipe 7b are not required. Another difference is that a fluid feed pipe 7c branches off from the coolant return pipe 5b and connects to the heat exchanger 9, thereby forming a separate circulation path from the fluid outlet 25 of the cold plate 20 through the cooling tank 3, the coolant return pipe 5b, the fluid return pipe 7c, the heat exchanger 9, the pump 8, the fluid feed pipe 7a, the inlet manifold 27, and back to the fluid inlet 23 of the cold plate 20 (see FIG. 3 ). To locate the opening of the fluid outlet 25 of the cold plate 20 outside the waterproof bag 11, the fluid outlet 25, which is made up of, for example, a pipe, must pass through a penetration formed in the waterproof bag 11. In this case, it is advisable to take appropriate measures such as providing a sealant at the penetration portion to ensure watertightness.

[0083] FIG. 21 shows a partial cross section of a waterproofed electronic device in yet another example of a cooling system. This cooling system differs from the cooling systems shown in FIGS. 18 and 19 in that, in a waterproofed electronic device 300, the opening of the fluid outlet 25 of the cold plate 20 and substantially the entire body 21 of the cold plate 20 are disposed outside the waterproof bag 11, an opening 15 having an area larger than the area of ​​the heating element 33 is formed in the waterproof bag 11, and the area surrounding the opening 15 is watertightly connected to the back surface of the body 21 of the cold plate 20 (and, as shown, between the slit in the waterproof bag 11 and the front surface of the body 21 of the cold plate 20) via a bonding layer 41. Similar to the example shown in FIG. 20, the outlet manifold 29 and fluid return pipe 7b are not required, and a fluid feed pipe 7c branches off from the coolant return pipe 5b and connects to the heat exchanger 9, forming a separate circulation path.

[0084] FIG. 23 shows a partial cross section of a waterproofed electronic device in yet another example of a cooling system. This cooling system differs from the cooling system including the waterproofed electronic device 300 shown in FIG. 21 in that, in the waterproofed electronic device 310, the opening of the fluid outlet 25 of the cold plate 20 and the entire body 21 of the cold plate 20 are disposed outside the waterproof bag 11, and the area surrounding the opening 15 of the waterproof bag 11 is watertightly connected to the back surface and the surface of the body 21 of the cold plate 20 facing the fluid inlet 23 via a bonding layer 41. Similar to the example shown in FIG. 21 , the outlet manifold 29 and fluid return pipe 7b are not required, and a fluid feed pipe 7c branches off from the coolant return pipe 5b and connects to the heat exchanger 9, forming a separate circulation path. Furthermore, the fluid inlet 23 of the cold plate 20 must pass through a penetration formed in the waterproof bag 11, but the penetration may be appropriately treated, such as by providing a sealant, to maintain watertightness.

[0085] Figure 23 shows a partial cross section of a waterproof electronic device in yet another example of a cooling system. This cooling system differs from the cooling system including the waterproof electronic device 310 shown in Figure 22 in that the openings of the fluid inlet 23 and fluid outlet 25 of the cold plate 20, as well as the entire main body 21, are disposed outside the waterproof bag 11 in the waterproof electronic device 320. The rest is the same as the example shown in Figure 22. Note that each outlet of the inlet manifold 27 must pass through a through-hole formed in the waterproof bag 11, and it is recommended to provide a sealant or other appropriate treatment at the through-hole to maintain watertightness.

[0086] FIG. 24 shows a partial cross section of a waterproofed electronic device in yet another example of a cooling system. This cooling system differs from the cooling system including the waterproofed electronic device 320 shown in FIG. 23 in that the inlet manifold 27, the opening of the fluid inlet 23 of the cold plate 20, the opening of the fluid outlet 25, and the entire main body 21 are disposed outside the waterproof bag 11. The rest is the same as the example shown in FIG. 23. Unlike the example shown in FIG. 23, except for the formation of the opening 15 in the waterproof bag 11, there is no need to form a penetration in the waterproof bag 11, resulting in excellent watertightness. The waterproofed electronic device 100 shown in FIGS. 2 and 3 also has excellent watertightness.

[0087] 25 and 26 are front and partial cross-sectional views of a waterproofed electronic device in yet another example of a cooling system. This cooling system differs from the cooling system including the waterproofed electronic device 210 shown in FIG. 20 in that the inlet manifold 27 and the openings of the fluid inlet 23 and fluid outlet 25 of the cold plate 20 are disposed outside the waterproof bag 11, and the openings of the fluid inlet 23 and fluid outlet 25 of the cold plate 20 are disposed on the front side of the cold plate 20. The rest of the cooling system is the same as the example shown in FIG. 20. The fluid inlet 23 and fluid outlet 25 of the cold plate 20 must pass through penetrations formed in the waterproof bag 11, and it is recommended to provide appropriate treatment, such as providing a sealant at the penetrations, to maintain watertightness.

[0088] FIG. 27 shows a partial cross section of a waterproofed electronic device in yet another example of a cooling system. This cooling system differs from the cooling system including the waterproofed electronic device 400 shown in FIG. 26 in that, in the waterproofed electronic device 500, multiple submersible pumps 28 are connected to the fluid inlets 23 of multiple cold plates 20, respectively. In this example, there is no need to configure a fluid circulation path from the cooling tank 3 through the coolant return pipe 5b, the fluid return pipe 7c, the heat exchanger 9, the pump 8, the fluid feed pipe 7a, the inlet manifold 27, and back to the fluid inlets 23 of the cold plates 20. Instead, a portion of the coolant may pass through a flow path formed within the body 21 of the cold plate 20, and the submersible pump 29 may apply pressure energy to this portion of the coolant. When the submersible pump 29 is connected to each of the multiple cold plates 20, the flow rate or volume of the fluid passing through the cold plates can be individually controlled. This enables appropriate temperature management in large-scale electronic devices incorporating high-performance semiconductor devices, depending on the heat generation of the high-performance semiconductor devices. In addition, the fluid inlet 23 and fluid outlet 25 of the cold plate 20 need to pass through a penetration formed in the waterproof bag 11, but it is recommended to take appropriate measures such as providing a sealing material at the penetration to maintain watertightness.

[0089] FIG. 28 shows a partial cross section of a waterproofed electronic device in yet another example of a cooling system. This cooling system differs from the cooling system including the waterproofed electronic device 330 shown in FIG. 24 in that a submersible pump 28 is connected to the fluid inlet 23 of each of the multiple cold plates 20 in the waterproofed electronic device 600, and the fluid inlet 23 may be disposed on the surface side of the cold plate 20. Like the example shown in FIG. 24 , this example does not require the formation of a penetration in the waterproof bag 11, except for the formation of the opening 15 in the waterproof bag 11, and thus has excellent watertightness. Also, like the example shown in FIG. 27 , this example does not require the formation of a fluid circulation path from the cooling tank 3 through the coolant return pipe 5b, the fluid return pipe 7c, the heat exchanger 9, the pump 8, the fluid feed pipe 7a, the inlet manifold 27, and back to the fluid inlet 23 of the cold plate 20. Additionally, this example has many advantages over the example in which a submersible pump 29 is connected to each of the multiple cold plates 20.

[0090] FIG. 29 shows the configuration of essential parts of yet another example of a cooling system. This cooling system differs from the cooling system including the waterproofed electronic device 200 shown in FIG. 18 in that, in the waterproofed electronic device 700, the fluid outlet 25 of one of the adjacent cold plates 20 (four cold plates in the illustrated example) is fluidly connected to the fluid inlet 23 of the other cold plate via the connecting pipe 18. In other words, the multiple cold plates 20 are connected via the connecting pipe 18. Unlike the example shown in FIG. 18 , this example does not require an inlet manifold or an outlet manifold. The fluid supply pipe 7b may be fluidly connected to the fluid inlet 23 of the first cold plate of the multiple connected cold plates, and the fluid return pipe 7b may be fluidly connected to the fluid outlet 25 of the last cold plate.

[0091] Fig. 30 shows the configuration of the main components of yet another example of a cooling system. This cooling system differs from the cooling system including the waterproofed electronic device 700 shown in Fig. 29 in that, in the waterproofed electronic device 710, at least one surface of the main body 21 of one cold plate 20 is thermally connected to multiple heat generating elements (four heat generating elements in the illustrated example). In other words, the multiple cold plates in the example of Fig. 29 may be integrated to form a single cold plate.

[0092] Although one example and several other examples of the cooling system have been described above with reference to the drawings, further modifications may be made to the details of the components. For example, with respect to the fluid circulation path, in the example of the cooling system shown in Figure 18, the pump 8 and the heat exchanger 9 are arranged outside the cooling tank 3, but one or both of them may be arranged inside the cooling tank 3 or immersed in the cooling liquid 4. When the pump 8 is immersed in the cooling liquid 4, it is preferable to use a submersible pump.

[0093] 27 and 28, multiple submersible pumps 28 are connected to the fluid inlets 23 of the multiple cold plates 20, but this configuration may be modified as follows. That is, as in the example shown in FIG. 25, an inlet manifold 27 may be used, and each outlet of the inlet manifold 27 may be connected to each fluid inlet of the multiple cold plates 20. The submersible pump 28 may then be connected to the inlet of the inlet manifold 27. In this configuration, the submersible pump connected to the inlet of the inlet manifold 27 applies pressure energy to a portion of the coolant, causing the portion of the coolant to pass through the outlets of the inlet manifold 27 and through flow paths formed in the bodies of each of the multiple cold plates.

[0094] Furthermore, a cooling system may be configured using a heat sink instead of a cold plate. Figures 31 and 32 show partial cross sections of a waterproofed electronic device in yet another example of such a cooling system. In the waterproofed electronic device 800 shown in Figure 31, a fin region 511 on the front side of the heat sink 51 may be provided with numerous plate-shaped fins rising from a base portion 512. The area surrounding the fin region 511 is a flat surface without fins, and this surface also forms the surface of the heat sink. The front surface of the heat sink 51 and the inner surface of the waterproof bag 11 may be watertightly connected via a bonding layer 41. The back surface of the heat sink is thermally connected to one side of the heating element 33 through an opening formed in the waterproof bag 11. In this case, to ensure surface contact and thermal connection, the minute gap between one side of the heating element 33 and the back surface 11B of the heat sink 51 may be filled with thermal conductive grease 34. By making water flow through the flow paths formed by the fin regions 511 on the surface of the heat sink 51, heat is absorbed from the heat generating element 33, and the heat generating element 33 is locally cooled.

[0095] In the waterproofed electronic device 810 shown in FIG. 32 , the heat sink 53 includes an outer block 513 and a base block 514. A fin region 515 on the front surface of the outer block 513 may have a number of plate-shaped fins extending upward from the base portion. A plurality of through holes may be formed near the center of the front surface of the base portion, extending from the front surface to the rear surface of the base portion. A disk-shaped protrusion may be formed on the rear surface of the base portion of the outer block 513. A recess may be formed on one flat surface of the base block 514, and a plurality of screw holes may be formed therein. The recess of the base block 514 faces the protrusion of the outer block 513 when the outer block 513 is fixed to the base block 514. The protrusion of the outer block 513 comes into surface contact with the bottom surface of the recess of the base block 514 through an opening formed in the waterproof bag 11, thereby thermally connecting the outer block 513 and the base block 514. By fastening with screws 525, the flat surface of outer block 513 and the surface of base block 514 apply an appropriate surface pressure to the area surrounding opening 15 of waterproof bag 11, and this appropriate surface pressure keeps both sides of the surrounding area watertight. The back surface of base block 514 inside waterproof bag 11 is thermally connected to one surface of the heating element. By flowing water through the flow path formed by fin area 515 on the surface of outer block 513, heat is removed from heating element 33, locally cooling heating element 33.

[0096] Furthermore, while the example of waterproofing an electronic device by covering it with a waterproof bag has been presented, other examples of waterproofing an electronic device include covering it with a thin film of parylene, which is electrically non-conductive and water-impermeable (see, for example, Kazuki Fujiwara et al., "The First Step Toward a Direct Natural Water-Cooled Computer," Information Processing Society of Japan Research Report, High Performance Computing (HPC), 2017-HPC-158(5), pp. 1-5 (March 1, 2017). URL: http: / / research.nii.ac.jp / ~koibuchi / pdf / ikki-sighpc158.pdf). Another example is covering an electronic device with an ultra-nanohydrophobic coating thin film using silicon compound nanoparticles, which is electrically non-conductive and water-impermeable (see, for example, U.S. Pat. No. 10,717,881). Such waterproofing is easier when the electronic device has a relatively flat structure.

[0097] 3 , an exemplary configuration of the cooling system 1 will be described in further detail. Two or more waterproofed electronic devices 100 may be immersed in the coolant 4 contained in the cooling tank 3. A top plate 3A may be installed in the cooling tank 3 to reduce evaporation of the coolant 4. Furthermore, the waterproofed electronic device 100 may include, in the waterproof bag 11, a wireless power supply unit (not shown) for supplying power to the electronic device 10, instead of a power cable, and may also include, in the waterproof bag 11, a wireless communication unit (not shown) for enabling wireless communication between the waterproofed electronic device 100 and the outside, instead of a network communication cable.

[0098] This application discloses various embodiments of methods for using semiconductor devices and configurations of semiconductor devices, and in particular includes the following disclosure of a water immersion cooling system that provides a suitable environment for using semiconductor devices.

[0099] (1) A cooling system for cooling an electronic device by immersing it in a cooling liquid, the cooling system comprising: a cooling tank filled with the cooling liquid; a waterproof electronic device in which an electronic device including a substrate and at least one heat generating element mounted on the substrate is covered with a waterproof coating or a waterproof bag; a cold plate including a main body, a fluid inlet, and a fluid outlet, at least one surface of the main body being thermally connected to the at least one heat generating element, and a part or all of the cold plate being disposed inside the waterproof coating or the waterproof bag or outside the waterproof coating or the waterproof bag; and at least one fluid machine that applies pressure energy from the fluid inlet to the fluid outlet to a fluid passing through a flow path formed in the main body of the cold plate.

[0100] (2) The cooling system of (1), wherein the cooling liquid is water, the fluid machine is a pump or a submersible pump placed in a circulation path that returns from the fluid outlet of the cold plate to the fluid inlet, and the fluid passing through a flow path formed in the body of the cold plate is a refrigerant that is cooled by a heat exchanger in the circulation path.

[0101] (3) The cooling system of (1), wherein the cooling liquid is water, the fluid machine is a submersible pump connected to the fluid inlet of the cold plate, the fluid passing through a flow path formed in the body of the cold plate is a portion of the cooling liquid, and the submersible pump applies the pressure energy to the portion of the cooling liquid.

[0102] (4) The cooling system of (1), further comprising an inlet manifold disposed inside the waterproof coating or the waterproof bag or outside the waterproof coating or the waterproof bag, the electronic device including a plurality of heating elements and a plurality of cold plates, and each outlet of the inlet manifold being fluidly connected to each fluid inlet of the plurality of cold plates.

[0103] (5) The cooling system of (4), further comprising an outlet manifold disposed inside the waterproof coating or the waterproof bag or outside the waterproof coating or the waterproof bag, wherein each inlet of the outlet manifold is fluidly connected to each fluid outlet of the plurality of cold plates.

[0104] (6) The cooling system of (1), wherein an opening having an area larger than an area of ​​the at least one heating element is formed in the waterproof coating or the waterproof bag, and when a part or all of the cold plate is disposed outside the waterproof coating or the waterproof bag, a peripheral area of ​​the opening of the waterproof coating or the waterproof bag is watertightly connected to at least one surface of the main body of the cold plate, and a surface of the at least one heating element and the at least one surface of the cold plate are thermally connected through the opening of the waterproof coating or the waterproof bag.

[0105] (7) The cooling system according to (6), further comprising a bonding layer that provides a watertight connection between the waterproof coating or the waterproof bag and the at least one surface of the cold plate, the bonding layer being formed from a dissimilar material bonding film, a double-sided adhesive tape, or a watertight packing.

[0106] (8) The cooling system of (4), wherein the inlet manifold, the main body of each of the plurality of cold plates, and each of the fluid inlets are disposed inside the waterproof coating or the waterproof bag, and openings of each of the fluid outlets of the plurality of cold plates are disposed outside the waterproof coating or the waterproof bag.

[0107] (9) The cooling system of (4), wherein the inlet manifold and the fluid inlet openings of the plurality of cold plates are disposed inside the waterproof coating or the waterproof bag, and the bodies of the plurality of cold plates and the fluid outlet openings are disposed outside the waterproof coating or the waterproof bag.

[0108] (10) The cooling system of (4), wherein the inlet manifold is disposed inside the waterproof coating or the waterproof bag, and the fluid inlet openings, the bodies, and the fluid outlet openings of the plurality of cold plates are disposed outside the waterproof coating or the waterproof bag.

[0109] (11) The cooling system of (4), wherein the inlet manifold, the openings of the fluid inlets of the plurality of cold plates, the main bodies, and the openings of the fluid outlets are disposed outside the waterproof coating or the waterproof bag.

[0110] (12) The cooling system of (4), wherein the main body of each of the plurality of cold plates is disposed inside the waterproof coating or the waterproof bag, and the inlet manifold and the fluid inlet openings and fluid outlet openings of the plurality of cold plates are disposed outside the waterproof coating or the waterproof bag.

[0111] (13) The cooling system of (1), wherein the fluid machinery includes a plurality of submersible pumps, the electronic device includes a plurality of heat generating elements and a plurality of cold plates, the coolant is water, each of the plurality of submersible pumps is connected to a respective fluid inlet of the plurality of cold plates, the fluid passing through a flow path formed in each body of the plurality of cold plates is a portion of the coolant, and each submersible pump applies a respective pressure energy to a portion of the coolant.

[0112] (14) The cooling system of (13), wherein the bodies of the plurality of cold plates are disposed inside the waterproof coating or the waterproof bag, and the plurality of submersible pumps and the fluid inlet openings and fluid outlet openings of the plurality of cold plates are disposed outside the waterproof coating or the waterproof bag.

[0113] (15) The cooling system of (13), wherein the plurality of submersible pumps, the bodies of the plurality of cold plates, the fluid inlet openings, and the fluid outlet openings are disposed outside the waterproof coating or the waterproof bag.

[0114] (16) The cooling system of (1), further comprising an inlet manifold and an underwater pump as the fluid machine, wherein the electronic device comprises a plurality of heat generating elements and a plurality of cold plates, the cooling liquid is water, the underwater pump is connected to an inlet of the inlet manifold, each outlet of the inlet manifold is fluidly connected to each fluid inlet of the plurality of cold plates, the fluid passing through the flow path formed in each body of the plurality of cold plates is a portion of the cooling liquid, and the underwater pump applies pressure energy to the portion of the cooling liquid.

[0115] (17) The cooling system of (16), wherein the bodies of the plurality of cold plates are disposed inside the waterproof coating or the waterproof bag, and the submersible pump, the inlet manifold, and the fluid inlet openings and fluid outlet openings of the plurality of cold plates are disposed outside the waterproof coating or the waterproof bag.

[0116] (18) The cooling system of (16), wherein the submersible pump, the inlet manifold, the bodies of the plurality of cold plates, the fluid inlet openings, and the fluid outlet openings are disposed outside the waterproof coating or the waterproof bag.

[0117] (19) The cooling system of (1), further comprising one or more connecting pipes disposed inside the waterproof coating or the waterproof bag or outside the waterproof coating or the waterproof bag, the electronic device comprising a plurality of heating elements and a plurality of cold plates, and a fluid outlet of one of the plurality of adjacent cold plates being fluidly connected to a fluid inlet of the other cold plate via the connecting pipes.

[0118] (20) The cooling system according to (1), wherein the electronic device includes a plurality of heat generating elements, and at least one surface of the body of the cold plate is thermally connected to the plurality of heat generating elements.

[0119] The present invention can be widely applied to high-performance semiconductor devices for artificial intelligence (AI) or high-performance computing (HPC).

[0120] 1 Cooling system 3 Cooling tank (immersion tank) 3A Top plate 4 Coolant (cooling water) 5a Coolant feed pipe 5b Coolant return pipe 7a Fluid feed pipe 7b, 7c Fluid return pipe 8 Pump 9 Heat exchanger 10 Electronic device 100, 200, 210, 300, 310, 320, 330, 400, 500, 600, 700, 710, 800, 810 Waterproofed electronic device 101, 102, 103, 104, 105, 106, 107, 201, 202, 203, 301, 302, 303 Semiconductor device 111 Package substrate 112, 312 Logic die 113 Discrete SRAM die 213, 313 HBSM 114, 117 HBM (DRAM) 115 IO die 116 Interposer (connection structure) 11 Waterproof bag 15 Opening 18 Connecting piping 20 Cold plate 21 Cold plate body 23 Fluid inlet (pipe) 25 Fluid outlet (pipe) 27 Inlet manifold 28 Submersible pump 29 Outlet manifold 31 Substrate (PCB) 33 Heat generating element (semiconductor device) 35 Electronic component 36 Network communication cable 37 Power cable 41 Bonding layer 51, 53 Heat sink 511, 515 Fin area 512 Base portion 513 Outer block 514 Base block 525 Screw

Claims

1. A method for using a semiconductor device, comprising: waterproofing an electronic substrate including at least one semiconductor device, the at least one semiconductor device including: a package substrate; one or more logic dies arranged on one side of the package substrate and electrically connected to the package substrate; a plurality of memory dies arranged on the one side of the package substrate and electrically connected to the package substrate; one or more connection structures connecting the logic die to each of the plurality of memory dies; and a packaging material surrounding the logic die, the plurality of memory dies, and the connection structures, wherein the semiconductor device is designed to operate at a design junction temperature Tjd of 1°C or higher and 40°C or lower, and the waterproofed electronic substrate is immersed in water at a temperature Tw lower than the design junction temperature Tjd, to operate the semiconductor device at an operating junction temperature Tjo lower than the design junction temperature Tjd.

2. The method of using a semiconductor device according to claim 1, wherein the semiconductor device is designed to operate while satisfying the condition that the design junction temperature Tjd is 20°C or higher and 30°C or lower.

3. The method for using a semiconductor device according to claim 1 or 2, wherein the waterproofing treatment includes covering the electronic board including the semiconductor device with a waterproof coating or a waterproof bag.

4. A method of using a semiconductor device according to claim 3, comprising: thermally connecting a cold plate to the surfaces of the logic die and the plurality of memory dies; immersing the waterproofed electronic substrate in a cooling bath through which water flows to cool the entire electronic substrate; and flowing a coolant through a flow path in the cold plate to locally cool the logic die and the plurality of memory dies.

5. The method for using a semiconductor device according to claim 3, wherein the coolant flowing through the flow paths in the cold plate is water.

6. A method of using a semiconductor device according to claim 3, comprising: thermally connecting a heat sink to the surfaces of the logic die and the plurality of memory dies so that the surfaces of the heat sink are positioned outside the waterproof coating or the waterproof bag; immersing the waterproofed electronic substrate in a cooling bath through which water flows to cool the entire electronic substrate; and locally cooling the logic die and the plurality of memory dies by flowing water through channels on the surface of the heat sink.

7. The method of using a semiconductor device according to claim 1, wherein the semiconductor device is a logic semiconductor including at least one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit) including a GPGPU (General Purpose Graphics Processing Unit), an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit), and the memory die is an SRAM (Static Random Access Memory) die and / or an HBM (High Bandwidth Memory) formed by vertically stacking multiple DRAM (Dynamic Random Access Memory) dies.

8. The method of using a semiconductor device according to claim 7, wherein the SRAM die is a large-scale discrete SRAM die or a High Bandwidth Static Memory (HBSM) formed by vertically stacking a plurality of large-scale discrete SRAM dies.

9. The method for using a semiconductor device according to claim 7 or 8, wherein the logic die is formed by arranging a plurality of logic dies horizontally or stacking a plurality of logic dies vertically.

10. The method for using a semiconductor device according to claim 9, wherein the connection structure further includes a connection structure that connects the plurality of logic dies together.

11. A semiconductor device comprising: a package substrate; one or more logic dies arranged on one side of the package substrate and electrically connected to the package substrate; a plurality of memory dies arranged on the one side of the package substrate and electrically connected to the package substrate; at least one connection structure connecting the logic die and each of the plurality of memory dies; and a packaging material surrounding the logic die, the plurality of memory dies, and the connection structure, wherein the semiconductor device is designed to operate at a design junction temperature Tjd of 1°C or higher and 40°C or lower, and is operated at an operating junction temperature Tjo lower than the design junction temperature Tjd by immersing the semiconductor device in a waterproofed state in water at a temperature Tw lower than the design junction temperature Tjd.

12. The semiconductor device according to claim 11, wherein the semiconductor device is designed to operate while satisfying the condition that the design junction temperature Tjd is 20° C. or higher and 30° C. or lower.

13. The semiconductor device according to claim 11 or 12, wherein the waterproofing treatment includes covering the semiconductor device with a waterproof film or a waterproof bag.

14. The semiconductor device according to claim 13, wherein a cold plate is thermally connected to surfaces of the logic die and the plurality of memory dies, and the logic die and the plurality of memory dies are locally cooled by a coolant flowing through a flow path in the cold plate.

15. The semiconductor device according to claim 14, wherein the coolant flowing through the flow passages in the cold plate is water.

16. The semiconductor device according to claim 13, wherein a heat sink is thermally connected to surfaces of the logic die and the plurality of memory dies so that the surfaces of the heat sink are positioned outside the waterproof coating or the waterproof bag, and the waterproof semiconductor device is immersed in a cooling bath through which water flows, and the logic die and the plurality of memory dies are locally cooled by the water flowing through channels on the surfaces of the heat sink.

17. The semiconductor device according to claim 11, wherein the semiconductor device is a logic semiconductor including at least one of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit) including a GPGPU (General Purpose Graphics Processing Unit), an FPGA (Field Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit), and the memory die is an SRAM (Static Random Access Memory) die and / or an HBM (High Bandwidth Memory) formed by vertically stacking multiple DRAM (Dynamic Random Access Memory) dies.

18. The semiconductor device according to claim 17, wherein the SRAM die is a large-scale discrete SRAM die or a High Bandwidth Static Memory (HBSM) formed by vertically stacking a plurality of large-scale discrete SRAM dies.

19. The semiconductor device according to claim 17 or 18, wherein the logic die is formed by arranging a plurality of logic dies horizontally or stacking a plurality of logic dies vertically.

20. The semiconductor device according to claim 19, wherein the connection structure further includes a connection structure that connects the plurality of logic dies together.

21. The semiconductor device according to claim 11, wherein the logic die executes computational processing for generative AI processing, and the plurality of memory dies function as memory for inference processing and / or training processing.

Images