Semiconductor device

Abstract

This semiconductor device has first and second semiconductor chips. A first circuit of the first semiconductor chip has a first power supply line, a second power supply line, a signal line connected to a second circuit of the second semiconductor chip, and a plurality of first transistors provided between either the first or the second power supply line and the signal line. In the plurality of first transistors, first sources are disposed adjacent to each other and drains are disposed adjacent to each other in a plan view. By appropriately arranging circuit elements included in circuits that transmit or receive signals between the semiconductor chips, a decline in the characteristics of the semiconductor device can be suppressed.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Semiconductor devices having multiple semiconductor chips mounted on a single substrate and semiconductor devices having multiple stacked semiconductor chips are known. In these types of semiconductor devices, signals may be transmitted and received between the multiple semiconductor chips. Also known are semiconductor chips that are provided with I / O (Input / Output) circuits that transmit and receive signals to and from the outside.

[0003] US Patent No. 11024625 US Patent No. 10332871 US Patent Application Publication No. 2023 / 0260987 US Patent Application Publication No. 2023 / 0076856 US Patent No. 10411095

[0004] When signals are transmitted and received between a plurality of semiconductor chips mounted on a semiconductor device, sufficient consideration has not been given to what configuration an I / O circuit should have.

[0005] The present invention has been made in consideration of the above points, and aims to appropriately arrange circuit elements included in circuits that transmit or receive signals between semiconductor chips in a semiconductor device that incorporates multiple semiconductor chips, thereby suppressing deterioration in the characteristics of the semiconductor device.

[0006] In one aspect of the present invention, a semiconductor device includes a first semiconductor chip having a first circuit and a second semiconductor chip having a second circuit connected to the first circuit, the first circuit including a first power supply line, a second power supply line, a signal line connected to the second circuit, and a plurality of first transistors each having a first source and a first drain, the plurality of first transistors being arranged between the signal line and one of the first power supply line or the second power supply line in a planar view, the first source of one of the first transistors being arranged adjacent to the first source of another of the first transistors in a planar view, and the first drain of one of the first transistors being arranged adjacent to the first drain of another of the first transistors in a planar view.

[0007] According to the disclosed technology, in a semiconductor device equipped with multiple semiconductor chips, circuit elements included in a circuit that transmits or receives signals between the semiconductor chips can be appropriately arranged, thereby suppressing deterioration of the characteristics of the semiconductor device.

[0008] 9 is a cross-sectional view showing an example of a cross section of a semiconductor device to which various embodiments described in FIG. 2 and subsequent figures are applied. FIG. 10 is an explanatory diagram showing a legend for circuit elements used in plan views of the circuits shown in FIG. 3 and subsequent figures. FIG. 11 is a plan view showing an example of a circuit layout of an output circuit formed in the semiconductor device in the first embodiment. FIG. 12 is a plan view showing an example of a circuit layout of an input circuit of the semiconductor device in the first embodiment. FIG. 13 is a plan view showing a first modified example of the circuit layout of the output circuit of the semiconductor device in the first embodiment. FIG. 14 is a plan view showing a second modified example of the circuit layout of the output circuit of the semiconductor device in the first embodiment. FIG. 15 is a plan view showing a third modified example of the circuit layout of the output circuit of the semiconductor device in the first embodiment. FIG. 16 is a plan view showing a fourth modified example of the circuit layout of the output circuit of the semiconductor device in the first embodiment. FIG. 17 is a cross-sectional view showing an example of a cross section taken along line Y1-Y1' of FIG. 9. FIG. 18 is a plan view showing an example of the layout of the diode shown in FIG. 9. FIG. 19 is a plan view showing a first modified example of the circuit layout of the output circuit of the semiconductor device in the second embodiment. FIG. 19 is a plan view showing a second modified example of the circuit layout of the output circuit of the semiconductor device in the second embodiment. 20 is a plan view showing a fourth modified example of the circuit layout of the output circuit of the semiconductor device according to the second embodiment. FIG. 21 is a plan view showing an example of the circuit layout of the output circuit of the semiconductor device according to the third embodiment. FIG. 22 is a cross-sectional view showing an example of a cross section taken along line Y2-Y2' in FIG. 17. FIG. 23 is a plan view showing an example of the layout of the resistive element shown in FIG. 17. FIG. 24 is a plan view showing a first modified example of the circuit layout of the output circuit of the semiconductor device according to the third embodiment. FIG. 25 is a cross-sectional view showing an example of a cross section taken along line Y3-Y3' in FIG. 20. FIG. 26 is a plan view showing a second modified example of the circuit layout of the output circuit of the semiconductor device according to the third embodiment. FIG. 27 is a plan view showing a third modified example of the circuit layout of the output circuit of the semiconductor device according to the third embodiment. FIG. 28 is a plan view showing an example of the circuit layout of the output circuit of the semiconductor device according to the fourth embodiment. FIG. 29 is a plan view showing an example of the circuit layout of the input circuit of the semiconductor device according to the fourth embodiment.10A and 10B are diagrams illustrating an example of a circuit configuration of an output circuit of a semiconductor device according to a fifth embodiment, and another example of a circuit configuration of an output circuit of a semiconductor device according to the fifth embodiment.

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply potential is also used to indicate a power supply line or a power supply terminal to which the power supply potential is supplied.

[0010] 1 shows an example of a cross section of semiconductor devices SEM1 and SEM2 to which various embodiments described in the following figures are applied. The semiconductor device SEM1 has a wiring substrate such as an interposer INTP, and chips CP1 and CP2 mounted on the interposer INTP. Each of the chips CP1 and CP2 is electrically connected to the interposer INTP via a bump BMP.

[0011] The interposer INTP has external connection terminals EXT and wiring W that connect the external connection terminals EXT to the bumps BMP. The interposer INTP also has wiring W that connects the plurality of bumps BMP to each other. For example, the external connection terminals EXT may include a signal terminal SIG and a power supply terminal VDD1 for the chip CP1, a signal terminal OUT2 and a power supply terminal VDD2 for the chip CP2, and a ground terminal VSS common to the chips CP1 and CP2. The interposer INTP may be formed of a silicon material, an organic material, or other materials.

[0012] For example, chip CP1 has an input / output circuit IOC1 including an output terminal OUT1, and chip CP2 has an input / output circuit IOC2 having an input terminal IN2. The output terminal OUT1 of the input / output circuit IOC1 is electrically connected to the input terminal IN2 of the input / output circuit IOC2 via a bump BMP, wiring W in the interposer INTP, and another bump BMP. The chips CP1 and CP2 then transmit and receive signals via the input / output circuits IOC1 and IOC2. This type of interconnection of two chips CP1 and CP2 within a semiconductor device is sometimes called die-to-die (D2D).

[0013] 1 shows a configuration in which the input / output circuit IOC1 is an output circuit and the input / output circuit IOC2 is an input circuit, but the input / output circuit IOC1 may be an input circuit and the input / output circuit IOC2 may be an output circuit.Furthermore, the input / output circuits IOC1 and IOC2 may each have an input circuit and an output circuit.

[0014] The semiconductor device SEM2 has a wiring substrate such as an interposer INTP and chips CP1 and CP2 stacked on the interposer INTP. The chip CP1 is electrically connected to the interposer INTP via bumps BMP. The interposer INTP has external connection terminals EXT and wiring W that connects the external connection terminals EXT to the bumps BMP. For example, the external connection terminals EXT may include a signal terminal IN1, a power supply terminal VDD1, and a ground terminal VSS that are electrically connected to the chip CP1. Hereinafter, when the semiconductor devices SEM1 and SEM2 are described without distinction, they will also be referred to as the semiconductor device SEM.

[0015] The chip CP2 is connected to the chip CP1 via a via VIA such as a TSV (Through Silicon Via), and the power supply terminal VDD1 and the ground terminal VSS are also electrically connected to the chip CP2 via the chip CP1. The chip CP1 has an input / output circuit IOC1, and the chip CP2 has an input / output circuit IOC2 connected to the input / output circuit IOC1 via a via VIA. The chips CP1 and CP2 transmit and receive signals via the input / output circuits IOC1 and IOC2.

[0016] The chip CP1 is an example of either a first semiconductor chip or a second semiconductor chip, and the chip CP2 is an example of the other of the first semiconductor chip or the second semiconductor chip. The input / output circuit IOC1 is an example of either a first circuit or a second circuit, and the input / output circuit IOC2 is an example of the other of the first circuit or the second circuit. The ground line VSS is an example of either a first power supply line or a second power supply line, and the power supply line VDD is an example of the other of the first power supply line or the second power supply line.

[0017] The chips CP1 and CP2 may be arranged with the input / output circuits IOC1 and IOC2 facing each other, and in this case, the input / output circuits IOC1 and IOC2 may be connected to each other via bumps or the like.

[0018] 2 shows an example of a legend for circuit elements used in the plan views of the circuits shown in Fig. 3 and subsequent figures. The symbol "diff" attached to the vias shown as white circles indicates an N-type semiconductor layer Ndiff (N-type impurity region) or a P-type semiconductor layer Pdiff (P-type impurity region). In the circuit layouts shown in Fig. 3 and subsequent figures, the various vias VIA are hidden by the wiring in the upper layer in plan view, but are shown above the wiring for ease of viewing.

[0019] 3 shows an example of a circuit layout of the output circuit OUTC formed in the semiconductor device SEM according to the first embodiment. The output circuit OUTC is included in either the input / output circuit IOC1 of the chip CP1 or the input / output circuit IOC2 of the chip CP2 shown in FIG. 1. If the input / output circuits IOC1 and IOC2 have a signal transmission / reception function, the output circuit OUTC may be included in both the input / output circuits IOC1 and IOC2.

[0020] Referring to the circuit diagram, the output circuit OUTC includes an output transistor OTR and a protection circuit ESDC that protects the device from ESD (Electro-Static Discharge). For example, the output transistor OTR includes a CMOS (Complementary Metal Oxide Semiconductor) inverter including an NMOS transistor TN1 and a PMOS transistor TP1.

[0021] The NMOS transistor TN1 has a source connected to the ground line VSS, a drain connected to the pad Pad, and a gate electrode GT connected to the internal signal line OUT. The PMOS transistor TP1 has a source connected to the power supply line VDD, a drain connected to the signal line pad Pad, and a gate electrode GT connected to the internal signal line OUT.

[0022] Hereinafter, the NMOS transistor TN1 and the PMOS transistor TP1 will also be simply referred to as transistors TN1 and TP1, respectively, and the gate electrode GT will also be simply referred to as gate GT. The output transistor OTR may be a tristate buffer.

[0023] The protection circuit ESDC has diodes D1a and D1b connected in series between the ground line VSS and the power supply line VDD. A signal line pad Pad is connected to the output of the CMOS inverter, the cathode of diode D1a, and the anode of diode D1b. The pad Pad is electrically connected via a signal line to an input circuit formed in an input / output circuit IOC1 of another chip CP1 connected to the output circuit OUTC, or to an input circuit formed in an input / output circuit IOC2 of chip CP2. The output circuit OUTC outputs an output signal to the input circuit of the other chip CP1 or the other chip CP2 via the pad Pad. Hereinafter, the wiring connected to the pad Pad will also be referred to as a pad wiring Pad.

[0024] Referring to the layout diagram, the transistors TN1 and TP1 are arranged side by side in the Y direction. Each of the transistors TN1 and TP1 is divided into a plurality of partial transistors arranged side by side in the X direction. Hereinafter, the partial transistor included in the transistor TN1 will be referred to as the partial transistor TN1, and the partial transistor included in the transistor TP1 will be referred to as the partial transistor TP1. The partial transistor TN1 is an example of either the first transistor or the second transistor, and the partial transistor TP1 is an example of the other of the first transistor or the second transistor.

[0025] The source of each partial transistor TN1 is connected to the ground line VSS of the wiring layer M2 through a via VIA (diff-M1), a wiring W1 of the wiring layer M1, and a via VIA (M1-M2). The source of each partial transistor TN1 is connected to the pad wiring Pad of the wiring layer M2 through a via VIA (diff-M1), a wiring W1 of the wiring layer M1, and a via VIA (M1-M2).

[0026] The source of each partial transistor TP1 is connected to the power supply line VDD of the wiring layer M2 via a via VIA (diff-M1), a wire W1 of the wiring layer M1, and a via VIA (M1-M2). The source of each partial transistor TP1 is connected to the pad wiring Pad of the wiring layer M2 via a via VIA (diff-M1), a wire W1 of the wiring layer M1, and a via VIA (M1-M2).

[0027] The diodes D1a and D1b shown in the circuit diagram are arranged in an area not shown in the layout diagram. The ground line VSS, power supply line VDD, and pad wiring Pad are connected to the ground terminal VSS, power supply terminal VDD, and pad Pad, respectively, via vias and upper layer wiring (not shown). The gates GT of the partial transistors TN1 and TP1 are connected to vias and upper layer wiring (not shown).

[0028] A pair of adjacent partial transistors TN1 are arranged with their drain regions or source regions adjacent in the X direction. Similarly, a pair of adjacent partial transistors TP1 are arranged with their drain regions or source regions adjacent in the X direction. That is, in each of the plurality of partial transistors TN1 and the plurality of partial transistors TP1, the drain regions facing each other in the X direction are separated, and the source regions facing each other in the X direction are separated.

[0029] By separating the drain region and the source region, it is possible to suppress the influence of heat generated by the partial transistor TN1 on other adjacent partial transistors TN1. Similarly, it is possible to suppress the influence of heat generated by the partial transistor TP1 on other adjacent partial transistors TP1. This makes it possible to suppress a local temperature rise when the transistors TN1 and TP1 are driven.

[0030] In the die-to-die approach, the signal lines connecting the chips CP1 and CP2 are not electrically connected to the external terminals of the semiconductor device SEM, so there is no need to worry about latch-up. This eliminates the need for a guard ring for the output transistor OTR, and reduces the layout area. In the circuit layouts shown in Figures 3 and subsequent figures, one or both of the power supply line VDD and the ground line VSS may be laid out above the area where the transistors TN1 and TP1 are formed.

[0031] 4 shows an example of a circuit layout of the input circuit INC of the semiconductor device SEM according to the first embodiment. Elements similar to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. The input circuit INC is included in either the input / output circuit IOC1 of the chip CP1 or the input / output circuit IOC2 of the chip CP2 in FIG. 1. When the input / output circuits IOC1 and IOC2 have a signal transmission / reception function, the input circuit INC may be included in both the input / output circuits IOC1 and IOC2.

[0032] Referring to the circuit diagram, the input circuit INC includes an input transistor INR and a protection circuit ESDC. For example, the input transistor INR is a CMOS inverter. The transistor NP1 of the input transistor INR has a source connected to the ground line VSS, a drain connected to the internal signal line IN, and a gate GT connected to the pad Pad. The transistor TP1 of the input transistor INR has a source connected to the power supply line VDD, a drain connected to the internal signal line IN, and a gate GT connected to the pad Pad.

[0033] The pad Pad is electrically connected to an output circuit formed in the input / output circuit IOC1 of another chip CP1 connected to the input circuit INC or an output circuit formed in the input / output circuit IOC2 of the chip CP2. The input circuit INC receives an input signal from the output circuit of the other chip CP1 or the other chip CP2 via the pad Pad.

[0034] 3 in which the pad wiring Pad is connected to the drain, except that the pad wiring Pad is connected to the gate GT of each partial transistor TN1 and the gate GT of each partial transistor TP1. That is, in the input circuit INC as well, in the plurality of partial transistors TN1, the drain regions opposing each other in the X direction are separated, and the source regions opposing each other in the X direction are separated. In the plurality of partial transistors TP1, the drain regions opposing each other in the X direction are separated, and the source regions opposing each other in the X direction are separated.

[0035] This makes it possible to suppress the influence of heat generated by the partial transistor TN1 on other adjacent partial transistors TN1 in the input circuit INC, and to suppress the influence of heat generated by the partial transistor TP1 on other adjacent partial transistors TN1, thereby suppressing a local temperature rise when the transistors TN1 and TP1 are driven.

[0036] The layouts of the input circuit INC and the output circuit OUTC are similar except for the connection destinations of the pad wiring Pad, and therefore the layout of the output circuit OUTC shown in Figure 5 and subsequent figures can also be applied to the input circuit INC. Similarly, the layout of the input circuit INC shown in Figure 5 and subsequent figures can also be applied to the output circuit OUTC.

[0037] 5 shows a first modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the first embodiment. Elements similar to those in FIG. 3 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted. In the layout diagram, the source (Ndiff) of a pair of central partial transistors TN1 arranged side by side in the X direction is shared and connected to the ground line VSS via a common wiring W1 in the wiring layer M1. The source (Pdiff) of a pair of central partial transistors TP1 arranged side by side in the X direction is shared and connected to the power supply line VDD via a common wiring W1 in the wiring layer M1. The rest of the layout is the same as in FIG. 3.

[0038] By sharing the sources of the adjacent partial transistors TN1 and TP1, the area of ​​the output transistor OUTC can be made smaller than the area of ​​the output circuit OUTC in Fig. 3. Note that the source of the transistor is electrically connected to the back gate of the transistor and electrically isolated from the node of the pad Pad, so that the parasitic capacitance related to the node of the pad Pad does not change.

[0039] On the other hand, the heat generated by the plurality of partial transistors TN1 that share the semiconductor layer Ndiff is transferred to each other, and the heat generated by the partial transistors TP1 that share the semiconductor layer Pdiff is transferred to each other. However, if the temperature rise due to the operation of the output circuit OUTC is kept below the upper limit of the temperature specification of the semiconductor device SEM (for example, if the operation frequency of the output circuit OUTC is low), there is no problem even if the source region is shared.

[0040] 6 shows a second modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the first embodiment. While FIGS. 3 to 5 show layouts of planar transistors, FIG. 6 shows a FinFET (Field Effect Transistor) or nanosheet transistor. Therefore, the source and drain of the partial transistor TN1 are interconnected by a fin FIN or nanosheet NS, and a channel is formed by the fin FIN or nanosheet NS in the gate GT. Similarly, the source and drain of the partial transistor TP1 are interconnected by a fin FIN or nanosheet NS, and a channel is formed by the fin FIN or nanosheet NS in the gate GT.

[0041] 6, the partial transistor TN1 and the partial transistor TP1 have four fins FIN or nanosheets NS aligned in the Y direction, but they may have one or a number other than four. In other embodiments or modifications, a FinFET or nanosheet transistor can be used instead of a planar transistor, and even in this case, the partial transistor TN1 and the partial transistor TP1 have one or more fins FIN or nanosheet NS. In addition, in the case of a FinFET or nanosheet transistor, the wiring connected to the source and drain may be called local wiring.

[0042] 7 shows a third modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the first embodiment. Elements similar to those in FIG. 3 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. As shown in the circuit diagram, the output transistor OTR of the output circuit OUTC shown in FIG. 7 has cascaded NMOS transistors TN1 and TN2 and cascaded PMOS transistors TP1 and TP2. The circuit configuration other than the transistors is the same as that of the output circuit OUTC shown in FIG. 3.

[0043] Hereinafter, the NMOS transistors TN1 and TN2 and the PMOS transistors TP1 and TP2 will also be simply referred to as transistors TN1 and TN2 and transistors TP1 and TP2, respectively. Furthermore, parts of the NMOS transistors TN1 and TP2 and parts of the PMOS transistors TP1 and TP2 will be referred to as partial transistors TN1 and TN2 and partial transistors TP1 and TP2, respectively.

[0044] Referring to the layout diagram, four pairs of cascaded partial transistors TN1 and TN2 are arranged side by side in the X direction, and the partial transistors TN1 and TN2 of each pair are arranged side by side in the Y direction. Similarly, four pairs of cascaded partial transistors TP1 and TP2 are arranged side by side in the X direction, and the partial transistors TP1 and TP2 of each pair are arranged side by side in the Y direction.

[0045] Two pairs of adjacent partial transistors TN1 and TN2 are arranged with their drain regions facing each other in the X direction and their source regions facing each other in the X direction. Similarly, two pairs of adjacent partial transistors TP1 and TP2 are arranged with their drain regions facing each other in the X direction or their source regions facing each other in the X direction. This makes it possible to prevent the heat generated by the partial transistors TN1 and TN2 from affecting the other adjacent partial transistors TN1 and TN2, as in FIG. 3 . Similarly, it is possible to prevent the heat generated by the partial transistors TP1 and TP2 from affecting the other adjacent partial transistors TP1 and TP2. Therefore, it is possible to prevent a local temperature rise when the transistors TN1 and TP1 are driven.

[0046] 8 shows a fourth modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the first embodiment. The same elements as those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the output circuit OUTC shown in FIG. 8, the output transistor OTR has cascaded NMOS partial transistors TN1 and TN2 and cascaded PMOS partial transistors TP1 and TP2, similar to FIG. 7.

[0047] 8, the drains (semiconductor layer Ndiff) of the pair of central partial transistors TN1 arranged side by side in the X direction are shared, and the drains (semiconductor layer Ndiff) of the pair of central partial transistors TN2 arranged side by side in the X direction are shared, as in the case of FIG. 5. Similarly, the drains (semiconductor layer Pdiff) of the pair of central partial transistors TP1 arranged side by side in the X direction are shared, and the sources (semiconductor layer Pdiff) of the pair of central partial transistors TP2 arranged side by side in the X direction are shared.

[0048] At an intermediate node (semiconductor layer Ndiff) connecting the transistors TN1 and TN2 to each other, a pair of two partial transistors TN1 aligned in the X direction are arranged adjacent to each other, and a pair of two partial transistors TN2 aligned in the X direction are arranged adjacent to each other. The intermediate node of the partial transistor TN1 is connected to the intermediate node of the partial transistor TN2 using a via VIA (Ndiff-M1) and a wire W1 of the wiring layer M1.

[0049] Similarly, the intermediate node (semiconductor layer Pdiff) connecting the transistors TP1 and TP2 is arranged such that a pair of two partial transistors TP1 aligned in the X direction are adjacent to each other, and a pair of two partial transistors TP2 aligned in the X direction are adjacent to each other. The intermediate node of the partial transistor TP1 is connected to the intermediate node of the partial transistor TP2 using a via VIA (Ndiff-M1) and a wire W1 of the wiring layer M1.

[0050] 8, the cascade transistor pairs, each consisting of a pair of partial transistors TN1 and a pair of partial transistors TN2, whose sources and drains are shared, are arranged only in the center in the X direction. However, two cascade transistor pairs, each consisting of a pair of partial transistors TN1 and a pair of partial transistors TN2, may be arranged side by side in the X direction. Similarly, two cascade transistor pairs, each consisting of a pair of partial transistors TP1 and a pair of partial transistors TP2, may be arranged side by side in the X direction. Furthermore, the circuit layouts of cascade-connected transistors shown in FIGS. 7 and 8 may be applied to the circuit layouts shown in FIG. 9 and subsequent figures.

[0051] As described above, in the first embodiment, the transistors TN1 are arranged so that the drain regions and source regions of the plurality of partial transistors TN1 arranged in the X direction are adjacent to each other, and the transistors TP1 are arranged so that the drain regions and source regions of the plurality of partial transistors TP1 arranged in the X direction are adjacent to each other.

[0052] This makes it possible to suppress the influence of heat generated by the partial transistor TN1 on other adjacent partial transistors TN1. Similarly, it makes it possible to suppress the influence of heat generated by the partial transistor TP1 on other adjacent partial transistors TP1. As a result, it is possible to suppress a local increase in temperature when the transistors TN1 and TP1 are driven, and it is possible to suppress a deterioration in the characteristics of the semiconductor device SEM.

[0053] For example, when semiconductor chips CP1 and CP2 mounted on the semiconductor device SEM are stacked, the stacking may result in a decrease in the heat dissipation performance of the entire semiconductor device SEM. However, by suppressing a local temperature increase, it is possible to suppress a decrease in the characteristics of the semiconductor device SEM even when the heat dissipation performance is decreased.

[0054] Second Embodiment Fig. 9 shows an example of a circuit layout of an output circuit OUTC of a semiconductor device SEM according to a second embodiment. Elements similar to those in Fig. 3 are given the same reference numerals, and detailed descriptions thereof will be omitted. The circuit layout shown in Fig. 9 is similar to the circuit layout shown in Fig. 3, except that it includes diodes D1a and D1b.

[0055] The diode D1a is disposed between the pad wiring Pad and the transistor TN1, and the diode D1b is disposed between the pad wiring Pad and the transistor TP1. The diodes D1a and D1b each have an elongated shape extending in the X direction. The diode D1a is an example of either a first diode or a second diode, and the diode D1b is an example of the other of the first diode or the second diode.

[0056] The semiconductor layer Pdiff (anode) of the diode D1a is connected to the source of the partial transistor TN1 using a via VIA (diff-M1) and a wiring W1 of the wiring layer M1, and is further connected to the ground line VSS of the wiring layer M2 using a via VIA (M1-M2). The semiconductor layer Ndiff (cathode) of the diode D1a is connected to the drain of the partial transistor TN1 using a via VIA (diff-M1) and a wiring W1 of the wiring layer M1, and is further connected to the pad wiring Pad of the wiring layer M2 using a via VIA (M1-M2).

[0057] The semiconductor layer Ndiff (cathode) of the diode D1b is connected to the source of the partial transistor TP1 using a via VIA (diff-M1) and a wiring W1 of the wiring layer M1, and is further connected to the power supply line VDD using a via VIA (M1-M2). The semiconductor layer Pdiff (anode) of the diode D1b is connected to the drain of the partial transistor TP1 using a via VIA (diff-M1) and a wiring W1 of the wiring layer M1, and is further connected to the pad wiring Pad of the wiring layer M2 using a via VIA (M1-M2). One or both of the power supply line VDD and the ground line VSS may be laid out above the region where the transistors TN1 and TP1 are formed or above the region where the diodes D1a and D1b are formed.

[0058] 1, in the die-to-die output circuit OUTC in which the signal lines connecting between the chips CP1 and CP2 are not electrically connected to the external terminals of the semiconductor device SEM, the capability (scale) of the protection circuit ESDC can be made smaller than in a chip that outputs signals to the external terminals of the semiconductor device SEM. Therefore, as shown in FIG. 9, the layout area of ​​the diodes D1a and D1b that function as the protection circuit ESDC can be made smaller than the layout area of ​​the diodes mounted in the protection circuit ESDC of the output circuit that outputs signals to the external terminals. As a result, the output transistor OTR and the protection circuit ESDC can be arranged efficiently.

[0059] By making the diodes D1a and D1b elongated and extending in the X direction, the distance from the pad wiring Pad to each transistor TN1 and TP1 can be prevented from becoming long, and an increase in the parasitic capacitance of the pad wiring Pad can be prevented.

[0060] 10 shows an example of a cross section taken along line Y1-Y1' in FIG. 9. For example, the semiconductor layer Ndiff of transistor TN1, the semiconductor layer Ndiff of diode D1a, the semiconductor layer Pdiff of diode D1b, and the semiconductor layer Pdiff of transistor TP1, which are formed in a P-type substrate SUB, are connected to wiring W1 through vias VIA. The semiconductor layer Pdiff of each diode D1a and the semiconductor layer Ndiff of diode D1b are connected through the P-type substrate SUB to form a P / N junction. The semiconductor layer Pdiff of transistor TP1 is connected to the substrate SUB through an N-type well region NW. The wiring W1 is connected to an upper wiring pad Pad through a via VIA.

[0061] 10 shows an example in which a planar transistor manufacturing process is used, but as shown in the lower part of FIG. 10, a FinFET manufacturing process may also be used. In this case, the transistors TN1 and TP1 and the diodes D1a and D1b are formed using fins FIN made of semiconductor material protruding from the substrate SUB. The local wiring LI formed on the fin FIN is connected to the wiring W1 through a via VIA, and is further connected to the upper layer wiring pad PAD through the via VIA. The local wiring LI is formed using a wiring layer between the substrate SUB and the wiring W1 of the wiring layer M1.

[0062] 11 shows an example of the layout of the diodes D1a and D1b shown in Fig. 9. As described in Fig. 10, each of the diodes D1a and D1b has a P / N junction formed between a P-type semiconductor layer Pdiff and an N-type semiconductor layer Ndiff via a P-type substrate SUB. While Fig. 9 shows an example in which the diodes D1a and D1b are formed extending in the X direction, the diodes D1a and D1b may also be formed extending in the Y direction.

[0063] The diodes D1 a and D1 b may be formed using a FinFET manufacturing process. In this case, due to manufacturing constraints that the gates GT are included in the diodes D1 a and D1 b, it is necessary to align the extension direction of the fins FIN and the arrangement direction of the gates GT with the arrangement direction of the FinFETs.

[0064] 12 shows a first modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the second embodiment. The same elements as those in FIGS. 3 and 9 are denoted by the same reference numerals, and detailed description thereof will be omitted. The circuit layout shown in FIG. 12 is the same as the circuit layout shown in FIG. 9 except that, in a plan view, the diodes D1a and D1b are arranged so as to partially overlap with the pad wiring Pad. Note that, if the width of the pad wiring Pad in the Y direction is large, the entire regions of the diodes D1a and D1b arranged in the Y direction may be laid out in a position overlapping with the pad wiring Pad.

[0065] By overlapping the diodes D1a and D1b with the pad wiring Pad in a plan view, the layout area of ​​the output circuit OUTC can be made smaller than in Fig. 9, and the output transistor OTR and the protection circuit ESDC can be arranged more efficiently. In addition, since the distance from the pad wiring Pad to each of the transistors TN1 and TP1 can be made smaller than in Fig. 9, an increase in the parasitic capacitance of the pad wiring Pad can be further suppressed.

[0066] 13 shows a second modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the second embodiment. The same elements as those in FIGS. 3 and 9 are denoted by the same reference numerals, and detailed description thereof will be omitted. The circuit layout shown in FIG. 13 is the same as the circuit layout shown in FIG. 9 except that the diodes D1a and D1b are arranged side by side in the X direction and are positioned so as to overlap the pad wiring Pad in plan view.

[0067] By completely overlapping the diodes D1a and D1b with the pad wiring Pad in a plan view, the layout area of ​​the diodes D1a and D1b can be made substantially zero. As a result, the layout area of ​​the output circuit OUTC can be made smaller than that of FIG. 12, and the output transistor OTR and the protection circuit ESDC can be arranged more efficiently. In addition, since the distance from the pad wiring Pad to each of the transistors TN1 and TP1 can be made smaller than that of FIG. 12, an increase in the parasitic capacitance of the pad wiring Pad can be further suppressed.

[0068] 14 shows an example of a circuit layout of the input circuit INC of the semiconductor device SEM according to the second embodiment. Elements similar to those in FIGS. 3 and 9 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. In the input circuit INC, the pad wiring Pad is electrically connected to the gates GT of the transistors TN1 and TP1. Therefore, the connection between the cathode of the diode D1a and the gate GT of the partial transistor TN1 can be made using the wiring connected to the gate GT of the transistor TN1. The connection between the anode of the diode D1b and the gate GT of the partial transistor TP1 can be made using the wiring connected to the gate GT of the transistor TP1.

[0069] 14, two diodes D1a extending in the Y direction are arranged side by side adjacent to each other in the X direction in the region where transistor TN1 is arranged. Also, two diodes D1b extending in the Y direction are arranged side by side adjacent to each other in the X direction in the region where transistor TP1 is arranged. In this case, the diodes D1a and D1b may be arranged in positions where they partially overlap with the pad wiring Pad in a plan view.

[0070] The diode D1a may be arranged between the partial transistors TN1 arranged in the X direction, and the diode D1b may be arranged between the partial transistors TP1 arranged in the X direction. By arranging the diode D1a between the partial transistors TN1 and the diode D1b between the partial transistors TP1, the distance to the partial transistor TN1, which is a heat source, can be increased, and the distance to the partial transistor TP1 can be increased. As a result, the temperature rise of the input circuit INC can be suppressed.

[0071] 15 shows a third modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the second embodiment. Elements similar to those in FIGS. 3 and 14 are given the same reference numerals, and detailed description thereof will be omitted.

[0072] 15, as in Fig. 14, two diodes D1a extending in the Y direction are arranged side by side adjacent to each other in the X direction in the region where transistor TN1 is arranged, and two diodes D1b extending in the Y direction are arranged side by side adjacent to each other in the X direction in the region where transistor TP1 is arranged. Parts of diodes D1a and D1b may be arranged at positions overlapping with pad wiring Pad.

[0073] The layout area of ​​the diodes D1a and D1b mounted in the die-to-die input circuit INC and output circuit OUTC can be made smaller than the layout area of ​​the diodes mounted in the protection circuit ESDC of the chip that outputs signals to the external terminals. Furthermore, when the diodes D1a and D1b are formed using a planar transistor manufacturing process, unlike when a FinFET manufacturing process is used, there are no restrictions on the extension direction of the fins FIN and the arrangement direction of the gates GT. Therefore, for example, by arranging the vertically elongated diodes D1a and D1b extending in the Y direction to match the Y-direction lengths of the transistors TN1 and TP1, the available space can be effectively utilized.

[0074] 16 shows a fourth modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the second embodiment. The same elements as those in FIGS. 3, 11, and 15 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0075] The output circuit OUTC shown in FIG. 16 has a layout similar to that of the output circuit OUTC shown in FIG. 15 , except that the transistors TN1 and TP1 and the diodes D1a and D1b are formed using a FinFET manufacturing process. The FinFETs of the transistors TN1 and TP1, as well as the wiring and vias connected to the FinFETs, are omitted. For example, in FIG. 16 , six diodes D1a and D1b formed using the FinFET manufacturing process shown in FIG. 11 are arranged adjacent to the arrangement area of ​​the transistors TN1 and TP1 in the X direction. A portion of the diodes D1a and D1b may be arranged overlapping the pad wiring Pad. In FIG. 16 , the diodes D1a and D1b are arranged vertically extending in the Y direction, thereby making effective use of available space.

[0076] As described above, the second embodiment can also achieve the same effects as the first embodiment. For example, it is possible to suppress the influence of heat generated by the partial transistor TN1 on other adjacent partial transistors TN1, and it is possible to suppress the influence of heat generated by the partial transistor TP1 on other adjacent partial transistors TP1. As a result, it is possible to suppress a local increase in temperature when the transistors TN1 and TP1 are driven, and it is possible to suppress a deterioration in the characteristics of the semiconductor device SEM.

[0077] Furthermore, in the second embodiment, by taking advantage of the die-to-die technique, which can reduce the layout area of ​​the diodes D1a and D1b that function as the protection circuit ESDC, the diodes D1a and D1b, which have a small layout area, can be arranged between the transistors TN1 and TP1 and the pad wiring Pad, or can be arranged so as to overlap the pad wiring Pad. Alternatively, the diodes D1a and D1b can be arranged adjacent to the arrangement area of ​​the transistors TN1 and TP1 in the X direction. As a result, the output transistor OTR or the input transistor and the protection circuit ESDC can be arranged efficiently.

[0078] 17 shows an example of a circuit layout of an output circuit OUTC of a semiconductor device SEM according to a third embodiment. Elements similar to those in FIGS. 3 and 9 are given the same reference numerals, and detailed description thereof will be omitted.

[0079] Referring to the circuit diagram, the output circuit OUTC has a resistor Rsn arranged between the pad Pad and the drain of the transistor TN1, and a resistor Rsp arranged between the pad Pad and the drain of the transistor TP1. The resistor Rsn is connected to the drain of the transistor TN1 via a node NA, and the resistor Rsp is connected to the drain of the transistor TP1 via a node NB. The rest of the configuration of the output circuit OUTC is similar to that of the output circuit OUTC in FIG. 9, except that the ground line VSS for the diode D1a and the power supply line VDD for the diode D1b are formed using the wiring layer M2.

[0080] Referring to the layout diagram, the resistor element Rsn is arranged between the transistor TN1 and the diode D1a. For example, the resistor element Rsn has ten partial resistor elements, two of which are connected in parallel. Hereinafter, the partial resistor element of the resistor element Rsn will also be referred to as the partial resistor element Rsn. The partial resistor element Rsn is an example of either the first resistor element or the second resistor element.

[0081] The two parallel-connected partial resistor elements Rsn are also referred to as a partial resistor element pair Rsn. One end of the partial resistor element pair Rsn is connected to the drain of each partial transistor TN1 via the wiring W1 and the wiring NA of the node NA. The other end of the partial resistor element pair Rsn is connected to the cathode of the diode D1a and the pad wiring Pad via the wiring W1.

[0082] The resistor element Rsp is arranged between the plurality of partial transistors TP1 and the diode D1b. For example, the resistor element Rsp has ten partial resistor elements, two of which are connected in parallel. Hereinafter, the partial resistor element of the resistor element Rsp will also be referred to as the partial resistor element Rsp. The partial resistor element Rsp is an example of the other of the first resistor element or the second resistor element.

[0083] The two parallel-connected partial resistor elements Rsp are also referred to as a partial resistor element pair Rsp. One end of the partial resistor element pair Rsp is connected to the drain of each partial transistor TP1 via the wiring W1 and the wiring NB of the node NB. The other end of the partial resistor element pair Rsp is connected to the anode of the diode D1b and the pad wiring Pad via the wiring W1.

[0084] For example, each of the partial resistor elements Rsn and Rsp is formed using poly-Si, which is the material of the gate GT, and is connected to the wiring W1 of the wiring layer M1 through a via VIA. Note that each of the partial resistor elements Rsn and Rsp may also be formed using wiring of the wiring layer M2 or M3, etc.

[0085] Above the region (Z direction) overlapping with the resistor Rsn and the diode D1a in plan view, a ground line VSS is formed using the wiring layer M2. The anode of the diode D1a is connected to the ground line VSS above the diode D1a in plan view through a via VIA (diff-M1), a wiring W1, and a via VIA (M1-M2). The cathode of the diode D1a is connected to the wiring W1 extending in the Y direction through a via VIA (diff-M1).

[0086] A power supply line VDD is formed using the wiring layer M2 above the region overlapping with the resistor element Rsp and the diode D1b in plan view (in the Z direction). The cathode (Ndiff) of the diode D1b is connected to the power supply line VDD above the diode D1b in plan view through a via VIA (diff-M1), a wiring W1, and a via VIA (M1-M2). The anode (Pdiff) of the diode D1b is connected to the wiring W1 extending in the Y direction through a via VIA (diff-M1).

[0087] The anode of the diode D1a may be connected to a ground line VSS wired at the end in the direction opposite to the Y direction. In this case, the ground line VSS is not provided above the resistive element Rsn and the diode D1a in plan view, but instead a wire W1 extending in the Y direction is provided to connect the anode of the diode D1a to the ground line VSS located at the end in the direction opposite to the Y direction.

[0088] Similarly, the cathode of the diode D1b may be connected to the power supply line VDD wired at the end in the Y direction. In this case, the power supply line VDD is not provided above the resistive element Rsp and the diode D1b in plan view, but instead a wire W1 extending in the Y direction is provided to connect the cathode of the diode D1b to the power supply line VDD at the end in the Y direction.

[0089] 13, the diodes D1a and D1b may be arranged at positions overlapping the pad wiring Pad in plan view. Furthermore, as in Fig. 15, the diode D1a may be arranged adjacent to the region in which the transistor TN1 is arranged in the X direction, and the diode D1b may be arranged adjacent to the region in which the transistor TP1 is arranged in the X direction.

[0090] By providing the resistor elements Rsn and Rsp in an area other than on the transistors TN1 and TP1, the area where heat is generated by the resistor elements Rsn and Rsp and the area where heat is generated by the transistors TN1 and TP1 can be dispersed, thereby suppressing local temperature increases. The circuit layout shown in FIG. 17 may be applied to the input circuit INC.

[0091] Fig. 18 shows an example of a cross section taken along line Y2-Y2' in Fig. 17. Detailed description of the layout similar to that of Fig. 10 will be omitted. In Fig. 18, a resistive element Rsn is arranged between diode D1a and transistor TN1, and a resistive element Rsp is arranged between diode D1b and transistor TP1. In addition, a ground line VSS and a line NA, and a power supply line VDD and a line NB are arranged on both sides of pad wiring Pad in the X direction, respectively.

[0092] 19 shows an example of the layout of the resistor elements Rsn and Rsp shown in FIG. 17. The resistor elements Rsn and Rsp may be formed in a zigzag pattern using multiple wires in multiple wiring layers. In this case, for example, multiple wires W2 extending in the Y direction and arranged in the X direction may be connected to multiple wires W3 extending in the X direction by vias. One end and the other end of the zigzag wiring shape are connected to a pad wiring Pad (not shown) and the drain of the transistor TP1 (or TN1), respectively. Note that the wires forming the resistor elements Rsn and Rsp may be other than the wires W2 and W3.

[0093] Furthermore, the resistor elements Rsn and Rsp may be formed in a zigzag pattern using poly-Si wiring and wiring in a wiring layer. In this case, for example, a plurality of poly-Si wirings extending in the Y direction and arranged in the X direction may be connected to a plurality of wirings W2 extending in the X direction by vias. To make the drawing easier to understand, the vias (white circles) connecting the poly-Si wiring to wiring W1 and the vias (black circles) connecting wiring W1 (not shown) to wiring W2 are shown shifted from each other.

[0094] One end and the other end of the zigzag wiring (poly-Si wiring in this example) are connected to a pad wiring Pad (not shown) and the drain of the transistor TP1 (or TN1), respectively. Note that the wiring connecting the poly-Si wiring forming the resistance elements Rsn and Rsp may be other than the wiring W2.

[0095] In FIG. 19 , the resistor elements Rsn and Rsp are formed using wiring above and below the wiring W1 in a plan view. However, they may be formed using only the wiring W1 or only other wiring, or may be formed using three or more layers of wiring. The resistor elements Rsn and Rsp may have a shape other than a zigzag shape. Furthermore, the zigzag resistor elements Rsn and Rsp may be formed using multiple wirings (including poly-Si wirings) extending in the X direction and arranged in the Y direction. The poly-Si wiring may be formed in the same process as the conductor used in the gate electrode of the transistor. If the gate electrode of the transistor is made of metal, a metal pattern formed in the same process as the gate electrode may be used instead of the poly-Si wiring.

[0096] 20 shows a first modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the third embodiment. Elements similar to those in FIG. 17 are given the same reference numerals, and detailed descriptions thereof will be omitted. Note that in the layout diagrams from FIG. 20 onward, the main circuit elements of the circuit elements shown in FIG. 2 are shown as examples.

[0097] Referring to the layout diagram, the resistor elements Rsn and Rsp are arranged above the region where the diodes D1a and D1b and the pad wiring Pad are formed in a plan view. For example, the resistor elements Rsn and Rsp are formed using the wiring W4 of the wiring layer M4. Note that the resistor elements Rsn and Rsp may be formed using wiring other than the wiring W4 of the wiring layer M4.

[0098] For example, the resistor elements Rsn are connected in series in pairs along the Y direction, forming four partial resistor element pairs Rsn arranged in the X direction. One end of each partial resistor element pair Rsn is connected to the drain of each partial transistor TN1 via a via VIA (M3-M4), a wiring W3, a via VIA (M2-M3), a wiring NA (M2), a via VIA (M1-M2), a wiring W1 (M1), and a via VIA (diff-M1). The other end of each partial resistor element pair Rsn is connected to the pad wiring Pad via a via VIA (M3-M4), a wiring W3, a via VIA (M2-M3), a wiring W2, and a via VIA (M1-M2). Note that the via VIA (M3-M4) is shown extending beyond the wiring W3 in the X direction for ease of viewing.

[0099] For example, the resistor elements Rsp are connected in series in pairs along the Y direction, forming four partial resistor element pairs Rsp arranged in the X direction. One end of each partial resistor element pair Rsp is connected to the drain of each partial transistor TP1 via a via VIA (M3-M4), a wiring W3, a via VIA (M2-M3), a wiring NB (M2), a via VIA (M1-M2), a wiring W1 (M1), and a via VIA (diff-M1). The other end of each partial resistor element pair Rsp is connected to the pad wiring Pad via a via VIA (M3-M4), a wiring W3, a via VIA (M2-M3), a wiring W2, and a via VIA (M1-M2).

[0100] When the resistor elements Rsn and Rsp are formed by wiring in a wiring layer, the resistor elements Rsn and Rsp can be arranged on one or both of the transistors TN1 and TP1 and the diodes D1a and D1b, thereby reducing the layout area of ​​the output circuit OUTC. The diodes D1a and D1b are not involved in the operation of the output circuit OUTC and do not generate heat. Therefore, when the resistor elements Rsn and Rsp, which generate heat, are arranged on the diodes D1a and D1b, local temperature increases during operation of the transistors TN1 and TP1 can be prevented. The circuit layout shown in FIG. 20 may also be applied to the input circuit INC.

[0101] 21 shows an example of a cross section taken along line Y3-Y3' in FIG. 20. Elements similar to those in FIG. 18 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 21, resistive elements Rsn and Rsp are formed using wiring in wiring layer M4. Resistive elements Rsn and Rsp are connected to pad wiring Pad via via VIA (M3-M4), wiring W3 in wiring layer M3, and other wiring and via VIA (not shown), and are connected to the drain of transistor TN1 (or TP1).

[0102] 22 shows a second modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the third embodiment. Elements similar to those in FIG. 20 are designated by the same reference numerals, and detailed description thereof will be omitted. In FIG. 22, the resistive element Rsn is formed above the region where the transistor TN1 is formed in a plan view, and the resistive element Rsp is formed above the region where the transistor TP1 is formed in a plan view. For example, the resistive elements Rsn and Rsp are formed using the wiring W4 of the wiring layer M4. The resistive elements Rsn and Rsp may also be formed using wiring other than the wiring W4 of the wiring layer M4.

[0103] In Figure 22, there is no need for an area to place resistive elements Rsn and Rsp between transistors TN1 and TP1, so the length of the output circuit OUTC in the Y direction can be made smaller than in Figure 20, and the layout area of ​​the output circuit OUTC can be made even smaller than in Figure 20.

[0104] Note that the transistors TN1 and TP1 and the resistor elements Rsn and Rsp both generate heat themselves, which may result in localized temperature increases. However, if the temperature increase due to the operation of the output circuit OUTC is kept below the upper limit of the temperature specification of the semiconductor device SEM (for example, if the operation frequency of the output circuit OUTC is low), there is no problem even if the transistor TN1 and the resistor element Rsn are arranged overlapping each other in a planar view, and the transistor TP1 and the resistor element Rsp are arranged overlapping each other in a planar view. Note that the circuit layout shown in FIG. 22 may be applied to the input circuit INC.

[0105] 23 shows a third modified example of the circuit layout of the output circuit OUTC of the semiconductor device SEM according to the third embodiment. The same elements as those in FIG. 22 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 23, similarly to FIG. 15, the diode D1a is arranged adjacent in the X direction to the region in which the transistor TN1 is arranged, and the diode D1b is arranged adjacent in the X direction to the region in which the transistor TP1 is arranged.

[0106] The diode D1a may be arranged between the partial transistors TN1 arranged in the X direction, and the diode D1b may be arranged between the partial transistors TP1 arranged in the X direction. By arranging the diode D1a between the partial transistors TN1 and the diode D1b between the partial transistors TP1, the distance between the partial transistors TN1, which are heat sources, can be increased, and the distance between the partial transistors TN1 can be increased. As a result, the temperature rise of the output circuit OUTC can be suppressed. The circuit layout shown in FIG. 23 may also be applied to the input circuit INC.

[0107] As described above, the third embodiment can also achieve the same effects as the first and second embodiments. For example, it is possible to suppress the influence of heat generated by the partial transistor TN1 on other adjacent partial transistors TN1, and it is possible to suppress the influence of heat generated by the partial transistor TP1 on other adjacent partial transistors TP1. As a result, it is possible to suppress a local increase in temperature when the transistors TN1 and TP1 are driven, and it is possible to suppress a deterioration in the characteristics of the semiconductor device SEM.

[0108] Furthermore, the diodes D1a and D1b, which have a small layout area, can be arranged between the transistors TN1 and TP1 and the pad wiring Pad, or can be arranged adjacent to the arrangement area of ​​the transistors TN1 and TP1 in the X direction. As a result, the output transistor OTR or the input transistor and the protection circuit ESDC can be arranged efficiently.

[0109] 17 and 20, by arranging the resistor elements Rsn and Rsp in an area other than on the transistors TN1 and TP1, it is possible to separate the area where heat is generated by the resistor elements Rsn and Rsp from the area where heat is generated by the transistors TN1 and TP1. As a result, it is possible to suppress a local increase in temperature in the output circuit OUTC or the input circuit INC.

[0110] Furthermore, by arranging the resistive elements Rsn and Rsp in a position that overlaps with the pad wiring Pad or the diodes D1a and D1b, which do not generate heat, in a planar view, it is possible to reduce the layout area of ​​the output circuit OUTC or the input circuit INC while making it less likely that a local temperature rise will occur when the transistors TN1 and TP1 are driven.

[0111] 24 shows an example of a circuit layout of an output circuit OUTC of a semiconductor device SEM according to a fourth embodiment. Elements similar to those in FIGS. 9 and 17 are given the same reference numerals, and detailed description thereof will be omitted.

[0112] Referring to the circuit diagram, the output circuit OUTC has a resistive element Rs arranged between the drains of the transistors TN1 and TP1 and the pad Pad, instead of the resistive elements Rsn and Rsp shown in Fig. 23. Other circuit configurations of the output circuit OUTC are the same as those in Fig. 23.

[0113] 24, for example, the resistance element Rs is formed using poly-Si, which is the material of the gate GT, but it may also be formed using wiring in lower layers such as wiring layers M1 and M2. For example, the resistance element Rs is formed by connecting 16 partial resistance elements in groups of four in parallel. Hereinafter, the partial resistance elements of the resistance element Rs will also be referred to as partial resistance element Rs.

[0114] Referring to the layout diagram, the diode D1a, pad wiring Pad, diode D1b, resistor element Rs, power supply line VDD, transistors TP1 and TN1, and ground line VSS are arranged along the Y direction. The positional relationship between the diode D1a, pad wiring Pad, and diode D1b is the same as in Fig. 9, but in Fig. 24, the pad wiring Pad is formed using wiring W4 of wiring layer M4. Furthermore, the ground line VSS is arranged above the diode D1a in plan view using the wiring layer M4, and the power supply line VDD is arranged above the diode D1b in plan view using the wiring layer M4.

[0115] The transistors TN1 and TP1 are arranged adjacent to each other without a pad wiring Pad in between. The arrangement order of the power supply line VDD and the ground line VSS by the wiring layer M2 and the transistors TN1 and TP1 in the Y direction is reversed from that in Figure 9. The transistor TP1 is divided into four partial transistors TP1 arranged in the X direction. The transistor TN1 is divided into four partial transistors TN1 arranged in the X direction.

[0116] The drains of the partial transistors TN1 and TP1 arranged in the Y direction are connected to one end of the four partial resistor elements RS arranged in the Y direction via a via VIA (diff-M1), wiring W1, and a via VIA (GT-M1). The other ends of the four partial resistor elements RS arranged in the Y direction are connected to the anode (Pdiff) of the diode D1b and the cathode (Ndiff) of the diode D1a via a via VIA (GT-M1), wiring W1, a via VIA (M1-M2), wiring W2, a via VIA (M2-M3), and wiring W3, and are further connected to a pad wiring Pad formed in the wiring layer M4 via a via VIA (M3-M4). Note that in FIG. 24, the black circle via VIA (M1-M2) and the square via VIA (M2-M3) arranged at the other end of the partial resistor elements RS are shown overlapping.

[0117] The cathode of the diode D1b is connected to the power supply line VDD formed in the wiring layer M4 through a via VIA (diff-M1), a wiring W1, a via VIA (M1-M2), a wiring W2, a via VIA (M2-M3), a wiring W3, and a via VIA (M3-M4). Note that the via VIA (M3-M4) is not shown.

[0118] The anode of the diode D1a is connected to the ground line VSS formed in the wiring layer M4 through the via VIA (diff-M1), the wiring W1, the via VIA (M1-M2), the wiring W2, the via VIA (M2-M3), the wiring W3, and the via VIA (M3-M4). Note that the via VIA (M3-M4) is not shown.

[0119] When the resistive element Rs is formed using poly-Si, which is the material of the gate GT, or the wiring W1, W2, etc., of the lower wiring layers M1, M2, the output circuit OUTC can be formed using the layout shown in FIG. 24. For example, when the resistive element Rs is formed using the wiring W1, the via VIA (GT-M1) is unnecessary. Furthermore, the Y-direction arrangement order of the ground line VSS, transistors TN1, TP1, and power supply line VDD may be reversed. The Y-direction arrangement order of the diode D1a and the ground line VSS of the wiring layer M4 and the diode D1b and the power supply line VDD of the wiring layer M4 may also be reversed. The circuit layout shown in FIG. 24 may also be applied to the input circuit INC.

[0120] 25 shows an example of a circuit layout of the input circuit INC of the semiconductor device SEM according to the fourth embodiment. Elements similar to those in FIG. 24 are given the same reference numerals, and detailed description thereof will be omitted.

[0121] Referring to the circuit diagram, the input circuit INC has a resistor element Rs arranged between the gates of the transistors TN1 and TP1 and the pad Pad. The resistor element Rs is connected to the gates of the transistors TN1 and TP1 via a node NC. Other circuit configurations of the input circuit INC are the same as those in FIG. 14.

[0122] Referring to the layout diagram, the input circuit INC has a diode D1a, pad wiring Pad, diode D1b, resistor element Rs, power supply line VDD, transistors TP1 and TN1, and ground line VSS arranged along the Y direction, similar to the output circuit OUTC shown in Figure 24. However, the input circuit INC has a wiring NC of the node NC formed using wiring layer M2 extending in the X direction between resistor element Rs and power supply line VDD using wiring layer M2. The layout of the diode D1a, pad wiring Pad, diode D1b, resistor element Rs, and the ground line VSS and power supply line VDD using wiring layer M4 is the same as in Figure 24.

[0123] The gates GT of the transistors TN1 and TP1 are connected to a wiring NC of the wiring layer M2 through a via VIA (GT-M1), a wiring W1, and a via VIA (M1-M2). The wiring NC is connected to one end of four partial resistance elements RS arranged in the Y direction through a via VIA (M1-M2), a wiring W1, and a via VIA (GT-M1).

[0124] The arrangement order in the Y direction of the ground line VSS, transistors TN1 and TP1, and power line VDD may be reversed. The arrangement order in the Y direction of the ground line VSS of diode D1a and wiring layer M4 and the arrangement order in the Y direction of the power line VDD of diode D1b and wiring layer M4 may be reversed. Furthermore, similar to the layout of the output circuit OUTC in Figure 22 or 23, the resistive element Rs may be positioned so as to overlap with the transistors TN1 and TP1 in a plan view.

[0125] As described above, the fourth embodiment can also provide the same effects as the above-described embodiments.

[0126] Fifth Embodiment Figure 26 shows an example of the circuit configuration of an output circuit OUTC of a semiconductor device SEM according to a fifth embodiment. The output circuit OUTC shown in Figure 26(A) has an NMOS transistor TN3 instead of the PMOS transistor TP1 of the output circuit OUTC of Figure 3. The output circuit OUTC shown in Figure 26(B) has an NMOS transistor TN3 instead of the PMOS transistor TP1 of the output circuit OUTC of Figure 17.

[0127] The output circuit OUTC shown in Fig. 26C has an NMOS transistor TN3 instead of the PMOS transistor TP1 of the output circuit OUTC of Fig. 24. The output circuit OUTC shown in Fig. 26D has a PMOS transistor TP3 instead of the NMOS transistor TN1 of the output circuit OUTC of Fig. 3.

[0128] The output circuit OUTC shown in Fig. 26(E) has a PMOS transistor TP3 instead of the NMOS transistor TN1 of the output circuit OUTC of Fig. 17. The output circuit OUTC shown in Fig. 26(F) has a PMOS transistor TP3 instead of the NMOS transistor TN1 of the output circuit OUTC of Fig. 24.

[0129] In a normal CMOS circuit, a PMOS transistor is used as a transistor that outputs a high level, and an NMOS transistor is used as a transistor that outputs a low level. On the other hand, in an output circuit that requires high-speed operation, the output transistor OTR may be configured to output a high level and a low level using either an NMOS transistor or a PMOS transistor that has a higher driving capability.

[0130] When a PMOS transistor is replaced with an NMOS transistor, or when an NMOS transistor is replaced with a PMOS transistor, the conductivity type of the semiconductor layer (source, drain) is different, but the layout structure can be the same as before the replacement. As shown in Figures 26(A) to 26(F), the circuit configuration in which the transistors have one conductivity type is applicable to each embodiment of the output circuit OUTC described above. Furthermore, the circuit configurations shown in Figures 26(A) to 26(F) are applicable to each embodiment of the input circuit INC described above.

[0131] Figure 27 shows another example of the circuit configuration of the output circuit OUTC of the semiconductor device SEM according to the fifth embodiment. The output circuit OUTC shown in Figure 27(A) has NMOS transistors TN3 and TN4 instead of the PMOS transistors TP1 and TP2 of the output circuit OUTC of Figure 7. The output circuits OUTTC shown in Figures 27(B) and 27(C) also have cascaded NMOS transistors TN3 and TN4 instead of the cascaded PMOS transistors TP1 and TP2 of a normal CMOS circuit.

[0132] The output circuit OUTC shown in Fig. 27(D) has PMOS transistors TP3 and TP4 instead of the NMOS transistors TN1 and TN2 of the output circuit OUTC of Fig. 7. The output circuits OUTC shown in Fig. 27(E) and (F) also have cascaded PMOS transistors TP3 and TP4 instead of the cascaded NMOS transistors TN1 and TN2 of a normal CMOS circuit.

[0133] The circuit configurations shown in Figures 27A to 27F, which use a single type of transistor conductivity, are applicable to each of the embodiments of the output circuit OUTC described above.Furthermore, the circuit configurations shown in Figures 27A to 27F are applicable to each of the embodiments of the input circuit INC described above.

[0134] As described above, the fifth embodiment can also provide the same effects as the above-described embodiments.

[0135] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0136] BMP Bump CP1, CP2 Chip D1b, D1a Diode ESD Protection circuit EXT External connection terminal FIN Fin GT Gate electrode IN Internal signal line IN2 input terminal INC Input circuit INTP Interposer IOC1, IOC2 Input / output circuit LI Local wiring M1, M2, M3, M4 Wiring layer NA, NB, NC Node Ndiff, Pdiff Semiconductor layer NS Nanosheet NW Well region OTR Output transistor OUT Internal signal line OUT1 Output terminal OUTC Output circuit Pad Pad Rs, Rsn, Rsp Resistive element SEM1, SEM2 Semiconductor device SUB Substrate TP1, TP2 PMOS transistor TN1, TN2 NMOS transistor VDD Power supply line VIA via VSS ground line W, W1, W2, W3, W4 wiring

Claims

1. A semiconductor device comprising: a first semiconductor chip having a first circuit; and a second semiconductor chip having a second circuit connected to the first circuit, wherein the first circuit comprises: a first power supply line; a second power supply line; a signal line connected to the second circuit; and a plurality of first transistors, each having a first source and a first drain, wherein the plurality of first transistors are arranged between the signal line and either the first power supply line or the second power supply line in a planar view, the first source of one of the first transistors being arranged adjacent to the first source of another of the first transistors in a planar view, and the first drain of one of the first transistors being arranged adjacent to the first drain of the other of the first transistors in a planar view.

2. The semiconductor device according to claim 1, wherein the first circuit has a plurality of second transistors each having a second source and a second drain, the plurality of second transistors being arranged between the other of the first power supply line or the second power supply line and the signal line in a planar view, the second source of one of the second transistors being arranged adjacent to the second source of another of the second transistors in a planar view, and the second drain of one of the second transistors being arranged adjacent to the second drain of another of the second transistors in a planar view.

3. A semiconductor device comprising: a first semiconductor chip having a first circuit; and a second semiconductor chip having a second circuit connected to the first circuit, wherein the first circuit comprises: a first power supply line, a second power supply line, a signal line connected to the second circuit, a plurality of first transistors, and a first diode connected to one of the first power supply line or the second power supply line and having a first semiconductor region having a first conductivity type, and a second semiconductor region connected to the signal line and having a second conductivity type different from the first conductivity type, wherein the plurality of first transistors are arranged between the signal line and one of the first power supply line or the second power supply line in a planar view, and the first diode is arranged between the plurality of first transistors and the signal line, or arranged so as to overlap the signal line, or arranged adjacent to any of the plurality of first transistors along the arrangement direction of the plurality of first transistors.

4. The semiconductor device according to claim 3, comprising: a plurality of second transistors; and a second diode connected to the other of the first power supply line or the second power supply line and having the second conductivity type, and having a fourth semiconductor region connected to the signal line and having the first conductivity type, wherein the plurality of second transistors are arranged between the other of the first power supply line or the second power supply line and the signal line in a planar view; and the second diode is arranged between the plurality of second transistors and the signal line, or arranged overlapping with the signal line, or arranged adjacent to any of the plurality of second transistors along the arrangement direction of the plurality of second transistors.

5. The semiconductor device according to claim 1, further comprising a plurality of first resistance elements connecting the signal line and first gates or first drains of the plurality of first transistors, wherein the plurality of first resistance elements are arranged between the plurality of first transistors and the signal line, or arranged overlapping the plurality of first transistors, or arranged overlapping the signal line in a plan view.

6. The semiconductor device according to claim 5, further comprising a first diode connected to one of the first power supply line or the second power supply line and having a first semiconductor region of a first conductivity type, and a second semiconductor region connected to the signal line and having a second conductivity type different from the first conductivity type, and wherein the plurality of first resistance elements are arranged to overlap the first diode in a planar view.

7. A semiconductor device according to any one of claims 1, 5 and 6, comprising: a plurality of second transistors each having a second gate and a second drain; and a plurality of second resistance elements connecting the signal line and the second gates or second drains of the plurality of second transistors, wherein the plurality of second resistance elements are arranged between the plurality of second transistors and the signal line, or arranged overlapping the plurality of second transistors, or arranged overlapping the signal line in a planar view.

8. The semiconductor device according to claim 7, further comprising: a second diode connected to the other of the first power supply line or the second power supply line and having a third semiconductor region; and a fourth semiconductor region connected to the signal line and having a conductivity type different from that of the third semiconductor region; and wherein the plurality of second resistance elements are arranged so as to overlap the second diode in a planar view.

9. The semiconductor device according to claim 1, wherein the first circuit has an output circuit that outputs a signal to the second circuit via the signal line.

10. The semiconductor device according to claim 1, wherein the first circuit has an input circuit that receives a signal from the second circuit via the signal line.

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